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jonathanrainer/serial_processors_project | simulations/greendroid_core_simulations/sources/utsa-var-args/utsa_var_args_testbench.vhd | 1 | 3125 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04.03.2016 11:22:26
-- Design Name:
-- Module Name: rem_testbench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity utsa_var_args_testbench is
end utsa_var_args_testbench;
architecture Behavioural of utsa_var_args_testbench is
signal sig_i00, sig_i01, sig_i02, sig_r00, sig_r01, sig_r02,
sig_FP, sig_FPout,sig_MDAT : std_logic_vector(31 DOWNTO 0);
signal sig_reset, sig_CLK, sig_MWAIT : std_logic;
component UTSA_VA_ARGSCoreAndMemory is
PORT (
in0 : IN std_logic_vector(31 DOWNTO 0);
in1 : IN std_logic_vector(31 DOWNTO 0);
in2 : IN std_logic_vector(31 DOWNTO 0);
out0 : OUT std_logic_vector(31 DOWNTO 0);
out1 : OUT std_logic_vector(31 DOWNTO 0);
out2 : OUT std_logic_vector(31 DOWNTO 0);
frame_pointer : IN std_logic_vector(31 DOWNTO 0);
frame_pointer_out : OUT std_logic_vector(31 DOWNTO 0);
rst : IN std_logic;
clck : IN std_logic;
mem_wait : IN std_logic;
mem_push : IN std_logic_vector(31 DOWNTO 0)
);
end component;
begin
uut: UTSA_VA_ARGSCoreAndMemory
port map (
in0 => sig_i00,
in1 => sig_i01,
in2 => sig_i02,
out0 => sig_r00,
out1 => sig_r01,
out2 => sig_r02,
frame_pointer => sig_FP,
frame_pointer_out => sig_FPout,
rst => sig_reset,
clck => sig_CLK,
mem_wait => sig_MWAIT,
mem_push => sig_MDAT
);
clock: process
constant clock_period:time := 40ns;
begin
wait for 200ns;
for I in 0 to 100 loop
sig_CLK <= '0';
wait for clock_period/2;
sig_CLK <= '1';
wait for clock_period/2;
end loop;
wait;
end process clock;
test: process begin
sig_MWAIT <= '1';
sig_reset <= '1';
wait for 100ns;
sig_reset <= '0';
wait for 100ns;
sig_i00 <= "00000000000000000000000000010000";
sig_i01 <= "00000000000000000000000000100000";
sig_i02 <= "00000000000000000000000001111001";
sig_MDAT <= "00000000000000000000000000011111";
sig_FP <= "00000000000000000000000001010000";
wait;
end process test;
end Behavioural;
| mit |
Pajeh/mips1 | src/vhdl/cpu_control.vhd | 1 | 7290 | -- Revision history:
-- 2015-08-12 Lukas Jaeger created
-- 2015-08-16 Lukas Jaeger fixed all bugs and made it working with the cpu
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library WORK;
use WORK.all;
entity cpu_control is
port(
clk : in std_logic;
rst : in std_logic;
rd_mask : out std_logic_vector(3 downto 0);
wr_mask : out std_logic_vector(3 downto 0);
instr_stall : in std_logic;
data_stall : in std_logic;
instr_in : in std_logic_vector(31 downto 0);
alu_op : out std_logic_vector(5 downto 0);
exc_mux1 : out std_logic_vector(1 downto 0);
exc_mux2 : out std_logic_vector(1 downto 0);
exc_alu_zero : in std_logic_vector(0 downto 0);
memstg_mux : out std_logic;
id_regdest_mux : out std_logic_vector (1 downto 0);
id_regshift_mux : out std_logic_vector (1 downto 0);
id_enable_regs : out std_logic;
in_mux_pc : out std_logic;
stage_control : out std_logic_vector (4 downto 0)
);
end entity cpu_control;
architecture structure_cpu_control of cpu_control is
signal instr_1, instr_2, instr_3, instr_4: std_logic_vector (31 downto 0);
begin
pipeline: process(clk, rst) is
begin
if (rst = '1') then
instr_1 <= x"00000000";
instr_2 <= x"00000000";
instr_3 <= x"00000000";
instr_4 <= x"00000000";
elsif (rising_edge(clk) and instr_stall /= '1' and data_stall /= '1') then
instr_1 <= instr_in;
instr_2 <= instr_1;
instr_3 <= instr_2;
instr_4 <= instr_3;
end if;
end process;
id: process (instr_1) is
begin
if (instr_1(31 downto 26) = "000000") then -- R-type instructions
id_regdest_mux <= "00";
id_regshift_mux <= "00";
if (instr_1(20 downto 0) = "000000000000000001000") then -- JR-instruction
in_mux_pc <= '1';
else
in_mux_pc <= '0';
end if;
else -- I-Type- and J-Type instructions. They can go together, because nobody cares about
-- the alu-result of a J-Type, so it does not matter, which value is yielded to ex
id_regdest_mux <= "10";
if (instr_1(31 downto 26) = "001111") then -- LUI needs a shift
id_regshift_mux <= "01";
elsif ((instr_1(31 downto 26) = "000010") -- J
or (instr_1 (31 downto 26) = "000011") -- JAL
or (instr_1 (31 downto 26) = "011101") -- JALX
or (instr_1 (31 downto 26) = "000100") -- BEQ
or (instr_1 (31 downto 26) = "000001") -- BGEZ
or (instr_1 (31 downto 26) = "000111") -- BGTZ
or (instr_1 (31 downto 26) = "000110") -- BLEZ
or (instr_1 (31 downto 26) = "000101") -- BEQZ
) then
id_regshift_mux <= "00";
in_mux_pc <= '1';
else
id_regshift_mux <= "00";
in_mux_pc <= '0';
end if;
end if;
end process;
ex: process (instr_2) is
begin
if (instr_2 (31 downto 26) = "001111") then --LUI
exc_mux1 <= "00";
exc_mux2 <= "01";
alu_op <="000100";
elsif ((instr_2 (31 downto 26) = "001001") --ADDIU
or (instr_2 (31 downto 26) = "100011") --LW
or (instr_2 (31 downto 26) = "101011") --SW
or (instr_2 (31 downto 26) = "101000") --SB
or (instr_2 (31 downto 26) = "100100") --LBU
)then
exc_mux1 <="10";
exc_mux2 <="01";
alu_op <="100000";
elsif (instr_2 (31 downto 26) = "001010") then --SLTI
exc_mux1 <="10";
exc_mux2 <="01";
alu_op <="001000";
elsif (instr_2 (31 downto 26) = "001100") then --ANDI
exc_mux1 <="10";
exc_mux2 <="01";
alu_op <="100100";
elsif (instr_2 (31 downto 26) = "001101") then --ORI
exc_mux1 <="10";
exc_mux2 <="01";
alu_op <="100101";
elsif ((instr_2 (31 downto 26) = "000000") and (instr_2(10 downto 0) = "00000101010")) then
exc_mux1 <= "10";
exc_mux2 <= "00";
alu_op <= "001000";
else --if (instr_2 (31 downto 26) = "000000") then -- NOP and other R-types and Ops, where the result does not matter
exc_mux1 <= "10";
exc_mux2 <= "00";
alu_op <= "000100";
end if;
end process;
mem: process (instr_3) is
begin
if (instr_3 (31 downto 26) = "100011") then --LW
memstg_mux <= '1';
rd_mask <= "1111";
wr_mask <= "0000";
elsif (instr_3 (31 downto 26) = "100100") then --LBU
memstg_mux <= '1';
rd_mask <= "0001";
wr_mask <= "0000";
elsif (instr_3 (31 downto 26) = "101011") then --SW
memstg_mux <= '0';
rd_mask <= "0000";
wr_mask <= "1111";
elsif (instr_3 (31 downto 26) = "101000") then --SB
memstg_mux <= '0';
rd_mask <= "0000";
wr_mask <= "0001";
else
memstg_mux <= '0';
rd_mask <= "0000";
wr_mask <= "0000";
end if;
end process;
wb: process (instr_4) is
begin
if ((instr_4 (31 downto 26) = "001111") or --LUI
(instr_4 (31 downto 26) = "001001") or --ADDIU
(instr_4 (31 downto 26) = "100011") or --LW
(instr_4 (31 downto 26) = "100100") or --LBU
(instr_4 (31 downto 26) = "001010") or --SLTI
(instr_4 (31 downto 26) = "001100") or --ANDI
(instr_4 (31 downto 26) = "001101") or --ORI
(instr_4 (31 downto 26) = "000000") and (instr_4(10 downto 0) = "00000101010")) --SLT
) then
id_enable_regs <= '1';
else
id_enable_regs <= '0';
end if;
end process;
stall: process (data_stall, instr_stall) is
begin
if (data_stall = '1' or instr_stall = '1') then
stage_control <= "00000";
else
stage_control <= "11111";
end if;
end process;
end architecture;
| mit |
plac-lab/TMIIaTest | Firmware/src/pulse2pulse.vhd | 1 | 5223 | --------------------------------------------------------------------------------
--! @file pulse2pulse.vhd
--! @brief Drive a pulse from one clock domain to another.
--!
--! Regardless of the duration of pulsein, the pulseout will be one out_clk
--! cycle wide and synchronized to out_clk. pulsein has to be synchronized to
--! in_clk already.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
--! A module that drive a pulse from one clock domain to another.
--! Regardless of the duration of pulsein, the pulseout will be one out_clk
--! cycle wide and synchronized to out_clk. pulsein has to be synchronized to
--! in_clk already.
entity pulse2pulse is
port (
in_clk :in std_logic; --! input clock
out_clk :in std_logic; --! output clock
rst :in std_logic; --! reset
pulsein :in std_logic; --! input pulse which is synchronized to in_clk
inbusy :out std_logic; --! notify input side that output is not ready yet
pulseout :out std_logic --! one out_clk wide output pulse, synchronized to out_clk
);
end pulse2pulse;
architecture syn of pulse2pulse is
-----------------------------------------------------------------------------------
--constant declarations
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--constant declarations
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--signal declarations
-----------------------------------------------------------------------------------
signal out_set :std_logic;
signal out_set_prev :std_logic;
signal out_set_prev2 :std_logic;
signal in_set :std_logic;
signal outreset :std_logic;
signal in_reset :std_logic;
signal in_reset_prev :std_logic;
signal in_reset_prev2:std_logic;
-----------------------------------------------------------------------------------
--component declarations
-----------------------------------------------------------------------------------
--*********************************************************************************
begin
--*********************************************************************************
-----------------------------------------------------------------------------------
--component instantiations
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--synchronous processes
-----------------------------------------------------------------------------------
in_proc:process(in_clk,rst)
begin
if(rst = '1') then
in_reset <= '0';
in_reset_prev <= '0';
in_reset_prev2<= '0';
in_set <= '0';
elsif(in_clk'event and in_clk = '1') then
--regitser a pulse on the pulse in port
--reset the signal when the ouput has registerred the pulse
if (in_reset_prev = '1' and in_reset_prev2 = '1') then
in_set <= '0';
elsif (pulsein = '1') then
in_set <= '1';
end if;
--register the reset signal from the other clock domain
--three times. double stage synchronising circuit
--reduces the MTB
in_reset <= outreset;
in_reset_prev <= in_reset;
in_reset_prev2 <= in_reset_prev;
end if;
end process in_proc;
out_proc:process(out_clk,rst)
begin
if(rst = '1') then
out_set <= '0';
out_set_prev <= '0';
out_set_prev2 <= '0';
outreset <= '0';
pulseout <= '0';
elsif(out_clk'event and out_clk = '1') then
--generate a pulse on the output when the
--set signal has travelled through the synchronising fip flops
if (out_set_prev = '1' and out_set_prev2 = '0') then
pulseout <= '1';
else
pulseout <= '0';
end if;
--feedback the corret reception of the set signal to reset the set pulse
if (out_set_prev = '1' and out_set_prev2 = '1') then
outreset <= '1';
elsif (out_set_prev = '0' and out_set_prev2 = '0') then
outreset <= '0';
end if;
--register the reset signal from the other clock domain
--three times. double stage synchronising circuit
--reduces the MTB
out_set <= in_set;
out_set_prev <= out_set;
out_set_prev2 <= out_set_prev;
end if;
end process out_proc;
-----------------------------------------------------------------------------------
--asynchronous processes
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--asynchronous mapping
-----------------------------------------------------------------------------------
inbusy <= in_set or in_reset_prev;
-------------------
-------------------
end syn;
| mit |
cadesalaberry/digital-system-design | lab2/g23_7_segment_decoder.vhd | 1 | 2127 | ---- generates the appropriate 7-segment display associated with the input code
--
-- entity name: g23_7_segment_decoder
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 13/02/2014
library ieee; -- allows use of the std_logic_vector type
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- allows use of the unsigned type
entity g23_7_segment_decoder is
port (
code : in std_logic_vector(3 downto 0);
RippleBlank_In : in std_logic;
RippleBlank_Out : out std_logic;
segments : out std_logic_vector(6 downto 0)
);
end g23_7_segment_decoder;
architecture alpha of g23_7_segment_decoder is
signal temp : std_logic_vector(7 downto 0);
begin
RippleBlank_Out <= temp(7);
segments <= temp(6 downto 0);
with RippleBlank_In & code select
temp <=
"0000001" when "00000", -- '0'
"1001111" when "00001", -- '1'
"0010010" when "00010", -- '2'
"0000110" when "00011", -- '3'
"1001100" when "00100", -- '4'
"0100100" when "00101", -- '5'
"0100000" when "00110", -- '6'
"0001111" when "00111", -- '7'
"0000000" when "01000", -- '8'
"0000100" when "01001", -- '9'
"0001000" when "01010", -- 'A'
"1100000" when "01011", -- 'b' (lowercase B)
"0110001" when "01100", -- 'C'
"1000010" when "01101", -- 'd' (lowercase D)
"0110000" when "01110", -- 'E'
"0111000" when "01111", -- 'F'
"1111111" when "10000",
"1001111" when "10001", -- '1'
"0010010" when "10010", -- '2'
"0000110" when "10011", -- '3'
"1001100" when "10100", -- '4'
"0100100" when "10101", -- '5'
"0100000" when "10110", -- '6'
"0001111" when "10111", -- '7'
"0000000" when "11000", -- '8'
"0000100" when "11001", -- '9'
"0001000" when "11010", -- 'A'
"0000000" when "11011", -- 'B'
"0110001" when "11100", -- 'C'
"0000001" when "11101", -- 'D'
"0110000" when "11110", -- 'E'
"0111000" when "11111", -- 'F'
"1011010" when others;
end alpha; | mit |
Pajeh/mips1 | test/vhdl/tb_fsm2.vhd | 1 | 203 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library WORK;
use WORK.cpu_pack.all;
entity tb_fsm2 is
end entity tb_fsm2;
architecture behavioural of tb_fsm2 is
end architecture; | mit |
Pajeh/mips1 | test/vhdl/tb_alu.vhd | 1 | 2276 | -- revision history:
-- 05.08.2015 Patrick Appenheimer created
-- 05.08.2015 Patrick Appenheimer testcase added
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
library WORK;
use WORK.cpu_pack.all;
entity tb_alu is
end entity tb_alu;
architecture behav_tb_alu of tb_alu is
-- -------- SIMULATION CONSTANTS -----
constant CLK_TIME : time := 2500 ps;
constant RST_TIME : time := 15 ns;
-- -------- ALU INTERFACE -----------------
signal clk : std_logic := '0';
signal rst : std_logic;
signal test_in_a : std_logic_vector(31 downto 0);
signal test_in_b : std_logic_vector(31 downto 0);
signal test_function_code : std_logic_vector(5 downto 0);
signal test_result : std_logic_vector(31 downto 0);
signal test_zero : std_logic_vector(0 downto 0);
-- ------ SIMULATION CONTROL ---------------
signal sim_finish : std_logic;
begin
-- GENERAL CONTROL SIGNALS
clk <= not clk after CLK_TIME;
rst <= '1', '0' after RST_TIME;
-- ALU
u1_alu: entity work.alu(behave)
PORT MAP(test_in_a, test_in_b, test_function_code, test_result, test_zero);
-- TEST PROCESS
test_process:
process
begin
sim_finish <= '0';
test_in_a <= x"0000_0001";
test_in_b <= x"0000_0001";
test_function_code <= b"10_0000";
wait for 1 ns;
test_in_a <= x"0000_0000";
test_in_b <= x"0000_0000";
wait for 1 ns;
test_in_a <= x"0000_0002";
test_in_b <= x"0000_0003";
test_function_code <= b"10_0000";
wait for 1 ns;
test_function_code <= b"11_0000";
wait for 1 ns;
test_in_a <= x"0000_0001";
test_in_b <= x"0000_0001";
test_function_code <= b"10_0100";
wait for 1 ns;
test_in_a <= x"0000_0001";
test_in_b <= x"0000_0002";
wait for 1 ns;
test_in_a <= x"0000_000F";
test_in_b <= x"0000_000C";
wait for 1 ns;
test_function_code <= b"10_0011";
wait for 1 ns;
test_in_a <= x"0000_0005";
test_in_b <= x"0000_000A";
test_function_code <= b"10_0101";
wait for 1 ns;
sim_finish <= '1';
wait;
end process;
end architecture behav_tb_alu;
| mit |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_m2s_memory_dc.vhd | 1 | 35061 | -------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_m2s_memory_dc.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.arg_mem_bank;
use axis_accelerator_adapter_v2_1_6.oarg_columnized_mem_bank;
use axis_accelerator_adapter_v2_1_6.srl_fifo_32_wt;
entity xd_m2s_memory_dc is
generic (
-- System generics:
C_FAMILY : string ; -- Xilinx FPGA family
C_MTBF_STAGES : integer;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
SIZE_WIDTH : integer;
CONV_DATA_WIDTH : integer;
CONV_ADDR_WIDTH : integer;
C_AP_ARG_DATA_WIDTH : integer;
C_AP_ARG_ADDR_WIDTH : integer;
C_MULTIBUFFER_DEPTH : integer;
C_AP_ARG_WIDTH : integer;
C_AP_ARG_N_DIM : integer;
C_AP_ARG_DIMS : int_vector;
C_AP_ARG_DIM_1 : integer;
C_AP_ARG_DIM_2 : integer;
C_AP_ARG_FORMAT_TYPE : integer;
C_AP_ARG_FORMAT_FACTOR : integer;
C_AP_ARG_FORMAT_DIM : integer;
C_NONE : integer := 2);
port (
clk : in std_logic;
rst : in std_logic;
conv_addr : in std_logic_vector(CONV_ADDR_WIDTH-1 downto 0);
conv_ce : in std_logic;
conv_we : in std_logic;
conv_last : in std_logic;
conv_rdy : out std_logic;
conv_data : out std_logic_vector(CONV_DATA_WIDTH-1 downto 0);
conv_size : out std_logic_vector(SIZE_WIDTH-1 downto 0);
sw_length : in std_logic_vector(31 downto 0);
sw_length_we : in std_logic;
use_sw_length : in std_logic;
ap_clk : in std_logic;
ap_rst : in std_logic;
ap_arg_addr : in std_logic_vector(C_AP_ARG_ADDR_WIDTH-1 downto 0);
ap_arg_ce : in std_logic;
ap_arg_we : in std_logic;
ap_arg_din : in std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
ap_arg_dout : out std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
ap_arg_rqt : out std_logic;
ap_arg_ack : in std_logic;
-- Status info
ap_arg_empty : out std_logic;
ap_arg_full : out std_logic;
ap_arg_used : out std_logic_vector(3 downto 0)); -- Number of used buffers
end entity;
architecture rtl of xd_m2s_memory_dc is
function calc_sw_length_fifo_width return integer is
variable N_elements : integer;
begin
if (C_AP_ARG_N_DIM = 2) then
N_elements := C_AP_ARG_DIM_1*C_AP_ARG_DIM_2;
else
N_elements := C_AP_ARG_DIM_1;
end if;
return log2(N_elements)+1;
end function calc_sw_length_fifo_width;
function calc_use_columnized_bank return boolean is
variable ret : boolean := false;
begin
if (C_AP_ARG_N_DIM = 2) then
if(C_AP_ARG_FORMAT_TYPE = FORMAT_TYPE_RESHAPE_BLOCK) then
if(C_AP_ARG_FORMAT_DIM = 1 and C_AP_ARG_FORMAT_FACTOR > 1) then
ret := true;
end if;
end if;
end if;
return ret;
end function calc_use_columnized_bank;
--------------------------------------------------------------------------
-- C_AP_ARG_DIMS generic is a vector with range between 1 and C_AP_ARG_N_DIM.
-- It follows VivadoHLS approach (i.e., dimension 1 is the closest to the
-- varibale declaration). For example, A[2][4][8]:
-- C_AP_ARG_DIMS[1] = 2
-- C_AP_ARG_DIMS[2] = 4
-- C_AP_ARG_DIMS[3] = 8
-- For the memory bank organization, it's easier to have this sorted
-- differently, so it reflects the linear organization in which is stored in
-- memory. That is, the dimension more far away from definition is 0 and
-- closest is C_AP_ARG_N_DIM-1. For previous example:
-- ARG_DIMS[2] = 2
-- ARG_DIMS[1] = 4
-- ARG_DIMS[0] = 8
constant ARG_DIMS : int_vector(0 to C_AP_ARG_N_DIM-1) := C_AP_ARG_DIMS;
function calc_addr_lsb return int_vector is
variable lsb_vector : int_vector(C_AP_ARG_N_DIM-1 downto 0);
variable msb_vector : int_vector(C_AP_ARG_N_DIM-1 downto 0);
variable lsb : integer := 0;
variable dim_width : integer;
begin
for i in 0 to C_AP_ARG_N_DIM-1 loop
dim_width := log2(ARG_DIMS(i));
lsb_vector(i) := lsb;
msb_vector(i) := lsb+dim_width-1;
lsb := lsb + dim_width;
end loop;
return lsb_vector;
end function calc_addr_lsb;
function calc_addr_msb return int_vector is
variable lsb_vector : int_vector(C_AP_ARG_N_DIM-1 downto 0);
variable msb_vector : int_vector(C_AP_ARG_N_DIM-1 downto 0);
variable lsb : integer := 0;
variable dim_width : integer;
begin
for i in 0 to C_AP_ARG_N_DIM-1 loop
dim_width := log2(ARG_DIMS(i));
lsb_vector(i) := lsb;
msb_vector(i) := lsb+dim_width-1;
lsb := lsb + dim_width;
end loop;
return msb_vector;
end function calc_addr_msb;
--constant PTR_WIDTH : integer := log2(C_MULTIBUFFER_DEPTH);
constant PTR_WIDTH : integer := if_then_else((C_MULTIBUFFER_DEPTH = 1),1,log2(C_MULTIBUFFER_DEPTH));
constant GRAY_WIDTH : integer := calc_gray_width(C_MULTIBUFFER_DEPTH);
constant INIT_RD_GRAY : integer := 0;
constant INIT_WR_GRAY : integer := INIT_RD_GRAY;
constant INIT_WR_GRAY_AHEAD : integer := INIT_RD_GRAY-C_MULTIBUFFER_DEPTH+1;
constant conv_din_zero : std_logic_vector(CONV_DATA_WIDTH-1 downto 0) := (others => '0');
constant SW_LENGTH_FIFO_WIDTH : integer := calc_sw_length_fifo_width;
constant USE_COLUMNIZED_BANK : boolean := calc_use_columnized_bank;
signal empty_n : std_logic;
signal full_n : std_logic;
-- Multibuffer push/pop
signal mb_push : std_logic;
signal mb_pop : std_logic;
signal mb_push_ok : std_logic;
signal mb_pop_ok : std_logic;
signal mb_pop_ok1 : std_logic;
signal mb_pop_ok_rd : std_logic;
signal mb_pop_ok_vect: std_logic_vector(0 downto 0);
--
signal iport_ce : std_logic; -- ap_arg_ce validated with full_n
signal oport_ce : std_logic; -- conv_ce validated with empty_n
-- Read buffer selection
signal rd_ptr : unsigned(PTR_WIDTH-1 downto 0);
signal rd_pntr : std_logic_vector(PTR_WIDTH-1 downto 0);
signal rd_pntr_wr : std_logic_vector(PTR_WIDTH-1 downto 0);
signal rd_ptr_dec : std_logic_vector(C_MULTIBUFFER_DEPTH-1 downto 0);
signal rd_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal rd_gray_wr : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal next_rd_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal next_rd_gray_wr: std_logic_vector(GRAY_WIDTH-1 downto 0);
signal prev_rd_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
-- Gray counter for writes synchronized with read clock
signal wr_gray_sync : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal rd_bin : unsigned(GRAY_WIDTH-1 downto 0);
signal rd_bins : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_bin : unsigned(GRAY_WIDTH-1 downto 0);
signal wr_bins : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal ptr_dist : unsigned(GRAY_WIDTH-1 downto 0);
signal pntr_dist : std_logic_vector(PTR_WIDTH-1 downto 0);
-- Write buffer selection
signal wr_ptr : unsigned(PTR_WIDTH-1 downto 0);
signal wr_pntr : std_logic_vector(PTR_WIDTH-1 downto 0);
signal wr_pntr_rd : std_logic_vector(PTR_WIDTH-1 downto 0);
signal wr_ptr_dec : std_logic_vector(C_MULTIBUFFER_DEPTH-1 downto 0);
signal wr_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_gray_rd : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_gray_ahead : std_logic_vector(GRAY_WIDTH-1 downto 0);
signal wr_gray_ahead_rd : std_logic_vector(GRAY_WIDTH-1 downto 0);
-- Only required for almost empty:
signal prev_wr_gray : std_logic_vector(GRAY_WIDTH-1 downto 0);
-- pragma translate_off
signal empty : std_logic;
signal full : std_logic;
-- pragma translate_on
signal ap_arg_hw_length : unsigned(C_AP_ARG_ADDR_WIDTH downto 0);
signal ap_arg_length : std_logic_vector(C_AP_ARG_ADDR_WIDTH downto 0);
signal sw_length_fifo_dout : std_logic_vector(SW_LENGTH_FIFO_WIDTH-1 downto 0);
signal sw_length_wr : std_logic_vector(SW_LENGTH_FIFO_WIDTH-1 downto 0);
signal sw_length_rd : std_logic_vector(SW_LENGTH_FIFO_WIDTH-1 downto 0);
signal sw_length_we_vector : std_logic_vector(0 downto 0);
signal sw_length_we_rd : std_logic;
signal sw_length_we_rd_vector : std_logic_vector(0 downto 0);
signal ap_arg_full_i : std_logic;
type length_mem_type is array (2**PTR_WIDTH-1 downto 0) of std_logic_vector(C_AP_ARG_ADDR_WIDTH downto 0);
signal hw_length_mem : length_mem_type;
signal hw_length_mem_dout : std_logic_vector(C_AP_ARG_ADDR_WIDTH downto 0);
signal hw_length_mem_dout_rd : std_logic_vector(C_AP_ARG_ADDR_WIDTH downto 0);
attribute ram_style : string;
attribute ram_style of hw_length_mem : signal is "distributed";
constant C_EXTRA_SYNCS : integer := 1;
begin
EXISTING : if (C_EXTRA_SYNCS = 0) generate
begin
-- pragma translate_off
empty <= not(empty_n);
full <= not(full_n);
-- pragma translate_on
-- New buffer has been produced when accelerator generates ack and the
-- multibuffer is not full.
mb_push <= full_n and ap_arg_ack;
-- New buffer consumed when the last data is read and the multibuffer is not
-- empty.
mb_pop <= empty_n and conv_ce and conv_last;
-- Selection pointer to write buffer (push)
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
wr_ptr <= (others => '0');
wr_ptr_dec <= (others => '0');
wr_ptr_dec(0) <= '1';
elsif(ap_clk'event and ap_clk = '1') then
if (mb_push_ok = '1') then
if(wr_ptr = C_MULTIBUFFER_DEPTH-1) then
wr_ptr <= (others => '0');
else
wr_ptr <= wr_ptr + 1;
end if;
wr_ptr_dec <= wr_ptr_dec(C_MULTIBUFFER_DEPTH-2 downto 0) & wr_ptr_dec(C_MULTIBUFFER_DEPTH-1);
end if;
end if;
end process;
-- Gray pointers (write) to manage status of multibuffer
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
wr_gray_ahead <= bin2gray(INIT_WR_GRAY_AHEAD, GRAY_WIDTH);
wr_gray <= bin2gray(INIT_WR_GRAY, GRAY_WIDTH);
prev_wr_gray <= bin2gray(INIT_WR_GRAY-1, GRAY_WIDTH);
elsif(ap_clk'event and ap_clk = '1') then
if (mb_push_ok = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
wr_gray <= gray_inc(wr_gray);
prev_wr_gray <= wr_gray;
end if;
end if;
end process;
-- Full status signal generation
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
full_n <= '0';
elsif(ap_clk'event and ap_clk = '1') then
if(full_n = '0') then
-- Stay in full if wr_gray_ahead = next_rd_gray
if(wr_gray_ahead = next_rd_gray) then
full_n <= '0';
else
full_n <= '1';
end if;
else
-- Go to full if writting and wr_gray_ahead = rd_gray
if(wr_gray_ahead = rd_gray) then
full_n <= not(mb_push_ok);
else
full_n <= '1';
end if;
end if;
end if;
end process;
-- Read buffer selection pointer (pop)
process(clk, rst)
begin
if(rst = '1') then
rd_ptr <= (others => '0');
rd_ptr_dec <= (others => '0');
rd_ptr_dec(0) <= '1';
elsif(clk'event and clk = '1') then
if (mb_pop_ok = '1') then
if(rd_ptr = C_MULTIBUFFER_DEPTH-1) then
rd_ptr <= (others => '0');
else
rd_ptr <= rd_ptr + 1;
end if;
rd_ptr_dec <= rd_ptr_dec(C_MULTIBUFFER_DEPTH-2 downto 0) & rd_ptr_dec(C_MULTIBUFFER_DEPTH-1);
end if;
end if;
end process;
-- Gray pointers (read) to manage status of multibuffer
process(clk, rst)
begin
if(rst = '1') then
next_rd_gray <= bin2gray(INIT_RD_GRAY+1, GRAY_WIDTH);
rd_gray <= bin2gray(INIT_RD_GRAY, GRAY_WIDTH);
prev_rd_gray <= bin2gray(INIT_RD_GRAY-1, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
if (mb_pop_ok = '1') then
next_rd_gray <= gray_inc(next_rd_gray);
rd_gray <= next_rd_gray;
prev_rd_gray <= rd_gray;
end if;
end if;
end process;
-- Empty status signal generation:
process(clk, rst)
begin
if(rst = '1') then
empty_n <= '0';
elsif(clk'event and clk = '1') then
if(empty_n = '0') then
-- Stay in empty if rd_gray = wr_gray
if(rd_gray = wr_gray) then
empty_n <= '0';
else
empty_n <= '1';
end if;
else
-- Move to empty if reading and next_rd_gray = wr_gray
if(next_rd_gray = wr_gray) then
empty_n <= not(mb_pop_ok);
else
empty_n <= '1';
end if;
end if;
end if;
end process;
mb_push_ok <= mb_push and full_n;
-- Management of pseudo-static buffers
-- Para los argumentos de salida no hay buffers pseudo-estáticos.
mb_pop_ok <= mb_pop and empty_n;
---------------------------------------------
conv_rdy <= empty_n;
ap_arg_rqt <= full_n;
iport_ce <= ap_arg_ce and full_n;
oport_ce <= conv_ce and empty_n;
-- Number of used buffers it's calculated as the distance between read/write
-- pointers
-- synch wr_gray to reduce metastability. Added one cycle clock latency on rd_clk
process(clk, rst)
begin
if(rst = '1') then
wr_gray_sync <= bin2gray(INIT_WR_GRAY, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
wr_gray_sync <= wr_gray;
end if;
end process;
wr_bin <= unsigned(gray2bin(wr_gray_sync));
process(clk, rst)
begin
if(rst = '1') then
rd_bin <= to_unsigned(INIT_RD_GRAY, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
if (mb_pop_ok = '1') then
rd_bin <= rd_bin + 1;
end if;
end if;
end process;
-- If we only look at the pointers, there will be one cycle latency to reflect
-- the status of the fifo. To refresh inmediately during a read, we decrement
-- the counter
process(clk, rst)
begin
if(rst = '1') then
ptr_dist <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_pop_ok = '1') then
ptr_dist <= ptr_dist - 1;
else
-- This ia also valid when we arrive at the end of sequence counter wr_bin < rd_bin
ptr_dist <= wr_bin - rd_bin;
end if;
end if;
end process;
process(ptr_dist)
begin
ap_arg_used <= (others => '0');
ap_arg_used(ptr_dist'range) <= std_logic_vector(ptr_dist);
end process;
-- Status signals empty/full should be synchronized with AXI clk
ap_arg_empty <= not(empty_n);
process(clk, rst)
begin
if(rst = '1') then
ap_arg_full_i <= '1';
elsif(clk'event and clk = '1') then
-- If read, we move out of full state
if(mb_pop_ok = '1') then
ap_arg_full_i <= '0';
else
-- Stay in full if wr_gray_ahead = next_rd_gray
if(wr_gray_ahead = next_rd_gray) then
ap_arg_full_i <= '1';
else
ap_arg_full_i <= '0';
end if;
end if;
end if;
end process;
ap_arg_full <= ap_arg_full_i;
end generate EXISTING;
NEW_INTRO : if (C_EXTRA_SYNCS = 1) generate
CONSTANT LOG2DEPTH : integer := log2(C_MULTIBUFFER_DEPTH);
CONSTANT ONE : std_logic_vector(PTR_WIDTH-1 DOWNTO 0)
:= int2lv(1, PTR_WIDTH);
begin
-- pragma translate_off
empty <= not(empty_n);
full <= not(full_n);
-- pragma translate_on
-- New buffer has been produced when accelerator generates ack and the
-- multibuffer is not full.
mb_push <= full_n and ap_arg_ack;
-- New buffer consumed when the last data is read and the multibuffer is not
-- empty.
mb_pop <= empty_n and conv_ce and conv_last;
-- Selection pointer to write buffer (push)
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
wr_pntr <= (others => '0');
elsif(ap_clk'event and ap_clk = '1') then
if (mb_push_ok = '1') then
if(wr_pntr = int2lv(C_MULTIBUFFER_DEPTH-1,PTR_WIDTH)) then
wr_pntr <= (others => '0');
else
wr_pntr <= wr_pntr + ONE;
end if;
end if;
end if;
end process;
process(clk, rst)
begin
if(rst = '1') then
rd_pntr <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_pop_ok_rd = '1') then
if(rd_pntr = int2lv(C_MULTIBUFFER_DEPTH-1,PTR_WIDTH)) then
rd_pntr <= (others => '0');
else
rd_pntr <= rd_pntr + ONE;
end if;
end if;
end if;
end process;
-- Gray pointers (write) to manage status of multibuffer
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
wr_gray_ahead <= bin2gray(INIT_WR_GRAY_AHEAD, GRAY_WIDTH);
wr_gray <= bin2gray(INIT_WR_GRAY, GRAY_WIDTH);
prev_wr_gray <= bin2gray(INIT_WR_GRAY-1, GRAY_WIDTH);
elsif(ap_clk'event and ap_clk = '1') then
if (mb_push_ok = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
wr_gray <= gray_inc(wr_gray);
prev_wr_gray <= wr_gray;
end if;
end if;
end process;
-- Gray pointers (read) to manage status of multibuffer
process(clk, rst)
begin
if(rst = '1') then
next_rd_gray <= bin2gray(INIT_RD_GRAY+1, GRAY_WIDTH);
rd_gray <= bin2gray(INIT_RD_GRAY, GRAY_WIDTH);
prev_rd_gray <= bin2gray(INIT_RD_GRAY-1, GRAY_WIDTH);
elsif(clk'event and clk = '1') then
if (mb_pop_ok_rd = '1') then
next_rd_gray <= gray_inc(next_rd_gray);
rd_gray <= next_rd_gray;
prev_rd_gray <= rd_gray;
end if;
end if;
end process;
clkx_1: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
GENERIC MAP(
C_HAS_RST => 1,
C_RD_PNTR_WIDTH => GRAY_WIDTH,
C_WR_PNTR_WIDTH => GRAY_WIDTH,
C_MSGON_VAL => 1,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES
)
PORT MAP(
WR_CLK => ap_clk,
RD_CLK => clk,
WR_RST => ap_rst,
RD_RST => rst,
WR_PNTR => wr_gray,
RD_PNTR => rd_gray,
WR_PNTR_RD => wr_gray_rd,
RD_PNTR_WR => rd_gray_wr
);
clkx_2: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
GENERIC MAP(
C_HAS_RST => 1,
C_RD_PNTR_WIDTH => GRAY_WIDTH,
C_WR_PNTR_WIDTH => GRAY_WIDTH,
C_MSGON_VAL => 1,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES
)
PORT MAP(
WR_CLK => ap_clk,
RD_CLK => clk,
WR_RST => ap_rst,
RD_RST => rst,
WR_PNTR => wr_gray_ahead,
RD_PNTR => next_rd_gray,
WR_PNTR_RD => wr_gray_ahead_rd,
RD_PNTR_WR => next_rd_gray_wr
);
clkx_3: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
GENERIC MAP(
C_HAS_RST => 1,
C_RD_PNTR_WIDTH => PTR_WIDTH,
C_WR_PNTR_WIDTH => PTR_WIDTH,
C_MSGON_VAL => 1,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES
)
PORT MAP(
WR_CLK => ap_clk,
RD_CLK => clk,
WR_RST => ap_rst,
RD_RST => rst,
WR_PNTR => wr_pntr,
RD_PNTR => rd_pntr,
WR_PNTR_RD => wr_pntr_rd,
RD_PNTR_WR => rd_pntr_wr
);
-- Full status signal generation
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
full_n <= '0';
elsif(ap_clk'event and ap_clk = '1') then
if(full_n = '0') then
-- Stay in full if wr_gray_ahead = next_rd_gray
if(wr_gray_ahead = next_rd_gray_wr) then
full_n <= '0';
else
full_n <= '1';
end if;
else
-- Go to full if writting and wr_gray_ahead = rd_gray
if(wr_gray_ahead = rd_gray_wr) then
full_n <= not(mb_push_ok);
else
full_n <= '1';
end if;
end if;
end if;
end process;
prd1: PROCESS (clk, rst)
BEGIN
-- Register Stage #1
IF (rst = '1') THEN
mb_pop_ok1 <= '0';
mb_pop_ok_rd <= '0';
ELSIF (clk'event and clk = '1') THEN
mb_pop_ok1 <= mb_pop_ok;
mb_pop_ok_rd <= mb_pop_ok1;
END IF;
END PROCESS prd1;
-- Empty status signal generation:
process(clk, rst)
begin
if(rst = '1') then
empty_n <= '0';
elsif(clk'event and clk = '1') then
if(empty_n = '0') then
-- Stay in empty if rd_gray = wr_gray
if(rd_gray = wr_gray_rd) then
empty_n <= '0';
else
empty_n <= '1';
end if;
else
-- Move to empty if reading and next_rd_gray = wr_gray
if(next_rd_gray = wr_gray_rd) then
empty_n <= not(mb_pop_ok_rd);
else
empty_n <= '1';
end if;
end if;
end if;
end process;
mb_push_ok <= mb_push and full_n;
-- Management of pseudo-static buffers
-- Para los argumentos de salida no hay buffers pseudo-estáticos.
mb_pop_ok <= mb_pop and empty_n;
---------------------------------------------
conv_rdy <= empty_n;
ap_arg_rqt <= full_n;
iport_ce <= ap_arg_ce and full_n;
oport_ce <= conv_ce and empty_n;
-- If we only look at the pointers, there will be one cycle latency to reflect
-- the status of the fifo. To refresh inmediately during a read, we decrement
-- the counter
MBn : if (C_MULTIBUFFER_DEPTH > 1) generate
begin
process(clk, rst)
begin
if(rst = '1') then
pntr_dist <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_pop_ok_rd = '1') then
pntr_dist <= pntr_dist - 1;
else
-- This ia also valid when we arrive at the end of sequence counter wr_bin < rd_bin
--pntr_dist <= ('0' & wr_pntr_rd) - ('0' & rd_pntr);
pntr_dist <= (wr_pntr_rd) - (rd_pntr);
end if;
end if;
end process;
end generate MBn;
MB1 : if (C_MULTIBUFFER_DEPTH = 1) generate
begin
process(clk, rst)
begin
if(rst = '1') then
rd_bins <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_pop_ok_rd = '1') then
rd_bins <= rd_bins + 1;
end if;
end if;
end process;
wr_bins <= wr_gray_rd;
process(clk, rst)
begin
if(rst = '1') then
pntr_dist <= (others => '0');
elsif(clk'event and clk = '1') then
if (mb_pop_ok_rd = '1') then
pntr_dist <= pntr_dist - 1;
else
-- This ia also valid when we arrive at the end of sequence counter wr_bin < rd_bin
--pntr_dist <= ('0' & wr_pntr_rd) - ('0' & rd_pntr);
pntr_dist <= (wr_bins) - (rd_bins);
end if;
end if;
end process;
end generate MB1;
process(pntr_dist)
begin
ap_arg_used <= (others => '0');
ap_arg_used(pntr_dist'range) <= (pntr_dist);
end process;
-- Status signals empty/full should be synchronized with AXI clk
ap_arg_empty <= not(empty_n);
process(clk, rst)
begin
if(rst = '1') then
ap_arg_full_i <= '1';
elsif(clk'event and clk = '1') then
-- If read, we move out of full state
if(mb_pop_ok_rd = '1') then
ap_arg_full_i <= '0';
else
-- Stay in full if wr_gray_ahead = next_rd_gray
if(wr_gray_ahead_rd = next_rd_gray) then
ap_arg_full_i <= '1';
else
ap_arg_full_i <= '0';
end if;
end if;
end if;
end process;
ap_arg_full <= ap_arg_full_i;
end generate NEW_INTRO;
LINEAR_BANK_GEN : if not(USE_COLUMNIZED_BANK) generate
-- address width for input port is the addition of required bits for the
-- argument plus the required bits to select buffer (PTR_WIDTH).
constant IPORT_ADDR_WIDTH : integer := C_AP_ARG_ADDR_WIDTH+log2(C_MULTIBUFFER_DEPTH);
constant OPORT_ADDR_WIDTH : integer := CONV_ADDR_WIDTH+log2(C_MULTIBUFFER_DEPTH);
signal iport_addr : std_logic_vector(IPORT_ADDR_WIDTH-1 downto 0);
signal oport_addr : std_logic_vector(OPORT_ADDR_WIDTH-1 downto 0);
begin
MB1_addr : if (C_MULTIBUFFER_DEPTH = 1) generate
begin
iport_addr <= ap_arg_addr;
oport_addr <= conv_addr;
end generate MB1_addr;
MBn_addr : if (C_MULTIBUFFER_DEPTH > 1) generate
begin
iport_addr <= std_logic_vector(wr_pntr) & ap_arg_addr;
oport_addr <= std_logic_vector(rd_pntr) & conv_addr;
end generate MBn_addr;
MEM_I : entity axis_accelerator_adapter_v2_1_6.arg_mem_bank
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_IS_UNIDIR => 0,
C_IPORT_DWIDTH => C_AP_ARG_DATA_WIDTH,
C_IPORT_AWIDTH => IPORT_ADDR_WIDTH,
C_OPORT_DWIDTH => CONV_DATA_WIDTH,
C_OPORT_AWIDTH => OPORT_ADDR_WIDTH)
port map (
rst => ap_rst,
iport_clk => ap_clk,
iport_ce => iport_ce,
iport_we => ap_arg_we,
iport_addr => iport_addr,
iport_din => ap_arg_din,
iport_dout => ap_arg_dout,
oport_clk => clk,
oport_ce => oport_ce,
oport_we => conv_we,
oport_addr => oport_addr,
oport_din => conv_din_zero,
oport_dout => conv_data);
end generate LINEAR_BANK_GEN;
COLUMNIZED_BANK_GEN : if (USE_COLUMNIZED_BANK) generate
begin
MEM_I : entity axis_accelerator_adapter_v2_1_6.oarg_columnized_mem_bank
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_FACTOR => C_AP_ARG_FORMAT_FACTOR,
C_BUFFER_WIDTH => PTR_WIDTH,
C_CONV_AWIDTH => CONV_ADDR_WIDTH,
C_CONV_DWIDTH => CONV_DATA_WIDTH,
C_ARG_WIDTH => C_AP_ARG_WIDTH,
C_ARG_AWIDTH => C_AP_ARG_ADDR_WIDTH)
port map (
ap_rst => ap_rst,
ap_clk => ap_clk,
ap_arg_ce => ap_arg_ce,
ap_arg_we => ap_arg_we,
ap_arg_buffer => std_logic_vector(wr_ptr),
ap_arg_addr => ap_arg_addr,
ap_arg_din => ap_arg_din,
ap_arg_dout => ap_arg_dout,
clk => clk,
conv_ce => conv_ce,
conv_we => conv_we,
conv_buffer => std_logic_vector(rd_ptr),
conv_addr => conv_addr,
conv_data => conv_data);
end generate COLUMNIZED_BANK_GEN;
-- To know how many beats to produce on output stream, we track the highest
-- address written
process(ap_clk, ap_rst)
begin
if(ap_rst = '1') then
ap_arg_hw_length <= (others => '0');
elsif(ap_clk'event and ap_clk = '1') then
if(ap_arg_ack = '1') then
ap_arg_hw_length <= (others => '0');
elsif(iport_ce = '1' and ap_arg_we = '1') then
if(unsigned(ap_arg_addr) >= ap_arg_hw_length) then
ap_arg_hw_length <= unsigned('0' & ap_arg_addr) + 1;
end if;
end if;
end if;
end process;
-- length memory modeling (XST infer)
process(ap_clk)
begin
if(ap_clk'event and ap_clk = '1') then
if(ap_arg_ack = '1') then
hw_length_mem(to_integer(wr_ptr)) <= std_logic_vector(ap_arg_hw_length);
end if;
end if;
end process;
hw_length_mem_dout <= hw_length_mem(to_integer(rd_ptr));
-- clkx_4: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
-- GENERIC MAP(
-- C_HAS_RST => 1,
-- C_RD_PNTR_WIDTH => SW_LENGTH_FIFO_WIDTH,
-- C_WR_PNTR_WIDTH => SW_LENGTH_FIFO_WIDTH,
-- C_MSGON_VAL => 1,
-- C_SYNCHRONIZER_STAGE => 2
-- )
-- PORT MAP(
-- WR_CLK => ap_clk,
-- RD_CLK => clk,
-- WR_RST => ap_rst,
-- RD_RST => rst,
-- WR_PNTR => sw_length_wr,
-- RD_PNTR => open,
-- WR_PNTR_RD => sw_length_rd,
-- RD_PNTR_WR => open
-- );
-- SW_LENGTH_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
-- generic map (
-- C_CDC_TYPE => 1,
-- C_RESET_STATE => 0,
-- C_SINGLE_BIT => 0,
-- C_VECTOR_WIDTH => SW_LENGTH_FIFO_WIDTH,
-- C_MTBF_STAGES => 2
-- )
-- port map (
-- prmry_aclk => '0',
-- prmry_resetn => '0',
-- prmry_in => '0',
-- prmry_vect_in => sw_length_wr,
--
-- scndry_aclk => clk,
-- scndry_resetn => rst,
-- scndry_out => open,
-- scndry_vect_out => sw_length_rd
-- );
clkx_5: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
GENERIC MAP(
C_HAS_RST => 1,
C_RD_PNTR_WIDTH => C_AP_ARG_ADDR_WIDTH+1,
C_WR_PNTR_WIDTH => C_AP_ARG_ADDR_WIDTH+1,
C_MSGON_VAL => 1,
C_SYNCHRONIZER_STAGE => 2
)
PORT MAP(
WR_CLK => ap_clk,
RD_CLK => clk,
WR_RST => ap_rst,
RD_RST => rst,
WR_PNTR => hw_length_mem_dout,
RD_PNTR => open,
WR_PNTR_RD => hw_length_mem_dout_rd,
RD_PNTR_WR => open
);
sw_length_rd <= sw_length(SW_LENGTH_FIFO_WIDTH-1 downto 0);
sw_length_we_vector(0) <= sw_length_we;
sw_length_we_rd <= sw_length_we_rd_vector(0);
wr_stg_inst: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff
GENERIC MAP (
C_HAS_RST => 1,
C_WIDTH => 1
)
PORT MAP (
RST => rst,
CLK => clk,
D => sw_length_we_vector,
Q => sw_length_we_rd_vector
);
SW_LENGTH_FIFO : entity axis_accelerator_adapter_v2_1_6.srl_fifo_32_wt
generic map (
C_FAMILY => C_FAMILY,
WIDTH => SW_LENGTH_FIFO_WIDTH)
port map (
rst => rst,
clk => clk,
din => sw_length_rd,
din_vld => sw_length_we_rd,
din_rdy => open,
dout => sw_length_fifo_dout,
dout_vld => open,
dout_rdy => mb_pop_ok_rd
);
process(use_sw_length, hw_length_mem_dout_rd, sw_length_fifo_dout)
constant HW_LSB : integer := log2(C_AP_ARG_DATA_WIDTH/8);
constant SW_LSB : integer := log2(C_AP_ARG_WIDTH/8);
constant SW_MSB : integer := SW_LSB+SW_LENGTH_FIFO_WIDTH-1;
begin
conv_size <= (others => '0');
if(use_sw_length = '0') then
conv_size(SIZE_WIDTH-1 downto HW_LSB) <= hw_length_mem_dout_rd;
else
conv_size(SW_MSB downto SW_LSB) <= sw_length_fifo_dout;
end if;
end process;
end rtl;
| mit |
agural/FPGA-Oscilloscope | osc/lpm_counter9.vhd | 1 | 4349 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter9.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter9 IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0)
);
END lpm_counter9;
ARCHITECTURE SYN OF lpm_counter9 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (23 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(23 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 24
)
PORT MAP (
clock => clock,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "24"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter9.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter9.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter9.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter9.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter9_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| mit |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/oarg_columnized_mem_bank.vhd | 1 | 8266 | -------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : oarg_columnized_mem_bank.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.arg_mem_bank;
entity oarg_columnized_mem_bank is
generic (
C_FAMILY : string;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_FACTOR : integer;
C_BUFFER_WIDTH : integer;
C_CONV_AWIDTH : integer;
C_CONV_DWIDTH : integer;
C_ARG_WIDTH : integer;
C_ARG_AWIDTH : integer);
port (
ap_rst : in std_logic;
ap_clk : in std_logic;
ap_arg_ce : in std_logic;
ap_arg_we : in std_logic;
ap_arg_buffer : in std_logic_vector(C_BUFFER_WIDTH-1 downto 0);
ap_arg_addr : in std_logic_vector(C_ARG_AWIDTH-1 downto 0);
ap_arg_din : in std_logic_vector(C_ARG_WIDTH*C_FACTOR-1 downto 0);
ap_arg_dout : out std_logic_vector(C_ARG_WIDTH*C_FACTOR-1 downto 0);
clk : in std_logic;
conv_ce : in std_logic;
conv_we : in std_logic;
conv_buffer : in std_logic_vector(C_BUFFER_WIDTH-1 downto 0);
conv_addr : in std_logic_vector(C_CONV_AWIDTH-1 downto 0);
conv_data : out std_logic_vector(C_CONV_DWIDTH-1 downto 0));
end oarg_columnized_mem_bank;
architecture rtl of oarg_columnized_mem_bank is
constant BANK_AWIDTH : integer := log2(C_FACTOR);
constant IPORT_AWIDTH : integer := C_BUFFER_WIDTH+C_ARG_AWIDTH;
constant OPORT_AWIDTH : integer := C_BUFFER_WIDTH+(C_CONV_AWIDTH-BANK_AWIDTH);
signal oport_addr : std_logic_vector(OPORT_AWIDTH-1 downto 0);
signal iport_addr : std_logic_vector(IPORT_AWIDTH-1 downto 0);
signal oport_ce : std_logic_vector(C_FACTOR-1 downto 0);
signal oport_din : std_logic_vector(C_CONV_DWIDTH*C_FACTOR-1 downto 0);
signal oport_dout : std_logic_vector(C_CONV_DWIDTH*C_FACTOR-1 downto 0);
begin
ONLY_ONE_BANK : if (C_FACTOR = 1) generate
begin
oport_ce(0) <= conv_ce;
iport_addr <= ap_arg_buffer & ap_arg_addr;
oport_addr <= conv_buffer & conv_addr;
conv_data <= oport_dout;
end generate ONLY_ONE_BANK;
SEVERAL_BANKS : if (C_FACTOR > 1) generate
constant OFFSET_WIDTH : integer := C_CONV_AWIDTH-BANK_AWIDTH;
constant BANK_MSB : integer := C_CONV_AWIDTH-1;
constant BANK_LSB : integer := BANK_MSB-BANK_AWIDTH+1;
constant OFFSET_MSB : integer := BANK_LSB-1;
constant OFFSET_LSB : integer := 0;
signal conv_bank : std_logic_vector(BANK_AWIDTH-1 downto 0);
signal conv_offset : std_logic_vector(OFFSET_WIDTH-1 downto 0);
signal conv_bank_r : std_logic_vector(BANK_AWIDTH-1 downto 0);
begin
iport_addr <= ap_arg_buffer & ap_arg_addr;
conv_bank <= conv_addr(BANK_MSB downto BANK_LSB);
conv_offset <= conv_addr(OFFSET_MSB downto OFFSET_LSB);
process(conv_ce, conv_bank)
begin
oport_ce <= (others => '0');
for i in 0 to C_FACTOR-1 loop
if(unsigned(conv_bank) = i) then
oport_ce(i) <= conv_ce;
end if;
end loop;
end process;
oport_addr <= conv_buffer & conv_offset;
-- Register part of address used to select the bank
process(clk)
begin
if(clk'event and clk = '1') then
if(conv_ce = '1') then
conv_bank_r <= conv_bank;
end if;
end if;
end process;
-- use conv_bank_r to select the mux at the output
process(conv_bank_r, oport_dout)
begin
conv_data <= (others => '0');
for i in 0 to C_FACTOR-1 loop
if(unsigned(conv_bank_r) = i) then
conv_data <= oport_dout(C_CONV_DWIDTH*(i+1)-1 downto C_CONV_DWIDTH*i);
end if;
end loop;
end process;
end generate SEVERAL_BANKS;
BANK_GEN : for i in 0 to C_FACTOR-1 generate
begin
MEM_I : entity axis_accelerator_adapter_v2_1_6.arg_mem_bank
generic map (
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => C_BRAM_TYPE,
C_IS_UNIDIR => 0,
C_IPORT_DWIDTH => C_ARG_WIDTH,
C_IPORT_AWIDTH => IPORT_AWIDTH,
C_OPORT_DWIDTH => C_CONV_DWIDTH,
C_OPORT_AWIDTH => OPORT_AWIDTH)
port map (
rst => ap_rst,
iport_clk => ap_clk,
iport_ce => ap_arg_ce,
iport_we => ap_arg_we,
iport_addr => iport_addr,
iport_din => ap_arg_din(C_ARG_WIDTH*(i+1)-1 downto C_ARG_WIDTH*i),
iport_dout => ap_arg_dout(C_ARG_WIDTH*(i+1)-1 downto C_ARG_WIDTH*i),
oport_clk => clk,
oport_ce => oport_ce(i),
oport_we => conv_we,
oport_addr => oport_addr,
oport_din => oport_din(C_CONV_DWIDTH*(i+1)-1 downto C_CONV_DWIDTH*i),
oport_dout => oport_dout(C_CONV_DWIDTH*(i+1)-1 downto C_CONV_DWIDTH*i));
end generate BANK_GEN;
end rtl;
| mit |
DacHt/CU_Droptest | component/work/CU_TOP/FPGA_UART/rtl/vhdl/core/components.vhd | 1 | 2651 |
library ieee;
use ieee.std_logic_1164.all;
package CU_TOP_FPGA_UART_components is
component CU_TOP_FPGA_UART_CoreUARTapb
GENERIC (
RX_LEGACY_MODE : integer := 0;
-- DEVICE FAMILY
FAMILY : integer := 15;
-- UART configuration parameters
TX_FIFO : integer := 0; -- 1 = with tx fifo, 0 = without tx fifo
RX_FIFO : integer := 0; -- 1 = with rx fifo, 0 = without rx fifo
BAUD_VALUE : integer := 0; -- Baud value is set only when fixed buad rate is selected
FIXEDMODE : integer := 0; -- fixed or programmable mode, 0: programmable; 1:fixed
PRG_BIT8 : integer := 0; -- This bit value is selected only when FIXEDMODE is set to 1
PRG_PARITY : integer := 0; -- This bit value is selected only when FIXEDMODE is set to 1
BAUD_VAL_FRCTN : integer := 0; -- 0 = +0.0, 1 = +0.125, 2 = +0.25, 3 = +0.375, 4 = +0.5, 5 = +0.625, 6 = +0.75, 7 = +0.875,
BAUD_VAL_FRCTN_EN : integer := 0 -- 1 = enable baud fraction, 0 = disable baud fraction
);
PORT (
-- Inputs and Outputs
-- APB signals
PCLK : IN std_logic; -- APB system clock
PRESETN : IN std_logic; -- APB system reset
PADDR : IN std_logic_vector(4 DOWNTO 0); -- Address
PSEL : IN std_logic; -- Peripheral select signal
PENABLE : IN std_logic; -- Enable (data valid strobe)
PWRITE : IN std_logic; -- Write/nRead signal
PWDATA : IN std_logic_vector(7 DOWNTO 0); -- 8 bit write data
PRDATA : OUT std_logic_vector(7 DOWNTO 0); -- 8 bit read data
-- AS: Added PREADY and PSLVERR
PREADY : OUT std_logic; -- APB READY signal (tied to 1)
PSLVERR : OUT std_logic; -- APB slave error signal (tied to 0)
-- transmit ready and receive full indicators
TXRDY : OUT std_logic;
RXRDY : OUT std_logic;
-- FLAGS
FRAMING_ERR : OUT std_logic;
PARITY_ERR : OUT std_logic;
OVERFLOW : OUT std_logic;
-- Serial receive and transmit data
RX : IN std_logic;
TX : OUT std_logic
);
end component;
end CU_TOP_FPGA_UART_components; | mit |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/vhls/set/solution/impl/ip/hdl/vhdl/set.vhd | 4 | 37773 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity set is
generic (
C_M_AXI_GMEM_ADDR_WIDTH : INTEGER := 32;
C_M_AXI_GMEM_ID_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_DATA_WIDTH : INTEGER := 32;
C_M_AXI_GMEM_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_BUSER_WIDTH : INTEGER := 1;
C_M_AXI_GMEM_CACHE_VALUE : INTEGER := 3;
C_M_AXI_GMEM_USER_VALUE : INTEGER := 0;
C_M_AXI_GMEM_PROT_VALUE : INTEGER := 0 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_gmem_AWVALID : OUT STD_LOGIC;
m_axi_gmem_AWREADY : IN STD_LOGIC;
m_axi_gmem_AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);
m_axi_gmem_AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_gmem_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_AWUSER_WIDTH-1 downto 0);
m_axi_gmem_WVALID : OUT STD_LOGIC;
m_axi_gmem_WREADY : IN STD_LOGIC;
m_axi_gmem_WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH-1 downto 0);
m_axi_gmem_WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH/8-1 downto 0);
m_axi_gmem_WLAST : OUT STD_LOGIC;
m_axi_gmem_WID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_WUSER_WIDTH-1 downto 0);
m_axi_gmem_ARVALID : OUT STD_LOGIC;
m_axi_gmem_ARREADY : IN STD_LOGIC;
m_axi_gmem_ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ADDR_WIDTH-1 downto 0);
m_axi_gmem_ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
m_axi_gmem_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_gmem_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_gmem_ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_GMEM_ARUSER_WIDTH-1 downto 0);
m_axi_gmem_RVALID : IN STD_LOGIC;
m_axi_gmem_RREADY : OUT STD_LOGIC;
m_axi_gmem_RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_DATA_WIDTH-1 downto 0);
m_axi_gmem_RLAST : IN STD_LOGIC;
m_axi_gmem_RID : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_RUSER_WIDTH-1 downto 0);
m_axi_gmem_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_BVALID : IN STD_LOGIC;
m_axi_gmem_BREADY : OUT STD_LOGIC;
m_axi_gmem_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_gmem_BID : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_ID_WIDTH-1 downto 0);
m_axi_gmem_BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_GMEM_BUSER_WIDTH-1 downto 0);
data : IN STD_LOGIC_VECTOR (31 downto 0);
key : IN STD_LOGIC_VECTOR (31 downto 0);
val_r : IN STD_LOGIC_VECTOR (31 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of set is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"set,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=8.500000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.437500,HLS_SYN_LAT=8,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=623,HLS_SYN_LUT=743}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_M_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_20 : BOOLEAN;
signal gmem_AWVALID : STD_LOGIC;
signal gmem_AWREADY : STD_LOGIC;
signal gmem_AWADDR : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_AWID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_AWLEN : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_AWSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_AWBURST : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_AWLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_AWCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWPROT : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_AWQOS : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWREGION : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_AWUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_WVALID : STD_LOGIC;
signal gmem_WREADY : STD_LOGIC;
signal gmem_WDATA : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_WSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_WLAST : STD_LOGIC;
signal gmem_WID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_WUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_ARVALID : STD_LOGIC;
signal gmem_ARREADY : STD_LOGIC;
signal gmem_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_ARID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_ARLEN : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_ARSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_ARBURST : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_ARLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_ARCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARPROT : STD_LOGIC_VECTOR (2 downto 0);
signal gmem_ARQOS : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARREGION : STD_LOGIC_VECTOR (3 downto 0);
signal gmem_ARUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RVALID : STD_LOGIC;
signal gmem_RREADY : STD_LOGIC;
signal gmem_RDATA : STD_LOGIC_VECTOR (31 downto 0);
signal gmem_RLAST : STD_LOGIC;
signal gmem_RID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RUSER : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_RRESP : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_BVALID : STD_LOGIC;
signal gmem_BREADY : STD_LOGIC;
signal gmem_BRESP : STD_LOGIC_VECTOR (1 downto 0);
signal gmem_BID : STD_LOGIC_VECTOR (0 downto 0);
signal gmem_BUSER : STD_LOGIC_VECTOR (0 downto 0);
signal set_gmem_m_axi_U_ap_dummy_ce : STD_LOGIC;
signal data1_reg_90 : STD_LOGIC_VECTOR (29 downto 0);
signal grp_set_assign_val_fu_58_ap_start : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_done : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_idle : STD_LOGIC;
signal grp_set_assign_val_fu_58_ap_ready : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_AWADDR : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWLEN : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWBURST : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWPROT : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWQOS : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWREGION : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_AWUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WDATA : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WSTRB : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WLAST : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_WID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_WUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_ARREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_ARADDR : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARLEN : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARSIZE : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARBURST : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARLOCK : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARCACHE : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARPROT : STD_LOGIC_VECTOR (2 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARQOS : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARREGION : STD_LOGIC_VECTOR (3 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_ARUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RDATA : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RLAST : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_RID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_RRESP : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BVALID : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_BREADY : STD_LOGIC;
signal grp_set_assign_val_fu_58_m_axi_dest_BRESP : STD_LOGIC_VECTOR (1 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BID : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_m_axi_dest_BUSER : STD_LOGIC_VECTOR (0 downto 0);
signal grp_set_assign_val_fu_58_data1 : STD_LOGIC_VECTOR (29 downto 0);
signal grp_set_assign_val_fu_58_tmp : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_src : STD_LOGIC_VECTOR (31 downto 0);
signal grp_set_assign_val_fu_58_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_230 : BOOLEAN;
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
component set_assign_val IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_dest_AWVALID : OUT STD_LOGIC;
m_axi_dest_AWREADY : IN STD_LOGIC;
m_axi_dest_AWADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_AWLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WVALID : OUT STD_LOGIC;
m_axi_dest_WREADY : IN STD_LOGIC;
m_axi_dest_WDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_WSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_WLAST : OUT STD_LOGIC;
m_axi_dest_WID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARVALID : OUT STD_LOGIC;
m_axi_dest_ARREADY : IN STD_LOGIC;
m_axi_dest_ARADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RVALID : IN STD_LOGIC;
m_axi_dest_RREADY : OUT STD_LOGIC;
m_axi_dest_RDATA : IN STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_RLAST : IN STD_LOGIC;
m_axi_dest_RID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RUSER : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BVALID : IN STD_LOGIC;
m_axi_dest_BREADY : OUT STD_LOGIC;
m_axi_dest_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_BUSER : IN STD_LOGIC_VECTOR (0 downto 0);
data1 : IN STD_LOGIC_VECTOR (29 downto 0);
tmp : IN STD_LOGIC_VECTOR (31 downto 0);
src : IN STD_LOGIC_VECTOR (31 downto 0) );
end component;
component set_gmem_m_axi IS
generic (
USER_DW : INTEGER;
USER_AW : INTEGER;
USER_MAXREQS : INTEGER;
C_M_AXI_ID_WIDTH : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_AWUSER_WIDTH : INTEGER;
C_M_AXI_ARUSER_WIDTH : INTEGER;
C_M_AXI_WUSER_WIDTH : INTEGER;
C_M_AXI_RUSER_WIDTH : INTEGER;
C_M_AXI_BUSER_WIDTH : INTEGER;
C_USER_VALUE : INTEGER;
C_PROT_VALUE : INTEGER;
C_CACHE_VALUE : INTEGER );
port (
AWVALID : OUT STD_LOGIC;
AWREADY : IN STD_LOGIC;
AWADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
AWID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
AWLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
AWUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_AWUSER_WIDTH-1 downto 0);
WVALID : OUT STD_LOGIC;
WREADY : IN STD_LOGIC;
WDATA : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : OUT STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : OUT STD_LOGIC;
WID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
WUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_WUSER_WIDTH-1 downto 0);
ARVALID : OUT STD_LOGIC;
ARREADY : IN STD_LOGIC;
ARADDR : OUT STD_LOGIC_VECTOR (C_M_AXI_ADDR_WIDTH-1 downto 0);
ARID : OUT STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
ARLEN : OUT STD_LOGIC_VECTOR (7 downto 0);
ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
ARUSER : OUT STD_LOGIC_VECTOR (C_M_AXI_ARUSER_WIDTH-1 downto 0);
RVALID : IN STD_LOGIC;
RREADY : OUT STD_LOGIC;
RDATA : IN STD_LOGIC_VECTOR (C_M_AXI_DATA_WIDTH-1 downto 0);
RLAST : IN STD_LOGIC;
RID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
RUSER : IN STD_LOGIC_VECTOR (C_M_AXI_RUSER_WIDTH-1 downto 0);
RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BVALID : IN STD_LOGIC;
BREADY : OUT STD_LOGIC;
BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
BID : IN STD_LOGIC_VECTOR (C_M_AXI_ID_WIDTH-1 downto 0);
BUSER : IN STD_LOGIC_VECTOR (C_M_AXI_BUSER_WIDTH-1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
I_ARVALID : IN STD_LOGIC;
I_ARREADY : OUT STD_LOGIC;
I_ARADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARID : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_ARSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_ARPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_ARUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_ARBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_ARREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_RVALID : OUT STD_LOGIC;
I_RREADY : IN STD_LOGIC;
I_RDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
I_RID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
I_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_RLAST : OUT STD_LOGIC;
I_AWVALID : IN STD_LOGIC;
I_AWREADY : OUT STD_LOGIC;
I_AWADDR : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWID : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWLEN : IN STD_LOGIC_VECTOR (31 downto 0);
I_AWSIZE : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWLOCK : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWCACHE : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWQOS : IN STD_LOGIC_VECTOR (3 downto 0);
I_AWPROT : IN STD_LOGIC_VECTOR (2 downto 0);
I_AWUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_AWBURST : IN STD_LOGIC_VECTOR (1 downto 0);
I_AWREGION : IN STD_LOGIC_VECTOR (3 downto 0);
I_WVALID : IN STD_LOGIC;
I_WREADY : OUT STD_LOGIC;
I_WDATA : IN STD_LOGIC_VECTOR (31 downto 0);
I_WID : IN STD_LOGIC_VECTOR (0 downto 0);
I_WUSER : IN STD_LOGIC_VECTOR (0 downto 0);
I_WLAST : IN STD_LOGIC;
I_WSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
I_BVALID : OUT STD_LOGIC;
I_BREADY : IN STD_LOGIC;
I_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
I_BID : OUT STD_LOGIC_VECTOR (0 downto 0);
I_BUSER : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
begin
set_gmem_m_axi_U : component set_gmem_m_axi
generic map (
USER_DW => 32,
USER_AW => 32,
USER_MAXREQS => 5,
C_M_AXI_ID_WIDTH => C_M_AXI_GMEM_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_GMEM_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_GMEM_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_GMEM_AWUSER_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_GMEM_ARUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_GMEM_WUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_GMEM_RUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_GMEM_BUSER_WIDTH,
C_USER_VALUE => C_M_AXI_GMEM_USER_VALUE,
C_PROT_VALUE => C_M_AXI_GMEM_PROT_VALUE,
C_CACHE_VALUE => C_M_AXI_GMEM_CACHE_VALUE)
port map (
AWVALID => m_axi_gmem_AWVALID,
AWREADY => m_axi_gmem_AWREADY,
AWADDR => m_axi_gmem_AWADDR,
AWID => m_axi_gmem_AWID,
AWLEN => m_axi_gmem_AWLEN,
AWSIZE => m_axi_gmem_AWSIZE,
AWBURST => m_axi_gmem_AWBURST,
AWLOCK => m_axi_gmem_AWLOCK,
AWCACHE => m_axi_gmem_AWCACHE,
AWPROT => m_axi_gmem_AWPROT,
AWQOS => m_axi_gmem_AWQOS,
AWREGION => m_axi_gmem_AWREGION,
AWUSER => m_axi_gmem_AWUSER,
WVALID => m_axi_gmem_WVALID,
WREADY => m_axi_gmem_WREADY,
WDATA => m_axi_gmem_WDATA,
WSTRB => m_axi_gmem_WSTRB,
WLAST => m_axi_gmem_WLAST,
WID => m_axi_gmem_WID,
WUSER => m_axi_gmem_WUSER,
ARVALID => m_axi_gmem_ARVALID,
ARREADY => m_axi_gmem_ARREADY,
ARADDR => m_axi_gmem_ARADDR,
ARID => m_axi_gmem_ARID,
ARLEN => m_axi_gmem_ARLEN,
ARSIZE => m_axi_gmem_ARSIZE,
ARBURST => m_axi_gmem_ARBURST,
ARLOCK => m_axi_gmem_ARLOCK,
ARCACHE => m_axi_gmem_ARCACHE,
ARPROT => m_axi_gmem_ARPROT,
ARQOS => m_axi_gmem_ARQOS,
ARREGION => m_axi_gmem_ARREGION,
ARUSER => m_axi_gmem_ARUSER,
RVALID => m_axi_gmem_RVALID,
RREADY => m_axi_gmem_RREADY,
RDATA => m_axi_gmem_RDATA,
RLAST => m_axi_gmem_RLAST,
RID => m_axi_gmem_RID,
RUSER => m_axi_gmem_RUSER,
RRESP => m_axi_gmem_RRESP,
BVALID => m_axi_gmem_BVALID,
BREADY => m_axi_gmem_BREADY,
BRESP => m_axi_gmem_BRESP,
BID => m_axi_gmem_BID,
BUSER => m_axi_gmem_BUSER,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => set_gmem_m_axi_U_ap_dummy_ce,
I_ARVALID => gmem_ARVALID,
I_ARREADY => gmem_ARREADY,
I_ARADDR => gmem_ARADDR,
I_ARID => gmem_ARID,
I_ARLEN => gmem_ARLEN,
I_ARSIZE => gmem_ARSIZE,
I_ARLOCK => gmem_ARLOCK,
I_ARCACHE => gmem_ARCACHE,
I_ARQOS => gmem_ARQOS,
I_ARPROT => gmem_ARPROT,
I_ARUSER => gmem_ARUSER,
I_ARBURST => gmem_ARBURST,
I_ARREGION => gmem_ARREGION,
I_RVALID => gmem_RVALID,
I_RREADY => gmem_RREADY,
I_RDATA => gmem_RDATA,
I_RID => gmem_RID,
I_RUSER => gmem_RUSER,
I_RRESP => gmem_RRESP,
I_RLAST => gmem_RLAST,
I_AWVALID => gmem_AWVALID,
I_AWREADY => gmem_AWREADY,
I_AWADDR => gmem_AWADDR,
I_AWID => gmem_AWID,
I_AWLEN => gmem_AWLEN,
I_AWSIZE => gmem_AWSIZE,
I_AWLOCK => gmem_AWLOCK,
I_AWCACHE => gmem_AWCACHE,
I_AWQOS => gmem_AWQOS,
I_AWPROT => gmem_AWPROT,
I_AWUSER => gmem_AWUSER,
I_AWBURST => gmem_AWBURST,
I_AWREGION => gmem_AWREGION,
I_WVALID => gmem_WVALID,
I_WREADY => gmem_WREADY,
I_WDATA => gmem_WDATA,
I_WID => gmem_WID,
I_WUSER => gmem_WUSER,
I_WLAST => gmem_WLAST,
I_WSTRB => gmem_WSTRB,
I_BVALID => gmem_BVALID,
I_BREADY => gmem_BREADY,
I_BRESP => gmem_BRESP,
I_BID => gmem_BID,
I_BUSER => gmem_BUSER);
grp_set_assign_val_fu_58 : component set_assign_val
port map (
ap_clk => ap_clk,
ap_rst => ap_rst_n_inv,
ap_start => grp_set_assign_val_fu_58_ap_start,
ap_done => grp_set_assign_val_fu_58_ap_done,
ap_idle => grp_set_assign_val_fu_58_ap_idle,
ap_ready => grp_set_assign_val_fu_58_ap_ready,
m_axi_dest_AWVALID => grp_set_assign_val_fu_58_m_axi_dest_AWVALID,
m_axi_dest_AWREADY => grp_set_assign_val_fu_58_m_axi_dest_AWREADY,
m_axi_dest_AWADDR => grp_set_assign_val_fu_58_m_axi_dest_AWADDR,
m_axi_dest_AWID => grp_set_assign_val_fu_58_m_axi_dest_AWID,
m_axi_dest_AWLEN => grp_set_assign_val_fu_58_m_axi_dest_AWLEN,
m_axi_dest_AWSIZE => grp_set_assign_val_fu_58_m_axi_dest_AWSIZE,
m_axi_dest_AWBURST => grp_set_assign_val_fu_58_m_axi_dest_AWBURST,
m_axi_dest_AWLOCK => grp_set_assign_val_fu_58_m_axi_dest_AWLOCK,
m_axi_dest_AWCACHE => grp_set_assign_val_fu_58_m_axi_dest_AWCACHE,
m_axi_dest_AWPROT => grp_set_assign_val_fu_58_m_axi_dest_AWPROT,
m_axi_dest_AWQOS => grp_set_assign_val_fu_58_m_axi_dest_AWQOS,
m_axi_dest_AWREGION => grp_set_assign_val_fu_58_m_axi_dest_AWREGION,
m_axi_dest_AWUSER => grp_set_assign_val_fu_58_m_axi_dest_AWUSER,
m_axi_dest_WVALID => grp_set_assign_val_fu_58_m_axi_dest_WVALID,
m_axi_dest_WREADY => grp_set_assign_val_fu_58_m_axi_dest_WREADY,
m_axi_dest_WDATA => grp_set_assign_val_fu_58_m_axi_dest_WDATA,
m_axi_dest_WSTRB => grp_set_assign_val_fu_58_m_axi_dest_WSTRB,
m_axi_dest_WLAST => grp_set_assign_val_fu_58_m_axi_dest_WLAST,
m_axi_dest_WID => grp_set_assign_val_fu_58_m_axi_dest_WID,
m_axi_dest_WUSER => grp_set_assign_val_fu_58_m_axi_dest_WUSER,
m_axi_dest_ARVALID => grp_set_assign_val_fu_58_m_axi_dest_ARVALID,
m_axi_dest_ARREADY => grp_set_assign_val_fu_58_m_axi_dest_ARREADY,
m_axi_dest_ARADDR => grp_set_assign_val_fu_58_m_axi_dest_ARADDR,
m_axi_dest_ARID => grp_set_assign_val_fu_58_m_axi_dest_ARID,
m_axi_dest_ARLEN => grp_set_assign_val_fu_58_m_axi_dest_ARLEN,
m_axi_dest_ARSIZE => grp_set_assign_val_fu_58_m_axi_dest_ARSIZE,
m_axi_dest_ARBURST => grp_set_assign_val_fu_58_m_axi_dest_ARBURST,
m_axi_dest_ARLOCK => grp_set_assign_val_fu_58_m_axi_dest_ARLOCK,
m_axi_dest_ARCACHE => grp_set_assign_val_fu_58_m_axi_dest_ARCACHE,
m_axi_dest_ARPROT => grp_set_assign_val_fu_58_m_axi_dest_ARPROT,
m_axi_dest_ARQOS => grp_set_assign_val_fu_58_m_axi_dest_ARQOS,
m_axi_dest_ARREGION => grp_set_assign_val_fu_58_m_axi_dest_ARREGION,
m_axi_dest_ARUSER => grp_set_assign_val_fu_58_m_axi_dest_ARUSER,
m_axi_dest_RVALID => grp_set_assign_val_fu_58_m_axi_dest_RVALID,
m_axi_dest_RREADY => grp_set_assign_val_fu_58_m_axi_dest_RREADY,
m_axi_dest_RDATA => grp_set_assign_val_fu_58_m_axi_dest_RDATA,
m_axi_dest_RLAST => grp_set_assign_val_fu_58_m_axi_dest_RLAST,
m_axi_dest_RID => grp_set_assign_val_fu_58_m_axi_dest_RID,
m_axi_dest_RUSER => grp_set_assign_val_fu_58_m_axi_dest_RUSER,
m_axi_dest_RRESP => grp_set_assign_val_fu_58_m_axi_dest_RRESP,
m_axi_dest_BVALID => grp_set_assign_val_fu_58_m_axi_dest_BVALID,
m_axi_dest_BREADY => grp_set_assign_val_fu_58_m_axi_dest_BREADY,
m_axi_dest_BRESP => grp_set_assign_val_fu_58_m_axi_dest_BRESP,
m_axi_dest_BID => grp_set_assign_val_fu_58_m_axi_dest_BID,
m_axi_dest_BUSER => grp_set_assign_val_fu_58_m_axi_dest_BUSER,
data1 => grp_set_assign_val_fu_58_data1,
tmp => grp_set_assign_val_fu_58_tmp,
src => grp_set_assign_val_fu_58_src);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_set_assign_val_fu_58_ap_start_ap_start_reg assign process. --
grp_set_assign_val_fu_58_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_set_assign_val_fu_58_ap_ready)) then
grp_set_assign_val_fu_58_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
data1_reg_90 <= data(31 downto 2);
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, grp_set_assign_val_fu_58_ap_done)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(grp_set_assign_val_fu_58_ap_done, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(grp_set_assign_val_fu_58_ap_done, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_logic_0 = grp_set_assign_val_fu_58_ap_done)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= ap_const_lv32_0;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_20 assign process. --
ap_sig_bdd_20_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_20 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_230 assign process. --
ap_sig_bdd_230_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_230 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_20)
begin
if (ap_sig_bdd_20) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_230)
begin
if (ap_sig_bdd_230) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
gmem_ARADDR <= ap_const_lv32_0;
gmem_ARBURST <= ap_const_lv2_0;
gmem_ARCACHE <= ap_const_lv4_0;
gmem_ARID <= ap_const_lv1_0;
gmem_ARLEN <= ap_const_lv32_0;
gmem_ARLOCK <= ap_const_lv2_0;
gmem_ARPROT <= ap_const_lv3_0;
gmem_ARQOS <= ap_const_lv4_0;
gmem_ARREGION <= ap_const_lv4_0;
gmem_ARSIZE <= ap_const_lv3_0;
gmem_ARUSER <= ap_const_lv1_0;
gmem_ARVALID <= ap_const_logic_0;
gmem_AWADDR <= grp_set_assign_val_fu_58_m_axi_dest_AWADDR;
gmem_AWBURST <= grp_set_assign_val_fu_58_m_axi_dest_AWBURST;
gmem_AWCACHE <= grp_set_assign_val_fu_58_m_axi_dest_AWCACHE;
gmem_AWID <= grp_set_assign_val_fu_58_m_axi_dest_AWID;
gmem_AWLEN <= grp_set_assign_val_fu_58_m_axi_dest_AWLEN;
gmem_AWLOCK <= grp_set_assign_val_fu_58_m_axi_dest_AWLOCK;
gmem_AWPROT <= grp_set_assign_val_fu_58_m_axi_dest_AWPROT;
gmem_AWQOS <= grp_set_assign_val_fu_58_m_axi_dest_AWQOS;
gmem_AWREGION <= grp_set_assign_val_fu_58_m_axi_dest_AWREGION;
gmem_AWSIZE <= grp_set_assign_val_fu_58_m_axi_dest_AWSIZE;
gmem_AWUSER <= grp_set_assign_val_fu_58_m_axi_dest_AWUSER;
-- gmem_AWVALID assign process. --
gmem_AWVALID_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_AWVALID, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_AWVALID <= grp_set_assign_val_fu_58_m_axi_dest_AWVALID;
else
gmem_AWVALID <= ap_const_logic_0;
end if;
end process;
-- gmem_BREADY assign process. --
gmem_BREADY_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_BREADY, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_BREADY <= grp_set_assign_val_fu_58_m_axi_dest_BREADY;
else
gmem_BREADY <= ap_const_logic_0;
end if;
end process;
gmem_RREADY <= ap_const_logic_0;
gmem_WDATA <= grp_set_assign_val_fu_58_m_axi_dest_WDATA;
gmem_WID <= grp_set_assign_val_fu_58_m_axi_dest_WID;
gmem_WLAST <= grp_set_assign_val_fu_58_m_axi_dest_WLAST;
gmem_WSTRB <= grp_set_assign_val_fu_58_m_axi_dest_WSTRB;
gmem_WUSER <= grp_set_assign_val_fu_58_m_axi_dest_WUSER;
-- gmem_WVALID assign process. --
gmem_WVALID_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, grp_set_assign_val_fu_58_m_axi_dest_WVALID, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1))) then
gmem_WVALID <= grp_set_assign_val_fu_58_m_axi_dest_WVALID;
else
gmem_WVALID <= ap_const_logic_0;
end if;
end process;
grp_set_assign_val_fu_58_ap_start <= grp_set_assign_val_fu_58_ap_start_ap_start_reg;
grp_set_assign_val_fu_58_data1 <= data1_reg_90;
grp_set_assign_val_fu_58_m_axi_dest_ARREADY <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_AWREADY <= gmem_AWREADY;
grp_set_assign_val_fu_58_m_axi_dest_BID <= gmem_BID;
grp_set_assign_val_fu_58_m_axi_dest_BRESP <= gmem_BRESP;
grp_set_assign_val_fu_58_m_axi_dest_BUSER <= gmem_BUSER;
grp_set_assign_val_fu_58_m_axi_dest_BVALID <= gmem_BVALID;
grp_set_assign_val_fu_58_m_axi_dest_RDATA <= ap_const_lv32_0;
grp_set_assign_val_fu_58_m_axi_dest_RID <= ap_const_lv1_0;
grp_set_assign_val_fu_58_m_axi_dest_RLAST <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_RRESP <= ap_const_lv2_0;
grp_set_assign_val_fu_58_m_axi_dest_RUSER <= ap_const_lv1_0;
grp_set_assign_val_fu_58_m_axi_dest_RVALID <= ap_const_logic_0;
grp_set_assign_val_fu_58_m_axi_dest_WREADY <= gmem_WREADY;
grp_set_assign_val_fu_58_src <= val_r;
grp_set_assign_val_fu_58_tmp <= key;
set_gmem_m_axi_U_ap_dummy_ce <= ap_const_logic_1;
end behav;
| mit |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_set_0_if_0/sim/zc702_set_0_if_0.vhd | 1 | 50762 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
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-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axis_accelerator_adapter:2.1
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axis_accelerator_adapter_v2_1_6;
USE axis_accelerator_adapter_v2_1_6.axis_accelerator_adapter;
ENTITY zc702_set_0_if_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : OUT STD_LOGIC;
ap_start : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_continue : OUT STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_iscalar_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
interrupt : OUT STD_LOGIC
);
END zc702_set_0_if_0;
ARCHITECTURE zc702_set_0_if_0_arch OF zc702_set_0_if_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_set_0_if_0_arch: ARCHITECTURE IS "yes";
COMPONENT axis_accelerator_adapter IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_AP_ADAPTER_ID : INTEGER;
C_N_INPUT_ARGS : INTEGER;
C_N_OUTPUT_ARGS : INTEGER;
C_S_AXIS_TDATA_WIDTH : INTEGER;
C_S_AXIS_TUSER_WIDTH : INTEGER;
C_S_AXIS_TID_WIDTH : INTEGER;
C_S_AXIS_TDEST_WIDTH : INTEGER;
C_AP_IARG_TYPE : STD_LOGIC_VECTOR;
C_AP_IARG_MB_DEPTH : STD_LOGIC_VECTOR;
C_AP_IARG_WIDTH : STD_LOGIC_VECTOR;
C_AP_IARG_N_DIM : STD_LOGIC_VECTOR;
C_AP_IARG_DIM_1 : STD_LOGIC_VECTOR;
C_AP_IARG_DIM_2 : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_TYPE : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_FACTOR : STD_LOGIC_VECTOR;
C_AP_IARG_FORMAT_DIM : STD_LOGIC_VECTOR;
C_AP_IARG_0_DWIDTH : INTEGER;
C_AP_IARG_1_DWIDTH : INTEGER;
C_AP_IARG_2_DWIDTH : INTEGER;
C_AP_IARG_3_DWIDTH : INTEGER;
C_AP_IARG_4_DWIDTH : INTEGER;
C_AP_IARG_5_DWIDTH : INTEGER;
C_AP_IARG_6_DWIDTH : INTEGER;
C_AP_IARG_7_DWIDTH : INTEGER;
C_M_AXIS_TDATA_WIDTH : INTEGER;
C_M_AXIS_TUSER_WIDTH : INTEGER;
C_M_AXIS_TID_WIDTH : INTEGER;
C_M_AXIS_TDEST_WIDTH : INTEGER;
C_AP_OARG_TYPE : STD_LOGIC_VECTOR;
C_AP_OARG_MB_DEPTH : STD_LOGIC_VECTOR;
C_AP_OARG_WIDTH : STD_LOGIC_VECTOR;
C_AP_OARG_N_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_DIM_1 : STD_LOGIC_VECTOR;
C_AP_OARG_DIM_2 : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_TYPE : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_FACTOR : STD_LOGIC_VECTOR;
C_AP_OARG_FORMAT_DIM : STD_LOGIC_VECTOR;
C_AP_OARG_0_DWIDTH : INTEGER;
C_AP_OARG_1_DWIDTH : INTEGER;
C_AP_OARG_2_DWIDTH : INTEGER;
C_AP_OARG_3_DWIDTH : INTEGER;
C_AP_OARG_4_DWIDTH : INTEGER;
C_AP_OARG_5_DWIDTH : INTEGER;
C_AP_OARG_6_DWIDTH : INTEGER;
C_AP_OARG_7_DWIDTH : INTEGER;
C_N_INOUT_SCALARS : INTEGER;
C_N_INPUT_SCALARS : INTEGER;
C_INPUT_SCALAR_DWIDTH : STD_LOGIC_VECTOR;
C_INPUT_SCALAR_MODE : STD_LOGIC_VECTOR;
C_OUTPUT_SCALAR_MODE : STD_LOGIC_VECTOR;
C_AP_ISCALAR_DOUT_WIDTH : INTEGER;
C_AP_ISCALAR_IO_DOUT_WIDTH : INTEGER;
C_INPUT_SCALAR_0_WIDTH : INTEGER;
C_INPUT_SCALAR_1_WIDTH : INTEGER;
C_INPUT_SCALAR_2_WIDTH : INTEGER;
C_INPUT_SCALAR_3_WIDTH : INTEGER;
C_INPUT_SCALAR_4_WIDTH : INTEGER;
C_INPUT_SCALAR_5_WIDTH : INTEGER;
C_INPUT_SCALAR_6_WIDTH : INTEGER;
C_INPUT_SCALAR_7_WIDTH : INTEGER;
C_INPUT_SCALAR_8_WIDTH : INTEGER;
C_INPUT_SCALAR_9_WIDTH : INTEGER;
C_INPUT_SCALAR_10_WIDTH : INTEGER;
C_INPUT_SCALAR_11_WIDTH : INTEGER;
C_INPUT_SCALAR_12_WIDTH : INTEGER;
C_INPUT_SCALAR_13_WIDTH : INTEGER;
C_INPUT_SCALAR_14_WIDTH : INTEGER;
C_INPUT_SCALAR_15_WIDTH : INTEGER;
C_OUTPUT_SCALAR_0_WIDTH : INTEGER;
C_OUTPUT_SCALAR_1_WIDTH : INTEGER;
C_OUTPUT_SCALAR_2_WIDTH : INTEGER;
C_OUTPUT_SCALAR_3_WIDTH : INTEGER;
C_OUTPUT_SCALAR_4_WIDTH : INTEGER;
C_OUTPUT_SCALAR_5_WIDTH : INTEGER;
C_OUTPUT_SCALAR_6_WIDTH : INTEGER;
C_OUTPUT_SCALAR_7_WIDTH : INTEGER;
C_OUTPUT_SCALAR_8_WIDTH : INTEGER;
C_OUTPUT_SCALAR_9_WIDTH : INTEGER;
C_OUTPUT_SCALAR_10_WIDTH : INTEGER;
C_OUTPUT_SCALAR_11_WIDTH : INTEGER;
C_OUTPUT_SCALAR_12_WIDTH : INTEGER;
C_OUTPUT_SCALAR_13_WIDTH : INTEGER;
C_OUTPUT_SCALAR_14_WIDTH : INTEGER;
C_OUTPUT_SCALAR_15_WIDTH : INTEGER;
C_N_OUTPUT_SCALARS : INTEGER;
C_OUTPUT_SCALAR_DWIDTH : STD_LOGIC_VECTOR;
C_AP_OSCALAR_DIN_WIDTH : INTEGER;
C_AP_OSCALAR_IO_DIN_WIDTH : INTEGER;
C_ENABLE_STREAM_CLK : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_S_AXIS_HAS_TSTRB : INTEGER;
C_S_AXIS_HAS_TKEEP : INTEGER;
C_NONE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axis_aclk : IN STD_LOGIC;
s_axis_aresetn : IN STD_LOGIC;
s_axis_0_aclk : IN STD_LOGIC;
s_axis_0_aresetn : IN STD_LOGIC;
s_axis_0_tvalid : IN STD_LOGIC;
s_axis_0_tready : OUT STD_LOGIC;
s_axis_0_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_0_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_0_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_0_tlast : IN STD_LOGIC;
s_axis_0_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_0_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_0_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_aclk : IN STD_LOGIC;
s_axis_1_aresetn : IN STD_LOGIC;
s_axis_1_tvalid : IN STD_LOGIC;
s_axis_1_tready : OUT STD_LOGIC;
s_axis_1_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_1_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_1_tlast : IN STD_LOGIC;
s_axis_1_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_1_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_1_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_aclk : IN STD_LOGIC;
s_axis_2_aresetn : IN STD_LOGIC;
s_axis_2_tvalid : IN STD_LOGIC;
s_axis_2_tready : OUT STD_LOGIC;
s_axis_2_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_2_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_2_tlast : IN STD_LOGIC;
s_axis_2_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_2_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_2_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_aclk : IN STD_LOGIC;
s_axis_3_aresetn : IN STD_LOGIC;
s_axis_3_tvalid : IN STD_LOGIC;
s_axis_3_tready : OUT STD_LOGIC;
s_axis_3_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_3_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_3_tlast : IN STD_LOGIC;
s_axis_3_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_3_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_3_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_aclk : IN STD_LOGIC;
s_axis_4_aresetn : IN STD_LOGIC;
s_axis_4_tvalid : IN STD_LOGIC;
s_axis_4_tready : OUT STD_LOGIC;
s_axis_4_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_4_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_4_tlast : IN STD_LOGIC;
s_axis_4_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_4_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_4_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_aclk : IN STD_LOGIC;
s_axis_5_aresetn : IN STD_LOGIC;
s_axis_5_tvalid : IN STD_LOGIC;
s_axis_5_tready : OUT STD_LOGIC;
s_axis_5_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_5_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_5_tlast : IN STD_LOGIC;
s_axis_5_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_5_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_5_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_aclk : IN STD_LOGIC;
s_axis_6_aresetn : IN STD_LOGIC;
s_axis_6_tvalid : IN STD_LOGIC;
s_axis_6_tready : OUT STD_LOGIC;
s_axis_6_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_6_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_6_tlast : IN STD_LOGIC;
s_axis_6_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_6_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_6_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_aclk : IN STD_LOGIC;
s_axis_7_aresetn : IN STD_LOGIC;
s_axis_7_tvalid : IN STD_LOGIC;
s_axis_7_tready : OUT STD_LOGIC;
s_axis_7_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_7_tstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_tkeep : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_7_tlast : IN STD_LOGIC;
s_axis_7_tid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_7_tdest : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_7_tuser : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ap_iarg_0_clk : IN STD_LOGIC;
ap_iarg_0_rst : IN STD_LOGIC;
ap_iarg_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_0_ce : IN STD_LOGIC;
ap_iarg_0_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_clk : IN STD_LOGIC;
ap_iarg_1_rst : IN STD_LOGIC;
ap_iarg_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_ce : IN STD_LOGIC;
ap_iarg_1_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_clk : IN STD_LOGIC;
ap_iarg_2_rst : IN STD_LOGIC;
ap_iarg_2_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_ce : IN STD_LOGIC;
ap_iarg_2_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_clk : IN STD_LOGIC;
ap_iarg_3_rst : IN STD_LOGIC;
ap_iarg_3_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_ce : IN STD_LOGIC;
ap_iarg_3_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_clk : IN STD_LOGIC;
ap_iarg_4_rst : IN STD_LOGIC;
ap_iarg_4_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_ce : IN STD_LOGIC;
ap_iarg_4_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_clk : IN STD_LOGIC;
ap_iarg_5_rst : IN STD_LOGIC;
ap_iarg_5_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_ce : IN STD_LOGIC;
ap_iarg_5_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_clk : IN STD_LOGIC;
ap_iarg_6_rst : IN STD_LOGIC;
ap_iarg_6_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_ce : IN STD_LOGIC;
ap_iarg_6_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_clk : IN STD_LOGIC;
ap_iarg_7_rst : IN STD_LOGIC;
ap_iarg_7_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_ce : IN STD_LOGIC;
ap_iarg_7_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_iarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_0_read : IN STD_LOGIC;
ap_fifo_iarg_0_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_1_read : IN STD_LOGIC;
ap_fifo_iarg_1_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_2_read : IN STD_LOGIC;
ap_fifo_iarg_2_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_3_read : IN STD_LOGIC;
ap_fifo_iarg_3_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_4_read : IN STD_LOGIC;
ap_fifo_iarg_4_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_5_read : IN STD_LOGIC;
ap_fifo_iarg_5_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_6_read : IN STD_LOGIC;
ap_fifo_iarg_6_empty_n : OUT STD_LOGIC;
ap_fifo_iarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_iarg_7_read : IN STD_LOGIC;
ap_fifo_iarg_7_empty_n : OUT STD_LOGIC;
m_axis_aclk : IN STD_LOGIC;
m_axis_aresetn : IN STD_LOGIC;
m_axis_0_aclk : IN STD_LOGIC;
m_axis_0_aresetn : IN STD_LOGIC;
m_axis_0_tvalid : OUT STD_LOGIC;
m_axis_0_tready : IN STD_LOGIC;
m_axis_0_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_0_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_0_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_0_tlast : OUT STD_LOGIC;
m_axis_0_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_0_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_0_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_aclk : IN STD_LOGIC;
m_axis_1_aresetn : IN STD_LOGIC;
m_axis_1_tvalid : OUT STD_LOGIC;
m_axis_1_tready : IN STD_LOGIC;
m_axis_1_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_1_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_1_tlast : OUT STD_LOGIC;
m_axis_1_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_1_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_1_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_aclk : IN STD_LOGIC;
m_axis_2_aresetn : IN STD_LOGIC;
m_axis_2_tvalid : OUT STD_LOGIC;
m_axis_2_tready : IN STD_LOGIC;
m_axis_2_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_2_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_2_tlast : OUT STD_LOGIC;
m_axis_2_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_2_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_2_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_aclk : IN STD_LOGIC;
m_axis_3_aresetn : IN STD_LOGIC;
m_axis_3_tvalid : OUT STD_LOGIC;
m_axis_3_tready : IN STD_LOGIC;
m_axis_3_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_3_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_3_tlast : OUT STD_LOGIC;
m_axis_3_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_3_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_3_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_aclk : IN STD_LOGIC;
m_axis_4_aresetn : IN STD_LOGIC;
m_axis_4_tvalid : OUT STD_LOGIC;
m_axis_4_tready : IN STD_LOGIC;
m_axis_4_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_4_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_4_tlast : OUT STD_LOGIC;
m_axis_4_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_4_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_4_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_aclk : IN STD_LOGIC;
m_axis_5_aresetn : IN STD_LOGIC;
m_axis_5_tvalid : OUT STD_LOGIC;
m_axis_5_tready : IN STD_LOGIC;
m_axis_5_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_5_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_5_tlast : OUT STD_LOGIC;
m_axis_5_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_5_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_5_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_aclk : IN STD_LOGIC;
m_axis_6_aresetn : IN STD_LOGIC;
m_axis_6_tvalid : OUT STD_LOGIC;
m_axis_6_tready : IN STD_LOGIC;
m_axis_6_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_6_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_6_tlast : OUT STD_LOGIC;
m_axis_6_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_6_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_6_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_aclk : IN STD_LOGIC;
m_axis_7_aresetn : IN STD_LOGIC;
m_axis_7_tvalid : OUT STD_LOGIC;
m_axis_7_tready : IN STD_LOGIC;
m_axis_7_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_7_tstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_tkeep : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_7_tlast : OUT STD_LOGIC;
m_axis_7_tid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_7_tdest : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_7_tuser : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
ap_oarg_0_clk : IN STD_LOGIC;
ap_oarg_0_rst : IN STD_LOGIC;
ap_oarg_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_0_ce : IN STD_LOGIC;
ap_oarg_0_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_clk : IN STD_LOGIC;
ap_oarg_1_rst : IN STD_LOGIC;
ap_oarg_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_ce : IN STD_LOGIC;
ap_oarg_1_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_clk : IN STD_LOGIC;
ap_oarg_2_rst : IN STD_LOGIC;
ap_oarg_2_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_ce : IN STD_LOGIC;
ap_oarg_2_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_clk : IN STD_LOGIC;
ap_oarg_3_rst : IN STD_LOGIC;
ap_oarg_3_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_ce : IN STD_LOGIC;
ap_oarg_3_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_clk : IN STD_LOGIC;
ap_oarg_4_rst : IN STD_LOGIC;
ap_oarg_4_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_ce : IN STD_LOGIC;
ap_oarg_4_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_clk : IN STD_LOGIC;
ap_oarg_5_rst : IN STD_LOGIC;
ap_oarg_5_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_ce : IN STD_LOGIC;
ap_oarg_5_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_clk : IN STD_LOGIC;
ap_oarg_6_rst : IN STD_LOGIC;
ap_oarg_6_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_ce : IN STD_LOGIC;
ap_oarg_6_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_clk : IN STD_LOGIC;
ap_oarg_7_rst : IN STD_LOGIC;
ap_oarg_7_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_ce : IN STD_LOGIC;
ap_oarg_7_we : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ap_oarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oarg_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_0_write : IN STD_LOGIC;
ap_fifo_oarg_0_full_n : OUT STD_LOGIC;
ap_fifo_oarg_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_1_write : IN STD_LOGIC;
ap_fifo_oarg_1_full_n : OUT STD_LOGIC;
ap_fifo_oarg_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_2_write : IN STD_LOGIC;
ap_fifo_oarg_2_full_n : OUT STD_LOGIC;
ap_fifo_oarg_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_3_write : IN STD_LOGIC;
ap_fifo_oarg_3_full_n : OUT STD_LOGIC;
ap_fifo_oarg_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_4_write : IN STD_LOGIC;
ap_fifo_oarg_4_full_n : OUT STD_LOGIC;
ap_fifo_oarg_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_5_write : IN STD_LOGIC;
ap_fifo_oarg_5_full_n : OUT STD_LOGIC;
ap_fifo_oarg_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_6_write : IN STD_LOGIC;
ap_fifo_oarg_6_full_n : OUT STD_LOGIC;
ap_fifo_oarg_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_fifo_oarg_7_write : IN STD_LOGIC;
ap_fifo_oarg_7_full_n : OUT STD_LOGIC;
aclk : IN STD_LOGIC;
aresetn : OUT STD_LOGIC;
ap_start : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_continue : OUT STD_LOGIC;
ap_idle : IN STD_LOGIC;
ap_iscalar_0_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_1_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_2_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_3_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_4_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_5_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_6_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_7_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_8_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_9_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_10_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_11_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_12_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_13_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_14_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_iscalar_15_dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_1_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_2_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_3_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_4_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_5_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_6_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_7_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_8_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_9_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_10_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_11_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_12_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_13_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_14_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_15_din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ap_oscalar_0_vld : IN STD_LOGIC;
ap_oscalar_1_vld : IN STD_LOGIC;
ap_oscalar_2_vld : IN STD_LOGIC;
ap_oscalar_3_vld : IN STD_LOGIC;
ap_oscalar_4_vld : IN STD_LOGIC;
ap_oscalar_5_vld : IN STD_LOGIC;
ap_oscalar_6_vld : IN STD_LOGIC;
ap_oscalar_7_vld : IN STD_LOGIC;
ap_oscalar_8_vld : IN STD_LOGIC;
ap_oscalar_9_vld : IN STD_LOGIC;
ap_oscalar_10_vld : IN STD_LOGIC;
ap_oscalar_11_vld : IN STD_LOGIC;
ap_oscalar_12_vld : IN STD_LOGIC;
ap_oscalar_13_vld : IN STD_LOGIC;
ap_oscalar_14_vld : IN STD_LOGIC;
ap_oscalar_15_vld : IN STD_LOGIC;
ap_oscalar_0_ack : OUT STD_LOGIC;
ap_oscalar_1_ack : OUT STD_LOGIC;
ap_oscalar_2_ack : OUT STD_LOGIC;
ap_oscalar_3_ack : OUT STD_LOGIC;
ap_oscalar_4_ack : OUT STD_LOGIC;
ap_oscalar_5_ack : OUT STD_LOGIC;
ap_oscalar_6_ack : OUT STD_LOGIC;
ap_oscalar_7_ack : OUT STD_LOGIC;
ap_oscalar_8_ack : OUT STD_LOGIC;
ap_oscalar_9_ack : OUT STD_LOGIC;
ap_oscalar_10_ack : OUT STD_LOGIC;
ap_oscalar_11_ack : OUT STD_LOGIC;
ap_oscalar_12_ack : OUT STD_LOGIC;
ap_oscalar_13_ack : OUT STD_LOGIC;
ap_oscalar_14_ack : OUT STD_LOGIC;
ap_oscalar_15_ack : OUT STD_LOGIC;
ap_iscalar_0_ack : IN STD_LOGIC;
ap_iscalar_1_ack : IN STD_LOGIC;
ap_iscalar_2_ack : IN STD_LOGIC;
ap_iscalar_3_ack : IN STD_LOGIC;
ap_iscalar_4_ack : IN STD_LOGIC;
ap_iscalar_5_ack : IN STD_LOGIC;
ap_iscalar_6_ack : IN STD_LOGIC;
ap_iscalar_7_ack : IN STD_LOGIC;
ap_iscalar_8_ack : IN STD_LOGIC;
ap_iscalar_9_ack : IN STD_LOGIC;
ap_iscalar_10_ack : IN STD_LOGIC;
ap_iscalar_11_ack : IN STD_LOGIC;
ap_iscalar_12_ack : IN STD_LOGIC;
ap_iscalar_13_ack : IN STD_LOGIC;
ap_iscalar_14_ack : IN STD_LOGIC;
ap_iscalar_15_ack : IN STD_LOGIC;
ap_iscalar_0_vld : OUT STD_LOGIC;
ap_iscalar_1_vld : OUT STD_LOGIC;
ap_iscalar_2_vld : OUT STD_LOGIC;
ap_iscalar_3_vld : OUT STD_LOGIC;
ap_iscalar_4_vld : OUT STD_LOGIC;
ap_iscalar_5_vld : OUT STD_LOGIC;
ap_iscalar_6_vld : OUT STD_LOGIC;
ap_iscalar_7_vld : OUT STD_LOGIC;
ap_iscalar_8_vld : OUT STD_LOGIC;
ap_iscalar_9_vld : OUT STD_LOGIC;
ap_iscalar_10_vld : OUT STD_LOGIC;
ap_iscalar_11_vld : OUT STD_LOGIC;
ap_iscalar_12_vld : OUT STD_LOGIC;
ap_iscalar_13_vld : OUT STD_LOGIC;
ap_iscalar_14_vld : OUT STD_LOGIC;
ap_iscalar_15_vld : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC
);
END COMPONENT axis_accelerator_adapter;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF ap_start: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL start";
ATTRIBUTE X_INTERFACE_INFO OF ap_ready: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL ready";
ATTRIBUTE X_INTERFACE_INFO OF ap_done: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL done";
ATTRIBUTE X_INTERFACE_INFO OF ap_continue: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL continue";
ATTRIBUTE X_INTERFACE_INFO OF ap_idle: SIGNAL IS "xilinx.com:interface:acc_handshake:1.0 AP_CTRL idle";
ATTRIBUTE X_INTERFACE_INFO OF interrupt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axis_accelerator_adapter
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 13,
C_S_AXI_DATA_WIDTH => 32,
C_AP_ADAPTER_ID => 1,
C_N_INPUT_ARGS => 0,
C_N_OUTPUT_ARGS => 0,
C_S_AXIS_TDATA_WIDTH => 64,
C_S_AXIS_TUSER_WIDTH => 8,
C_S_AXIS_TID_WIDTH => 4,
C_S_AXIS_TDEST_WIDTH => 4,
C_AP_IARG_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_IARG_MB_DEPTH => X"0000000400000004000000040000000400000004000000040000000400000004",
C_AP_IARG_WIDTH => X"0000002000000020000000200000002000000020000000200000002000000020",
C_AP_IARG_N_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_DIM_1 => X"0000040000000400000004000000040000000400000004000000040000000400",
C_AP_IARG_DIM_2 => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_FORMAT_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_IARG_FORMAT_FACTOR => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_FORMAT_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_IARG_0_DWIDTH => 32,
C_AP_IARG_1_DWIDTH => 32,
C_AP_IARG_2_DWIDTH => 32,
C_AP_IARG_3_DWIDTH => 32,
C_AP_IARG_4_DWIDTH => 32,
C_AP_IARG_5_DWIDTH => 32,
C_AP_IARG_6_DWIDTH => 32,
C_AP_IARG_7_DWIDTH => 32,
C_M_AXIS_TDATA_WIDTH => 64,
C_M_AXIS_TUSER_WIDTH => 8,
C_M_AXIS_TID_WIDTH => 4,
C_M_AXIS_TDEST_WIDTH => 4,
C_AP_OARG_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_OARG_MB_DEPTH => X"0000000400000004000000040000000400000004000000040000000400000004",
C_AP_OARG_WIDTH => X"0000002000000020000000200000002000000020000000200000002000000020",
C_AP_OARG_N_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_DIM => X"0000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000080000000001000000010000000100000008",
C_AP_OARG_DIM_1 => X"0000040000000400000004000000040000000400000004000000040000000400",
C_AP_OARG_DIM_2 => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_FORMAT_TYPE => X"0000000000000000000000000000000000000000000000000000000000000000",
C_AP_OARG_FORMAT_FACTOR => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_FORMAT_DIM => X"0000000100000001000000010000000100000001000000010000000100000001",
C_AP_OARG_0_DWIDTH => 32,
C_AP_OARG_1_DWIDTH => 32,
C_AP_OARG_2_DWIDTH => 32,
C_AP_OARG_3_DWIDTH => 32,
C_AP_OARG_4_DWIDTH => 32,
C_AP_OARG_5_DWIDTH => 32,
C_AP_OARG_6_DWIDTH => 32,
C_AP_OARG_7_DWIDTH => 32,
C_N_INOUT_SCALARS => 0,
C_N_INPUT_SCALARS => 3,
C_INPUT_SCALAR_DWIDTH => X"00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020",
C_INPUT_SCALAR_MODE => X"0000000000000000",
C_OUTPUT_SCALAR_MODE => X"0000000000000000",
C_AP_ISCALAR_DOUT_WIDTH => 96,
C_AP_ISCALAR_IO_DOUT_WIDTH => 32,
C_INPUT_SCALAR_0_WIDTH => 32,
C_INPUT_SCALAR_1_WIDTH => 32,
C_INPUT_SCALAR_2_WIDTH => 32,
C_INPUT_SCALAR_3_WIDTH => 32,
C_INPUT_SCALAR_4_WIDTH => 32,
C_INPUT_SCALAR_5_WIDTH => 32,
C_INPUT_SCALAR_6_WIDTH => 32,
C_INPUT_SCALAR_7_WIDTH => 32,
C_INPUT_SCALAR_8_WIDTH => 32,
C_INPUT_SCALAR_9_WIDTH => 32,
C_INPUT_SCALAR_10_WIDTH => 32,
C_INPUT_SCALAR_11_WIDTH => 32,
C_INPUT_SCALAR_12_WIDTH => 32,
C_INPUT_SCALAR_13_WIDTH => 32,
C_INPUT_SCALAR_14_WIDTH => 32,
C_INPUT_SCALAR_15_WIDTH => 32,
C_OUTPUT_SCALAR_0_WIDTH => 32,
C_OUTPUT_SCALAR_1_WIDTH => 32,
C_OUTPUT_SCALAR_2_WIDTH => 32,
C_OUTPUT_SCALAR_3_WIDTH => 32,
C_OUTPUT_SCALAR_4_WIDTH => 32,
C_OUTPUT_SCALAR_5_WIDTH => 32,
C_OUTPUT_SCALAR_6_WIDTH => 32,
C_OUTPUT_SCALAR_7_WIDTH => 32,
C_OUTPUT_SCALAR_8_WIDTH => 32,
C_OUTPUT_SCALAR_9_WIDTH => 32,
C_OUTPUT_SCALAR_10_WIDTH => 32,
C_OUTPUT_SCALAR_11_WIDTH => 32,
C_OUTPUT_SCALAR_12_WIDTH => 32,
C_OUTPUT_SCALAR_13_WIDTH => 32,
C_OUTPUT_SCALAR_14_WIDTH => 32,
C_OUTPUT_SCALAR_15_WIDTH => 32,
C_N_OUTPUT_SCALARS => 1,
C_OUTPUT_SCALAR_DWIDTH => X"00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020",
C_AP_OSCALAR_DIN_WIDTH => 32,
C_AP_OSCALAR_IO_DIN_WIDTH => 32,
C_ENABLE_STREAM_CLK => 0,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_S_AXIS_HAS_TSTRB => 0,
C_S_AXIS_HAS_TKEEP => 0,
C_NONE => 2
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axis_aclk => '0',
s_axis_aresetn => '0',
s_axis_0_aclk => '0',
s_axis_0_aresetn => '0',
s_axis_0_tvalid => '0',
s_axis_0_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_0_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_0_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_0_tlast => '0',
s_axis_0_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_0_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_0_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_aclk => '0',
s_axis_1_aresetn => '0',
s_axis_1_tvalid => '0',
s_axis_1_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_1_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_1_tlast => '0',
s_axis_1_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_1_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_1_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_aclk => '0',
s_axis_2_aresetn => '0',
s_axis_2_tvalid => '0',
s_axis_2_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_2_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_2_tlast => '0',
s_axis_2_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_2_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_2_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_aclk => '0',
s_axis_3_aresetn => '0',
s_axis_3_tvalid => '0',
s_axis_3_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_3_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_3_tlast => '0',
s_axis_3_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_3_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_3_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_aclk => '0',
s_axis_4_aresetn => '0',
s_axis_4_tvalid => '0',
s_axis_4_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_4_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_4_tlast => '0',
s_axis_4_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_4_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_4_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_aclk => '0',
s_axis_5_aresetn => '0',
s_axis_5_tvalid => '0',
s_axis_5_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_5_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_5_tlast => '0',
s_axis_5_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_5_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_5_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_aclk => '0',
s_axis_6_aresetn => '0',
s_axis_6_tvalid => '0',
s_axis_6_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_6_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_6_tlast => '0',
s_axis_6_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_6_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_6_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_aclk => '0',
s_axis_7_aresetn => '0',
s_axis_7_tvalid => '0',
s_axis_7_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_7_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_7_tlast => '0',
s_axis_7_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_7_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_7_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
ap_iarg_0_clk => '0',
ap_iarg_0_rst => '0',
ap_iarg_0_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_0_ce => '0',
ap_iarg_0_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_1_clk => '0',
ap_iarg_1_rst => '0',
ap_iarg_1_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_1_ce => '0',
ap_iarg_1_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_2_clk => '0',
ap_iarg_2_rst => '0',
ap_iarg_2_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_2_ce => '0',
ap_iarg_2_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_3_clk => '0',
ap_iarg_3_rst => '0',
ap_iarg_3_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_3_ce => '0',
ap_iarg_3_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_4_clk => '0',
ap_iarg_4_rst => '0',
ap_iarg_4_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_4_ce => '0',
ap_iarg_4_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_5_clk => '0',
ap_iarg_5_rst => '0',
ap_iarg_5_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_5_ce => '0',
ap_iarg_5_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_6_clk => '0',
ap_iarg_6_rst => '0',
ap_iarg_6_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_6_ce => '0',
ap_iarg_6_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_7_clk => '0',
ap_iarg_7_rst => '0',
ap_iarg_7_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_iarg_7_ce => '0',
ap_iarg_7_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_iarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_iarg_0_read => '0',
ap_fifo_iarg_1_read => '0',
ap_fifo_iarg_2_read => '0',
ap_fifo_iarg_3_read => '0',
ap_fifo_iarg_4_read => '0',
ap_fifo_iarg_5_read => '0',
ap_fifo_iarg_6_read => '0',
ap_fifo_iarg_7_read => '0',
m_axis_aclk => '0',
m_axis_aresetn => '0',
m_axis_0_aclk => '0',
m_axis_0_aresetn => '0',
m_axis_0_tready => '0',
m_axis_1_aclk => '0',
m_axis_1_aresetn => '0',
m_axis_1_tready => '0',
m_axis_2_aclk => '0',
m_axis_2_aresetn => '0',
m_axis_2_tready => '0',
m_axis_3_aclk => '0',
m_axis_3_aresetn => '0',
m_axis_3_tready => '0',
m_axis_4_aclk => '0',
m_axis_4_aresetn => '0',
m_axis_4_tready => '0',
m_axis_5_aclk => '0',
m_axis_5_aresetn => '0',
m_axis_5_tready => '0',
m_axis_6_aclk => '0',
m_axis_6_aresetn => '0',
m_axis_6_tready => '0',
m_axis_7_aclk => '0',
m_axis_7_aresetn => '0',
m_axis_7_tready => '0',
ap_oarg_0_clk => '0',
ap_oarg_0_rst => '0',
ap_oarg_0_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_0_ce => '0',
ap_oarg_0_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_1_clk => '0',
ap_oarg_1_rst => '0',
ap_oarg_1_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_1_ce => '0',
ap_oarg_1_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_2_clk => '0',
ap_oarg_2_rst => '0',
ap_oarg_2_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_2_ce => '0',
ap_oarg_2_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_3_clk => '0',
ap_oarg_3_rst => '0',
ap_oarg_3_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_3_ce => '0',
ap_oarg_3_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_4_clk => '0',
ap_oarg_4_rst => '0',
ap_oarg_4_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_4_ce => '0',
ap_oarg_4_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_5_clk => '0',
ap_oarg_5_rst => '0',
ap_oarg_5_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_5_ce => '0',
ap_oarg_5_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_6_clk => '0',
ap_oarg_6_rst => '0',
ap_oarg_6_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_6_ce => '0',
ap_oarg_6_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_7_clk => '0',
ap_oarg_7_rst => '0',
ap_oarg_7_addr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oarg_7_ce => '0',
ap_oarg_7_we => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
ap_oarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_0_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_0_write => '0',
ap_fifo_oarg_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_1_write => '0',
ap_fifo_oarg_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_2_write => '0',
ap_fifo_oarg_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_3_write => '0',
ap_fifo_oarg_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_4_write => '0',
ap_fifo_oarg_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_5_write => '0',
ap_fifo_oarg_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_6_write => '0',
ap_fifo_oarg_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_fifo_oarg_7_write => '0',
aclk => aclk,
aresetn => aresetn,
ap_start => ap_start,
ap_ready => ap_ready,
ap_done => ap_done,
ap_continue => ap_continue,
ap_idle => ap_idle,
ap_iscalar_0_dout => ap_iscalar_0_dout,
ap_iscalar_1_dout => ap_iscalar_1_dout,
ap_iscalar_2_dout => ap_iscalar_2_dout,
ap_oscalar_0_din => ap_oscalar_0_din,
ap_oscalar_1_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_2_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_3_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_4_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_5_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_6_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_7_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_8_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_9_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_10_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_11_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_12_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_13_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_14_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_15_din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
ap_oscalar_0_vld => '0',
ap_oscalar_1_vld => '0',
ap_oscalar_2_vld => '0',
ap_oscalar_3_vld => '0',
ap_oscalar_4_vld => '0',
ap_oscalar_5_vld => '0',
ap_oscalar_6_vld => '0',
ap_oscalar_7_vld => '0',
ap_oscalar_8_vld => '0',
ap_oscalar_9_vld => '0',
ap_oscalar_10_vld => '0',
ap_oscalar_11_vld => '0',
ap_oscalar_12_vld => '0',
ap_oscalar_13_vld => '0',
ap_oscalar_14_vld => '0',
ap_oscalar_15_vld => '0',
ap_iscalar_0_ack => '0',
ap_iscalar_1_ack => '0',
ap_iscalar_2_ack => '0',
ap_iscalar_3_ack => '0',
ap_iscalar_4_ack => '0',
ap_iscalar_5_ack => '0',
ap_iscalar_6_ack => '0',
ap_iscalar_7_ack => '0',
ap_iscalar_8_ack => '0',
ap_iscalar_9_ack => '0',
ap_iscalar_10_ack => '0',
ap_iscalar_11_ack => '0',
ap_iscalar_12_ack => '0',
ap_iscalar_13_ack => '0',
ap_iscalar_14_ack => '0',
ap_iscalar_15_ack => '0',
interrupt => interrupt
);
END zc702_set_0_if_0_arch;
| mit |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/vhls/set/solution/syn/vhdl/set_gmem_m_axi.vhd | 4 | 110726 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity set_gmem_m_axi;
architecture behave of set_gmem_m_axi is
component set_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component set_gmem_m_axi_write;
component set_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component set_gmem_m_axi_read;
component set_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component set_gmem_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : set_gmem_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : set_gmem_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : set_gmem_m_axi_write
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : set_gmem_m_axi_read
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity set_gmem_m_axi_fifo;
architecture behave of set_gmem_m_axi_fifo is
signal push, pop, data_vld : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if rdreq = '1' then
full_n_tmp <= '1';
elsif push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity set_gmem_m_axi_decoder;
architecture behav of set_gmem_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity set_gmem_m_axi_throttl;
architecture behav of set_gmem_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity set_gmem_m_axi_read;
architecture behave of set_gmem_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component set_gmem_m_axi_fifo;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
fifo_rreq : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_rreq_valid,
full_n => rreq_ack,
rdreq => fifo_rreq_read,
wrreq => rreq_valid,
q => fifo_rreq_data,
data => rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : set_gmem_m_axi_fifo
generic map (
DATA_BITS => BUS_DATA_WIDTH + 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => beat_valid,
full_n => RREADY,
rdreq => next_beat,
wrreq => RVALID,
q => data_pack,
data => fifo_rresp_rdata);
fifo_rresp_rdata <= (RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity set_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity set_gmem_m_axi_write;
architecture behave of set_gmem_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal burst_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal resp_total : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal resp_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : BOOLEAN;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component set_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component set_gmem_m_axi_fifo;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
fifo_wreq : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_wreq_valid,
full_n => wreq_ack,
rdreq => fifo_wreq_read,
wrreq => wreq_valid,
q => fifo_wreq_data,
data => wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when last_sect and next_sect else '0';
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_wreq then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_sect then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_sect else '0';
burst_end <= sect_end;
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop and last_loop and last_sect_buf = '1' else '0';
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_sect and first_sect then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_loop then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
fifo_wdata : set_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_DW + USER_DW/8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => data_valid,
full_n => wdata_ack,
rdreq => next_data,
wrreq => wdata_valid,
q => data_pack,
data => fifo_wdata_wstrb);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component set_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component set_gmem_m_axi_decoder;
begin
-- Instantiation
fifo_burst : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : set_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : set_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : set_gmem_m_axi_fifo
generic map (
DATA_BITS => C_M_AXI_ADDR_WIDTH - 12,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => resp_match,
wrreq => fifo_resp_w,
q => resp_total,
data => burst_cnt);
fifo_resp_to_user : set_gmem_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
resp_match <= '1' when (resp_cnt = resp_total and need_wrsp = '1') else '0';
next_resp <= BVALID = '1' and resp_ready = '1';
resp_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
resp_cnt <= (others => '0');
elsif (resp_match = '1' and next_resp) then
resp_cnt <= (others => '0');
resp_cnt(0) <= '1';
elsif (next_resp) then
resp_cnt <= resp_cnt + 1;
end if;
end if;
end if;
end process resp_cnt_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp) then
bresp_tmp <= BRESP;
elsif (next_resp and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
| mit |
agural/FPGA-Oscilloscope | osc/lpm_counter11.vhd | 1 | 4161 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter11.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter11 IS
PORT
(
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_counter11;
ARCHITECTURE SYN OF lpm_counter11 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 8
)
PORT MAP (
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter11.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter11.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter11.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter11.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter11_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| mit |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_input_scalars_fifo.vhd | 1 | 57851 | -------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_input_scalars_fifo.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-11-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
library fifo_generator_v13_0_1;
use fifo_generator_v13_0_1.all;
entity xd_input_scalars_fifo is
generic (
C_FAMILY : string := "virtex6";
C_MTBF_STAGES : integer := 4;
WIDTH : integer := 16);
port (
din : in std_logic_vector(WIDTH-1 downto 0);
din_vld : in std_logic;
din_rdy : out std_logic;
wr_used : out std_logic_vector(3 downto 0);
wr_empty : out std_logic;
wr_full : out std_logic;
wr_clk : in std_logic;
dout : out std_logic_vector(WIDTH-1 downto 0);
dout_vld : out std_logic;
dout_rdy : in std_logic;
rd_clk : in std_logic;
rst : in std_logic);
end xd_input_scalars_fifo;
architecture rtl of xd_input_scalars_fifo is
constant DEPTH : integer := 16;
constant FIFO_DEPTH : integer := calc_fifo_depth(DEPTH)+ 1;
constant ADDR_BITS : integer := log2(FIFO_DEPTH);
signal rst_vec : std_logic_vector(0 downto 0);
signal wr_rst_vec : std_logic_vector(0 downto 0);
signal rd_rst_vec : std_logic_vector(0 downto 0);
signal wr_rst : std_logic;
signal rd_rst : std_logic;
signal rd_addr : unsigned(ADDR_BITS-1 downto 0);
signal wr_addr : unsigned(ADDR_BITS-1 downto 0);
-- Next signals are gray values:
signal wr_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal next_wr_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal wr_gray_ahead : std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal next_rd_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal prev_rd_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal fifo_we : std_logic;
signal fifo_re : std_logic;
signal din_rdy_i : std_logic;
signal empty_i : std_logic;
signal rd_en : std_logic;
signal dout_vld_i : std_logic;
signal empty : std_logic;
signal rd_en_dly : std_logic;
signal wr_en_dly : std_logic;
signal din_dly : std_logic_vector(WIDTH-1 downto 0);
signal full : std_logic;
signal rstn : std_logic;
signal almost_full :std_logic;
signal wr_ack :std_logic;
signal overflow :std_logic;
signal almost_empty :std_logic;
signal valid :std_logic;
signal underflow :std_logic;
signal data_count :std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_data_count :std_logic_vector(ADDR_BITS-1 downto 0);
signal wr_data_count :std_logic_vector(ADDR_BITS-1 downto 0);
signal prog_full :std_logic;
signal prog_empty :std_logic;
signal sbiterr :std_logic;
signal dbiterr :std_logic;
signal wr_rst_busy :std_logic;
signal rd_rst_busy :std_logic;
signal m_axi_awid :std_logic_vector(0 downto 0);
signal m_axi_awaddr :std_logic_vector(31 downto 0);
signal m_axi_awlen :std_logic_vector(7 downto 0);
signal m_axi_awsize :std_logic_vector(2 downto 0);
signal m_axi_awburst :std_logic_vector(1 downto 0);
signal m_axi_awlock :std_logic_vector(0 downto 0);
signal m_axi_awcache :std_logic_vector(3 downto 0);
signal m_axi_awprot :std_logic_vector(2 downto 0);
signal m_axi_awqos :std_logic_vector(3 downto 0);
signal m_axi_awregion :std_logic_vector(3 downto 0);
signal m_axi_awuser :std_logic_vector(0 downto 0);
signal m_axi_awvalid :std_logic;
signal m_axi_wid :std_logic_vector(0 downto 0);
signal m_axi_wdata :std_logic_vector(63 downto 0);
signal m_axi_wstrb :std_logic_vector(7 downto 0);
signal m_axi_wlast :std_logic;
signal m_axi_wuser :std_logic_vector(0 downto 0);
signal m_axi_wvalid :std_logic;
signal m_axi_bready :std_logic;
signal s_axi_awready :std_logic;
signal s_axi_wready :std_logic;
signal s_axi_bid :std_logic_vector(0 downto 0);
signal s_axi_bresp :std_logic_vector(1 downto 0);
signal s_axi_buser :std_logic_vector(0 downto 0);
signal m_axi_arid :std_logic_vector(0 downto 0);
signal m_axi_araddr :std_logic_vector(31 downto 0);
signal m_axi_arlen :std_logic_vector(7 downto 0);
signal m_axi_arsize :std_logic_vector(2 downto 0);
signal m_axi_arburst :std_logic_vector(1 downto 0);
signal m_axi_arlock :std_logic_vector(0 downto 0);
signal m_axi_arcache :std_logic_vector(3 downto 0);
signal m_axi_arprot :std_logic_vector(2 downto 0);
signal m_axi_arqos :std_logic_vector(3 downto 0);
signal m_axi_arregion :std_logic_vector(3 downto 0);
signal m_axi_aruser :std_logic_vector(0 downto 0);
signal m_axi_arvalid :std_logic;
signal m_axi_rready :std_logic;
signal s_axi_arready :std_logic;
signal s_axi_rid :std_logic_vector(0 downto 0);
signal s_axi_rdata :std_logic_vector(63 downto 0);
signal s_axi_rresp :std_logic_vector(1 downto 0);
signal s_axi_rlast :std_logic;
signal s_axi_ruser :std_logic_vector(0 downto 0);
signal m_axis_tvalid :std_logic;
signal m_axis_tdata :std_logic_vector(7 downto 0);
signal m_axis_tstrb :std_logic_vector(0 downto 0);
signal m_axis_tlast :std_logic;
signal m_axis_tkeep :std_logic_vector(0 downto 0);
signal m_axis_tid :std_logic_vector(0 downto 0);
signal m_axis_tdest :std_logic_vector(0 downto 0);
signal m_axis_tuser :std_logic_vector(3 downto 0);
signal s_axis_tready :std_logic;
signal axi_aw_data_count :std_logic_vector(4 downto 0);
signal axi_aw_wr_data_count :std_logic_vector(4 downto 0);
signal axi_aw_rd_data_count :std_logic_vector(4 downto 0);
signal axi_aw_sbiterr :std_logic;
signal axi_aw_dbiterr :std_logic;
signal axi_aw_overflow :std_logic;
signal axi_aw_underflow :std_logic;
signal axi_aw_prog_full :std_logic;
signal axi_aw_prog_empty :std_logic;
signal axi_w_data_count :std_logic_vector(10 downto 0);
signal axi_w_wr_data_count :std_logic_vector(10 downto 0);
signal axi_w_rd_data_count :std_logic_vector(10 downto 0);
signal axi_w_sbiterr :std_logic;
signal axi_w_dbiterr :std_logic;
signal axi_w_overflow :std_logic;
signal axi_w_underflow :std_logic;
signal axi_w_prog_full :std_logic;
signal axi_w_prog_empty :std_logic;
signal axi_b_data_count :std_logic_vector(4 downto 0);
signal axi_b_wr_data_count :std_logic_vector(4 downto 0);
signal axi_b_rd_data_count :std_logic_vector(4 downto 0);
signal axi_b_sbiterr :std_logic;
signal axi_b_dbiterr :std_logic;
signal axi_b_overflow :std_logic;
signal axi_b_underflow :std_logic;
signal axi_b_prog_full :std_logic;
signal axi_b_prog_empty :std_logic;
signal axi_ar_data_count :std_logic_vector(4 downto 0);
signal axi_ar_wr_data_count :std_logic_vector(4 downto 0);
signal axi_ar_rd_data_count :std_logic_vector(4 downto 0);
signal axi_ar_sbiterr :std_logic;
signal axi_ar_dbiterr :std_logic;
signal axi_ar_overflow :std_logic;
signal axi_ar_underflow :std_logic;
signal axi_ar_prog_full :std_logic;
signal axi_ar_prog_empty :std_logic;
signal axi_r_data_count :std_logic_vector(10 downto 0);
signal axi_r_wr_data_count :std_logic_vector(10 downto 0);
signal axi_r_rd_data_count :std_logic_vector(10 downto 0);
signal axi_r_sbiterr :std_logic;
signal axi_r_dbiterr :std_logic;
signal axi_r_overflow :std_logic;
signal axi_r_underflow :std_logic;
signal axi_r_prog_full :std_logic;
signal axi_r_prog_empty :std_logic;
signal axis_data_count :std_logic_vector(10 downto 0);
signal axis_wr_data_count :std_logic_vector(10 downto 0);
signal axis_rd_data_count :std_logic_vector(10 downto 0);
signal axis_sbiterr :std_logic;
signal axis_dbiterr :std_logic;
signal axis_overflow :std_logic;
signal axis_underflow :std_logic;
signal axis_prog_full :std_logic;
signal axis_prog_empty :std_logic;
type mem_type is array (2**ADDR_BITS-1 downto 0) of std_logic_vector (WIDTH-1 downto 0);
signal mem : mem_type;
attribute ram_style : string;
attribute ram_style of mem : signal is "distributed";
signal mem_dout : std_logic_vector(WIDTH-1 downto 0);
-- Read gray counter synchronized with write clock.
signal reg_rd_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_gray_sync : std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_bin : unsigned(ADDR_BITS-1 downto 0);
signal wr_bin : unsigned(ADDR_BITS-1 downto 0);
signal ptr_dist : unsigned(ADDR_BITS-1 downto 0);
signal wr_used_i : std_logic_vector(ADDR_BITS-1 downto 0);
signal wr_empty_i : std_logic;
constant C_EXTRA_SYNCS : integer := 5;
begin
EXISTING : if (C_EXTRA_SYNCS = 0) generate
begin
fifo_we <= din_vld and din_rdy_i;
process(wr_clk, rst)
begin
if(rst = '1') then
wr_addr <= (others => '0');
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_addr <= wr_addr + 1;
end if;
end if;
end process;
fifo_re <= rd_en and not(empty_i);
process(rd_clk, rst)
begin
if(rst = '1') then
rd_addr <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
rd_addr <= rd_addr + 1;
end if;
end if;
end process;
---------------------------------------------------------
process(rd_clk, rst)
begin
if(rst = '1') then
next_rd_gray <= bin2gray(2**ADDR_BITS-1, ADDR_BITS);
rd_gray <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
prev_rd_gray <= bin2gray(2**ADDR_BITS-3, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
prev_rd_gray <= rd_gray;
rd_gray <= next_rd_gray;
next_rd_gray <= bin2gray(std_logic_vector(rd_addr));
end if;
end if;
end process;
process(wr_clk, rst)
begin
if(rst = '1') then
next_wr_gray <= bin2gray(2**ADDR_BITS-1, ADDR_BITS);
wr_gray <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray <= next_wr_gray;
next_wr_gray <= bin2gray(std_logic_vector(wr_addr));
end if;
end if;
end process;
process(wr_clk, rst)
begin
if(rst = '1') then
wr_gray_ahead <= bin2gray(2**ADDR_BITS-0, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
end if;
end if;
end process;
-----------------------------------------------------------------
process(wr_clk, rst)
begin
if(rst = '1') then
din_rdy_i <= '0';
elsif(wr_clk'event and wr_clk = '1') then
if(din_rdy_i = '1') then
if (wr_gray_ahead = prev_rd_gray) then
din_rdy_i <= not(fifo_we);
else
din_rdy_i <= '1';
end if;
else
if (wr_gray_ahead = rd_gray) then
din_rdy_i <= '0';
else
din_rdy_i <= '1';
end if;
end if;
end if;
end process;
din_rdy <= din_rdy_i;
process(rd_clk, rst)
begin
if(rst = '1') then
empty_i <= '1';
elsif(rd_clk'event and rd_clk = '1') then
if(empty_i = '0') then
if(next_rd_gray = wr_gray) then
empty_i <= fifo_re;
else
empty_i <= '0';
end if;
else
if(rd_gray = wr_gray) then
empty_i <= '1';
else
empty_i <= '0';
end if;
end if;
end if;
end process;
rd_en <= not(dout_vld_i) or (dout_vld_i and dout_rdy);
process(rd_clk, rst)
begin
if(rst = '1') then
dout_vld_i <= '0';
elsif(rd_clk'event and rd_clk = '1') then
if(rd_en = '1') then
dout_vld_i <= not(empty_i);
end if;
end if;
end process;
dout_vld <= dout_vld_i;
-----------------------------------------------------------------------
-- Memory bank modeling. Tool to infer the memory.
process(wr_clk)
begin
if(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
mem(to_integer(wr_addr)) <= din;
end if;
end if;
end process;
mem_dout <= mem(to_integer(rd_addr));
process(rd_clk, rst)
begin
if(rst = '1') then
dout <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
dout <= mem_dout;
end if;
end if;
end process;
-----------------------------------------------------------------------
process(rd_clk, rst)
begin
if(rst = '1') then
reg_rd_gray <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if(rd_en = '1') then
reg_rd_gray <= rd_gray;
end if;
end if;
end process;
process(wr_clk, rst)
begin
if(rst = '1') then
rd_gray_sync <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
rd_gray_sync <= reg_rd_gray;
end if;
end process;
rd_bin <= unsigned(gray2bin(rd_gray_sync));
process(wr_clk, rst)
begin
if(rst = '1') then
wr_bin <= to_unsigned(2**ADDR_BITS-2, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if (fifo_we = '1') then
wr_bin <= wr_bin + 1;
end if;
end if;
end process;
process(wr_clk, rst)
begin
if(rst = '1') then
ptr_dist <= (others => '0');
elsif(wr_clk'event and wr_clk = '1') then
if (fifo_we = '1') then
ptr_dist <= ptr_dist + 1;
else
ptr_dist <= wr_bin - rd_bin;
end if;
end if;
end process;
wr_used <= std_logic_vector(ptr_dist);
wr_full <= not(din_rdy_i);
process(wr_clk, rst)
begin
if(rst = '1') then
wr_empty_i <= '1';
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_empty_i <= '0';
else
if(rd_gray_sync = wr_gray) then
wr_empty_i <= '1';
else
wr_empty_i <= '0';
end if;
end if;
end if;
end process;
wr_empty <= wr_empty_i;
end generate EXISTING;
NEW_INTRO : if (C_EXTRA_SYNCS = 2) generate
begin
rst_vec(0) <= rst;
wr_rst <= wr_rst_vec(0);
rd_rst <= rd_rst_vec(0);
wr_rst_sync: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff
GENERIC MAP (
C_HAS_RST => 0,
C_WIDTH => 1
)
PORT MAP (
RST => open,
CLK => wr_clk,
D => rst_vec,
Q => wr_rst_vec
);
rd_rst_sync: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff
GENERIC MAP (
C_HAS_RST => 0,
C_WIDTH => 1
)
PORT MAP (
RST => open,
CLK => rd_clk,
D => rst_vec,
Q => rd_rst_vec
);
fifo_we <= din_vld and din_rdy_i;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
wr_addr <= (others => '0');
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_addr <= wr_addr + 1;
end if;
end if;
end process;
fifo_re <= rd_en and not(empty_i);
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
rd_addr <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
rd_addr <= rd_addr + 1;
end if;
end if;
end process;
---------------------------------------------------------
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
next_rd_gray <= bin2gray(2**ADDR_BITS-1, ADDR_BITS);
rd_gray <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
prev_rd_gray <= bin2gray(2**ADDR_BITS-3, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
prev_rd_gray <= rd_gray;
rd_gray <= next_rd_gray;
next_rd_gray <= bin2gray(std_logic_vector(rd_addr));
end if;
end if;
end process;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
next_wr_gray <= bin2gray(2**ADDR_BITS-1, ADDR_BITS);
wr_gray <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray <= next_wr_gray;
next_wr_gray <= bin2gray(std_logic_vector(wr_addr));
end if;
end if;
end process;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
wr_gray_ahead <= bin2gray(2**ADDR_BITS-0, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
end if;
end if;
end process;
-----------------------------------------------------------------
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
din_rdy_i <= '0';
elsif(wr_clk'event and wr_clk = '1') then
if(din_rdy_i = '1') then
if (wr_gray_ahead = prev_rd_gray) then
din_rdy_i <= not(fifo_we);
else
din_rdy_i <= '1';
end if;
else
if (wr_gray_ahead = rd_gray) then
din_rdy_i <= '0';
else
din_rdy_i <= '1';
end if;
end if;
end if;
end process;
din_rdy <= din_rdy_i;
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
empty_i <= '1';
elsif(rd_clk'event and rd_clk = '1') then
if(empty_i = '0') then
if(next_rd_gray = wr_gray) then
empty_i <= fifo_re;
else
empty_i <= '0';
end if;
else
if(rd_gray = wr_gray) then
empty_i <= '1';
else
empty_i <= '0';
end if;
end if;
end if;
end process;
rd_en <= not(dout_vld_i) or (dout_vld_i and dout_rdy);
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
dout_vld_i <= '0';
elsif(rd_clk'event and rd_clk = '1') then
if(rd_en = '1') then
dout_vld_i <= not(empty_i);
end if;
end if;
end process;
dout_vld <= dout_vld_i;
-----------------------------------------------------------------------
-- Memory bank modeling. Tool to infer the memory.
process(wr_clk)
begin
if(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
mem(to_integer(wr_addr)) <= din;
end if;
end if;
end process;
mem_dout <= mem(to_integer(rd_addr));
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
dout <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
dout <= mem_dout;
end if;
end if;
end process;
-----------------------------------------------------------------------
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
reg_rd_gray <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if(rd_en = '1') then
reg_rd_gray <= rd_gray;
end if;
end if;
end process;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
rd_gray_sync <= bin2gray(2**ADDR_BITS-2, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
rd_gray_sync <= reg_rd_gray;
end if;
end process;
rd_bin <= unsigned(gray2bin(rd_gray_sync));
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
wr_bin <= to_unsigned(2**ADDR_BITS-2, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if (fifo_we = '1') then
wr_bin <= wr_bin + 1;
end if;
end if;
end process;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
ptr_dist <= (others => '0');
elsif(wr_clk'event and wr_clk = '1') then
if (fifo_we = '1') then
ptr_dist <= ptr_dist + 1;
else
ptr_dist <= wr_bin - rd_bin;
end if;
end if;
end process;
wr_used <= std_logic_vector(ptr_dist(3 downto 0));
wr_full <= not(din_rdy_i);
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
wr_empty_i <= '1';
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_empty_i <= '0';
else
if(rd_gray_sync = wr_gray) then
wr_empty_i <= '1';
else
wr_empty_i <= '0';
end if;
end if;
end if;
end process;
wr_empty <= wr_empty_i;
end generate NEW_INTRO;
NEW_INTRO3 : if (C_EXTRA_SYNCS = 5) generate
begin
rstn <= not(rst);
din_rdy <= not(full);
din_rdy_i <= not(full);
wr_full <= (full);
wr_empty <= (empty);
dout_vld <= not(empty);
wr_en_dly <= din_vld ;--AFTER 100ps;
rd_en_dly <= dout_rdy ;--AFTER 100ps;
din_dly <= din ;--AFTER 100ps;
wr_used <= wr_used_i(3 downto 0);
FIF_DMG_INST : entity fifo_generator_v13_0_1.fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 4,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => WIDTH,
C_ENABLE_RLOCS => 0,
C_FAMILY => C_FAMILY,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 1,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 29,
C_PROG_FULL_THRESH_NEGATE_VAL => 28,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => ADDR_BITS,
C_RD_DEPTH => FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADDR_BITS,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => ADDR_BITS,
C_WR_DEPTH => FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADDR_BITS,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_MTBF_STAGES,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 3,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din_dly,
wr_en => wr_en_dly,
rd_en => rd_en_dly,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
almost_full => almost_full,
wr_ack => wr_ack,
overflow => overflow,
empty => empty,
almost_empty => almost_empty,
valid => valid,
underflow => underflow,
data_count => data_count,
rd_data_count => rd_data_count,
wr_data_count => wr_used_i,
prog_full => prog_full,
prog_empty => prog_empty,
sbiterr => sbiterr,
dbiterr => dbiterr,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awregion => m_axi_awregion,
m_axi_awuser => m_axi_awuser,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => '0',
m_axi_wid => m_axi_wid,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wuser => m_axi_wuser,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
m_axi_bready => m_axi_bready,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_awready => s_axi_awready,
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_buser => s_axi_buser,
s_axi_bready => '0',
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arregion => m_axi_arregion,
m_axi_aruser => m_axi_aruser,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
m_axi_rready => m_axi_rready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_ruser => s_axi_ruser,
s_axi_rready => '0',
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => '0',
m_axis_tdata => m_axis_tdata ,
m_axis_tstrb => m_axis_tstrb ,
m_axis_tkeep => m_axis_tkeep ,
m_axis_tlast => m_axis_tlast ,
m_axis_tid => m_axis_tid ,
m_axis_tdest => m_axis_tdest ,
m_axis_tuser => m_axis_tuser ,
s_axis_tvalid => '0',
s_axis_tready => s_axis_tready,
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_data_count => axi_aw_data_count,
axi_aw_wr_data_count => axi_aw_wr_data_count,
axi_aw_rd_data_count => axi_aw_rd_data_count,
axi_aw_sbiterr => axi_aw_sbiterr,
axi_aw_dbiterr => axi_aw_dbiterr,
axi_aw_overflow => axi_aw_overflow,
axi_aw_underflow => axi_aw_underflow,
axi_aw_prog_full => axi_aw_prog_full,
axi_aw_prog_empty => axi_aw_prog_empty,
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_data_count => axi_w_data_count,
axi_w_wr_data_count => axi_w_wr_data_count,
axi_w_rd_data_count => axi_w_rd_data_count,
axi_w_sbiterr => axi_w_sbiterr,
axi_w_dbiterr => axi_w_dbiterr,
axi_w_overflow => axi_w_overflow,
axi_w_underflow => axi_w_underflow,
axi_w_prog_full => axi_w_prog_full,
axi_w_prog_empty => axi_w_prog_empty,
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_data_count => axi_b_data_count,
axi_b_wr_data_count => axi_b_wr_data_count,
axi_b_rd_data_count => axi_b_rd_data_count,
axi_b_sbiterr => axi_b_sbiterr,
axi_b_dbiterr => axi_b_dbiterr,
axi_b_overflow => axi_b_overflow,
axi_b_underflow => axi_b_underflow,
axi_b_prog_full => axi_b_prog_full,
axi_b_prog_empty => axi_b_prog_empty,
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_data_count => axi_ar_data_count,
axi_ar_wr_data_count => axi_ar_wr_data_count,
axi_ar_rd_data_count => axi_ar_rd_data_count,
axi_ar_sbiterr => axi_ar_sbiterr,
axi_ar_dbiterr => axi_ar_dbiterr,
axi_ar_overflow => axi_ar_overflow,
axi_ar_underflow => axi_ar_underflow,
axi_ar_prog_full => axi_ar_prog_full,
axi_ar_prog_empty => axi_ar_prog_empty,
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_data_count => axi_r_data_count,
axi_r_wr_data_count => axi_r_wr_data_count,
axi_r_rd_data_count => axi_r_rd_data_count,
axi_r_sbiterr => axi_r_sbiterr,
axi_r_dbiterr => axi_r_dbiterr,
axi_r_overflow => axi_r_overflow,
axi_r_underflow => axi_r_underflow,
axi_r_prog_full => axi_r_prog_full,
axi_r_prog_empty => axi_r_prog_empty,
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_data_count => axis_data_count,
axis_wr_data_count => axis_wr_data_count,
axis_rd_data_count => axis_rd_data_count,
axis_sbiterr => axis_sbiterr,
axis_dbiterr => axis_dbiterr,
axis_overflow => axis_overflow,
axis_underflow => axis_underflow,
axis_prog_full => axis_prog_full,
axis_prog_empty => axis_prog_empty
);
-- COMP_FIFO : entity fifo_generator_v12_0_5.fifo_generator_v12_0_5
-- generic map (
-- C_COMMON_CLOCK => 0,
-- C_COUNT_TYPE => 0,
-- C_DATA_COUNT_WIDTH => 10,
-- C_DEFAULT_VALUE => "BlankString",
-- C_DIN_WIDTH => 18,
-- C_DOUT_RST_VAL => "0",
-- C_DOUT_WIDTH => 18,
-- C_ENABLE_RLOCS => 0,
-- C_FAMILY => C_FAMILY,
-- C_FULL_FLAGS_RST_VAL => 1,
-- C_HAS_ALMOST_EMPTY => 0,
-- C_HAS_ALMOST_FULL => 0,
-- C_HAS_BACKUP => 0,
-- C_HAS_DATA_COUNT => 0,
-- C_HAS_INT_CLK => 0,
-- C_HAS_MEMINIT_FILE => 0,
-- C_HAS_OVERFLOW => 0,
-- C_HAS_RD_DATA_COUNT => 0,
-- C_HAS_RD_RST => 0,
-- C_HAS_RST => 1,
-- C_HAS_SRST => 0,
-- C_HAS_UNDERFLOW => 0,
-- C_HAS_VALID => 0,
-- C_HAS_WR_ACK => 0,
-- C_HAS_WR_DATA_COUNT => 0,
-- C_HAS_WR_RST => 0,
-- C_IMPLEMENTATION_TYPE => 0,
-- C_INIT_WR_PNTR_VAL => 0,
-- C_MEMORY_TYPE => 1,
-- C_MIF_FILE_NAME => "BlankString",
-- C_OPTIMIZATION_MODE => 0,
-- C_OVERFLOW_LOW => 0,
-- C_PRELOAD_LATENCY => 1,
-- C_PRELOAD_REGS => 0,
-- C_PRIM_FIFO_TYPE => "4kx4",
-- C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
-- C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
-- C_PROG_EMPTY_TYPE => 0,
-- C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
-- C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
-- C_PROG_FULL_TYPE => 0,
-- C_RD_DATA_COUNT_WIDTH => 10,
-- C_RD_DEPTH => 16,
-- C_RD_FREQ => 1,
-- C_RD_PNTR_WIDTH => ADDR_BITS,
-- C_UNDERFLOW_LOW => 0,
-- C_USE_DOUT_RST => 1,
-- C_USE_ECC => 0,
-- C_USE_EMBEDDED_REG => 0,
-- C_USE_PIPELINE_REG => 0,
-- C_POWER_SAVING_MODE => 0,
-- C_USE_FIFO16_FLAGS => 0,
-- C_USE_FWFT_DATA_COUNT => 0,
-- C_VALID_LOW => 0,
-- C_WR_ACK_LOW => 0,
-- C_WR_DATA_COUNT_WIDTH => 10,
-- C_WR_DEPTH => 16,
-- C_WR_FREQ => 1,
-- C_WR_PNTR_WIDTH => ADDR_BITS,
-- C_WR_RESPONSE_LATENCY => 1,
-- C_MSGON_VAL => 1,
-- C_ENABLE_RST_SYNC => 1,
-- C_ERROR_INJECTION_TYPE => 0,
-- C_SYNCHRONIZER_STAGE => 2,
-- C_INTERFACE_TYPE => 1,
-- C_AXI_TYPE => 1,
-- C_HAS_AXI_WR_CHANNEL => 1,
-- C_HAS_AXI_RD_CHANNEL => 1,
-- C_HAS_SLAVE_CE => 0,
-- C_HAS_MASTER_CE => 0,
-- C_ADD_NGC_CONSTRAINT => 0,
-- C_USE_COMMON_OVERFLOW => 0,
-- C_USE_COMMON_UNDERFLOW => 0,
-- C_USE_DEFAULT_SETTINGS => 0,
-- C_AXI_ID_WIDTH => 1,
-- C_AXI_ADDR_WIDTH => 32,
-- C_AXI_DATA_WIDTH => 64,
-- C_AXI_LEN_WIDTH => 8,
-- C_AXI_LOCK_WIDTH => 1,
-- C_HAS_AXI_ID => 0,
-- C_HAS_AXI_AWUSER => 0,
-- C_HAS_AXI_WUSER => 0,
-- C_HAS_AXI_BUSER => 0,
-- C_HAS_AXI_ARUSER => 0,
-- C_HAS_AXI_RUSER => 0,
-- C_AXI_ARUSER_WIDTH => 1,
-- C_AXI_AWUSER_WIDTH => 1,
-- C_AXI_WUSER_WIDTH => 1,
-- C_AXI_BUSER_WIDTH => 1,
-- C_AXI_RUSER_WIDTH => 1,
-- C_HAS_AXIS_TDATA => 0,
-- C_HAS_AXIS_TID => 0,
-- C_HAS_AXIS_TDEST => 0,
-- C_HAS_AXIS_TUSER => 0,
-- C_HAS_AXIS_TREADY => 1,
-- C_HAS_AXIS_TLAST => 1,
-- C_HAS_AXIS_TSTRB => 0,
-- C_HAS_AXIS_TKEEP => 0,
-- C_AXIS_TDATA_WIDTH => 1,
-- C_AXIS_TID_WIDTH => 1,
-- C_AXIS_TDEST_WIDTH => 1,
-- C_AXIS_TUSER_WIDTH => 1,
-- C_AXIS_TSTRB_WIDTH => 1,
-- C_AXIS_TKEEP_WIDTH => 1,
-- C_WACH_TYPE => 0,
-- C_WDCH_TYPE => 0,
-- C_WRCH_TYPE => 0,
-- C_RACH_TYPE => 0,
-- C_RDCH_TYPE => 0,
-- C_AXIS_TYPE => 0,
-- C_IMPLEMENTATION_TYPE_WACH => 12,
-- C_IMPLEMENTATION_TYPE_WDCH => 11,
-- C_IMPLEMENTATION_TYPE_WRCH => 12,
-- C_IMPLEMENTATION_TYPE_RACH => 12,
-- C_IMPLEMENTATION_TYPE_RDCH => 11,
-- C_IMPLEMENTATION_TYPE_AXIS => 11,
-- C_APPLICATION_TYPE_WACH => 0,
-- C_APPLICATION_TYPE_WDCH => 0,
-- C_APPLICATION_TYPE_WRCH => 0,
-- C_APPLICATION_TYPE_RACH => 0,
-- C_APPLICATION_TYPE_RDCH => 0,
-- C_APPLICATION_TYPE_AXIS => 1,
-- C_PRIM_FIFO_TYPE_WACH => "512x36",
-- C_PRIM_FIFO_TYPE_WDCH => "1kx36",
-- C_PRIM_FIFO_TYPE_WRCH => "512x36",
-- C_PRIM_FIFO_TYPE_RACH => "512x36",
-- C_PRIM_FIFO_TYPE_RDCH => "1kx36",
-- C_PRIM_FIFO_TYPE_AXIS => "512x36",
-- C_USE_ECC_WACH => 0,
-- C_USE_ECC_WDCH => 0,
-- C_USE_ECC_WRCH => 0,
-- C_USE_ECC_RACH => 0,
-- C_USE_ECC_RDCH => 0,
-- C_USE_ECC_AXIS => 0,
-- C_ERROR_INJECTION_TYPE_WACH => 0,
-- C_ERROR_INJECTION_TYPE_WDCH => 0,
-- C_ERROR_INJECTION_TYPE_WRCH => 0,
-- C_ERROR_INJECTION_TYPE_RACH => 0,
-- C_ERROR_INJECTION_TYPE_RDCH => 0,
-- C_ERROR_INJECTION_TYPE_AXIS => 0,
-- C_DIN_WIDTH_WACH => 32,
-- C_DIN_WIDTH_WDCH => 64,
-- C_DIN_WIDTH_WRCH => 2,
-- C_DIN_WIDTH_RACH => 32,
-- C_DIN_WIDTH_RDCH => 64,
-- C_DIN_WIDTH_AXIS => 1,
-- C_WR_DEPTH_WACH => 16,
-- C_WR_DEPTH_WDCH => 1024,
-- C_WR_DEPTH_WRCH => 16,
-- C_WR_DEPTH_RACH => 16,
-- C_WR_DEPTH_RDCH => 1024,
-- C_WR_DEPTH_AXIS => 16,
-- C_WR_PNTR_WIDTH_WACH => ADDR_BITS,
-- C_WR_PNTR_WIDTH_WDCH => 10,
-- C_WR_PNTR_WIDTH_WRCH => ADDR_BITS,
-- C_WR_PNTR_WIDTH_RACH => ADDR_BITS,
-- C_WR_PNTR_WIDTH_RDCH => 10,
-- C_WR_PNTR_WIDTH_AXIS => ADDR_BITS,
-- C_HAS_DATA_COUNTS_WACH => 0,
-- C_HAS_DATA_COUNTS_WDCH => 0,
-- C_HAS_DATA_COUNTS_WRCH => 0,
-- C_HAS_DATA_COUNTS_RACH => 0,
-- C_HAS_DATA_COUNTS_RDCH => 0,
-- C_HAS_DATA_COUNTS_AXIS => 3,
-- C_HAS_PROG_FLAGS_WACH => 0,
-- C_HAS_PROG_FLAGS_WDCH => 0,
-- C_HAS_PROG_FLAGS_WRCH => 0,
-- C_HAS_PROG_FLAGS_RACH => 0,
-- C_HAS_PROG_FLAGS_RDCH => 0,
-- C_HAS_PROG_FLAGS_AXIS => 0,
-- C_PROG_FULL_TYPE_WACH => 0,
-- C_PROG_FULL_TYPE_WDCH => 0,
-- C_PROG_FULL_TYPE_WRCH => 0,
-- C_PROG_FULL_TYPE_RACH => 0,
-- C_PROG_FULL_TYPE_RDCH => 0,
-- C_PROG_FULL_TYPE_AXIS => 0,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
-- C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
-- C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 15,
-- C_PROG_EMPTY_TYPE_WACH => 0,
-- C_PROG_EMPTY_TYPE_WDCH => 0,
-- C_PROG_EMPTY_TYPE_WRCH => 0,
-- C_PROG_EMPTY_TYPE_RACH => 0,
-- C_PROG_EMPTY_TYPE_RDCH => 0,
-- C_PROG_EMPTY_TYPE_AXIS => 0,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 13,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1021,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 13,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 13,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1021,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 13,
-- C_REG_SLICE_MODE_WACH => 0,
-- C_REG_SLICE_MODE_WDCH => 0,
-- C_REG_SLICE_MODE_WRCH => 0,
-- C_REG_SLICE_MODE_RACH => 0,
-- C_REG_SLICE_MODE_RDCH => 0,
-- C_REG_SLICE_MODE_AXIS => 0
-- )
-- PORT MAP (
-- backup => '0',
-- backup_marker => '0',
-- clk => '0',
-- rst => '0',
-- srst => '0',
-- wr_clk => '0',
-- wr_rst => '0',
-- rd_clk => '0',
-- rd_rst => '0',
-- din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
-- wr_en => '0',
-- rd_en => '0',
-- prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- int_clk => '0',
-- injectdbiterr => '0',
-- injectsbiterr => '0',
-- sleep => '0',
-- m_aclk => rd_clk,
-- s_aclk => wr_clk,
-- s_aresetn => rstn,
-- m_aclk_en => '0',
-- s_aclk_en => '0',
-- s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
-- s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awvalid => '0',
-- s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
-- s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_wlast => '0',
-- s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_wvalid => '0',
-- s_axi_bready => '0',
-- m_axi_awready => '0',
-- m_axi_wready => '0',
-- m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_bvalid => '0',
-- s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
-- s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_arvalid => '0',
-- s_axi_rready => '0',
-- m_axi_arready => '0',
-- m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
-- m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- m_axi_rlast => '0',
-- m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_rvalid => '0',
-- s_axis_tvalid => din_vld,
-- s_axis_tready => open,
-- s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tlast => din_rdy_i,
-- s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axis_tvalid => dout_vld_i,
-- m_axis_tready => m_axis_tready,
-- m_axis_tlast => m_axis_tlast,
-- axi_aw_injectsbiterr => '0',
-- axi_aw_injectdbiterr => '0',
-- axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_w_injectsbiterr => '0',
-- axi_w_injectdbiterr => '0',
-- axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_b_injectsbiterr => '0',
-- axi_b_injectdbiterr => '0',
-- axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- axi_ar_injectsbiterr => '0',
-- axi_ar_injectdbiterr => '0',
-- axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_r_injectsbiterr => '0',
-- axi_r_injectdbiterr => '0',
-- axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axis_injectsbiterr => '0',
-- axis_injectdbiterr => '0',
-- axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axis_wr_data_count => wr_used_i,
-- axis_rd_data_count => open
-- );
end generate NEW_INTRO3;
end rtl;
| mit |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/axi_lite_adapter.vhd | 1 | 63260 | -------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : axi_lite_adapter.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-12-03
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-08-05 2.0 pvk updated
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.cdc_sync;
entity axi_lite_adapter is
generic (
-- System generics:
C_FAMILY : string := "virtex7"; -- Xilinx FPGA family
-- AXI generics:
C_S_AXI_ADDR_WIDTH : integer := 13;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
C_MAX_N_IARGS : integer;
C_MAX_N_OARGS : integer;
C_MAX_MB_DEPTH : integer;
C_N_INPUT_ARGS : integer;
C_N_OUTPUT_ARGS : integer;
C_PRMRY_IS_ACLK_ASYNC : integer;
C_MTBF_STAGES : integer;
C_MAX_ARG_AWIDTH : integer;
C_MAX_N_ISCALARS : integer;
C_N_INOUT_SCALARS : integer;
C_MAX_N_IOSCALARS : integer;
C_N_INPUT_SCALARS : integer;
C_MAX_N_OSCALARS : integer;
C_N_OUTPUT_SCALARS : integer;
C_MAX_SCALAR_DWIDTH : integer;
C_M_AXIS_TDEST_WIDTH : integer);
port (
-- AXI LITE interface signals:
S_AXI_ACLK : in std_logic; -- AXI Clock
S_AXI_ARESETN : in std_logic; -- AXI Reset, active low
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); -- AXI Write address
S_AXI_AWVALID : in std_logic; -- Write address valid
S_AXI_AWREADY : out std_logic; -- Write address ready
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); -- Write data
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); -- Write strobes
S_AXI_WVALID : in std_logic; -- Write valid
S_AXI_WREADY : out std_logic; -- Write ready
S_AXI_BRESP : out std_logic_vector(1 downto 0); -- Write response
S_AXI_BVALID : out std_logic; -- Write response valid
S_AXI_BREADY : in std_logic; -- Response ready
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); -- Read address
S_AXI_ARVALID : in std_logic; -- Read address valid
S_AXI_ARREADY : out std_logic; -- Read address ready
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); -- Read data
S_AXI_RRESP : out std_logic_vector(1 downto 0); -- Read response
S_AXI_RVALID : out std_logic; -- Read valid
S_AXI_RREADY : in std_logic; -- Read ready
--- App. ports
ap_rst : out std_logic; -- Read valid
-- Command input port:
host_cmd_data : out std_logic_vector(31 downto 0);
host_cmd_we : out std_logic;
host_cmd_rdy : in std_logic;
host_complete_re : out std_logic;
host_cmd_error : in std_logic;
-- AP core status signals:
status_ap_start : in std_logic;
status_ap_done : in std_logic;
status_ap_idle : in std_logic;
status_ap_ready : in std_logic;
status_ap_start_clr : out std_logic;
status_ap_done_clr : out std_logic;
status_ap_idle_clr : out std_logic;
status_ap_ready_clr : out std_logic;
-- Input arguments management:
host_iarg_rst : out std_logic_vector(C_MAX_N_IARGS-1 downto 0);
iarg_rqt_enable : out std_logic_vector(C_MAX_N_IARGS-1 downto 0);
status_iarg_empty : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
status_iarg_full : in std_logic_vector(C_MAX_N_IARGS-1 downto 0);
status_iarg_used : in std_logic_vector(C_MAX_N_IARGS*4-1 downto 0);
status_iarg_n_words : in std_logic_vector(C_MAX_N_IARGS*(C_MAX_ARG_AWIDTH+1)-1 downto 0);
-- Output arguments management:
host_oarg_rst : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
oarg_rqt_enable : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
oarg_sw_length : out std_logic_vector(31 downto 0);
oarg_sw_length_m2s : out std_logic_vector(31 downto 0);
oarg_sw_length_we : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
oarg_use_sw_length : out std_logic_vector(C_MAX_N_OARGS-1 downto 0);
host_oarg_tdest : out std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDEST_WIDTH-1 downto 0);
status_oarg_empty : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
status_oarg_full : in std_logic_vector(C_MAX_N_OARGS-1 downto 0);
status_oarg_used : in std_logic_vector(C_MAX_N_OARGS*4-1 downto 0);
-- Input scalar management:
host_iscalar_rst : out std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
host_iscalar_dout : out std_logic_vector(31 downto 0);
host_iscalar_we : out std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
host_iscalar_rdy : in std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
status_iscalar_empty : in std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
status_iscalar_full : in std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
status_iscalar_used : in std_logic_vector((C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS)*4-1 downto 0);
-- Output scalar management:
host_oscalar_rst : out std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
host_oscalar_din : in std_logic_vector((C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS)*C_MAX_SCALAR_DWIDTH-1 downto 0);
host_oscalar_re : out std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
host_oscalar_rdy : in std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
status_oscalar_empty : in std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
status_oscalar_full : in std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
status_oscalar_used : in std_logic_vector((C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS)*4-1 downto 0);
dbg_iarg_stream_nwords : in std_logic_vector(C_MAX_N_IARGS*16-1 downto 0);
dbg_iarg_buffer_nwords : in std_logic_vector(C_MAX_N_IARGS*16-1 downto 0);
dbg_oarg_stream_nwords : in std_logic_vector(C_MAX_N_OARGS*16-1 downto 0);
dbg_oarg_buffer_nwords : in std_logic_vector(C_MAX_N_OARGS*16-1 downto 0);
iscalar_rqt_enable : out std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
oscalar_rqt_enable : out std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
---
interrupt : out std_logic);
attribute SIGIS : string;
attribute SIGIS of S_AXI_ACLK : signal is "CLK";
attribute SIGIS of S_AXI_ARESETN : signal is "RST";
end entity;
architecture rtl of axi_lite_adapter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
constant DATA_WIDTH : integer := 32;
constant STRB_WIDTH : integer := (C_S_AXI_DATA_WIDTH/8);
constant AXI_RESP_OKAY : std_logic_vector(1 downto 0) := "00";
constant AXI_RESP_EXOKAY : std_logic_vector(1 downto 0) := "01";
constant AXI_RESP_SLVERR : std_logic_vector(1 downto 0) := "10";
constant AXI_RESP_DECERR : std_logic_vector(1 downto 0) := "11";
function ext_32 (
value : std_logic_vector;
width : natural := 32)
return std_logic_vector is
constant N : integer := value'length;
variable ret : std_logic_vector(width-1 downto 0);
begin
ret := (others => '0');
ret(N-1 downto 0) := value;
return ret;
end function ext_32;
function sext_32 (
value : std_logic_vector;
width : natural := 32)
return std_logic_vector is
constant N : integer := value'length;
alias val_dn : std_logic_vector (N-1 downto 0) is value;
variable ret : std_logic_vector(width-1 downto 0);
begin
ret(N-1 downto 0) := val_dn;
if(N < 32) then
ret(31 downto N) := (others => val_dn(N-1));
end if;
return ret;
end function sext_32;
signal axi_rst : std_logic;
signal ap_rst_fb : std_logic;
signal axi_rst1 : std_logic;
signal ap_rst_i : std_logic;
signal axi_addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); -- AXI Write address
signal wr_data_i : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--------------------------------------------------
-- We use banks of 16 registers (32 bits, 4 bytes):
constant BANK_ADDR_WIDTH : integer := 4; -- Up to 16 banks can be used.
constant BANK_ADDR_LSB : integer := log2(16*4);
constant BANK_ADDR_MSB : integer := BANK_ADDR_LSB+BANK_ADDR_WIDTH-1;
constant GP_REGS_BANK_ADDR : integer := 0;
constant GP_REGS_BANK1_ADDR : integer := 1;
constant ISCALAR_BANK_ADDR : integer := 2;
constant OSCALAR_BANK_ADDR : integer := 3;
constant IARG_STATUS_BANK_ADDR : integer := 4;
constant OARG_STATUS_BANK_ADDR : integer := 5;
constant ISCALAR_STATUS_BANK_ADDR : integer := 6;
constant OSCALAR_STATUS_BANK_ADDR : integer := 7;
constant OARG_LENGTH_BANK_ADDR : integer := 8;
constant OARG_TDEST_BANK_ADDR : integer := 9;
constant CTRL_REG_INDEX : integer := 0;
constant STATUS_REG_INDEX : integer := 1;
constant IARG_RST_REG_INDEX : integer := 2;
constant OARG_RST_REG_INDEX : integer := 3;
constant IARG_RQT_ENABLE_REG_INDEX : integer := 4;
constant OARG_RQT_ENABLE_REG_INDEX : integer := 5;
constant COMMAND_REG_INDEX : integer := 10;
constant COMPLETE_REG_INDEX : integer := 11;
constant INT_ENABLE_REG_INDEX : integer := 12;
constant INT_FLAG_REG_INDEX : integer := 13;
constant OARG_LENGTH_MODE_REG_INDEX : integer := 15;
constant ISCALAR_RST_REG_INDEX : integer := 16;
constant OSCALAR_RST_REG_INDEX : integer := 17;
constant ISCALAR_RQT_ENABLE_REG_INDEX : integer := 18;
constant OSCALAR_RQT_ENABLE_REG_INDEX : integer := 19;
constant BANK1_INDEX : integer := 16;
signal gp_bank : std_logic; -- bank 0
signal gp_bank1 : std_logic; -- bank 1
signal iscalar_bank : std_logic; -- bank 2
signal oscalar_bank : std_logic; -- bank 3
signal iarg_status_bank : std_logic; -- bank 4
signal oarg_status_bank : std_logic; -- bank 5
signal iscalar_status_bank : std_logic; -- bank 6
signal oscalar_status_bank : std_logic; -- bank 7
signal oarg_length_bank : std_logic; -- bank 8
signal oarg_tdest_bank : std_logic; -- bank 9
signal mux_gp_regs : std_logic_vector(31 downto 0);
signal mux_oscalar_data : std_logic_vector(31 downto 0);
signal mux_iarg_status : std_logic_vector(31 downto 0);
signal mux_oarg_status : std_logic_vector(31 downto 0);
signal mux_iscalar_status : std_logic_vector(31 downto 0);
signal mux_oscalar_status : std_logic_vector(31 downto 0);
signal mux_oarg_tdest_regs : std_logic_vector(31 downto 0);
signal rd_bank_addr : std_logic_vector(BANK_ADDR_WIDTH-1 downto 0);
constant REGS_ADDR_WIDTH : integer := 4; -- Inner address width.
constant N_REGS : integer := 2**REGS_ADDR_WIDTH;
signal reg_sel : std_logic_vector(N_REGS-1 downto 0);
signal rd_reg_addr : std_logic_vector(REGS_ADDR_WIDTH-1 downto 0);
signal ctrl_reg : std_logic_vector(31 downto 0);
signal status_reg : std_logic_vector(31 downto 0);
signal ap_iarg_rst_reg : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal ap_oarg_rst_reg : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal iarg_rqt_enable_reg : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal oarg_rqt_enable_reg : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal oarg_length_mode_reg : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal reg_sel1 : std_logic_vector(N_REGS-1 downto 0);
signal iscalar_rst_reg : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
signal oscalar_rst_reg : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
signal iscalar_rqt_enable_reg : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
signal oscalar_rqt_enable_reg : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
------------------------------------------------
type state_type is (
-- pragma translate_off
stop,
-- pragma translate_on
idle,
read_regs,
write_regs,
send_resp);
signal state : state_type;
signal wr_addr_rdy : std_logic;
signal rd_addr_rdy : std_logic;
signal wr_resp_vld : std_logic;
signal wr_data_rdy : std_logic;
signal rd_data_vld : std_logic;
signal rd_data_ce : std_logic;
signal rd_data : std_logic_vector(31 downto 0);
signal gp_reg_start : std_logic;
signal rd_start : std_logic;
signal wr_start : std_logic;
signal access_start : std_logic;
signal gp_reg_start1 : std_logic;
--------------------------------------------------------------------
-- pragma translate_off
signal mem_rd : std_logic;
signal mem_wr : std_logic;
-- pragma translate_on
signal scalar_reg_start : std_logic;
signal glb_int_en : std_logic;
---------------------
-- INTERRUPT REGs: --
---------------------
constant N_INTS : integer := 8;
signal int_enable_reg : std_logic_vector(N_INTS-1 downto 0);
signal int_flag_reg : std_logic_vector(N_INTS-1 downto 0);
signal int_rqt : std_logic_vector(N_INTS-1 downto 0);
---------------------
-- Syncrhpnoaer signals
---------------------
signal status_iarg_empty_sync : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal oarg_sw_length_we_event : std_logic;
signal oarg_sw_length_we_i : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal host_ioscalar_re_i : std_logic_vector(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS);
signal host_oscalar_re_i : std_logic_vector(C_MAX_N_OSCALARS-1 downto 0);
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF axi_rst1 : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi_rst : SIGNAL IS "true";
begin
----------------------
--- status_iarg_empty Synchronizer
----------------------
EN_STRM_TO_LITE_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 1) generate
begin
XD_IARG_RQT_SYNC : entity axis_accelerator_adapter_v2_1_6.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_MAX_N_IARGS,
C_MTBF_STAGES => 2 --C_MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => status_iarg_empty,
scndry_aclk => S_AXI_ACLK,
scndry_resetn => S_AXI_ARESETN,
scndry_out => open,
scndry_vect_out => status_iarg_empty_sync
);
end generate EN_STRM_TO_LITE_SYNC_GEN;
NO_SYNC_GEN : if (C_PRMRY_IS_ACLK_ASYNC = 0) generate
begin
status_iarg_empty_sync <= status_iarg_empty;
end generate NO_SYNC_GEN;
----------------------
--- status_iarg_empty Synchronizer
----------------------
--axi_rst <= not(S_AXI_ARESETN);
prd1: PROCESS (S_AXI_ACLK, S_AXI_ARESETN)
BEGIN
-- Register Stage #1
IF (S_AXI_ARESETN = '0') THEN
axi_rst1 <= '1';
axi_rst <= '1';
ELSIF (S_AXI_ACLK'event and S_AXI_ACLK = '1') THEN
axi_rst1 <= '0';
axi_rst <= axi_rst1;
END IF;
END PROCESS prd1;
S_AXI_AWREADY <= wr_addr_rdy;
S_AXI_ARREADY <= rd_addr_rdy;
S_AXI_WREADY <= wr_data_rdy;
S_AXI_BVALID <= wr_resp_vld;
S_AXI_BRESP <= AXI_RESP_OKAY;
S_AXI_RDATA <= rd_data;
S_AXI_RVALID <= rd_data_vld;
S_AXI_RRESP <= AXI_RESP_OKAY;
-------------------------------------------
axi_addr <= S_AXI_ARADDR when (S_AXI_ARVALID = '1') else S_AXI_AWADDR;
process(axi_addr)
variable int_addr : integer range 0 to (2**BANK_ADDR_WIDTH)-1;
begin
gp_bank <= '0';
gp_bank1 <= '0';
iscalar_bank <= '0';
oscalar_bank <= '0';
iarg_status_bank <= '0';
oarg_status_bank <= '0';
iscalar_status_bank <= '0';
oscalar_status_bank <= '0';
oarg_length_bank <= '0';
oarg_tdest_bank <= '0';
int_addr := to_integer(unsigned(axi_addr(BANK_ADDR_MSB downto BANK_ADDR_LSB)));
case int_addr is
when GP_REGS_BANK_ADDR => gp_bank <= '1';
when GP_REGS_BANK1_ADDR => gp_bank1 <= '1';
when ISCALAR_BANK_ADDR => iscalar_bank <= '1';
when OSCALAR_BANK_ADDR => oscalar_bank <= '1';
when IARG_STATUS_BANK_ADDR => iarg_status_bank <= '1';
when OARG_STATUS_BANK_ADDR => oarg_status_bank <= '1';
when ISCALAR_STATUS_BANK_ADDR => iscalar_status_bank <= '1';
when OSCALAR_STATUS_BANK_ADDR => oscalar_status_bank <= '1';
when OARG_LENGTH_BANK_ADDR => oarg_length_bank <= '1';
when OARG_TDEST_BANK_ADDR => oarg_tdest_bank <= '1';
when others =>
end case;
end process;
process(S_AXI_ACLK)
constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
constant MSB : integer := LSB+REGS_ADDR_WIDTH-1;
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(rd_start = '1') then
rd_reg_addr <= S_AXI_ARADDR(MSB downto LSB);
end if;
end if;
end process;
process(S_AXI_ACLK)
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(rd_start = '1') then
rd_bank_addr <= S_AXI_ARADDR(BANK_ADDR_MSB downto BANK_ADDR_LSB);
end if;
end if;
end process;
process(S_AXI_ACLK, axi_rst)
begin
if(axi_rst = '1') then
state <= idle;
wr_resp_vld <= '0';
rd_data_vld <= '0';
rd_addr_rdy <= '0';
wr_addr_rdy <= '0';
wr_data_rdy <= '0';
-- pragma translate_off
mem_rd <= '0';
mem_wr <= '0';
-- pragma translate_on
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
rd_addr_rdy <= '0';
wr_addr_rdy <= '0';
wr_data_rdy <= '0';
-- pragma translate_off
mem_rd <= '0';
mem_wr <= '0';
-- pragma translate_on
case state is
when idle =>
if(S_AXI_ARVALID = '1') then
state <= read_regs;
rd_addr_rdy <= '1';
elsif(S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- During write accesses it's waited until both both address and
-- write data are stables.
state <= write_regs;
wr_addr_rdy <= '1';
wr_data_rdy <= '1';
end if;
when read_regs =>
state <= send_resp;
rd_data_vld <= '1';
when write_regs =>
state <= send_resp;
wr_resp_vld <= '1';
when send_resp =>
if ((wr_resp_vld = '1' and S_AXI_BREADY = '1') or
(rd_data_vld = '1' and S_AXI_RREADY = '1')) then
wr_resp_vld <= '0';
rd_data_vld <= '0';
state <= idle;
end if;
when others =>
end case;
end if;
end process;
process(state, gp_bank, gp_bank1, S_AXI_ARVALID, S_AXI_AWVALID, S_AXI_WVALID)
begin
rd_data_ce <= '0';
gp_reg_start <= '0';
gp_reg_start1 <= '0';
scalar_reg_start <= '0';
rd_start <= '0';
wr_start <= '0';
access_start <= '0';
case state is
when idle =>
rd_start <= S_AXI_ARVALID;
wr_start <= S_AXI_AWVALID and S_AXI_WVALID;
access_start <= S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID);
gp_reg_start <= gp_bank and (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID));
gp_reg_start1 <= gp_bank1 and (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID));
when read_regs =>
rd_data_ce <= '1';
when write_regs =>
when send_resp =>
when others =>
end case;
end process;
--------------------
-- INPUT DATAPATH --
--------------------
process(S_AXI_ACLK)
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
wr_data_i <= S_AXI_WDATA;
end if;
end process;
-----------------------------------------
--- BANK 0: GENERAL PURPOSE REGISTERS ---
-----------------------------------------
-- Selection signal generation for inner registers:
process(S_AXI_ACLK)
variable offset : unsigned(REGS_ADDR_WIDTH-1 downto 0);
constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
constant MSB : integer := LSB+REGS_ADDR_WIDTH-1;
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(axi_rst = '1' or wr_data_rdy = '1' or rd_data_vld = '1') then
reg_sel <= (others => '0');
elsif(gp_reg_start = '1') then
offset := unsigned(axi_addr(MSB downto LSB));
for i in reg_sel'range loop
if(offset = i) then
reg_sel(i) <= '1';
else
reg_sel(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
---------------------------------
-- CONTROL REGISTER (INDEX 0) --
---------------------------------
process(S_AXI_ACLK, axi_rst)
begin
if(axi_rst = '1') then
ctrl_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(CTRL_REG_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to STRB_WIDTH-1 loop
if(S_AXI_WSTRB(i) = '1') then
ctrl_reg(8*(i+1)-1 downto 8*i) <= S_AXI_WDATA(8*(i+1)-1 downto 8*i);
end if;
end loop;
end if;
end if;
end process;
ap_rst_i <= ctrl_reg(0) or axi_rst;
glb_int_en <= ctrl_reg(1);
process(S_AXI_ACLK, axi_rst)
begin
if(axi_rst = '1') then
ap_rst <= '1';
ap_rst_fb <= '1';
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
ap_rst <= ap_rst_i;
ap_rst_fb <= ap_rst_i;
end if;
end process;
--------------------------------
-- STATUS REGISTER (INDEX 1) --
--------------------------------
status_reg(0) <= status_ap_start;
status_reg(1) <= status_ap_done;
status_reg(2) <= status_ap_idle;
status_reg(3) <= status_ap_ready;
status_reg(31 downto 4) <= (others => '0');
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
status_ap_start_clr <= '0';
status_ap_done_clr <= '0';
status_ap_idle_clr <= '0';
status_ap_ready_clr <= '0';
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
status_ap_start_clr <= reg_sel(STATUS_REG_INDEX) and wr_data_rdy and S_AXI_WSTRB(0) and S_AXI_WDATA(0);
status_ap_done_clr <= reg_sel(STATUS_REG_INDEX) and wr_data_rdy and S_AXI_WSTRB(0) and S_AXI_WDATA(1);
status_ap_idle_clr <= reg_sel(STATUS_REG_INDEX) and wr_data_rdy and S_AXI_WSTRB(0) and S_AXI_WDATA(2);
status_ap_ready_clr <= reg_sel(STATUS_REG_INDEX) and wr_data_rdy and S_AXI_WSTRB(0) and S_AXI_WDATA(3);
end if;
end process;
-----------------------------------------------------
-- INPUT ARG MULTIBUFFER RESET REGISTER (INDEX 2) --
-----------------------------------------------------
IARGS_RST_GEN : if (C_N_INPUT_ARGS > 0) generate
signal reg : std_logic_vector(C_N_INPUT_ARGS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(IARG_RST_REG_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INPUT_ARGS-1 loop
reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(reg)
begin
host_iarg_rst <= (others => '0');
ap_iarg_rst_reg <= (others => '0');
host_iarg_rst(reg'range) <= reg;
ap_iarg_rst_reg(reg'range) <= reg;
end process;
end generate IARGS_RST_GEN;
NO_IARGS_RST_GEN : if (C_N_INPUT_ARGS = 0) generate
begin
host_iarg_rst <= (others => '0');
ap_iarg_rst_reg <= (others => '0');
end generate NO_IARGS_RST_GEN;
------------------------------------------------------
-- OUTPUT ARG MULTIBUFFER RESET REGISTER (INDEX 3) --
------------------------------------------------------
OARGS_RST_GEN : if (C_N_OUTPUT_ARGS > 0) generate
signal reg : std_logic_vector(C_N_OUTPUT_ARGS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(OARG_RST_REG_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_OUTPUT_ARGS-1 loop
reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(reg)
begin
host_oarg_rst <= (others => '0');
ap_oarg_rst_reg <= (others => '0');
host_oarg_rst(reg'range) <= reg;
ap_oarg_rst_reg(reg'range) <= reg;
end process;
end generate OARGS_RST_GEN;
NO_OARGS_RST_GEN : if (C_N_OUTPUT_ARGS = 0) generate
begin
host_oarg_rst <= (others => '0');
ap_oarg_rst_reg <= (others => '0');
end generate NO_OARGS_RST_GEN;
--------------------------------------------------
-- INPUT ARG REQUEST ENABLE REGISTER (INDEX 4) --
--------------------------------------------------
IARG_RQT_ENABLE_GEN : if (C_N_INPUT_ARGS > 0) generate
signal reg : std_logic_vector(C_N_INPUT_ARGS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
-- reg <= (others => '0');
reg <= (others => '1');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(IARG_RQT_ENABLE_REG_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INPUT_ARGS-1 loop
reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(reg)
begin
iarg_rqt_enable <= (others => '0');
iarg_rqt_enable_reg <= (others => '0');
iarg_rqt_enable(reg'range) <= reg;
iarg_rqt_enable_reg(reg'range) <= reg;
end process;
end generate IARG_RQT_ENABLE_GEN;
NO_IARG_RQT_ENABLE_GEN : if (C_N_INPUT_ARGS = 0) generate
begin
iarg_rqt_enable <= (others => '0');
iarg_rqt_enable_reg <= (others => '0');
end generate NO_IARG_RQT_ENABLE_GEN;
---------------------------------------------------
-- OUTPUT ARG REQUEST ENABLE REGISTER (INDEX 5) --
---------------------------------------------------
OARG_RQT_ENABLE_GEN : if (C_N_OUTPUT_ARGS > 0) generate
signal reg : std_logic_vector(C_N_OUTPUT_ARGS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
-- reg <= (others => '0');
reg <= (others => '1');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(OARG_RQT_ENABLE_REG_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_OUTPUT_ARGS-1 loop
reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(reg)
begin
oarg_rqt_enable <= (others => '0');
oarg_rqt_enable_reg <= (others => '0');
oarg_rqt_enable(reg'range) <= reg;
oarg_rqt_enable_reg(reg'range) <= reg;
end process;
end generate OARG_RQT_ENABLE_GEN;
NO_OARG_RQT_ENABLE_GEN : if (C_N_OUTPUT_ARGS = 0) generate
begin
oarg_rqt_enable <= (others => '0');
oarg_rqt_enable_reg <= (others => '0');
end generate NO_OARG_RQT_ENABLE_GEN;
---------------------------------
-- COMMAND REGISTER (INDEX 10) --
---------------------------------
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
host_cmd_we <= '0';
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
host_cmd_we <= reg_sel(COMMAND_REG_INDEX) and wr_data_rdy;
end if;
end process;
host_cmd_data <= wr_data_i;
-----------------------------------
-- COMPLETE REGISTER (INDEX 11) --
-----------------------------------
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
host_complete_re <= '0';
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
host_complete_re <= reg_sel(COMPLETE_REG_INDEX) and rd_data_vld; -- ????
end if;
end process;
--------------------------
-- INTERRUPT MANAGEMENT --
--------------------------
------------------------------------------
-- INTERRUPT ENABLE REGISTER (INDEX 12) --
------------------------------------------
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
int_enable_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(INT_ENABLE_REG_INDEX) = '1' and wr_data_rdy = '1') then
int_enable_reg <= S_AXI_WDATA(N_INTS-1 downto 0);
end if;
end if;
end process;
-- Individual asigment for each interrupt source:
int_rqt(0) <= host_cmd_error;
int_rqt(N_INTS-1 downto 1) <= (others => '0');
----------------------------------------
-- INTERRUPT FLAG REGISTER (INDEX 13) --
----------------------------------------
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
int_flag_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(INT_FLAG_REG_INDEX) = '1' and wr_data_rdy = '1') then
int_flag_reg <= int_flag_reg and not(S_AXI_WDATA(N_INTS-1 downto 0));
else
int_flag_reg <= int_flag_reg or int_rqt;
end if;
end if;
end process;
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
interrupt <= '0';
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
interrupt <= or_reduce(int_flag_reg and int_enable_reg) and glb_int_en;
end if;
end process;
-----------------------------------------
--- BANK 1: GENERAL PURPOSE REGISTERS ---
-----------------------------------------
-- Selection signal generation for inner registers:
process(S_AXI_ACLK)
variable offset : unsigned(REGS_ADDR_WIDTH-1 downto 0);
constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
constant MSB : integer := LSB+REGS_ADDR_WIDTH-1;
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(ap_rst_fb = '1' or wr_data_rdy = '1' or rd_data_vld = '1') then
reg_sel1 <= (others => '0');
elsif(gp_reg_start1 = '1') then
offset := unsigned(axi_addr(MSB downto LSB));
for i in reg_sel1'range loop
if(offset = i) then
reg_sel1(i) <= '1';
else
reg_sel1(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
-------------------------------------------------
-- INPUT SCALAR FIFO RESET REGISTER (INDEX 16) --
-------------------------------------------------
ISCALAR_RST_GEN : if (C_N_INPUT_SCALARS > 0) generate
signal rst_reg : std_logic_vector(C_N_INPUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
rst_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(ISCALAR_RST_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INPUT_SCALARS-1 loop
rst_reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(rst_reg)
begin
host_iscalar_rst(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
iscalar_rst_reg(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
host_iscalar_rst(rst_reg'range) <= rst_reg;
iscalar_rst_reg(rst_reg'range) <= rst_reg;
end process;
end generate ISCALAR_RST_GEN;
NO_ISCALAR_RST_GEN : if (C_N_INPUT_SCALARS = 0) generate
begin
host_iscalar_rst(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
iscalar_rst_reg(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
end generate NO_ISCALAR_RST_GEN;
ISCALAR_IO_RST_GEN : if (C_N_INOUT_SCALARS > 0) generate
signal rst_reg : std_logic_vector(C_N_INOUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
rst_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(ISCALAR_RST_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INOUT_SCALARS-1 loop
rst_reg(i) <= S_AXI_WDATA(i+C_MAX_N_ISCALARS) and S_AXI_WSTRB((i+C_MAX_N_ISCALARS)/8);
end loop;
end if;
end if;
end process;
process(rst_reg)
begin
host_iscalar_rst(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
iscalar_rst_reg(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
host_iscalar_rst(C_MAX_N_ISCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_ISCALARS) <= rst_reg;
iscalar_rst_reg(C_MAX_N_ISCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_ISCALARS) <= rst_reg;
end process;
end generate ISCALAR_IO_RST_GEN;
NO_ISCALAR_IO_RST_GEN : if (C_N_INOUT_SCALARS = 0) generate
begin
host_iscalar_rst(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
iscalar_rst_reg(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
end generate NO_ISCALAR_IO_RST_GEN;
--------------------------------------------------
-- OUTPUT SCALAR FIFO RESET REGISTER (INDEX 17) --
--------------------------------------------------
OSCALAR_RST_GEN : if (C_N_OUTPUT_SCALARS > 0) generate
signal rst_reg : std_logic_vector(C_N_OUTPUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
rst_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(OSCALAR_RST_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_OUTPUT_SCALARS-1 loop
rst_reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(rst_reg)
begin
host_oscalar_rst(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
oscalar_rst_reg(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
host_oscalar_rst(rst_reg'range) <= rst_reg;
oscalar_rst_reg(rst_reg'range) <= rst_reg;
end process;
end generate OSCALAR_RST_GEN;
NO_OSCALAR_RST_GEN : if (C_N_OUTPUT_SCALARS = 0) generate
begin
host_oscalar_rst(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
oscalar_rst_reg(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
end generate NO_OSCALAR_RST_GEN;
OSCALAR_IO_RST_GEN : if (C_N_INOUT_SCALARS > 0) generate
signal os_rst_reg : std_logic_vector(C_N_INOUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
os_rst_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(OSCALAR_RST_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INOUT_SCALARS-1 loop
os_rst_reg(i) <= S_AXI_WDATA(i+C_MAX_N_OSCALARS) and S_AXI_WSTRB((i+C_MAX_N_OSCALARS)/8);
end loop;
end if;
end if;
end process;
process(os_rst_reg)
begin
host_oscalar_rst(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
oscalar_rst_reg(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
host_oscalar_rst(C_MAX_N_OSCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_OSCALARS) <= os_rst_reg;
oscalar_rst_reg(C_MAX_N_OSCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_OSCALARS) <= os_rst_reg;
end process;
end generate OSCALAR_IO_RST_GEN;
NO_OSCALAR_IO_RST_GEN : if (C_N_INOUT_SCALARS = 0) generate
begin
host_oscalar_rst(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
oscalar_rst_reg(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
end generate NO_OSCALAR_IO_RST_GEN;
-----------------------------------------------------
-- INPUT SCALAR REQUEST ENABLE REGISTER (INDEX 18) --
-----------------------------------------------------
ISCALAR_RQT_ENABLE_GEN : if (C_N_INPUT_SCALARS > 0) generate
signal reg : std_logic_vector(C_N_INPUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
-- reg <= (others => '0');
reg <= (others => '1');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(ISCALAR_RQT_ENABLE_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INPUT_SCALARS-1 loop
reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(reg)
begin
iscalar_rqt_enable(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
iscalar_rqt_enable_reg(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
iscalar_rqt_enable(reg'range) <= reg;
iscalar_rqt_enable_reg(reg'range) <= reg;
end process;
end generate ISCALAR_RQT_ENABLE_GEN;
NO_ISCALAR_RQT_ENABLE_GEN : if (C_N_INPUT_SCALARS = 0) generate
begin
iscalar_rqt_enable(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
iscalar_rqt_enable_reg(C_MAX_N_ISCALARS-1 downto 0) <= (others => '0');
end generate NO_ISCALAR_RQT_ENABLE_GEN;
ISCALAR_IO_RQT_ENABLE_GEN : if (C_N_INOUT_SCALARS > 0) generate
signal rqt_reg : std_logic_vector(C_N_INOUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
-- reg <= (others => '0');
rqt_reg <= (others => '1');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(ISCALAR_RQT_ENABLE_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INOUT_SCALARS-1 loop
rqt_reg(i) <= S_AXI_WDATA(i+C_MAX_N_ISCALARS) and S_AXI_WSTRB((i+C_MAX_N_ISCALARS)/8);
end loop;
end if;
end if;
end process;
process(rqt_reg)
begin
iscalar_rqt_enable(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
iscalar_rqt_enable_reg(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
iscalar_rqt_enable(C_MAX_N_ISCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_ISCALARS) <= rqt_reg;
iscalar_rqt_enable_reg(C_MAX_N_ISCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_ISCALARS) <= rqt_reg;
end process;
end generate ISCALAR_IO_RQT_ENABLE_GEN;
NO_ISCALAR_IO_RQT_ENABLE_GEN : if (C_N_INOUT_SCALARS = 0) generate
begin
iscalar_rqt_enable(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
iscalar_rqt_enable_reg(C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
end generate NO_ISCALAR_IO_RQT_ENABLE_GEN;
------------------------------------------------------
-- OUTPUT SCALAR REQUEST ENABLE REGISTER (INDEX 19) --
------------------------------------------------------
OSCALAR_RQT_ENABLE_GEN : if (C_N_OUTPUT_SCALARS > 0) generate
signal reg : std_logic_vector(C_N_OUTPUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
-- reg <= (others => '0');
reg <= (others => '1');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(OSCALAR_RQT_ENABLE_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_OUTPUT_SCALARS-1 loop
reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(reg)
begin
oscalar_rqt_enable(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
oscalar_rqt_enable_reg(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
oscalar_rqt_enable(reg'range) <= reg;
oscalar_rqt_enable_reg(reg'range) <= reg;
end process;
end generate OSCALAR_RQT_ENABLE_GEN;
NO_OSCALAR_RQT_ENABLE_GEN : if (C_N_OUTPUT_SCALARS = 0) generate
begin
oscalar_rqt_enable(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
oscalar_rqt_enable_reg(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
end generate NO_OSCALAR_RQT_ENABLE_GEN;
OSCALAR_IO_RQT_ENABLE_GEN : if (C_N_INOUT_SCALARS > 0) generate
signal os_rqt_reg : std_logic_vector(C_N_INOUT_SCALARS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
-- reg <= (others => '0');
os_rqt_reg <= (others => '1');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel1(OSCALAR_RQT_ENABLE_REG_INDEX-BANK1_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_INOUT_SCALARS-1 loop
os_rqt_reg(i) <= S_AXI_WDATA(i+C_MAX_N_OSCALARS) and S_AXI_WSTRB((i+C_MAX_N_OSCALARS)/8);
end loop;
end if;
end if;
end process;
process(os_rqt_reg)
begin
oscalar_rqt_enable(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
oscalar_rqt_enable_reg(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
oscalar_rqt_enable(C_MAX_N_OSCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_OSCALARS) <= os_rqt_reg;
oscalar_rqt_enable_reg(C_MAX_N_OSCALARS+C_N_INOUT_SCALARS-1 downto C_MAX_N_OSCALARS) <= os_rqt_reg;
end process;
end generate OSCALAR_IO_RQT_ENABLE_GEN;
NO_OSCALAR_IO_RQT_ENABLE_GEN : if (C_N_INOUT_SCALARS = 0) generate
begin
oscalar_rqt_enable(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
oscalar_rqt_enable_reg(C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
end generate NO_OSCALAR_IO_RQT_ENABLE_GEN;
-------------------------------------------------
-- OUTPUT ARGS LENGTH MODE REGISTER (INDEX 15) --
-------------------------------------------------
OARG_USE_SW_LENGTH_GEN : if (C_N_OUTPUT_ARGS > 0) generate
signal reg : std_logic_vector(C_N_OUTPUT_ARGS-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(reg_sel(OARG_LENGTH_MODE_REG_INDEX) = '1' and wr_data_rdy = '1') then
for i in 0 to C_N_OUTPUT_ARGS-1 loop
reg(i) <= S_AXI_WDATA(i) and S_AXI_WSTRB(i/8);
end loop;
end if;
end if;
end process;
process(reg)
begin
oarg_use_sw_length <= (others => '0');
oarg_length_mode_reg <= (others => '0');
oarg_use_sw_length(reg'range) <= reg;
oarg_length_mode_reg(reg'range) <= reg;
end process;
end generate OARG_USE_SW_LENGTH_GEN;
NO_OARG_USE_SW_LENGTH_GEN : if (C_N_OUTPUT_ARGS = 0) generate
begin
oarg_use_sw_length <= (others => '0');
oarg_length_mode_reg <= (others => '0');
end generate NO_OARG_USE_SW_LENGTH_GEN;
----------------------------
-- BANK 0 OUTPUT DATAPATH --
----------------------------
-- For V6/S6, when the number of channel of the multiplexer is lower than 16 it's more
-- efficient to use a mux with binary selection input.
-- Mux for general purpose register read datapath:
process(rd_reg_addr,
ctrl_reg, status_reg,
ap_iarg_rst_reg, ap_oarg_rst_reg,
iarg_rqt_enable_reg, oarg_rqt_enable_reg,
oarg_length_mode_reg)
variable addr : integer range 0 to N_REGS-1;
begin
mux_gp_regs <= (others => '0');
addr := to_integer(unsigned(rd_reg_addr));
case addr is
when CTRL_REG_INDEX => mux_gp_regs <= ext_32(ctrl_reg);
when STATUS_REG_INDEX => mux_gp_regs <= ext_32(status_reg);
when IARG_RST_REG_INDEX => mux_gp_regs <= ext_32(ap_iarg_rst_reg);
when OARG_RST_REG_INDEX => mux_gp_regs <= ext_32(ap_oarg_rst_reg);
when IARG_RQT_ENABLE_REG_INDEX => mux_gp_regs <= ext_32(iarg_rqt_enable_reg);
when OARG_RQT_ENABLE_REG_INDEX => mux_gp_regs <= ext_32(oarg_rqt_enable_reg);
when OARG_LENGTH_MODE_REG_INDEX => mux_gp_regs <= ext_32(oarg_length_mode_reg);
when others =>
end case;
end process;
----------------------------------
--- BANK 2: INPUT SCALAR FIFOs ---
----------------------------------
process(S_AXI_ACLK, ap_rst_fb)
constant N_ELEMENTS : integer := C_MAX_N_ISCALARS + C_MAX_N_IOSCALARS;
constant BANK_ADDR_WIDTH : integer := log2(N_ELEMENTS);
variable offset : unsigned(BANK_ADDR_WIDTH-1 downto 0);
constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
constant MSB : integer := LSB+BANK_ADDR_WIDTH-1;
begin
if(ap_rst_fb = '1') then
host_iscalar_we <= (others => '0');
--host_oscalar_re(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS -1 downto C_MAX_N_OSCALARS) <= (others => '0');
host_ioscalar_re_i <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
host_iscalar_we <= (others => '0');
--host_oscalar_re(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS -1 downto C_MAX_N_OSCALARS) <= (others => '0');
host_ioscalar_re_i <= (others => '0');
if(iscalar_bank = '1' and wr_start = '1') then
offset := unsigned(axi_addr(MSB downto LSB));
for i in 0 to N_ELEMENTS-1 loop
if(offset = i) then
host_iscalar_we(i) <= '1';
else
host_iscalar_we(i) <= '0';
end if;
end loop;
end if;
if(iscalar_bank = '1' and rd_start = '1') then
offset := unsigned(axi_addr(MSB downto LSB));
for i in C_MAX_N_ISCALARS to C_MAX_N_ISCALARS + C_MAX_N_IOSCALARS-1 loop
if(offset = i) then
--host_oscalar_re(i) <= '1';
host_ioscalar_re_i(i) <= '1';
else
--host_oscalar_re(i) <= '0';
host_ioscalar_re_i(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
host_iscalar_dout <= wr_data_i;
host_oscalar_re <= host_ioscalar_re_i & host_oscalar_re_i;
-----------------------------------
--- BANK 3: OUTPUT SCALAR FIFOs ---
-----------------------------------
process(S_AXI_ACLK, ap_rst_fb)
constant N_ELEMENTS : integer := C_MAX_N_OSCALARS;
constant BANK_ADDR_WIDTH : integer := log2(N_ELEMENTS);
variable offset : unsigned(BANK_ADDR_WIDTH-1 downto 0);
constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
constant MSB : integer := LSB+BANK_ADDR_WIDTH-1;
begin
if(ap_rst_fb = '1') then
--host_oscalar_re(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
host_oscalar_re_i(C_MAX_N_OSCALARS-1 downto 0) <=(others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
--host_oscalar_re(C_MAX_N_OSCALARS-1 downto 0) <= (others => '0');
host_oscalar_re_i(C_MAX_N_OSCALARS-1 downto 0) <=(others => '0');
if(oscalar_bank = '1' and rd_start = '1') then
offset := unsigned(axi_addr(MSB downto LSB));
for i in 0 to N_ELEMENTS-1 loop
if(offset = i) then
--host_oscalar_re(i) <= '1';
host_oscalar_re_i(i) <='1';
else
-- host_oscalar_re(i) <= '0';
host_oscalar_re_i(i) <='0';
end if;
end loop;
end if;
end if;
end process;
-- process(S_AXI_ACLK, ap_rst_fb)
-- constant N_ELEMENTS : integer := C_MAX_N_OSCALARS;
--
-- constant BANK_ADDR_WIDTH : integer := log2(N_ELEMENTS);
-- variable offset : unsigned(BANK_ADDR_WIDTH-1 downto 0);
-- constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
-- constant MSB : integer := LSB+BANK_ADDR_WIDTH-1;
-- begin
-- if(ap_rst_fb = '1') then
-- host_oscalar_re(7 downto 0) <= (others => '0');
-- elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- host_oscalar_re(7 downto 0) <= (others => '0');
-- if(oscalar_bank = '1' and rd_start = '1') then
-- offset := unsigned(axi_addr(MSB downto LSB));
-- for i in 0 to 7 loop
-- if(offset = i) then
-- host_oscalar_re(i) <= '1';
-- else
-- host_oscalar_re(i) <= '0';
-- end if;
-- end loop;
-- end if;
-- end if;
-- end process;
-- Output scalar data mux:
process(rd_reg_addr, host_oscalar_din)
begin
mux_oscalar_data <= (others => '0');
for i in 0 to C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 loop
if(i = unsigned(rd_reg_addr)) then
mux_oscalar_data <= ext_32(host_oscalar_din(C_MAX_SCALAR_DWIDTH*(i+1)-1 downto C_MAX_SCALAR_DWIDTH*i));
end if;
end loop;
end process;
-- -----------------------------------
-- --- BANK 2: INOUT SCALAR FIFOs ---
-- -----------------------------------
--
-- process(S_AXI_ACLK, ap_rst_fb)
-- constant N_ELEMENTS : integer := C_MAX_N_OSCALARS + C_MAX_N_IOSCALARS;
--
-- constant BANK_ADDR_WIDTH : integer := log2(N_ELEMENTS);
-- variable offset : unsigned(BANK_ADDR_WIDTH-1 downto 0);
-- constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
-- constant MSB : integer := LSB+BANK_ADDR_WIDTH-1;
-- begin
-- if(ap_rst_fb = '1') then
-- host_oscalar_re(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
-- host_iscalar_we(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
-- elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
-- host_oscalar_re(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto C_MAX_N_OSCALARS) <= (others => '0');
-- host_iscalar_we(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto C_MAX_N_ISCALARS) <= (others => '0');
-- if(iscalar_bank = '1' and wr_start = '1') then
-- offset := unsigned(axi_addr(MSB downto LSB));
-- for i in 8 to N_ELEMENTS-1 loop
-- if(offset = i) then
-- host_iscalar_we(i) <= '1';
-- else
-- host_iscalar_we(i) <= '0';
-- end if;
-- end loop;
-- end if;
-- if(iscalar_bank = '1' and rd_start = '1') then
-- offset := unsigned(axi_addr(MSB downto LSB));
-- for i in 8 to N_ELEMENTS-1 loop
-- if(offset = i) then
-- host_oscalar_re(i) <= '1';
-- else
-- host_oscalar_re(i) <= '0';
-- end if;
-- end loop;
-- end if;
-- end if;
-- end process;
--
------------------------------------------
--- BANK 4: INPUT ARG STATUS REGISTERS ---
------------------------------------------
-- Status registers for input arguments:
process(rd_reg_addr, status_iarg_used, status_iarg_empty_sync, status_iarg_full)
begin
mux_iarg_status <= (others => '0');
for i in 0 to C_MAX_N_IARGS-1 loop
if(i = unsigned(rd_reg_addr)) then
mux_iarg_status(3 downto 0) <= status_iarg_used(4*(i+1)-1 downto 4*i);
mux_iarg_status(4) <= status_iarg_empty_sync(i);
mux_iarg_status(5) <= status_iarg_full(i);
end if;
end loop;
end process;
-------------------------------------------
--- BANK 5: OUTPUT ARG STATUS REGISTERS ---
-------------------------------------------
-- Status registers for output arguments:
process(rd_reg_addr, status_oarg_used, status_oarg_empty, status_oarg_full)
begin
mux_oarg_status <= (others => '0');
for i in 0 to C_MAX_N_OARGS-1 loop
if(i = unsigned(rd_reg_addr)) then
mux_oarg_status(3 downto 0) <= status_oarg_used(4*(i+1)-1 downto 4*i);
mux_oarg_status(4) <= status_oarg_empty(i);
mux_oarg_status(5) <= status_oarg_full(i);
end if;
end loop;
end process;
---------------------------------------------
--- BANK 6: INPUT SCALAR STATUS REGISTERS ---
---------------------------------------------
-- Status registers for input scalars:
process(rd_reg_addr, status_iscalar_used, status_iscalar_empty, status_iscalar_full)
begin
mux_iscalar_status <= (others => '0');
for i in 0 to C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 loop
if(i = unsigned(rd_reg_addr)) then
mux_iscalar_status(3 downto 0) <= status_iscalar_used(4*(i+1)-1 downto 4*i);
mux_iscalar_status(4) <= status_iscalar_empty(i);
mux_iscalar_status(5) <= status_iscalar_full(i);
end if;
end loop;
end process;
----------------------------------------------
--- BANK 7: OUTPUT SCALAR STATUS REGISTERS ---
----------------------------------------------
-- Status registers for output scalars:
process(rd_reg_addr, status_oscalar_used, status_oscalar_empty, status_oscalar_full)
begin
mux_oscalar_status <= (others => '0');
for i in 0 to C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS-1 loop
if(i = unsigned(rd_reg_addr)) then
mux_oscalar_status(3 downto 0) <= status_oscalar_used(4*(i+1)-1 downto 4*i);
mux_oscalar_status(4) <= status_oscalar_empty(i);
mux_oscalar_status(5) <= status_oscalar_full(i);
end if;
end loop;
end process;
-------------------------------------------
--- BANK 8: OUTPUT ARGS SW LENGTH FIFOs ---
--------------------------------------------
process(S_AXI_ACLK, ap_rst_fb)
constant N_ELEMENTS : integer := C_MAX_N_OARGS;
constant BANK_ADDR_WIDTH : integer := log2(N_ELEMENTS);
variable offset : unsigned(BANK_ADDR_WIDTH-1 downto 0);
constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
constant MSB : integer := LSB+BANK_ADDR_WIDTH-1;
begin
if(ap_rst_fb = '1') then
oarg_sw_length_we_i <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
oarg_sw_length_we_i <= (others => '0');
if(oarg_length_bank = '1' and wr_start = '1') then
offset := unsigned(axi_addr(MSB downto LSB));
for i in 0 to N_ELEMENTS-1 loop
if(offset = i) then
oarg_sw_length_we_i(i) <= '1';
else
oarg_sw_length_we_i(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
--oarg_sw_length <= wr_data_i;
oarg_sw_length_we_event <= or_reduce(oarg_sw_length_we_i);
oarg_sw_length_we <= oarg_sw_length_we_i;
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
oarg_sw_length <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(oarg_sw_length_we_event = '1') then
oarg_sw_length <= wr_data_i;
end if;
end if;
end process;
process(S_AXI_ACLK)
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(oarg_sw_length_we_event = '1') then
oarg_sw_length_m2s <= wr_data_i;
end if;
end if;
end process;
-------------------------------------------
--- BANK 9: OUTPUT ARGS TDEST REGISTERS ---
-------------------------------------------
OARG_TDEST_GEN : if (C_N_OUTPUT_ARGS > 0) generate
signal oarg_tdest_reg_we : std_logic_vector(N_REGS-1 downto 0);
signal oarg_tdest_reg : std_logic_vector(C_N_OUTPUT_ARGS*C_M_AXIS_TDEST_WIDTH-1 downto 0);
begin
process(S_AXI_ACLK, ap_rst_fb)
constant N_ELEMENTS : integer := C_MAX_N_OARGS;
constant BANK_ADDR_WIDTH : integer := log2(N_ELEMENTS);
variable offset : unsigned(BANK_ADDR_WIDTH-1 downto 0);
constant LSB : integer := log2(C_S_AXI_DATA_WIDTH/8);
constant MSB : integer := LSB+BANK_ADDR_WIDTH-1;
begin
if(ap_rst_fb = '1') then
oarg_tdest_reg_we <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
oarg_tdest_reg_we <= (others => '0');
if(oarg_tdest_bank = '1' and wr_start = '1') then
offset := unsigned(axi_addr(MSB downto LSB));
for i in 0 to N_ELEMENTS-1 loop
if(offset = i) then
oarg_tdest_reg_we(i) <= '1';
else
oarg_tdest_reg_we(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
process(S_AXI_ACLK, ap_rst_fb)
begin
if(ap_rst_fb = '1') then
oarg_tdest_reg <= (others => '0');
elsif(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
for i in 0 to C_N_OUTPUT_ARGS-1 loop
if(oarg_tdest_reg_we(i) = '1') then
oarg_tdest_reg(C_M_AXIS_TDEST_WIDTH*(i+1)-1 downto C_M_AXIS_TDEST_WIDTH*i) <=
S_AXI_WDATA(C_M_AXIS_TDEST_WIDTH-1 downto 0);
end if;
end loop;
end if;
end process;
process(rd_reg_addr, oarg_tdest_reg)
variable addr : integer range 0 to N_REGS-1;
begin
mux_oarg_tdest_regs <= (others => '0');
addr := to_integer(unsigned(rd_reg_addr));
for i in 0 to C_N_OUTPUT_ARGS-1 loop
if(i = addr) then
mux_oarg_tdest_regs <= ext_32(oarg_tdest_reg(C_M_AXIS_TDEST_WIDTH*(i+1)-1 downto C_M_AXIS_TDEST_WIDTH*i));
end if;
end loop;
end process;
process(oarg_tdest_reg)
begin
host_oarg_tdest <= (others => '0');
host_oarg_tdest(C_N_OUTPUT_ARGS*C_M_AXIS_TDEST_WIDTH-1 downto 0) <= oarg_tdest_reg;
end process;
end generate OARG_TDEST_GEN;
NO_OARG_TDEST_GEN : if (C_N_OUTPUT_ARGS = 0) generate
begin
mux_oarg_tdest_regs <= (others => '0');
host_oarg_tdest <= (others => '0');
end generate NO_OARG_TDEST_GEN;
---------------------
-- OUTPUT DATAPATH --
---------------------
process(S_AXI_ACLK)
variable int_addr : integer range 0 to (2**BANK_ADDR_WIDTH)-1;
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if(axi_rst = '1' or (rd_data_vld and S_AXI_RREADY) = '1') then
rd_data <= (others => '0');
elsif(rd_data_ce = '1') then
int_addr := to_integer(unsigned(rd_bank_addr));
case int_addr is
when GP_REGS_BANK_ADDR => rd_data <= mux_gp_regs;
when OSCALAR_BANK_ADDR => rd_data <= mux_oscalar_data;
when ISCALAR_BANK_ADDR => rd_data <= mux_oscalar_data;
when IARG_STATUS_BANK_ADDR => rd_data <= mux_iarg_status;
when OARG_STATUS_BANK_ADDR => rd_data <= mux_oarg_status;
when ISCALAR_STATUS_BANK_ADDR => rd_data <= mux_iscalar_status;
when OSCALAR_STATUS_BANK_ADDR => rd_data <= mux_oscalar_status;
when OARG_TDEST_BANK_ADDR => rd_data <= mux_oarg_tdest_regs;
when others => rd_data <= (others => '0');
end case;
end if;
end if;
end process;
end rtl;
| mit |
agural/FPGA-Oscilloscope | osc/lpm_compare3.vhd | 1 | 4424 | -- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare3.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare3 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
aeb : OUT STD_LOGIC
);
END lpm_compare3;
ARCHITECTURE SYN OF lpm_compare3 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aeb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(5 DOWNTO 0) <= "110010";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
aeb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 6
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
aeb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "1"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "50"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "6"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6"
-- Retrieval info: USED_PORT: aeb 0 0 0 0 OUTPUT NODEFVAL "aeb"
-- Retrieval info: USED_PORT: dataa 0 0 6 0 INPUT NODEFVAL "dataa[5..0]"
-- Retrieval info: CONNECT: @dataa 0 0 6 0 dataa 0 0 6 0
-- Retrieval info: CONNECT: @datab 0 0 6 0 50 0 0 6 0
-- Retrieval info: CONNECT: aeb 0 0 0 0 @aeb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| mit |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/blk_mem_gen_v8_3/simulation/blk_mem_gen_v8_3.vhd | 13 | 222214 | -------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
| mit |
agural/FPGA-Oscilloscope | osc/lpm_compare2.vhd | 1 | 4448 | -- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare2.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare2 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
aeb : OUT STD_LOGIC
);
END lpm_compare2;
ARCHITECTURE SYN OF lpm_compare2 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (10 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (10 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aeb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(10 DOWNTO 0) <= "11111001111";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
aeb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 11
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
aeb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "1"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "1999"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "11"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "11"
-- Retrieval info: USED_PORT: aeb 0 0 0 0 OUTPUT NODEFVAL "aeb"
-- Retrieval info: USED_PORT: dataa 0 0 11 0 INPUT NODEFVAL "dataa[10..0]"
-- Retrieval info: CONNECT: @dataa 0 0 11 0 dataa 0 0 11 0
-- Retrieval info: CONNECT: @datab 0 0 11 0 1999 0 0 11 0
-- Retrieval info: CONNECT: aeb 0 0 0 0 @aeb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| mit |
SteelRaven7/soundbox-vhdl | Source/Packages/fixed_pkg.vhd | 2 | 2108 | --
-- Author: Erik Alveflo
-- Version:
-- * 1.0 2014-02-11 EA Inital release.
--
-- This package contains helper functions for fixed point math.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
package fixed_pkg is
type real_array_t is array(natural range <>) of real;
-- Converts a real number to a fixed number of supplied width on format SIF..F
function real_to_fixed (R:real; W:natural)
return std_logic_vector;
-- Same as above but more generic and also takes amount of fraction bits F.
function real_to_fixed (R:real; W:natural; F:natural)
return std_logic_vector;
-- Converts a fixed number on format SIF..F to a real number.
function fixed_to_real (V:std_logic_vector)
return real;
-- Same as above but more generic and also takes amount of fraction bits F.
function fixed_to_real (V:std_logic_vector; F:natural)
return real;
-- Round towards zero.
function round_zero (R:real)
return real;
-- Converts a gain in dB to fixed point, W bits wide, F fraction bits.
function db_to_fixed (R:real; W:natural; F:natural)
return std_logic_vector;
end package;
package body fixed_pkg is
function round_zero (R:real) return real is
begin
if (R < 0.0) then
return ceil(R);
else
return floor(R);
end if;
end function;
function real_to_fixed (R:real; W:natural) return std_logic_vector is
begin
return real_to_fixed(R,W,W-2);
end function;
function fixed_to_real (V:std_logic_vector) return real is
variable W : natural := V'high+1 - V'low;
begin
return fixed_to_real(V,W-2);
end function;
function db_to_fixed (R:real; W:natural; F:natural) return std_logic_vector is
variable mag : real := (10.0**(R / 20.0));
begin
return real_to_fixed(mag,W,F);
end function;
function fixed_to_real (V:std_logic_vector; F:natural) return real is
begin
return real(to_integer(signed(V))) / (2.0**(F));
end function;
function real_to_fixed (R:real; W:natural; F:natural) return std_logic_vector is
begin
return std_logic_vector(to_signed(integer(round_zero(R * (2.0**(F)))),W));
end function;
end package body; | mit |
SteelRaven7/soundbox-vhdl | Source/Decimator/FIR.vhd | 1 | 1805 | library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fixed_pkg.all;
use work.filter_pkg.all;
entity FIR is
generic (
wordLength : natural := 16;
order : natural := 3;
coefficients : coefficient_array := (0.0, 0.0, 0.0, 0.0)
);
port (
input : in std_logic_vector(wordLength-1 downto 0);
output : out std_logic_vector(wordLength-1 downto 0);
clk : in std_logic;
reset : in std_logic
);
end entity ; -- FIR
architecture arch of FIR is
type signalArray is array(0 to order) of std_logic_vector(wordLength-1 downto 0);
type sumArray is array(0 to order) of std_logic_vector((wordLength*2)-1 downto 0);
signal inputs : signalArray := (others => (others => '0'));
signal gainedInputs : sumArray := (others => (others => '0'));
signal sums : sumArray := (others => (others => '0'));
begin
inputs(0) <= input;
output <= sums(0)(wordLength*2-1 downto wordLength);
sums(order) <= gainedInputs(order);
delays : for i in 0 to order-1 generate
-- Delay stages
delay : entity work.VectorRegister
generic map (
wordLength => wordLength
)
port map (
input => inputs(i),
output => inputs(i+1),
clk => clk,
reset => reset
);
-- Output summation
adder : entity work.AdderSat
generic map (
wordLength => wordLength*2
)
port map (
a => gainedInputs(i),
b => sums(i+1),
s => sums(i)
);
end generate ; -- delays
multiplication : for i in 0 to order generate
-- Coefficient multiplication
mult : entity work.Mult
generic map (
wordLengthA => wordLength,
wordLengthB => wordLength,
wordLengthP => wordLength*2
)
port map (
a => inputs(i),
b => real_to_fixed(coefficients(i), wordLength),
p => gainedInputs(i)
);
end generate;
end architecture ; -- arch | mit |
kevinpt/symbolator | doc/images/scaled.vhdl | 2 | 156 | component scaled is
port (
Clock : in std_ulogic;
Reset : in std_ulogic;
Din : in unsigned;
Dout : out unsigned
);
end component;
| mit |
jakubcabal/mig_ddr3_wrapper_virtex6 | source/uart/comp/uart_fifo.vhd | 1 | 5156 | -- The MIT License (MIT)
--
-- Copyright (c) 2015 Jakub Cabal
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
-- Website: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
entity UART_FIFO is
Generic (
DATA_WIDTH : integer := 8;
FIFO_DEPTH : integer := 256
);
Port (
CLK : in std_logic; -- system clock
RST : in std_logic; -- high active synchronous reset
-- FIFO WRITE INTERFACE
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
WR_EN : in std_logic;
FULL : out std_logic;
-- FIFO READ INTERFACE
DATA_OUT : out std_logic_vector(DATA_WIDTH-1 downto 0);
DATA_VLD : out std_logic;
RD_EN : in std_logic;
EMPTY : out std_logic
);
end UART_FIFO;
architecture FULL of UART_FIFO is
constant addr_width : integer := integer(ceil(log2(real(FIFO_DEPTH))));
signal wr_addr : unsigned(addr_width-1 downto 0);
signal wr_ready : std_logic;
signal rd_addr : unsigned(addr_width-1 downto 0);
signal rd_ready : std_logic;
signal full_sig : std_logic;
signal empty_sig : std_logic;
type bram_type is array(FIFO_DEPTH-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal bram : bram_type := (others => (others => '0'));
begin
wr_ready <= WR_EN AND NOT full_sig AND NOT RST;
rd_ready <= RD_EN AND NOT empty_sig AND NOT RST;
FULL <= full_sig;
EMPTY <= empty_sig;
-- -------------------------------------------------------------------------
-- BRAM AND DATA VALID FLAG GENERATOR
-- -------------------------------------------------------------------------
bram_mem : process (CLK)
begin
if (rising_edge(CLK)) then
if (wr_ready = '1') then
bram(to_integer(wr_addr)) <= DATA_IN;
end if;
DATA_OUT <= bram(to_integer(rd_addr));
end if;
end process;
data_vld_flag_gen : process (CLK)
begin
if (rising_edge(CLK)) then
DATA_VLD <= rd_ready;
end if;
end process;
-- -------------------------------------------------------------------------
-- FIFO WRITE ADDRESS COUNTER
-- -------------------------------------------------------------------------
wr_addr_cnt : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
wr_addr <= (others => '0');
elsif (wr_ready = '1') then
wr_addr <= wr_addr + 1;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- FIFO READ ADDRESS COUNTER
-- -------------------------------------------------------------------------
rd_addr_cnt : process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then
rd_addr <= (others => '0');
elsif (rd_ready = '1') then
rd_addr <= rd_addr + 1;
end if;
end if;
end process;
-- -------------------------------------------------------------------------
-- FULL FLAG GENERATOR
-- -------------------------------------------------------------------------
full_flag_gen : process (rd_addr, wr_addr)
begin
if (rd_addr = (wr_addr+1)) then
full_sig <= '1';
else
full_sig <= '0';
end if;
end process;
-- -------------------------------------------------------------------------
-- EMPTY FLAG GENERATOR
-- -------------------------------------------------------------------------
empty_flag_gen : process (rd_addr, wr_addr)
begin
if (rd_addr = wr_addr) then
empty_sig <= '1';
else
empty_sig <= '0';
end if;
end process;
end FULL; | mit |
jakubcabal/mig_ddr3_wrapper_virtex6 | source/uart/comp/uart_parity.vhd | 1 | 2884 | -- The MIT License (MIT)
--
-- Copyright (c) 2015 Jakub Cabal
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
-- Website: https://github.com/jakubcabal/uart_for_fpga
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity UART_PARITY is
Generic (
DATA_WIDTH : integer := 8;
PARITY_TYPE : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
);
Port (
DATA_IN : in std_logic_vector(DATA_WIDTH-1 downto 0);
PARITY_OUT : out std_logic
);
end UART_PARITY;
architecture FULL of UART_PARITY is
begin
-- -------------------------------------------------------------------------
-- PARITY BIT GENERATOR
-- -------------------------------------------------------------------------
even_parity_g : if (PARITY_TYPE = "even") generate
process (DATA_IN)
variable parity_temp : std_logic;
begin
parity_temp := '0';
for i in DATA_IN'range loop
parity_temp := parity_temp XOR DATA_IN(i);
end loop;
PARITY_OUT <= parity_temp;
end process;
end generate;
odd_parity_g : if (PARITY_TYPE = "odd") generate
process (DATA_IN)
variable parity_temp : std_logic;
begin
parity_temp := '1';
for i in DATA_IN'range loop
parity_temp := parity_temp XOR DATA_IN(i);
end loop;
PARITY_OUT <= parity_temp;
end process;
end generate;
mark_parity_g : if (PARITY_TYPE = "mark") generate
PARITY_OUT <= '1';
end generate;
space_parity_g : if (PARITY_TYPE = "space") generate
PARITY_OUT <= '0';
end generate;
end FULL; | mit |
achan1989/SlowWorm | sim/memory/ram_256x16/testbench.vhd | 1 | 2719 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 24.08.2016 15:22:18
-- Design Name:
-- Module Name: testbench - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity testbench is
end testbench;
architecture Behavioral of testbench is
component ram_256x16 is port (
dout : out std_ulogic_vector (15 downto 0);
din : in std_ulogic_vector (15 downto 0);
addr : in unsigned (7 downto 0);
we : in std_ulogic;
clk : in std_ulogic);
end component;
signal clk : std_ulogic := '0';
signal we : std_ulogic := '0';
signal addr : unsigned (7 downto 0);
signal din : std_ulogic_vector (15 downto 0);
signal dout : std_ulogic_vector (15 downto 0);
constant ClockPeriod : TIME := 50 ns;
begin
UUT: ram_256x16 port map (
dout => dout,
din => din,
addr => addr,
we => we,
clk => clk
);
clock: process begin
clk <= '0';
wait for ClockPeriod;
loop
clk <= not clk;
wait for (ClockPeriod / 2);
end loop;
end process;
stimulus: process begin
-- Starting values.
addr <= TO_UNSIGNED(0, addr'length);
we <= '0';
wait until falling_edge(clk);
-- Write to address 1.
wait until rising_edge(clk);
addr <= TO_UNSIGNED(1, addr'length);
din <= x"ABCD";
we <= '1';
-- Write to address 2.
wait until rising_edge(clk);
we <= '1';
addr <= TO_UNSIGNED(2, addr'length);
din <= x"FACE";
-- Do nothing for 3 ticks.
wait until rising_edge(clk);
we <= '0';
addr <= TO_UNSIGNED(10, addr'length);
din <= x"0000";
wait until rising_edge(clk);
wait until rising_edge(clk);
-- Read address 1.
wait until rising_edge(clk);
addr <= TO_UNSIGNED(1, addr'length);
we <= '0';
-- Read address 2.
wait until rising_edge(clk);
addr <= TO_UNSIGNED(2, addr'length);
we <= '0';
-- Do nothing more.
wait until rising_edge(clk);
we <= '0';
addr <= TO_UNSIGNED(10, addr'length);
din <= x"0000";
wait;
end process;
end Behavioral;
| mit |
achan1989/SlowWorm | src/control/control.vhd | 1 | 5306 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 26.08.2016 16:22:30
-- Design Name:
-- Module Name: control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library SlowWorm;
use SlowWorm.SlowWorm.ALL;
entity control is
Port (
clk : in std_ulogic;
-- Instruction memory.
inst_mem_data : in data_t;
inst_mem_addr : out addr_t;
-- Data memory.
data_mem_data_read : in data_t;
data_mem_data_write : out data_t;
data_mem_addr : out addr_t;
data_mem_we : out std_ulogic;
-- Data stack.
dstack_data_read : in data_t;
dstack_data_write : out data_t;
dstack_push : out std_ulogic;
dstack_pop : out std_ulogic;
-- Return stack.
rstack_data_read : in data_t;
rstack_data_write : out data_t;
rstack_push : out std_ulogic;
rstack_pop : out std_ulogic
);
end control;
architecture Behavioral of control is
type state_t is (Reset, Fetch, Decode, Execute, Halt);
subtype instr_type_t is std_ulogic_vector(2 downto 0);
signal state : state_t := Reset;
signal data_addr, pc : addr_t;
signal instruction : data_t;
constant INSTR_TYPE_IMM_VAL : instr_type_t := "001";
constant INSTR_TYPE_LOGIC : instr_type_t := "011";
constant INSTR_TYPE_CONTROL : instr_type_t := "101";
constant INSTR_TYPE_UCODE : instr_type_t := "111";
begin
main: process (clk) is
-- General stuff used in decode state.
alias call_bit : std_ulogic is instruction(0);
alias instr_type : instr_type_t is instruction(2 downto 0);
variable call_address : addr_t;
variable is_call : boolean;
-- Used for Immediate Value instructions.
alias imm_stack : std_ulogic is instruction(3);
constant DATA_STACK : std_ulogic := '0';
alias imm_val : std_ulogic_vector(11 downto 0) is instruction(15 downto 4);
alias imm_sign_bit : std_ulogic is instruction(instruction'left);
variable imm_val_extended : data_t;
begin
if rising_edge(clk) then
-- Clear any control signals that cause a change of state in other modules.
dstack_push <= '0';
dstack_pop <= '0';
rstack_push <= '0';
rstack_pop <= '0';
data_mem_we <= '0';
case state is
when Reset =>
pc <= TO_UNSIGNED(0, pc'length);
inst_mem_addr <= TO_UNSIGNED(0, inst_mem_addr'length);
state <= Fetch;
-- Preconditions:
-- `inst_mem_addr` is loaded with the correct instruction memory address.
-- Postconditions:
-- `instruction` contains the next instruction to decode.
when Fetch =>
instruction <= inst_mem_data;
pc <= pc + 1;
state <= Decode;
when Decode =>
call_address := DATA_TO_ADDR(instruction(15 downto 0));
is_call := (call_bit = '0');
if is_call then
rstack_push <= '1';
rstack_data_write <= ADDR_TO_DATA(pc);
pc <= call_address;
inst_mem_addr <= call_address;
state <= Fetch;
else
case instr_type is
when INSTR_TYPE_IMM_VAL =>
imm_val_extended(imm_val'range) := imm_val;
imm_val_extended(imm_val_extended'left downto (imm_val'left + 1)) := (imm_val_extended'left downto (imm_val'left + 1) => imm_sign_bit);
if imm_stack = DATA_STACK then
dstack_push <= '1';
dstack_data_write <= imm_val_extended;
else
rstack_push <= '1';
rstack_data_write <= imm_val_extended;
end if;
inst_mem_addr <= pc;
state <= Fetch;
when INSTR_TYPE_LOGIC =>
--TODO. For now this is basically a no-op.
state <= Execute;
when INSTR_TYPE_CONTROL =>
--TODO. For now this is basically a no-op.
state <= Execute;
when INSTR_TYPE_UCODE =>
--TODO.
state <= Halt;
when others =>
-- something fucky has happened.
state <= Halt;
end case;
end if;
when Execute =>
inst_mem_addr <= pc;
state <= Fetch;
null; --TODO
when Halt =>
null;
end case;
end if;
end process;
end Behavioral;
| mit |
R4PaSs/linguist | samples/VHDL/foo.vhd | 91 | 217 | -- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/dp_addpipe.vhd | 10 | 2509 |
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CONVERSION - CORE LEVEL ***
--*** ***
--*** DP_ADDPIPE.VHD ***
--*** ***
--*** Function: Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_addpipe IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_addpipe;
ARCHITECTURE syn of dp_addpipe IS
component lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
cin : IN STD_LOGIC ;
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0)
);
end component;
BEGIN
addtwo: lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES",
lpm_pipeline => pipes,
lpm_type => "LPM_ADD_SUB",
lpm_width => width
)
PORT MAP (
dataa => aa,
datab => bb,
cin => carryin,
clken => enable,
aclr => reset,
clock => sysclk,
result => cc
);
END syn;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_div_lut1.vhd | 10 | 35988 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_LUT1.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_div_lut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END fp_div_lut1;
ARCHITECTURE rtl OF fp_div_lut1 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(2044,11);
WHEN "000000001" => data <= conv_std_logic_vector(2036,11);
WHEN "000000010" => data <= conv_std_logic_vector(2028,11);
WHEN "000000011" => data <= conv_std_logic_vector(2020,11);
WHEN "000000100" => data <= conv_std_logic_vector(2012,11);
WHEN "000000101" => data <= conv_std_logic_vector(2005,11);
WHEN "000000110" => data <= conv_std_logic_vector(1997,11);
WHEN "000000111" => data <= conv_std_logic_vector(1989,11);
WHEN "000001000" => data <= conv_std_logic_vector(1982,11);
WHEN "000001001" => data <= conv_std_logic_vector(1974,11);
WHEN "000001010" => data <= conv_std_logic_vector(1967,11);
WHEN "000001011" => data <= conv_std_logic_vector(1959,11);
WHEN "000001100" => data <= conv_std_logic_vector(1952,11);
WHEN "000001101" => data <= conv_std_logic_vector(1944,11);
WHEN "000001110" => data <= conv_std_logic_vector(1937,11);
WHEN "000001111" => data <= conv_std_logic_vector(1929,11);
WHEN "000010000" => data <= conv_std_logic_vector(1922,11);
WHEN "000010001" => data <= conv_std_logic_vector(1915,11);
WHEN "000010010" => data <= conv_std_logic_vector(1908,11);
WHEN "000010011" => data <= conv_std_logic_vector(1900,11);
WHEN "000010100" => data <= conv_std_logic_vector(1893,11);
WHEN "000010101" => data <= conv_std_logic_vector(1886,11);
WHEN "000010110" => data <= conv_std_logic_vector(1879,11);
WHEN "000010111" => data <= conv_std_logic_vector(1872,11);
WHEN "000011000" => data <= conv_std_logic_vector(1865,11);
WHEN "000011001" => data <= conv_std_logic_vector(1858,11);
WHEN "000011010" => data <= conv_std_logic_vector(1851,11);
WHEN "000011011" => data <= conv_std_logic_vector(1845,11);
WHEN "000011100" => data <= conv_std_logic_vector(1838,11);
WHEN "000011101" => data <= conv_std_logic_vector(1831,11);
WHEN "000011110" => data <= conv_std_logic_vector(1824,11);
WHEN "000011111" => data <= conv_std_logic_vector(1817,11);
WHEN "000100000" => data <= conv_std_logic_vector(1811,11);
WHEN "000100001" => data <= conv_std_logic_vector(1804,11);
WHEN "000100010" => data <= conv_std_logic_vector(1798,11);
WHEN "000100011" => data <= conv_std_logic_vector(1791,11);
WHEN "000100100" => data <= conv_std_logic_vector(1785,11);
WHEN "000100101" => data <= conv_std_logic_vector(1778,11);
WHEN "000100110" => data <= conv_std_logic_vector(1772,11);
WHEN "000100111" => data <= conv_std_logic_vector(1765,11);
WHEN "000101000" => data <= conv_std_logic_vector(1759,11);
WHEN "000101001" => data <= conv_std_logic_vector(1752,11);
WHEN "000101010" => data <= conv_std_logic_vector(1746,11);
WHEN "000101011" => data <= conv_std_logic_vector(1740,11);
WHEN "000101100" => data <= conv_std_logic_vector(1734,11);
WHEN "000101101" => data <= conv_std_logic_vector(1727,11);
WHEN "000101110" => data <= conv_std_logic_vector(1721,11);
WHEN "000101111" => data <= conv_std_logic_vector(1715,11);
WHEN "000110000" => data <= conv_std_logic_vector(1709,11);
WHEN "000110001" => data <= conv_std_logic_vector(1703,11);
WHEN "000110010" => data <= conv_std_logic_vector(1697,11);
WHEN "000110011" => data <= conv_std_logic_vector(1691,11);
WHEN "000110100" => data <= conv_std_logic_vector(1685,11);
WHEN "000110101" => data <= conv_std_logic_vector(1679,11);
WHEN "000110110" => data <= conv_std_logic_vector(1673,11);
WHEN "000110111" => data <= conv_std_logic_vector(1667,11);
WHEN "000111000" => data <= conv_std_logic_vector(1661,11);
WHEN "000111001" => data <= conv_std_logic_vector(1655,11);
WHEN "000111010" => data <= conv_std_logic_vector(1650,11);
WHEN "000111011" => data <= conv_std_logic_vector(1644,11);
WHEN "000111100" => data <= conv_std_logic_vector(1638,11);
WHEN "000111101" => data <= conv_std_logic_vector(1632,11);
WHEN "000111110" => data <= conv_std_logic_vector(1627,11);
WHEN "000111111" => data <= conv_std_logic_vector(1621,11);
WHEN "001000000" => data <= conv_std_logic_vector(1615,11);
WHEN "001000001" => data <= conv_std_logic_vector(1610,11);
WHEN "001000010" => data <= conv_std_logic_vector(1604,11);
WHEN "001000011" => data <= conv_std_logic_vector(1599,11);
WHEN "001000100" => data <= conv_std_logic_vector(1593,11);
WHEN "001000101" => data <= conv_std_logic_vector(1588,11);
WHEN "001000110" => data <= conv_std_logic_vector(1582,11);
WHEN "001000111" => data <= conv_std_logic_vector(1577,11);
WHEN "001001000" => data <= conv_std_logic_vector(1571,11);
WHEN "001001001" => data <= conv_std_logic_vector(1566,11);
WHEN "001001010" => data <= conv_std_logic_vector(1561,11);
WHEN "001001011" => data <= conv_std_logic_vector(1555,11);
WHEN "001001100" => data <= conv_std_logic_vector(1550,11);
WHEN "001001101" => data <= conv_std_logic_vector(1545,11);
WHEN "001001110" => data <= conv_std_logic_vector(1540,11);
WHEN "001001111" => data <= conv_std_logic_vector(1534,11);
WHEN "001010000" => data <= conv_std_logic_vector(1529,11);
WHEN "001010001" => data <= conv_std_logic_vector(1524,11);
WHEN "001010010" => data <= conv_std_logic_vector(1519,11);
WHEN "001010011" => data <= conv_std_logic_vector(1514,11);
WHEN "001010100" => data <= conv_std_logic_vector(1509,11);
WHEN "001010101" => data <= conv_std_logic_vector(1504,11);
WHEN "001010110" => data <= conv_std_logic_vector(1499,11);
WHEN "001010111" => data <= conv_std_logic_vector(1494,11);
WHEN "001011000" => data <= conv_std_logic_vector(1489,11);
WHEN "001011001" => data <= conv_std_logic_vector(1484,11);
WHEN "001011010" => data <= conv_std_logic_vector(1479,11);
WHEN "001011011" => data <= conv_std_logic_vector(1474,11);
WHEN "001011100" => data <= conv_std_logic_vector(1469,11);
WHEN "001011101" => data <= conv_std_logic_vector(1464,11);
WHEN "001011110" => data <= conv_std_logic_vector(1460,11);
WHEN "001011111" => data <= conv_std_logic_vector(1455,11);
WHEN "001100000" => data <= conv_std_logic_vector(1450,11);
WHEN "001100001" => data <= conv_std_logic_vector(1445,11);
WHEN "001100010" => data <= conv_std_logic_vector(1440,11);
WHEN "001100011" => data <= conv_std_logic_vector(1436,11);
WHEN "001100100" => data <= conv_std_logic_vector(1431,11);
WHEN "001100101" => data <= conv_std_logic_vector(1426,11);
WHEN "001100110" => data <= conv_std_logic_vector(1422,11);
WHEN "001100111" => data <= conv_std_logic_vector(1417,11);
WHEN "001101000" => data <= conv_std_logic_vector(1413,11);
WHEN "001101001" => data <= conv_std_logic_vector(1408,11);
WHEN "001101010" => data <= conv_std_logic_vector(1403,11);
WHEN "001101011" => data <= conv_std_logic_vector(1399,11);
WHEN "001101100" => data <= conv_std_logic_vector(1394,11);
WHEN "001101101" => data <= conv_std_logic_vector(1390,11);
WHEN "001101110" => data <= conv_std_logic_vector(1385,11);
WHEN "001101111" => data <= conv_std_logic_vector(1381,11);
WHEN "001110000" => data <= conv_std_logic_vector(1377,11);
WHEN "001110001" => data <= conv_std_logic_vector(1372,11);
WHEN "001110010" => data <= conv_std_logic_vector(1368,11);
WHEN "001110011" => data <= conv_std_logic_vector(1363,11);
WHEN "001110100" => data <= conv_std_logic_vector(1359,11);
WHEN "001110101" => data <= conv_std_logic_vector(1355,11);
WHEN "001110110" => data <= conv_std_logic_vector(1351,11);
WHEN "001110111" => data <= conv_std_logic_vector(1346,11);
WHEN "001111000" => data <= conv_std_logic_vector(1342,11);
WHEN "001111001" => data <= conv_std_logic_vector(1338,11);
WHEN "001111010" => data <= conv_std_logic_vector(1334,11);
WHEN "001111011" => data <= conv_std_logic_vector(1329,11);
WHEN "001111100" => data <= conv_std_logic_vector(1325,11);
WHEN "001111101" => data <= conv_std_logic_vector(1321,11);
WHEN "001111110" => data <= conv_std_logic_vector(1317,11);
WHEN "001111111" => data <= conv_std_logic_vector(1313,11);
WHEN "010000000" => data <= conv_std_logic_vector(1309,11);
WHEN "010000001" => data <= conv_std_logic_vector(1305,11);
WHEN "010000010" => data <= conv_std_logic_vector(1301,11);
WHEN "010000011" => data <= conv_std_logic_vector(1297,11);
WHEN "010000100" => data <= conv_std_logic_vector(1292,11);
WHEN "010000101" => data <= conv_std_logic_vector(1288,11);
WHEN "010000110" => data <= conv_std_logic_vector(1284,11);
WHEN "010000111" => data <= conv_std_logic_vector(1281,11);
WHEN "010001000" => data <= conv_std_logic_vector(1277,11);
WHEN "010001001" => data <= conv_std_logic_vector(1273,11);
WHEN "010001010" => data <= conv_std_logic_vector(1269,11);
WHEN "010001011" => data <= conv_std_logic_vector(1265,11);
WHEN "010001100" => data <= conv_std_logic_vector(1261,11);
WHEN "010001101" => data <= conv_std_logic_vector(1257,11);
WHEN "010001110" => data <= conv_std_logic_vector(1253,11);
WHEN "010001111" => data <= conv_std_logic_vector(1249,11);
WHEN "010010000" => data <= conv_std_logic_vector(1246,11);
WHEN "010010001" => data <= conv_std_logic_vector(1242,11);
WHEN "010010010" => data <= conv_std_logic_vector(1238,11);
WHEN "010010011" => data <= conv_std_logic_vector(1234,11);
WHEN "010010100" => data <= conv_std_logic_vector(1231,11);
WHEN "010010101" => data <= conv_std_logic_vector(1227,11);
WHEN "010010110" => data <= conv_std_logic_vector(1223,11);
WHEN "010010111" => data <= conv_std_logic_vector(1220,11);
WHEN "010011000" => data <= conv_std_logic_vector(1216,11);
WHEN "010011001" => data <= conv_std_logic_vector(1212,11);
WHEN "010011010" => data <= conv_std_logic_vector(1209,11);
WHEN "010011011" => data <= conv_std_logic_vector(1205,11);
WHEN "010011100" => data <= conv_std_logic_vector(1201,11);
WHEN "010011101" => data <= conv_std_logic_vector(1198,11);
WHEN "010011110" => data <= conv_std_logic_vector(1194,11);
WHEN "010011111" => data <= conv_std_logic_vector(1191,11);
WHEN "010100000" => data <= conv_std_logic_vector(1187,11);
WHEN "010100001" => data <= conv_std_logic_vector(1184,11);
WHEN "010100010" => data <= conv_std_logic_vector(1180,11);
WHEN "010100011" => data <= conv_std_logic_vector(1177,11);
WHEN "010100100" => data <= conv_std_logic_vector(1173,11);
WHEN "010100101" => data <= conv_std_logic_vector(1170,11);
WHEN "010100110" => data <= conv_std_logic_vector(1166,11);
WHEN "010100111" => data <= conv_std_logic_vector(1163,11);
WHEN "010101000" => data <= conv_std_logic_vector(1159,11);
WHEN "010101001" => data <= conv_std_logic_vector(1156,11);
WHEN "010101010" => data <= conv_std_logic_vector(1153,11);
WHEN "010101011" => data <= conv_std_logic_vector(1149,11);
WHEN "010101100" => data <= conv_std_logic_vector(1146,11);
WHEN "010101101" => data <= conv_std_logic_vector(1142,11);
WHEN "010101110" => data <= conv_std_logic_vector(1139,11);
WHEN "010101111" => data <= conv_std_logic_vector(1136,11);
WHEN "010110000" => data <= conv_std_logic_vector(1133,11);
WHEN "010110001" => data <= conv_std_logic_vector(1129,11);
WHEN "010110010" => data <= conv_std_logic_vector(1126,11);
WHEN "010110011" => data <= conv_std_logic_vector(1123,11);
WHEN "010110100" => data <= conv_std_logic_vector(1120,11);
WHEN "010110101" => data <= conv_std_logic_vector(1116,11);
WHEN "010110110" => data <= conv_std_logic_vector(1113,11);
WHEN "010110111" => data <= conv_std_logic_vector(1110,11);
WHEN "010111000" => data <= conv_std_logic_vector(1107,11);
WHEN "010111001" => data <= conv_std_logic_vector(1104,11);
WHEN "010111010" => data <= conv_std_logic_vector(1100,11);
WHEN "010111011" => data <= conv_std_logic_vector(1097,11);
WHEN "010111100" => data <= conv_std_logic_vector(1094,11);
WHEN "010111101" => data <= conv_std_logic_vector(1091,11);
WHEN "010111110" => data <= conv_std_logic_vector(1088,11);
WHEN "010111111" => data <= conv_std_logic_vector(1085,11);
WHEN "011000000" => data <= conv_std_logic_vector(1082,11);
WHEN "011000001" => data <= conv_std_logic_vector(1079,11);
WHEN "011000010" => data <= conv_std_logic_vector(1076,11);
WHEN "011000011" => data <= conv_std_logic_vector(1073,11);
WHEN "011000100" => data <= conv_std_logic_vector(1070,11);
WHEN "011000101" => data <= conv_std_logic_vector(1067,11);
WHEN "011000110" => data <= conv_std_logic_vector(1064,11);
WHEN "011000111" => data <= conv_std_logic_vector(1061,11);
WHEN "011001000" => data <= conv_std_logic_vector(1058,11);
WHEN "011001001" => data <= conv_std_logic_vector(1055,11);
WHEN "011001010" => data <= conv_std_logic_vector(1052,11);
WHEN "011001011" => data <= conv_std_logic_vector(1049,11);
WHEN "011001100" => data <= conv_std_logic_vector(1046,11);
WHEN "011001101" => data <= conv_std_logic_vector(1043,11);
WHEN "011001110" => data <= conv_std_logic_vector(1040,11);
WHEN "011001111" => data <= conv_std_logic_vector(1037,11);
WHEN "011010000" => data <= conv_std_logic_vector(1034,11);
WHEN "011010001" => data <= conv_std_logic_vector(1031,11);
WHEN "011010010" => data <= conv_std_logic_vector(1028,11);
WHEN "011010011" => data <= conv_std_logic_vector(1026,11);
WHEN "011010100" => data <= conv_std_logic_vector(1023,11);
WHEN "011010101" => data <= conv_std_logic_vector(1020,11);
WHEN "011010110" => data <= conv_std_logic_vector(1017,11);
WHEN "011010111" => data <= conv_std_logic_vector(1014,11);
WHEN "011011000" => data <= conv_std_logic_vector(1012,11);
WHEN "011011001" => data <= conv_std_logic_vector(1009,11);
WHEN "011011010" => data <= conv_std_logic_vector(1006,11);
WHEN "011011011" => data <= conv_std_logic_vector(1003,11);
WHEN "011011100" => data <= conv_std_logic_vector(1001,11);
WHEN "011011101" => data <= conv_std_logic_vector(998,11);
WHEN "011011110" => data <= conv_std_logic_vector(995,11);
WHEN "011011111" => data <= conv_std_logic_vector(992,11);
WHEN "011100000" => data <= conv_std_logic_vector(990,11);
WHEN "011100001" => data <= conv_std_logic_vector(987,11);
WHEN "011100010" => data <= conv_std_logic_vector(984,11);
WHEN "011100011" => data <= conv_std_logic_vector(982,11);
WHEN "011100100" => data <= conv_std_logic_vector(979,11);
WHEN "011100101" => data <= conv_std_logic_vector(976,11);
WHEN "011100110" => data <= conv_std_logic_vector(974,11);
WHEN "011100111" => data <= conv_std_logic_vector(971,11);
WHEN "011101000" => data <= conv_std_logic_vector(969,11);
WHEN "011101001" => data <= conv_std_logic_vector(966,11);
WHEN "011101010" => data <= conv_std_logic_vector(963,11);
WHEN "011101011" => data <= conv_std_logic_vector(961,11);
WHEN "011101100" => data <= conv_std_logic_vector(958,11);
WHEN "011101101" => data <= conv_std_logic_vector(956,11);
WHEN "011101110" => data <= conv_std_logic_vector(953,11);
WHEN "011101111" => data <= conv_std_logic_vector(951,11);
WHEN "011110000" => data <= conv_std_logic_vector(948,11);
WHEN "011110001" => data <= conv_std_logic_vector(946,11);
WHEN "011110010" => data <= conv_std_logic_vector(943,11);
WHEN "011110011" => data <= conv_std_logic_vector(941,11);
WHEN "011110100" => data <= conv_std_logic_vector(938,11);
WHEN "011110101" => data <= conv_std_logic_vector(936,11);
WHEN "011110110" => data <= conv_std_logic_vector(933,11);
WHEN "011110111" => data <= conv_std_logic_vector(931,11);
WHEN "011111000" => data <= conv_std_logic_vector(928,11);
WHEN "011111001" => data <= conv_std_logic_vector(926,11);
WHEN "011111010" => data <= conv_std_logic_vector(923,11);
WHEN "011111011" => data <= conv_std_logic_vector(921,11);
WHEN "011111100" => data <= conv_std_logic_vector(919,11);
WHEN "011111101" => data <= conv_std_logic_vector(916,11);
WHEN "011111110" => data <= conv_std_logic_vector(914,11);
WHEN "011111111" => data <= conv_std_logic_vector(911,11);
WHEN "100000000" => data <= conv_std_logic_vector(909,11);
WHEN "100000001" => data <= conv_std_logic_vector(907,11);
WHEN "100000010" => data <= conv_std_logic_vector(904,11);
WHEN "100000011" => data <= conv_std_logic_vector(902,11);
WHEN "100000100" => data <= conv_std_logic_vector(900,11);
WHEN "100000101" => data <= conv_std_logic_vector(897,11);
WHEN "100000110" => data <= conv_std_logic_vector(895,11);
WHEN "100000111" => data <= conv_std_logic_vector(893,11);
WHEN "100001000" => data <= conv_std_logic_vector(890,11);
WHEN "100001001" => data <= conv_std_logic_vector(888,11);
WHEN "100001010" => data <= conv_std_logic_vector(886,11);
WHEN "100001011" => data <= conv_std_logic_vector(884,11);
WHEN "100001100" => data <= conv_std_logic_vector(881,11);
WHEN "100001101" => data <= conv_std_logic_vector(879,11);
WHEN "100001110" => data <= conv_std_logic_vector(877,11);
WHEN "100001111" => data <= conv_std_logic_vector(875,11);
WHEN "100010000" => data <= conv_std_logic_vector(872,11);
WHEN "100010001" => data <= conv_std_logic_vector(870,11);
WHEN "100010010" => data <= conv_std_logic_vector(868,11);
WHEN "100010011" => data <= conv_std_logic_vector(866,11);
WHEN "100010100" => data <= conv_std_logic_vector(864,11);
WHEN "100010101" => data <= conv_std_logic_vector(861,11);
WHEN "100010110" => data <= conv_std_logic_vector(859,11);
WHEN "100010111" => data <= conv_std_logic_vector(857,11);
WHEN "100011000" => data <= conv_std_logic_vector(855,11);
WHEN "100011001" => data <= conv_std_logic_vector(853,11);
WHEN "100011010" => data <= conv_std_logic_vector(851,11);
WHEN "100011011" => data <= conv_std_logic_vector(848,11);
WHEN "100011100" => data <= conv_std_logic_vector(846,11);
WHEN "100011101" => data <= conv_std_logic_vector(844,11);
WHEN "100011110" => data <= conv_std_logic_vector(842,11);
WHEN "100011111" => data <= conv_std_logic_vector(840,11);
WHEN "100100000" => data <= conv_std_logic_vector(838,11);
WHEN "100100001" => data <= conv_std_logic_vector(836,11);
WHEN "100100010" => data <= conv_std_logic_vector(834,11);
WHEN "100100011" => data <= conv_std_logic_vector(832,11);
WHEN "100100100" => data <= conv_std_logic_vector(830,11);
WHEN "100100101" => data <= conv_std_logic_vector(827,11);
WHEN "100100110" => data <= conv_std_logic_vector(825,11);
WHEN "100100111" => data <= conv_std_logic_vector(823,11);
WHEN "100101000" => data <= conv_std_logic_vector(821,11);
WHEN "100101001" => data <= conv_std_logic_vector(819,11);
WHEN "100101010" => data <= conv_std_logic_vector(817,11);
WHEN "100101011" => data <= conv_std_logic_vector(815,11);
WHEN "100101100" => data <= conv_std_logic_vector(813,11);
WHEN "100101101" => data <= conv_std_logic_vector(811,11);
WHEN "100101110" => data <= conv_std_logic_vector(809,11);
WHEN "100101111" => data <= conv_std_logic_vector(807,11);
WHEN "100110000" => data <= conv_std_logic_vector(805,11);
WHEN "100110001" => data <= conv_std_logic_vector(803,11);
WHEN "100110010" => data <= conv_std_logic_vector(801,11);
WHEN "100110011" => data <= conv_std_logic_vector(799,11);
WHEN "100110100" => data <= conv_std_logic_vector(797,11);
WHEN "100110101" => data <= conv_std_logic_vector(796,11);
WHEN "100110110" => data <= conv_std_logic_vector(794,11);
WHEN "100110111" => data <= conv_std_logic_vector(792,11);
WHEN "100111000" => data <= conv_std_logic_vector(790,11);
WHEN "100111001" => data <= conv_std_logic_vector(788,11);
WHEN "100111010" => data <= conv_std_logic_vector(786,11);
WHEN "100111011" => data <= conv_std_logic_vector(784,11);
WHEN "100111100" => data <= conv_std_logic_vector(782,11);
WHEN "100111101" => data <= conv_std_logic_vector(780,11);
WHEN "100111110" => data <= conv_std_logic_vector(778,11);
WHEN "100111111" => data <= conv_std_logic_vector(777,11);
WHEN "101000000" => data <= conv_std_logic_vector(775,11);
WHEN "101000001" => data <= conv_std_logic_vector(773,11);
WHEN "101000010" => data <= conv_std_logic_vector(771,11);
WHEN "101000011" => data <= conv_std_logic_vector(769,11);
WHEN "101000100" => data <= conv_std_logic_vector(767,11);
WHEN "101000101" => data <= conv_std_logic_vector(765,11);
WHEN "101000110" => data <= conv_std_logic_vector(764,11);
WHEN "101000111" => data <= conv_std_logic_vector(762,11);
WHEN "101001000" => data <= conv_std_logic_vector(760,11);
WHEN "101001001" => data <= conv_std_logic_vector(758,11);
WHEN "101001010" => data <= conv_std_logic_vector(756,11);
WHEN "101001011" => data <= conv_std_logic_vector(755,11);
WHEN "101001100" => data <= conv_std_logic_vector(753,11);
WHEN "101001101" => data <= conv_std_logic_vector(751,11);
WHEN "101001110" => data <= conv_std_logic_vector(749,11);
WHEN "101001111" => data <= conv_std_logic_vector(747,11);
WHEN "101010000" => data <= conv_std_logic_vector(746,11);
WHEN "101010001" => data <= conv_std_logic_vector(744,11);
WHEN "101010010" => data <= conv_std_logic_vector(742,11);
WHEN "101010011" => data <= conv_std_logic_vector(740,11);
WHEN "101010100" => data <= conv_std_logic_vector(739,11);
WHEN "101010101" => data <= conv_std_logic_vector(737,11);
WHEN "101010110" => data <= conv_std_logic_vector(735,11);
WHEN "101010111" => data <= conv_std_logic_vector(734,11);
WHEN "101011000" => data <= conv_std_logic_vector(732,11);
WHEN "101011001" => data <= conv_std_logic_vector(730,11);
WHEN "101011010" => data <= conv_std_logic_vector(728,11);
WHEN "101011011" => data <= conv_std_logic_vector(727,11);
WHEN "101011100" => data <= conv_std_logic_vector(725,11);
WHEN "101011101" => data <= conv_std_logic_vector(723,11);
WHEN "101011110" => data <= conv_std_logic_vector(722,11);
WHEN "101011111" => data <= conv_std_logic_vector(720,11);
WHEN "101100000" => data <= conv_std_logic_vector(718,11);
WHEN "101100001" => data <= conv_std_logic_vector(717,11);
WHEN "101100010" => data <= conv_std_logic_vector(715,11);
WHEN "101100011" => data <= conv_std_logic_vector(713,11);
WHEN "101100100" => data <= conv_std_logic_vector(712,11);
WHEN "101100101" => data <= conv_std_logic_vector(710,11);
WHEN "101100110" => data <= conv_std_logic_vector(708,11);
WHEN "101100111" => data <= conv_std_logic_vector(707,11);
WHEN "101101000" => data <= conv_std_logic_vector(705,11);
WHEN "101101001" => data <= conv_std_logic_vector(704,11);
WHEN "101101010" => data <= conv_std_logic_vector(702,11);
WHEN "101101011" => data <= conv_std_logic_vector(700,11);
WHEN "101101100" => data <= conv_std_logic_vector(699,11);
WHEN "101101101" => data <= conv_std_logic_vector(697,11);
WHEN "101101110" => data <= conv_std_logic_vector(696,11);
WHEN "101101111" => data <= conv_std_logic_vector(694,11);
WHEN "101110000" => data <= conv_std_logic_vector(692,11);
WHEN "101110001" => data <= conv_std_logic_vector(691,11);
WHEN "101110010" => data <= conv_std_logic_vector(689,11);
WHEN "101110011" => data <= conv_std_logic_vector(688,11);
WHEN "101110100" => data <= conv_std_logic_vector(686,11);
WHEN "101110101" => data <= conv_std_logic_vector(685,11);
WHEN "101110110" => data <= conv_std_logic_vector(683,11);
WHEN "101110111" => data <= conv_std_logic_vector(682,11);
WHEN "101111000" => data <= conv_std_logic_vector(680,11);
WHEN "101111001" => data <= conv_std_logic_vector(679,11);
WHEN "101111010" => data <= conv_std_logic_vector(677,11);
WHEN "101111011" => data <= conv_std_logic_vector(676,11);
WHEN "101111100" => data <= conv_std_logic_vector(674,11);
WHEN "101111101" => data <= conv_std_logic_vector(672,11);
WHEN "101111110" => data <= conv_std_logic_vector(671,11);
WHEN "101111111" => data <= conv_std_logic_vector(669,11);
WHEN "110000000" => data <= conv_std_logic_vector(668,11);
WHEN "110000001" => data <= conv_std_logic_vector(667,11);
WHEN "110000010" => data <= conv_std_logic_vector(665,11);
WHEN "110000011" => data <= conv_std_logic_vector(664,11);
WHEN "110000100" => data <= conv_std_logic_vector(662,11);
WHEN "110000101" => data <= conv_std_logic_vector(661,11);
WHEN "110000110" => data <= conv_std_logic_vector(659,11);
WHEN "110000111" => data <= conv_std_logic_vector(658,11);
WHEN "110001000" => data <= conv_std_logic_vector(656,11);
WHEN "110001001" => data <= conv_std_logic_vector(655,11);
WHEN "110001010" => data <= conv_std_logic_vector(653,11);
WHEN "110001011" => data <= conv_std_logic_vector(652,11);
WHEN "110001100" => data <= conv_std_logic_vector(650,11);
WHEN "110001101" => data <= conv_std_logic_vector(649,11);
WHEN "110001110" => data <= conv_std_logic_vector(648,11);
WHEN "110001111" => data <= conv_std_logic_vector(646,11);
WHEN "110010000" => data <= conv_std_logic_vector(645,11);
WHEN "110010001" => data <= conv_std_logic_vector(643,11);
WHEN "110010010" => data <= conv_std_logic_vector(642,11);
WHEN "110010011" => data <= conv_std_logic_vector(641,11);
WHEN "110010100" => data <= conv_std_logic_vector(639,11);
WHEN "110010101" => data <= conv_std_logic_vector(638,11);
WHEN "110010110" => data <= conv_std_logic_vector(636,11);
WHEN "110010111" => data <= conv_std_logic_vector(635,11);
WHEN "110011000" => data <= conv_std_logic_vector(634,11);
WHEN "110011001" => data <= conv_std_logic_vector(632,11);
WHEN "110011010" => data <= conv_std_logic_vector(631,11);
WHEN "110011011" => data <= conv_std_logic_vector(630,11);
WHEN "110011100" => data <= conv_std_logic_vector(628,11);
WHEN "110011101" => data <= conv_std_logic_vector(627,11);
WHEN "110011110" => data <= conv_std_logic_vector(625,11);
WHEN "110011111" => data <= conv_std_logic_vector(624,11);
WHEN "110100000" => data <= conv_std_logic_vector(623,11);
WHEN "110100001" => data <= conv_std_logic_vector(621,11);
WHEN "110100010" => data <= conv_std_logic_vector(620,11);
WHEN "110100011" => data <= conv_std_logic_vector(619,11);
WHEN "110100100" => data <= conv_std_logic_vector(617,11);
WHEN "110100101" => data <= conv_std_logic_vector(616,11);
WHEN "110100110" => data <= conv_std_logic_vector(615,11);
WHEN "110100111" => data <= conv_std_logic_vector(613,11);
WHEN "110101000" => data <= conv_std_logic_vector(612,11);
WHEN "110101001" => data <= conv_std_logic_vector(611,11);
WHEN "110101010" => data <= conv_std_logic_vector(610,11);
WHEN "110101011" => data <= conv_std_logic_vector(608,11);
WHEN "110101100" => data <= conv_std_logic_vector(607,11);
WHEN "110101101" => data <= conv_std_logic_vector(606,11);
WHEN "110101110" => data <= conv_std_logic_vector(604,11);
WHEN "110101111" => data <= conv_std_logic_vector(603,11);
WHEN "110110000" => data <= conv_std_logic_vector(602,11);
WHEN "110110001" => data <= conv_std_logic_vector(601,11);
WHEN "110110010" => data <= conv_std_logic_vector(599,11);
WHEN "110110011" => data <= conv_std_logic_vector(598,11);
WHEN "110110100" => data <= conv_std_logic_vector(597,11);
WHEN "110110101" => data <= conv_std_logic_vector(595,11);
WHEN "110110110" => data <= conv_std_logic_vector(594,11);
WHEN "110110111" => data <= conv_std_logic_vector(593,11);
WHEN "110111000" => data <= conv_std_logic_vector(592,11);
WHEN "110111001" => data <= conv_std_logic_vector(591,11);
WHEN "110111010" => data <= conv_std_logic_vector(589,11);
WHEN "110111011" => data <= conv_std_logic_vector(588,11);
WHEN "110111100" => data <= conv_std_logic_vector(587,11);
WHEN "110111101" => data <= conv_std_logic_vector(586,11);
WHEN "110111110" => data <= conv_std_logic_vector(584,11);
WHEN "110111111" => data <= conv_std_logic_vector(583,11);
WHEN "111000000" => data <= conv_std_logic_vector(582,11);
WHEN "111000001" => data <= conv_std_logic_vector(581,11);
WHEN "111000010" => data <= conv_std_logic_vector(580,11);
WHEN "111000011" => data <= conv_std_logic_vector(578,11);
WHEN "111000100" => data <= conv_std_logic_vector(577,11);
WHEN "111000101" => data <= conv_std_logic_vector(576,11);
WHEN "111000110" => data <= conv_std_logic_vector(575,11);
WHEN "111000111" => data <= conv_std_logic_vector(574,11);
WHEN "111001000" => data <= conv_std_logic_vector(572,11);
WHEN "111001001" => data <= conv_std_logic_vector(571,11);
WHEN "111001010" => data <= conv_std_logic_vector(570,11);
WHEN "111001011" => data <= conv_std_logic_vector(569,11);
WHEN "111001100" => data <= conv_std_logic_vector(568,11);
WHEN "111001101" => data <= conv_std_logic_vector(566,11);
WHEN "111001110" => data <= conv_std_logic_vector(565,11);
WHEN "111001111" => data <= conv_std_logic_vector(564,11);
WHEN "111010000" => data <= conv_std_logic_vector(563,11);
WHEN "111010001" => data <= conv_std_logic_vector(562,11);
WHEN "111010010" => data <= conv_std_logic_vector(561,11);
WHEN "111010011" => data <= conv_std_logic_vector(560,11);
WHEN "111010100" => data <= conv_std_logic_vector(558,11);
WHEN "111010101" => data <= conv_std_logic_vector(557,11);
WHEN "111010110" => data <= conv_std_logic_vector(556,11);
WHEN "111010111" => data <= conv_std_logic_vector(555,11);
WHEN "111011000" => data <= conv_std_logic_vector(554,11);
WHEN "111011001" => data <= conv_std_logic_vector(553,11);
WHEN "111011010" => data <= conv_std_logic_vector(552,11);
WHEN "111011011" => data <= conv_std_logic_vector(551,11);
WHEN "111011100" => data <= conv_std_logic_vector(549,11);
WHEN "111011101" => data <= conv_std_logic_vector(548,11);
WHEN "111011110" => data <= conv_std_logic_vector(547,11);
WHEN "111011111" => data <= conv_std_logic_vector(546,11);
WHEN "111100000" => data <= conv_std_logic_vector(545,11);
WHEN "111100001" => data <= conv_std_logic_vector(544,11);
WHEN "111100010" => data <= conv_std_logic_vector(543,11);
WHEN "111100011" => data <= conv_std_logic_vector(542,11);
WHEN "111100100" => data <= conv_std_logic_vector(541,11);
WHEN "111100101" => data <= conv_std_logic_vector(540,11);
WHEN "111100110" => data <= conv_std_logic_vector(538,11);
WHEN "111100111" => data <= conv_std_logic_vector(537,11);
WHEN "111101000" => data <= conv_std_logic_vector(536,11);
WHEN "111101001" => data <= conv_std_logic_vector(535,11);
WHEN "111101010" => data <= conv_std_logic_vector(534,11);
WHEN "111101011" => data <= conv_std_logic_vector(533,11);
WHEN "111101100" => data <= conv_std_logic_vector(532,11);
WHEN "111101101" => data <= conv_std_logic_vector(531,11);
WHEN "111101110" => data <= conv_std_logic_vector(530,11);
WHEN "111101111" => data <= conv_std_logic_vector(529,11);
WHEN "111110000" => data <= conv_std_logic_vector(528,11);
WHEN "111110001" => data <= conv_std_logic_vector(527,11);
WHEN "111110010" => data <= conv_std_logic_vector(526,11);
WHEN "111110011" => data <= conv_std_logic_vector(525,11);
WHEN "111110100" => data <= conv_std_logic_vector(524,11);
WHEN "111110101" => data <= conv_std_logic_vector(523,11);
WHEN "111110110" => data <= conv_std_logic_vector(522,11);
WHEN "111110111" => data <= conv_std_logic_vector(521,11);
WHEN "111111000" => data <= conv_std_logic_vector(520,11);
WHEN "111111001" => data <= conv_std_logic_vector(519,11);
WHEN "111111010" => data <= conv_std_logic_vector(518,11);
WHEN "111111011" => data <= conv_std_logic_vector(517,11);
WHEN "111111100" => data <= conv_std_logic_vector(516,11);
WHEN "111111101" => data <= conv_std_logic_vector(515,11);
WHEN "111111110" => data <= conv_std_logic_vector(514,11);
WHEN "111111111" => data <= conv_std_logic_vector(513,11);
WHEN others => data <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/fp_atanpi_s5.vhd | 10 | 525003 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_atanpi_s5
-- VHDL created on Tue Mar 12 11:23:23 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_atanpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_atanpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBiasM2_uid6_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal ooPi_uid9_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal piO2_uid46_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal piO4_uid47_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid64_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal zS_uid67_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q : std_logic_vector (12 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 : std_logic_vector (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr : UNSIGNED (50 downto 0);
signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q : std_logic_vector (50 downto 0);
signal fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (10 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr : UNSIGNED (47 downto 0);
signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_q : std_logic_vector (40 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid366_pT1_uid348_invPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_b : std_logic_vector (21 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_pr : SIGNED (37 downto 0);
signal prodXY_uid369_pT2_uid354_invPolyEval_q : std_logic_vector (36 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid299_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid299_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid300_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid300_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid301_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid301_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid344_invTabGen_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid344_invTabGen_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid345_invTabGen_lutmem_ia : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_iq : std_logic_vector (19 downto 0);
signal memoryC1_uid345_invTabGen_lutmem_q : std_logic_vector (19 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid346_invTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid346_invTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q : std_logic_vector (19 downto 0);
signal reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q : std_logic_vector (21 downto 0);
signal reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q : std_logic_vector (28 downto 0);
signal reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (26 downto 0);
signal reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (8 downto 0);
signal reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (24 downto 0);
signal reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (32 downto 0);
signal reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (22 downto 0);
signal reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (22 downto 0);
signal reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (7 downto 0);
signal reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (7 downto 0);
signal reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (23 downto 0);
signal reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (11 downto 0);
signal reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (2 downto 0);
signal ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q : std_logic_vector (7 downto 0);
signal ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (8 downto 0);
signal ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (22 downto 0);
signal ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (7 downto 0);
signal ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (20 downto 0);
signal ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (18 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : signal is true;
signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true;
signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : signal is true;
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_c : std_logic_vector (0 downto 0);
signal excSelBits_uid114_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b : std_logic_vector(33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o : std_logic_vector (33 downto 0);
signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q : std_logic_vector (33 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b : std_logic_vector(32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o : std_logic_vector (32 downto 0);
signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid15_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid16_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal singX_uid17_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid36_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0);
signal path2_uid56_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0);
signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q : std_logic_vector (9 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_a : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_b : std_logic_vector(26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_o : std_logic_vector (26 downto 0);
signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (26 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOOPi_uid10_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_in : std_logic_vector (49 downto 0);
signal normBit_uid80_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in : std_logic_vector (48 downto 0);
signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b : std_logic_vector (22 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal R_uid221_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (14 downto 0);
signal R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal constOut_uid54_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal u_uid58_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(4 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal R_uid120_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (16 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (8 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in : std_logic_vector (8 downto 0);
signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in : std_logic_vector (25 downto 0);
signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (11 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (9 downto 0);
signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (33 downto 0);
signal fpOOPi_uid11_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (32 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (28 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (24 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid304_atanXOXPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid305_atanXOXPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid305_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid310_atanXOXPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid311_atanXOXPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid311_atanXOXPolyEval_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid349_invPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid349_invPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid350_invPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid350_invPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid355_invPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid355_invPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid356_invPolyEval_in : std_logic_vector (22 downto 0);
signal highBBits_uid356_invPolyEval_b : std_logic_vector (20 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0);
signal y_uid73_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal yT1_uid347_invPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid347_invPolyEval_b : std_logic_vector (11 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expU_uid59_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracU_uid60_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid38_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b : std_logic_vector (3 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0);
signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid306_atanXOXPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid312_atanXOXPolyEval_q : std_logic_vector (31 downto 0);
signal sumAHighB_uid351_invPolyEval_a : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_b : std_logic_vector(20 downto 0);
signal sumAHighB_uid351_invPolyEval_o : std_logic_vector (20 downto 0);
signal sumAHighB_uid351_invPolyEval_q : std_logic_vector (20 downto 0);
signal sumAHighB_uid357_invPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid357_invPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid357_invPolyEval_q : std_logic_vector (29 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0);
signal yAddr_uid75_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in : std_logic_vector (26 downto 0);
signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b : std_logic_vector (17 downto 0);
signal rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b : std_logic_vector (4 downto 0);
signal expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal s1_uid304_uid307_atanXOXPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid310_uid313_atanXOXPolyEval_q : std_logic_vector (33 downto 0);
signal s1_uid349_uid352_invPolyEval_q : std_logic_vector (21 downto 0);
signal s2_uid355_uid358_invPolyEval_q : std_logic_vector (31 downto 0);
signal yT1_uid302_atanXOXPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid302_atanXOXPolyEval_b : std_logic_vector (12 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (20 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0);
signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (18 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid119_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0);
signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0);
signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0);
signal pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0);
signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0);
signal excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0);
signal roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (25 downto 0);
begin
--xIn(GPIN,3)@0
--cstAllZWF_uid19_atanX_uid8_fpArctanPiTest(CONSTANT,18)
cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable(LOGICAL,878)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q <= not ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,1008)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a or ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,1004)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100001";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,1005)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,1006)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,1009)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,1010)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--fracX_uid16_atanX_uid8_fpArctanPiTest(BITSELECT,15)@0
fracX_uid16_atanX_uid8_fpArctanPiTest_in <= a(22 downto 0);
fracX_uid16_atanX_uid8_fpArctanPiTest_b <= fracX_uid16_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid35_atanX_uid8_fpArctanPiTest(LOGICAL,34)@0
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b else "0";
--InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest(LOGICAL,36)@0
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q <= not InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a;
--cstAllOWE_uid18_atanX_uid8_fpArctanPiTest(CONSTANT,17)
cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q <= "11111111";
--expX_uid15_atanX_uid8_fpArctanPiTest(BITSELECT,14)@0
expX_uid15_atanX_uid8_fpArctanPiTest_in <= a(30 downto 0);
expX_uid15_atanX_uid8_fpArctanPiTest_b <= expX_uid15_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--expXIsMax_uid33_atanX_uid8_fpArctanPiTest(LOGICAL,32)@0
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a = expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b else "0";
--exc_N_uid38_atanX_uid8_fpArctanPiTest(LOGICAL,37)@0
exc_N_uid38_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_b <= InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q;
exc_N_uid38_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_a and exc_N_uid38_atanX_uid8_fpArctanPiTest_b;
--InvExc_N_uid118_atanX_uid8_fpArctanPiTest(LOGICAL,117)@0
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q;
InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q <= not InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a;
--singX_uid17_atanX_uid8_fpArctanPiTest(BITSELECT,16)@0
singX_uid17_atanX_uid8_fpArctanPiTest_in <= a;
singX_uid17_atanX_uid8_fpArctanPiTest_b <= singX_uid17_atanX_uid8_fpArctanPiTest_in(31 downto 31);
--signR_uid119_atanX_uid8_fpArctanPiTest(LOGICAL,118)@0
signR_uid119_atanX_uid8_fpArctanPiTest_a <= singX_uid17_atanX_uid8_fpArctanPiTest_b;
signR_uid119_atanX_uid8_fpArctanPiTest_b <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
signR_uid119_atanX_uid8_fpArctanPiTest_q <= signR_uid119_atanX_uid8_fpArctanPiTest_a and signR_uid119_atanX_uid8_fpArctanPiTest_b;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,998)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid119_atanX_uid8_fpArctanPiTest_q, xout => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,1000)
-- every=1, low=0, high=33, step=1, init=1
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 32 THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 33;
ELSE
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,1001)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,1002)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,999)
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 34,
width_b => 1,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,879)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a or ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,875)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100000";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,876)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,877)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,880)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,881)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,869)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid17_atanX_uid8_fpArctanPiTest_b, xout => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,871)
-- every=1, low=0, high=32, step=1, init=1
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 31 THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 32;
ELSE
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6));
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,872)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,873)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,870)
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid22_atanX_uid8_fpArctanPiTest(CONSTANT,21)
cstBias_uid22_atanX_uid8_fpArctanPiTest_q <= "01111111";
--piO2_uid46_atanX_uid8_fpArctanPiTest(CONSTANT,45)
piO2_uid46_atanX_uid8_fpArctanPiTest_q <= "11001001000011111101101011";
--cstPiO2_uid48_atanX_uid8_fpArctanPiTest(BITSELECT,47)@35
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in <= piO2_uid46_atanX_uid8_fpArctanPiTest_q(24 downto 0);
cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b <= cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--fpPiO2C_uid49_atanX_uid8_fpArctanPiTest(BITJOIN,48)@35
fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBias_uid22_atanX_uid8_fpArctanPiTest_q & cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b;
--cstBiasM1_uid23_atanX_uid8_fpArctanPiTest(CONSTANT,22)
cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q <= "01111110";
--piO4_uid47_atanX_uid8_fpArctanPiTest(CONSTANT,46)
piO4_uid47_atanX_uid8_fpArctanPiTest_q <= "110010010000111111011011";
--cstPiO4_uid51_atanX_uid8_fpArctanPiTest(BITSELECT,50)@35
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in <= piO4_uid47_atanX_uid8_fpArctanPiTest_q(22 downto 0);
cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b <= cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--fpPiO4C_uid52_atanX_uid8_fpArctanPiTest(BITJOIN,51)@35
fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q & cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,892)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a or ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,893)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,894)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--exc_I_uid36_atanX_uid8_fpArctanPiTest(LOGICAL,35)@0
exc_I_uid36_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_b <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
exc_I_uid36_atanX_uid8_fpArctanPiTest_q <= exc_I_uid36_atanX_uid8_fpArctanPiTest_a and exc_I_uid36_atanX_uid8_fpArctanPiTest_b;
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,882)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid36_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,883)
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(0 downto 0);
--constOut_uid54_atanX_uid8_fpArctanPiTest(MUX,53)@35
constOut_uid54_atanX_uid8_fpArctanPiTest_s <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q;
constOut_uid54_atanX_uid8_fpArctanPiTest: PROCESS (constOut_uid54_atanX_uid8_fpArctanPiTest_s, en, fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q, fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE constOut_uid54_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expOutCst_uid112_atanX_uid8_fpArctanPiTest(BITSELECT,111)@35
expOutCst_uid112_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expOutCst_uid112_atanX_uid8_fpArctanPiTest_b <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5(REG,428)@35
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--cst01pWShift_uid69_atanX_uid8_fpArctanPiTest(CONSTANT,68)
cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q <= "0000000000000";
--reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2(REG,389)@0
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= signR_uid119_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c(DELAY,707)@1
ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,1022)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a or ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b);
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top(CONSTANT,1018)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp(LOGICAL,1019)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a = ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b else "0";
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg(REG,1020)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,1023)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,1024)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b;
--cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,230)
cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111110";
--expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest(SUB,259)@0
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,260)@0
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,229)
cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111101";
--expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest(SUB,256)@0
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b);
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b));
expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,257)@0
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0);
expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,249)@0
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b else "0";
--expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest(MUX,263)@0
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s <= fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expXIsZero_uid31_atanX_uid8_fpArctanPiTest(LOGICAL,30)@0
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a = expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b else "0";
--udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,258)@0
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(8)) & expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q);
udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in(9 downto 9);
--InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,245)@0
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a;
--InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,246)@0
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a <= expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q;
InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a;
--exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,247)@0
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a <= InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b <= InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q;
exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c;
--xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,264)@0
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b;
xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a and xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b;
--xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,265)@0
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q;
xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q <= xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a or xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b;
--excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,266)@0
excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q & expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q & xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q;
--reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0(REG,378)@0
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest(LOOKUP,267)@1
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest(MUX,269)@1
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,1012)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt(COUNTER,1014)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg(REG,1015)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux(MUX,1016)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,1013)
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia
);
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid20_atanX_uid8_fpArctanPiTest(CONSTANT,19)
cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000001";
--oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,248)@0
oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q <= VCC_q & fracX_uid16_atanX_uid8_fpArctanPiTest_b;
--y_uid251_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,250)@0
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in <= oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q(22 downto 0);
y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,252)@0
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b;
yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 15);
--reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0(REG,379)@0
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid346_invTabGen_lutmem(DUALMEM,376)@1
memoryC2_uid346_invTabGen_lutmem_ia <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_aa <= (others => '0');
memoryC2_uid346_invTabGen_lutmem_ab <= reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q;
memoryC2_uid346_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid346_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid346_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid346_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid346_invTabGen_lutmem_iq,
address_a => memoryC2_uid346_invTabGen_lutmem_aa,
data_a => memoryC2_uid346_invTabGen_lutmem_ia
);
memoryC2_uid346_invTabGen_lutmem_reset0 <= areset;
memoryC2_uid346_invTabGen_lutmem_q <= memoryC2_uid346_invTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1(REG,381)@3
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= memoryC2_uid346_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,1011)
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a(DELAY,680)@0
ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,253)@3
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in <= ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q(14 downto 0);
yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in(14 downto 0);
--yT1_uid347_invPolyEval(BITSELECT,346)@3
yT1_uid347_invPolyEval_in <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b;
yT1_uid347_invPolyEval_b <= yT1_uid347_invPolyEval_in(14 downto 3);
--reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0(REG,380)@3
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= yT1_uid347_invPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid366_pT1_uid348_invPolyEval(MULT,365)@4
prodXY_uid366_pT1_uid348_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid366_pT1_uid348_invPolyEval_a),13)) * SIGNED(prodXY_uid366_pT1_uid348_invPolyEval_b);
prodXY_uid366_pT1_uid348_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_b <= (others => '0');
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_a <= reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q;
prodXY_uid366_pT1_uid348_invPolyEval_b <= reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q;
prodXY_uid366_pT1_uid348_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid366_pT1_uid348_invPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid366_pT1_uid348_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid366_pT1_uid348_invPolyEval_q <= prodXY_uid366_pT1_uid348_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid367_pT1_uid348_invPolyEval(BITSELECT,366)@7
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in <= prodXY_uid366_pT1_uid348_invPolyEval_q;
prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in(23 downto 11);
--highBBits_uid350_invPolyEval(BITSELECT,349)@7
highBBits_uid350_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b;
highBBits_uid350_invPolyEval_b <= highBBits_uid350_invPolyEval_in(12 downto 1);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a(DELAY,804)@1
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid345_invTabGen_lutmem(DUALMEM,375)@4
memoryC1_uid345_invTabGen_lutmem_ia <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_aa <= (others => '0');
memoryC1_uid345_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q;
memoryC1_uid345_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 20,
widthad_a => 8,
numwords_a => 256,
width_b => 20,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid345_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid345_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid345_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid345_invTabGen_lutmem_iq,
address_a => memoryC1_uid345_invTabGen_lutmem_aa,
data_a => memoryC1_uid345_invTabGen_lutmem_ia
);
memoryC1_uid345_invTabGen_lutmem_reset0 <= areset;
memoryC1_uid345_invTabGen_lutmem_q <= memoryC1_uid345_invTabGen_lutmem_iq(19 downto 0);
--reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0(REG,383)@6
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= "00000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= memoryC1_uid345_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid351_invPolyEval(ADD,350)@7
sumAHighB_uid351_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q(19)) & reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q);
sumAHighB_uid351_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid350_invPolyEval_b(11)) & highBBits_uid350_invPolyEval_b);
sumAHighB_uid351_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid351_invPolyEval_a) + SIGNED(sumAHighB_uid351_invPolyEval_b));
sumAHighB_uid351_invPolyEval_q <= sumAHighB_uid351_invPolyEval_o(20 downto 0);
--lowRangeB_uid349_invPolyEval(BITSELECT,348)@7
lowRangeB_uid349_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b(0 downto 0);
lowRangeB_uid349_invPolyEval_b <= lowRangeB_uid349_invPolyEval_in(0 downto 0);
--s1_uid349_uid352_invPolyEval(BITJOIN,351)@7
s1_uid349_uid352_invPolyEval_q <= sumAHighB_uid351_invPolyEval_q & lowRangeB_uid349_invPolyEval_b;
--reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1(REG,385)@7
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= "0000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= s1_uid349_uid352_invPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor(LOGICAL,1059)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a or ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg(REG,966)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena(REG,1060)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd(LOGICAL,1061)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg(DELAY,1051)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt(COUNTER,962)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i,1));
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg(REG,963)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux(MUX,964)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux: PROCESS (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q)
BEGIN
CASE ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s IS
WHEN "0" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
WHEN "1" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q;
WHEN OTHERS => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem(DUALMEM,1052)
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0(REG,384)@7
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid369_pT2_uid354_invPolyEval(MULT,368)@8
prodXY_uid369_pT2_uid354_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid369_pT2_uid354_invPolyEval_a),16)) * SIGNED(prodXY_uid369_pT2_uid354_invPolyEval_b);
prodXY_uid369_pT2_uid354_invPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_b <= (others => '0');
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_a <= reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q;
prodXY_uid369_pT2_uid354_invPolyEval_b <= reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q;
prodXY_uid369_pT2_uid354_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid369_pT2_uid354_invPolyEval_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid369_pT2_uid354_invPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid369_pT2_uid354_invPolyEval_q <= prodXY_uid369_pT2_uid354_invPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid370_pT2_uid354_invPolyEval(BITSELECT,369)@11
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in <= prodXY_uid369_pT2_uid354_invPolyEval_q;
prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in(36 downto 14);
--highBBits_uid356_invPolyEval(BITSELECT,355)@11
highBBits_uid356_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b;
highBBits_uid356_invPolyEval_b <= highBBits_uid356_invPolyEval_in(22 downto 2);
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor(LOGICAL,1048)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top(CONSTANT,1031)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q <= "0100";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp(LOGICAL,1032)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b else "0";
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg(REG,1033)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena(REG,1049)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd(LOGICAL,1050)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg(DELAY,1038)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt(COUNTER,1027)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i,3));
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg(REG,1028)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux(MUX,1029)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem(DUALMEM,1039)
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid344_invTabGen_lutmem(DUALMEM,374)@8
memoryC0_uid344_invTabGen_lutmem_ia <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_aa <= (others => '0');
memoryC0_uid344_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q;
memoryC0_uid344_invTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid344_invTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid344_invTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid344_invTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid344_invTabGen_lutmem_iq,
address_a => memoryC0_uid344_invTabGen_lutmem_aa,
data_a => memoryC0_uid344_invTabGen_lutmem_ia
);
memoryC0_uid344_invTabGen_lutmem_reset0 <= areset;
memoryC0_uid344_invTabGen_lutmem_q <= memoryC0_uid344_invTabGen_lutmem_iq(28 downto 0);
--reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0(REG,387)@10
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= "00000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= memoryC0_uid344_invTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid357_invPolyEval(ADD,356)@11
sumAHighB_uid357_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q(28)) & reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q);
sumAHighB_uid357_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid356_invPolyEval_b(20)) & highBBits_uid356_invPolyEval_b);
sumAHighB_uid357_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid357_invPolyEval_a) + SIGNED(sumAHighB_uid357_invPolyEval_b));
sumAHighB_uid357_invPolyEval_q <= sumAHighB_uid357_invPolyEval_o(29 downto 0);
--lowRangeB_uid355_invPolyEval(BITSELECT,354)@11
lowRangeB_uid355_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b(1 downto 0);
lowRangeB_uid355_invPolyEval_b <= lowRangeB_uid355_invPolyEval_in(1 downto 0);
--s2_uid355_uid358_invPolyEval(BITJOIN,357)@11
s2_uid355_uid358_invPolyEval_q <= sumAHighB_uid357_invPolyEval_q & lowRangeB_uid355_invPolyEval_b;
--fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,255)@11
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in <= s2_uid355_uid358_invPolyEval_q(28 downto 0);
fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in(28 downto 5);
--fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,261)@11
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b(22 downto 0);
fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,688)@0
ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest(MUX,262)@11
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1(REG,388)@1
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,701)@2
ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest(MUX,268)@12
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q;
fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid273_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,272)@12
R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q <= ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q & fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,905)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a or ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,901)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "01001";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,902)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b else "0";
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,903)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,906)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,907)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,895)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,897)
-- every=1, low=0, high=9, step=1, init=1
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 8 THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 9;
ELSE
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,4));
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,898)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,899)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
WHEN "1" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,896)
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 4,
numwords_a => 10,
width_b => 32,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(31 downto 0);
--path2_uid56_atanX_uid8_fpArctanPiTest(COMPARE,55)@0
path2_uid56_atanX_uid8_fpArctanPiTest_cin <= GND_q;
path2_uid56_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid15_atanX_uid8_fpArctanPiTest_b) & '0';
path2_uid56_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q) & path2_uid56_atanX_uid8_fpArctanPiTest_cin(0);
path2_uid56_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_b));
path2_uid56_atanX_uid8_fpArctanPiTest_n(0) <= not path2_uid56_atanX_uid8_fpArctanPiTest_o(10);
--reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1(REG,390)@0
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= path2_uid56_atanX_uid8_fpArctanPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b(DELAY,466)@1
ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--u_uid58_atanX_uid8_fpArctanPiTest(MUX,57)@12
u_uid58_atanX_uid8_fpArctanPiTest_s <= ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q;
u_uid58_atanX_uid8_fpArctanPiTest: PROCESS (u_uid58_atanX_uid8_fpArctanPiTest_s, en, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q, R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE u_uid58_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => u_uid58_atanX_uid8_fpArctanPiTest_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "1" => u_uid58_atanX_uid8_fpArctanPiTest_q <= R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => u_uid58_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracU_uid60_atanX_uid8_fpArctanPiTest(BITSELECT,59)@12
fracU_uid60_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracU_uid60_atanX_uid8_fpArctanPiTest_b <= fracU_uid60_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a(DELAY,471)@12
ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracU_uid60_atanX_uid8_fpArctanPiTest_b, xout => ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest(BITJOIN,60)@13
oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q;
--oFracUExt_uid70_atanX_uid8_fpArctanPiTest(BITJOIN,69)@13
oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q <= cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q & oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
--X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,282)@13
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(24 downto 0);
X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(24 downto 0);
--leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,281)
leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,283)@13
leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5(REG,399)@13
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,279)@13
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(28 downto 0);
X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(28 downto 0);
--leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,280)@13
leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4(REG,398)@13
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,276)@13
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(32 downto 0);
X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(32 downto 0);
--leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,275)
leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "0000";
--leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,277)@13
leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3(REG,397)@13
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,396)@13
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--zS_uid67_atanX_uid8_fpArctanPiTest(CONSTANT,66)
zS_uid67_atanX_uid8_fpArctanPiTest_q <= "000000000";
--shiftBias_uid64_atanX_uid8_fpArctanPiTest(CONSTANT,63)
shiftBias_uid64_atanX_uid8_fpArctanPiTest_q <= "01110010";
--expU_uid59_atanX_uid8_fpArctanPiTest(BITSELECT,58)@12
expU_uid59_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expU_uid59_atanX_uid8_fpArctanPiTest_b <= expU_uid59_atanX_uid8_fpArctanPiTest_in(30 downto 23);
--reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1(REG,391)@12
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= expU_uid59_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--shiftValue_uid65_atanX_uid8_fpArctanPiTest(SUB,64)@13
shiftValue_uid65_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid64_atanX_uid8_fpArctanPiTest_q);
shiftValue_uid65_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_b));
shiftValue_uid65_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--ShiftValue8_uid66_atanX_uid8_fpArctanPiTest(BITSELECT,65)@13
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in(8 downto 8);
--shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest(MUX,67)@13
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b;
shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest: PROCESS (shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s, en, shiftValue_uid65_atanX_uid8_fpArctanPiTest_q, zS_uid67_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= zS_uid67_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest(BITSELECT,70)@13
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in <= shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q(3 downto 0);
fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,284)@13
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b;
leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,395)@13
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,285)@14
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q, reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q, reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q;
WHEN "11" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,293)@14
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(33 downto 0);
LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(33 downto 0);
--ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,725)@14
ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,292)
leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000";
--leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,294)@15
leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,290)@14
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(34 downto 0);
LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(34 downto 0);
--ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,723)@14
ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,289)
leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "00";
--leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,291)@15
leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
--LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,287)@14
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(35 downto 0);
--ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,721)@14
ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,288)@15
leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,401)@14
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,295)@13
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a(DELAY,829)@13
ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,400)@14
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,296)@15
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q;
leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid73_atanX_uid8_fpArctanPiTest(BITSELECT,72)@15
y_uid73_atanX_uid8_fpArctanPiTest_in <= leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0);
y_uid73_atanX_uid8_fpArctanPiTest_b <= y_uid73_atanX_uid8_fpArctanPiTest_in(35 downto 1);
--yAddr_uid75_atanX_uid8_fpArctanPiTest(BITSELECT,74)@15
yAddr_uid75_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b;
yAddr_uid75_atanX_uid8_fpArctanPiTest_b <= yAddr_uid75_atanX_uid8_fpArctanPiTest_in(34 downto 27);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0(REG,402)@15
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= yAddr_uid75_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid301_atanXOXTabGen_lutmem(DUALMEM,373)@16
memoryC2_uid301_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC2_uid301_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q;
memoryC2_uid301_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC2_uid301_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid301_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid301_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid301_atanXOXTabGen_lutmem_iq,
address_a => memoryC2_uid301_atanXOXTabGen_lutmem_aa,
data_a => memoryC2_uid301_atanXOXTabGen_lutmem_ia
);
memoryC2_uid301_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC2_uid301_atanXOXTabGen_lutmem_q <= memoryC2_uid301_atanXOXTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1(REG,404)@18
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= memoryC2_uid301_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPPolyEval_uid76_atanX_uid8_fpArctanPiTest(BITSELECT,75)@15
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b(26 downto 0);
yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in(26 downto 9);
--yT1_uid302_atanXOXPolyEval(BITSELECT,301)@15
yT1_uid302_atanXOXPolyEval_in <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
yT1_uid302_atanXOXPolyEval_b <= yT1_uid302_atanXOXPolyEval_in(17 downto 5);
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg(DELAY,1062)
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid302_atanXOXPolyEval_b, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a(DELAY,832)@15
ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0(REG,403)@18
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid360_pT1_uid303_atanXOXPolyEval(MULT,359)@19
prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_b);
prodXY_uid360_pT1_uid303_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= (others => '0');
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q;
prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid360_pT1_uid303_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval(BITSELECT,360)@22
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_q;
prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in(25 downto 12);
--highBBits_uid305_atanXOXPolyEval(BITSELECT,304)@22
highBBits_uid305_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b;
highBBits_uid305_atanXOXPolyEval_b <= highBBits_uid305_atanXOXPolyEval_in(13 downto 1);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a(DELAY,834)@15
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0(REG,405)@18
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid300_atanXOXTabGen_lutmem(DUALMEM,372)@19
memoryC1_uid300_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC1_uid300_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q;
memoryC1_uid300_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC1_uid300_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid300_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid300_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid300_atanXOXTabGen_lutmem_iq,
address_a => memoryC1_uid300_atanXOXTabGen_lutmem_aa,
data_a => memoryC1_uid300_atanXOXTabGen_lutmem_ia
);
memoryC1_uid300_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC1_uid300_atanXOXTabGen_lutmem_q <= memoryC1_uid300_atanXOXTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0(REG,406)@21
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= memoryC1_uid300_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid306_atanXOXPolyEval(ADD,305)@22
sumAHighB_uid306_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q);
sumAHighB_uid306_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid305_atanXOXPolyEval_b(12)) & highBBits_uid305_atanXOXPolyEval_b);
sumAHighB_uid306_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid306_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid306_atanXOXPolyEval_b));
sumAHighB_uid306_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_o(21 downto 0);
--lowRangeB_uid304_atanXOXPolyEval(BITSELECT,303)@22
lowRangeB_uid304_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b(0 downto 0);
lowRangeB_uid304_atanXOXPolyEval_b <= lowRangeB_uid304_atanXOXPolyEval_in(0 downto 0);
--s1_uid304_uid307_atanXOXPolyEval(BITJOIN,306)@22
s1_uid304_uid307_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_q & lowRangeB_uid304_atanXOXPolyEval_b;
--reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1(REG,408)@22
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= s1_uid304_uid307_atanXOXPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor(LOGICAL,1035)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b);
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena(REG,1036)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q = "1") THEN
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd(LOGICAL,1037)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b <= en;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b;
--reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0(REG,407)@15
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg(DELAY,1025)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem(DUALMEM,1026)
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq,
address_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa,
data_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia
);
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid363_pT2_uid309_atanXOXPolyEval(MULT,362)@23
prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_b);
prodXY_uid363_pT2_uid309_atanXOXPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= (others => '0');
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q;
prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid363_pT2_uid309_atanXOXPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval(BITSELECT,363)@26
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_q;
prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in(40 downto 17);
--highBBits_uid311_atanXOXPolyEval(BITSELECT,310)@26
highBBits_uid311_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b;
highBBits_uid311_atanXOXPolyEval_b <= highBBits_uid311_atanXOXPolyEval_in(23 downto 2);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor(LOGICAL,1073)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a or ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b);
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena(REG,1074)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q = "1") THEN
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd(LOGICAL,1075)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b <= en;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b;
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg(DELAY,1063)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem(DUALMEM,1064)
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia
);
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0(REG,409)@22
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid299_atanXOXTabGen_lutmem(DUALMEM,371)@23
memoryC0_uid299_atanXOXTabGen_lutmem_ia <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_aa <= (others => '0');
memoryC0_uid299_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q;
memoryC0_uid299_atanXOXTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 8,
numwords_a => 256,
width_b => 31,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_atanpi_s5_memoryC0_uid299_atanXOXTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid299_atanXOXTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid299_atanXOXTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid299_atanXOXTabGen_lutmem_iq,
address_a => memoryC0_uid299_atanXOXTabGen_lutmem_aa,
data_a => memoryC0_uid299_atanXOXTabGen_lutmem_ia
);
memoryC0_uid299_atanXOXTabGen_lutmem_reset0 <= areset;
memoryC0_uid299_atanXOXTabGen_lutmem_q <= memoryC0_uid299_atanXOXTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0(REG,410)@25
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= memoryC0_uid299_atanXOXTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid312_atanXOXPolyEval(ADD,311)@26
sumAHighB_uid312_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q);
sumAHighB_uid312_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid311_atanXOXPolyEval_b(21)) & highBBits_uid311_atanXOXPolyEval_b);
sumAHighB_uid312_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid312_atanXOXPolyEval_b));
sumAHighB_uid312_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_o(31 downto 0);
--lowRangeB_uid310_atanXOXPolyEval(BITSELECT,309)@26
lowRangeB_uid310_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b(1 downto 0);
lowRangeB_uid310_atanXOXPolyEval_b <= lowRangeB_uid310_atanXOXPolyEval_in(1 downto 0);
--s2_uid310_uid313_atanXOXPolyEval(BITJOIN,312)@26
s2_uid310_uid313_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_q & lowRangeB_uid310_atanXOXPolyEval_b;
--fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest(BITSELECT,77)@26
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in <= s2_uid310_uid313_atanXOXPolyEval_q(31 downto 0);
fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in(31 downto 5);
--reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1(REG,412)@26
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,918)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,914)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01010";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,915)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,916)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,919)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,920)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0(REG,411)@13
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,908)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,910)
-- every=1, low=0, high=10, step=1, init=1
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 9 THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 10;
ELSE
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,911)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,912)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,909)
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 11,
width_b => 24,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(23 downto 0);
--mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest(MULT,78)@27
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr <= UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a) * UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b);
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= (others => '0');
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid80_atanX_uid8_fpArctanPiTest(BITSELECT,79)@30
normBit_uid80_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(49 downto 0);
normBit_uid80_atanX_uid8_fpArctanPiTest_b <= normBit_uid80_atanX_uid8_fpArctanPiTest_in(49 downto 49);
--InvNormBit_uid84_atanX_uid8_fpArctanPiTest(LOGICAL,83)@30
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q <= not InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,931)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,927)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01111";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,928)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,929)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,932)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,933)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,921)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expU_uid59_atanX_uid8_fpArctanPiTest_b, xout => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,923)
-- every=1, low=0, high=15, step=1, init=1
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4));
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,924)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,925)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,922)
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 16,
width_b => 8,
widthad_b => 4,
numwords_b => 16,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(7 downto 0);
--expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest(SUB,84)@30
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q);
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b));
expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o(8 downto 0);
--fracRPath3High_uid81_atanX_uid8_fpArctanPiTest(BITSELECT,80)@30
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(48 downto 0);
fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in(48 downto 25);
--fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest(BITSELECT,81)@30
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(47 downto 0);
fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in(47 downto 24);
--fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest(MUX,82)@30
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s <= normBit_uid80_atanX_uid8_fpArctanPiTest_b;
fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s, en, fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b, fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest(BITJOIN,85)@30
expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q & fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q;
--reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0(REG,420)@30
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest(ADD,86)@31
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000" & VCC_q);
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b));
expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o(33 downto 0);
--expRPath3_uid89_atanX_uid8_fpArctanPiTest(BITSELECT,88)@31
expRPath3_uid89_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath3_uid89_atanX_uid8_fpArctanPiTest_b <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4(REG,427)@31
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,971)
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e(DELAY,534)@32
ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,337)@33
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,339)@33
rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= GND_q & RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,333)
rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000";
--rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,322)
rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000000000000000000000";
--X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,321)@32
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 24);
--rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,323)@32
rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,319)
rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "0000000000000000";
--X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,318)@32
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 16);
--rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,320)@32
rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,315)@32
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 8);
--rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,317)@32
rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q & X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
--ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a(DELAY,504)@30
ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q, xout => ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest(BITJOIN,93)@32
oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q;
--cstWFP2_uid25_atanX_uid8_fpArctanPiTest(CONSTANT,24)
cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q <= "00011001";
--reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1(REG,413)@30
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest(SUB,89)@31
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q(8)) & reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q);
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a) - SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b));
shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o(9 downto 0);
--shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest(BITSELECT,91)@31
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q(7 downto 0);
shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in(7 downto 0);
--cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest(CONSTANT,23)
cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q <= "01101000";
--shiftOut_uid91_atanX_uid8_fpArctanPiTest(COMPARE,90)@13
shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin <= GND_q;
shiftOut_uid91_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & '0';
shiftOut_uid91_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q) & shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin(0);
shiftOut_uid91_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_b));
shiftOut_uid91_atanX_uid8_fpArctanPiTest_c(0) <= shiftOut_uid91_atanX_uid8_fpArctanPiTest_o(10);
--ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b(DELAY,502)@13
ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => shiftOut_uid91_atanX_uid8_fpArctanPiTest_c, xout => ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--sValPostSOut_uid93_atanX_uid8_fpArctanPiTest(MUX,92)@31
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s <= ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q;
sValPostSOut_uid93_atanX_uid8_fpArctanPiTest: PROCESS (sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s, en, shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b, cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest(BITSELECT,94)@31
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in <= sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q(4 downto 0);
sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,324)@31
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b;
rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,414)@31
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,325)@32
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,332)@32
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 6);
--ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,762)@32
ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,334)@33
rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,329)@32
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 4);
--ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,760)@32
ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,331)@33
rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,326)@32
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 2);
--ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,758)@32
ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,328)@33
rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q;
--reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2(REG,416)@32
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,335)@31
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a(DELAY,844)@31
ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,415)@32
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,336)@33
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q;
rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q, rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,340)@31
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,417)@31
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b(DELAY,772)@32
ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,341)@33
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q;
rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest(BITJOIN,96)@33
pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & GND_q;
--reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1(REG,418)@33
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid97_atanX_uid8_fpArctanPiTest(SUB,97)@34
path2Diff_uid97_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid46_atanX_uid8_fpArctanPiTest_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q);
path2Diff_uid97_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_b));
path2Diff_uid97_atanX_uid8_fpArctanPiTest_q <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_o(26 downto 0);
--normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest(BITSELECT,98)@34
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(25 downto 0);
normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in(25 downto 25);
--expRPath2_uid103_atanX_uid8_fpArctanPiTest(MUX,102)@34
expRPath2_uid103_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
expRPath2_uid103_atanX_uid8_fpArctanPiTest: PROCESS (expRPath2_uid103_atanX_uid8_fpArctanPiTest_s, en, cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q, cstBias_uid22_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPath2_uid103_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q;
WHEN "1" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest(BITSELECT,99)@34
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(24 downto 0);
path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in(24 downto 1);
--path2DiffLow_uid101_atanX_uid8_fpArctanPiTest(BITSELECT,100)@34
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(23 downto 0);
path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in(23 downto 0);
--fracRPath2_uid102_atanX_uid8_fpArctanPiTest(MUX,101)@34
fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b;
fracRPath2_uid102_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s, en, path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b, path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b)
BEGIN
CASE fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s IS
WHEN "0" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b;
WHEN "1" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b;
WHEN OTHERS => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest(BITJOIN,103)@34
expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q <= expRPath2_uid103_atanX_uid8_fpArctanPiTest_q & fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q;
--reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0(REG,419)@34
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest(ADD,104)@35
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q);
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b));
expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o(32 downto 0);
--expRPath2_uid107_atanX_uid8_fpArctanPiTest(BITSELECT,106)@35
expRPath2_uid107_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(31 downto 0);
expRPath2_uid107_atanX_uid8_fpArctanPiTest_b <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_in(31 downto 24);
--reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3(REG,426)@35
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor(LOGICAL,1086)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q <= not (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a or ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b);
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena(REG,1087)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q = "1") THEN
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd(LOGICAL,1088)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b <= en;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a and ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b;
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg(DELAY,1076)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid15_atanX_uid8_fpArctanPiTest_b, xout => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem(DUALMEM,1077)
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 33,
width_b => 8,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq,
address_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa,
data_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia
);
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq(7 downto 0);
--reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2(REG,425)@35
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,944)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,940)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "010010";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,941)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b else "0";
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,942)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,945)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,946)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--expXIsBias_uid44_atanX_uid8_fpArctanPiTest(LOGICAL,43)@0
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q;
expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a = expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b else "0";
--inIsOne_uid45_atanX_uid8_fpArctanPiTest(LOGICAL,44)@0
inIsOne_uid45_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_b <= expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q;
inIsOne_uid45_atanX_uid8_fpArctanPiTest_q <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_a and inIsOne_uid45_atanX_uid8_fpArctanPiTest_b;
--arctanIsConst_uid55_atanX_uid8_fpArctanPiTest(LOGICAL,54)@0
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_q;
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a or arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c(DELAY,522)@1
ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q, xout => ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasMwShift_uid62_atanX_uid8_fpArctanPiTest(CONSTANT,61)
biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q <= "01110011";
--atanUIsU_uid63_atanX_uid8_fpArctanPiTest(COMPARE,62)@13
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin <= GND_q;
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q) & '0';
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin(0);
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b));
atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n(0) <= not atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o(10);
--ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a(DELAY,520)@0
ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => path2_uid56_atanX_uid8_fpArctanPiTest_n, xout => ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--pathSelBits_uid108_atanX_uid8_fpArctanPiTest(BITJOIN,107)@13
pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q <= ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n & ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q;
--reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0(REG,392)@13
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,934)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,936)
-- every=1, low=0, high=18, step=1, init=1
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 17 THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 18;
ELSE
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,5));
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,937)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,938)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,935)
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 19,
width_b => 3,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest(LOOKUP,108)@35
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "001" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "010" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "011" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "110" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "111" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN OTHERS =>
fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRCalc_uid113_atanX_uid8_fpArctanPiTest(MUX,112)@36
expRCalc_uid113_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
expRCalc_uid113_atanX_uid8_fpArctanPiTest: PROCESS (expRCalc_uid113_atanX_uid8_fpArctanPiTest_s, en, reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q, reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q, ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE expRCalc_uid113_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q;
WHEN "01" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q;
WHEN "11" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid21_atanX_uid8_fpArctanPiTest(CONSTANT,20)
cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q <= "00000000";
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,995)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a or ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,996)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,997)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,985)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid38_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,986)
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,982)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b);
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,983)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,984)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b;
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,972)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q, xout => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,973)
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia
);
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid114_atanX_uid8_fpArctanPiTest(BITJOIN,113)@35
excSelBits_uid114_atanX_uid8_fpArctanPiTest_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q;
--reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0(REG,377)@35
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid114_atanX_uid8_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest(LOOKUP,114)@36
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid117_atanX_uid8_fpArctanPiTest(MUX,116)@36
expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
expRPostExc_uid117_atanX_uid8_fpArctanPiTest: PROCESS (expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, expRCalc_uid113_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid113_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracOutCst_uid110_atanX_uid8_fpArctanPiTest(BITSELECT,109)@35
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in(22 downto 0);
--reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5(REG,424)@35
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor(LOGICAL,968)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q <= not (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a or ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b);
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena(REG,969)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q = "1") THEN
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd(LOGICAL,970)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b <= en;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a and ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b;
--fracRPath3_uid88_atanX_uid8_fpArctanPiTest(BITSELECT,87)@31
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4(REG,423)@31
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,960)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem(DUALMEM,961)
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq,
address_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa,
data_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia
);
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 <= areset;
ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq(22 downto 0);
--fracRPath2_uid106_atanX_uid8_fpArctanPiTest(BITSELECT,105)@35
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(23 downto 0);
fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in(23 downto 1);
--reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3(REG,422)@35
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,957)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a or ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b);
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,958)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,959)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b;
--reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2(REG,421)@0
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= fracX_uid16_atanX_uid8_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,947)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,948)
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 33,
width_b => 23,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq,
address_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa,
data_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia
);
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset;
ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(22 downto 0);
--fracRCalc_uid111_atanX_uid8_fpArctanPiTest(MUX,110)@36
fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q;
fracRCalc_uid111_atanX_uid8_fpArctanPiTest: PROCESS (fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s, en, ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q, reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q, reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q)
BEGIN
CASE fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q;
WHEN "01" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q;
WHEN "10" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q;
WHEN "11" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q;
WHEN OTHERS => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid116_atanX_uid8_fpArctanPiTest(MUX,115)@36
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q;
fracRPostExc_uid116_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q;
WHEN "10" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid120_atanX_uid8_fpArctanPiTest(BITJOIN,119)@36
R_uid120_atanX_uid8_fpArctanPiTest_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q & expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q & fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q;
--fracX_uid126_rAtanPi_uid13_fpArctanPiTest(BITSELECT,125)@36
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(22 downto 0);
fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1(REG,431)@36
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest(LOGICAL,137)@37
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a <= reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b else "0";
--expX_uid122_rAtanPi_uid13_fpArctanPiTest(BITSELECT,121)@36
expX_uid122_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(30 downto 0);
expX_uid122_rAtanPi_uid13_fpArctanPiTest_b <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1(REG,429)@36
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest(LOGICAL,135)@37
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b else "0";
--exc_I_uid139_rAtanPi_uid13_fpArctanPiTest(LOGICAL,138)@37
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b;
--cstBiasM2_uid6_fpArctanPiTest(CONSTANT,5)
cstBiasM2_uid6_fpArctanPiTest_q <= "01111101";
--ooPi_uid9_fpArctanPiTest(CONSTANT,8)
ooPi_uid9_fpArctanPiTest_q <= "101000101111100110000011";
--fracOOPi_uid10_fpArctanPiTest(BITSELECT,9)@36
fracOOPi_uid10_fpArctanPiTest_in <= ooPi_uid9_fpArctanPiTest_q(22 downto 0);
fracOOPi_uid10_fpArctanPiTest_b <= fracOOPi_uid10_fpArctanPiTest_in(22 downto 0);
--fpOOPi_uid11_fpArctanPiTest(BITJOIN,10)@36
fpOOPi_uid11_fpArctanPiTest_q <= GND_q & cstBiasM2_uid6_fpArctanPiTest_q & fracOOPi_uid10_fpArctanPiTest_b;
--expY_uid123_rAtanPi_uid13_fpArctanPiTest(BITSELECT,122)@36
expY_uid123_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(30 downto 0);
expY_uid123_rAtanPi_uid13_fpArctanPiTest_b <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23);
--expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest(LOGICAL,149)@36
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a(DELAY,581)@36
ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest(LOGICAL,203)@37
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b;
--fracY_uid128_rAtanPi_uid13_fpArctanPiTest(BITSELECT,127)@36
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(22 downto 0);
fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0);
--fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest(LOGICAL,153)@36
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b(DELAY,575)@36
ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest(LOGICAL,151)@36
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b else "0";
--ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a(DELAY,574)@36
ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid155_rAtanPi_uid13_fpArctanPiTest(LOGICAL,154)@37
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b <= ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q;
exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b;
--expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest(LOGICAL,133)@37
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b else "0";
--excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest(LOGICAL,204)@37
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b;
--ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest(LOGICAL,205)@37
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q;
ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a or ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b;
--InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest(LOGICAL,155)@36
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid157_rAtanPi_uid13_fpArctanPiTest(LOGICAL,156)@36
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b;
--ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a(DELAY,579)@36
ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest(LOGICAL,139)@37
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q;
InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a;
--exc_N_uid141_rAtanPi_uid13_fpArctanPiTest(LOGICAL,140)@37
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q;
exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b;
--excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest(LOGICAL,206)@37
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q;
excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c;
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest(LOGICAL,218)@37
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q;
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= not InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a;
END IF;
END PROCESS;
--signY_uid125_rAtanPi_uid13_fpArctanPiTest(BITSELECT,124)@36
signY_uid125_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q;
signY_uid125_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signX_uid124_rAtanPi_uid13_fpArctanPiTest(BITSELECT,123)@36
signX_uid124_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q;
signX_uid124_rAtanPi_uid13_fpArctanPiTest_b <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31);
--signR_uid190_rAtanPi_uid13_fpArctanPiTest(LOGICAL,189)@36
signR_uid190_rAtanPi_uid13_fpArctanPiTest_a <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_b;
signR_uid190_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= signR_uid190_rAtanPi_uid13_fpArctanPiTest_a xor signR_uid190_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a(DELAY,666)@37
ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid190_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest(LOGICAL,219)@38
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a <= ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b <= InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q;
signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q <= signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a and signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b;
--ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c(DELAY,670)@38
ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest(BITJOIN,128)@36
add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1(REG,433)@36
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest(BITJOIN,126)@36
add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b;
--reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0(REG,432)@36
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--prod_uid165_rAtanPi_uid13_fpArctanPiTest(MULT,164)@37
prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr <= UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_a) * UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_b);
prod_uid165_rAtanPi_uid13_fpArctanPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= (others => '0');
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q;
prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid165_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest(BITSELECT,165)@40
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q;
normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in(47 downto 47);
--roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest(CONSTANT,179)
roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q <= "010";
--fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest(BITSELECT,167)@40
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(46 downto 0);
fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in(46 downto 23);
--fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest(BITSELECT,168)@40
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(45 downto 0);
fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in(45 downto 22);
--fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest(MUX,169)@40
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s, en, fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b, fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b;
WHEN "1" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest(BITSELECT,177)@40
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in <= fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q(1 downto 0);
FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in(1 downto 0);
--Prod22_uid172_rAtanPi_uid13_fpArctanPiTest(BITSELECT,171)@40
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(22 downto 0);
Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in(22 downto 22);
--extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest(MUX,172)@40
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b;
extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest: PROCESS (extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s, en, GND_q, Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b)
BEGIN
CASE extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "0" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b;
WHEN OTHERS => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest(BITSELECT,170)@40
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(21 downto 0);
stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b <= stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in(21 downto 0);
--stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest(BITJOIN,173)@40
stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q <= extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q & stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b;
--stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest(LOGICAL,175)@40
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a <= stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q <= "1" when stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a = stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b else "0";
--sticky_uid177_rAtanPi_uid13_fpArctanPiTest(LOGICAL,176)@40
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a <= stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q;
sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q <= not sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a;
--lrs_uid179_rAtanPi_uid13_fpArctanPiTest(BITJOIN,178)@40
lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b & sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q;
--roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest(LOGICAL,180)@40
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a <= lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b <= roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q;
roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q <= "1" when roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a = roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b else "0";
--roundBit_uid182_rAtanPi_uid13_fpArctanPiTest(LOGICAL,181)@40
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a <= roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q;
roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q <= not roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a;
--roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest(BITJOIN,184)@40
roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q <= GND_q & normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b & cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q & roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q;
--reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1(REG,436)@40
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid163_rAtanPi_uid13_fpArctanPiTest(CONSTANT,162)
biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q <= "0001111111";
--ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b(DELAY,586)@36
ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expY_uid123_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expSum_uid162_rAtanPi_uid13_fpArctanPiTest(ADD,161)@37
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q);
expSum_uid162_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a) + UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q <= expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o(8 downto 0);
--ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a(DELAY,587)@38
ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest(SUB,163)@39
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q(9)) & biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q);
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o(10 downto 0);
--expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest(BITJOIN,182)@40
expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q & fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q;
--reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0(REG,435)@40
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest(ADD,185)@41
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q(34)) & reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q);
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a) + SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b));
expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o(35 downto 0);
--expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest(BITSELECT,187)@41
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q;
expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in(35 downto 24);
--expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest(BITSELECT,188)@41
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b(7 downto 0);
expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in(7 downto 0);
--ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d(DELAY,664)@41
ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c(DELAY,659)@37
ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1(REG,437)@41
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid193_rAtanPi_uid13_fpArctanPiTest(COMPARE,192)@42
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & '0';
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) & expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin(0);
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b));
expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o(14);
--InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest(LOGICAL,157)@37
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest(LOGICAL,158)@37
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest(LOGICAL,159)@37
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid161_rAtanPi_uid13_fpArctanPiTest(LOGICAL,160)@37
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b(DELAY,629)@37
ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest(LOGICAL,141)@37
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a;
--InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest(LOGICAL,142)@37
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a;
--InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest(LOGICAL,143)@37
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a;
--exc_R_uid145_rAtanPi_uid13_fpArctanPiTest(LOGICAL,144)@37
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q;
exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c;
--ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a(DELAY,628)@37
ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest(LOGICAL,201)@42
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c <= expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n;
ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c;
--excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest(LOGICAL,200)@37
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q <= excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a and excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c(DELAY,646)@37
ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest(LOGICAL,199)@37
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q <= excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a and excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b(DELAY,645)@37
ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest(LOGICAL,198)@37
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q;
excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q <= excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a and excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a(DELAY,644)@37
ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid203_rAtanPi_uid13_fpArctanPiTest(LOGICAL,202)@42
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q;
excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q <= excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d;
--expUdf_uid191_rAtanPi_uid13_fpArctanPiTest(COMPARE,190)@42
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q;
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin(0);
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b));
expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o(14);
--excZC3_uid197_rAtanPi_uid13_fpArctanPiTest(LOGICAL,196)@42
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c <= expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n;
excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c;
--excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest(LOGICAL,195)@37
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q;
excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c(DELAY,633)@37
ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest(LOGICAL,194)@37
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b(DELAY,632)@37
ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest(LOGICAL,193)@37
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q;
excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b;
--ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a(DELAY,631)@37
ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid198_rAtanPi_uid13_fpArctanPiTest(LOGICAL,197)@42
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q;
excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q <= excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d;
--concExc_uid208_rAtanPi_uid13_fpArctanPiTest(BITJOIN,207)@42
concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q <= ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q & excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q & excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q;
--reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0(REG,439)@42
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid209_rAtanPi_uid13_fpArctanPiTest(LOOKUP,208)@43
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest: PROCESS (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) IS
WHEN "000" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "01";
WHEN "001" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "010" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "10";
WHEN "011" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "100" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "11";
WHEN "101" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "110" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN "111" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest(MUX,217)@43
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest: PROCESS (expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest(BITSELECT,186)@41
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q(23 downto 0);
fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b <= fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in(23 downto 1);
--ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d(DELAY,662)@41
ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest(MUX,212)@43
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q;
fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q)
BEGIN
CASE fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s IS
WHEN "00" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "01" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q;
WHEN "10" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q;
WHEN "11" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q;
WHEN OTHERS => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid221_rAtanPi_uid13_fpArctanPiTest(BITJOIN,220)@43
R_uid221_rAtanPi_uid13_fpArctanPiTest_q <= ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q & expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q & fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q;
--xOut(GPOUT,4)@43
q <= R_uid221_rAtanPi_uid13_fpArctanPiTest_q;
end normal;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/fp_tanlut2.vhd | 10 | 45103 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_TANLUT2.VHD ***
--*** ***
--*** Function: Tangent Look Up Table ***
--*** (Generated by MATLAB Utility) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_tanlut2 IS
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
tanfraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_tanlut2;
ARCHITECTURE rtl OF fp_tanlut2 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "00000000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
WHEN "00000001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(1024,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
WHEN "00000010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(2048,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
WHEN "00000011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(3072,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1,18);
WHEN "00000100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(4096,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1,18);
WHEN "00000101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(5120,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(3,18);
WHEN "00000110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(6144,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(5,18);
WHEN "00000111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(7168,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(7,18);
WHEN "00001000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(8192,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(11,18);
WHEN "00001001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(9216,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(15,18);
WHEN "00001010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(10240,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(21,18);
WHEN "00001011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(11264,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(28,18);
WHEN "00001100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(12288,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(36,18);
WHEN "00001101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(13312,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(46,18);
WHEN "00001110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(14336,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(57,18);
WHEN "00001111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(15360,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(70,18);
WHEN "00010000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(16384,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(85,18);
WHEN "00010001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(17408,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(102,18);
WHEN "00010010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(18432,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(122,18);
WHEN "00010011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(19456,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(143,18);
WHEN "00010100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(20480,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(167,18);
WHEN "00010101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(21504,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(193,18);
WHEN "00010110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(22528,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(222,18);
WHEN "00010111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(23552,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(253,18);
WHEN "00011000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(24576,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(288,18);
WHEN "00011001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(25600,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(326,18);
WHEN "00011010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(26624,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(366,18);
WHEN "00011011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(27648,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(410,18);
WHEN "00011100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(28672,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(457,18);
WHEN "00011101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(29696,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(508,18);
WHEN "00011110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(30720,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(563,18);
WHEN "00011111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(31744,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(621,18);
WHEN "00100000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(32768,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(683,18);
WHEN "00100001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(33792,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(749,18);
WHEN "00100010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(34816,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(819,18);
WHEN "00100011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(35840,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(893,18);
WHEN "00100100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(36864,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(972,18);
WHEN "00100101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(37888,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1055,18);
WHEN "00100110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(38912,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1143,18);
WHEN "00100111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(39936,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1236,18);
WHEN "00101000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(40960,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1333,18);
WHEN "00101001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(41984,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1436,18);
WHEN "00101010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(43008,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1544,18);
WHEN "00101011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(44032,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1656,18);
WHEN "00101100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(45056,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1775,18);
WHEN "00101101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(46080,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1898,18);
WHEN "00101110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(47104,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(2028,18);
WHEN "00101111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(48128,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(2163,18);
WHEN "00110000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(49152,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(2304,18);
WHEN "00110001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(50176,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(2451,18);
WHEN "00110010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(51200,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(2604,18);
WHEN "00110011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(52224,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(2764,18);
WHEN "00110100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(53248,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(2929,18);
WHEN "00110101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(54272,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(3102,18);
WHEN "00110110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(55296,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(3281,18);
WHEN "00110111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(56320,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(3466,18);
WHEN "00111000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(57344,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(3659,18);
WHEN "00111001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(58368,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(3858,18);
WHEN "00111010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(59392,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(4065,18);
WHEN "00111011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(60416,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(4279,18);
WHEN "00111100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(61440,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(4500,18);
WHEN "00111101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(62464,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(4729,18);
WHEN "00111110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(63488,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(4965,18);
WHEN "00111111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(64512,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(5209,18);
WHEN "01000000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(65536,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(5461,18);
WHEN "01000001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(66560,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(5721,18);
WHEN "01000010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(67584,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(5990,18);
WHEN "01000011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(68608,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(6266,18);
WHEN "01000100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(69632,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(6551,18);
WHEN "01000101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(70656,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(6844,18);
WHEN "01000110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(71680,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(7146,18);
WHEN "01000111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(72704,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(7456,18);
WHEN "01001000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(73728,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(7776,18);
WHEN "01001001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(74752,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(8105,18);
WHEN "01001010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(75776,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(8442,18);
WHEN "01001011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(76800,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(8789,18);
WHEN "01001100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(77824,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(9145,18);
WHEN "01001101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(78848,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(9511,18);
WHEN "01001110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(79872,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(9887,18);
WHEN "01001111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(80896,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(10272,18);
WHEN "01010000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(81920,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(10667,18);
WHEN "01010001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(82944,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(11072,18);
WHEN "01010010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(83968,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(11487,18);
WHEN "01010011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(84992,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(11912,18);
WHEN "01010100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(86016,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(12348,18);
WHEN "01010101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(87040,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(12794,18);
WHEN "01010110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(88064,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(13251,18);
WHEN "01010111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(89088,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(13719,18);
WHEN "01011000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(90112,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(14197,18);
WHEN "01011001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(91136,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(14687,18);
WHEN "01011010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(92160,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(15188,18);
WHEN "01011011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(93184,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(15699,18);
WHEN "01011100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(94208,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(16223,18);
WHEN "01011101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(95232,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(16757,18);
WHEN "01011110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(96256,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(17304,18);
WHEN "01011111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(97280,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(17862,18);
WHEN "01100000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(98304,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(18432,18);
WHEN "01100001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(99328,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(19014,18);
WHEN "01100010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(100352,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(19608,18);
WHEN "01100011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(101376,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(20215,18);
WHEN "01100100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(102400,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(20833,18);
WHEN "01100101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(103424,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(21465,18);
WHEN "01100110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(104448,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(22109,18);
WHEN "01100111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(105472,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(22765,18);
WHEN "01101000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(106496,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(23435,18);
WHEN "01101001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(107520,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(24117,18);
WHEN "01101010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(108544,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(24813,18);
WHEN "01101011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(109568,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(25522,18);
WHEN "01101100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(110592,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(26244,18);
WHEN "01101101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(111616,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(26980,18);
WHEN "01101110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(112640,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(27729,18);
WHEN "01101111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(113664,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(28492,18);
WHEN "01110000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(114688,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(29269,18);
WHEN "01110001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(115712,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(30060,18);
WHEN "01110010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(116736,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(30866,18);
WHEN "01110011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(117760,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(31685,18);
WHEN "01110100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(118784,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(32519,18);
WHEN "01110101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(119808,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(33367,18);
WHEN "01110110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(120832,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(34230,18);
WHEN "01110111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(121856,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(35108,18);
WHEN "01111000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(122880,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(36000,18);
WHEN "01111001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(123904,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(36908,18);
WHEN "01111010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(124928,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(37830,18);
WHEN "01111011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(125952,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(38768,18);
WHEN "01111100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(126976,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(39721,18);
WHEN "01111101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(128000,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(40690,18);
WHEN "01111110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(129024,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(41675,18);
WHEN "01111111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(130048,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(42675,18);
WHEN "10000000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(131072,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(43691,18);
WHEN "10000001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(132096,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(44723,18);
WHEN "10000010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(133120,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(45771,18);
WHEN "10000011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(134144,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(46835,18);
WHEN "10000100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(135168,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(47916,18);
WHEN "10000101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(136192,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(49013,18);
WHEN "10000110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(137216,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(50127,18);
WHEN "10000111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(138240,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(51258,18);
WHEN "10001000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(139264,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(52405,18);
WHEN "10001001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(140288,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(53570,18);
WHEN "10001010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(141312,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(54752,18);
WHEN "10001011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(142336,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(55950,18);
WHEN "10001100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(143360,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(57167,18);
WHEN "10001101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(144384,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(58401,18);
WHEN "10001110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(145408,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(59652,18);
WHEN "10001111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(146432,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(60921,18);
WHEN "10010000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(147456,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(62208,18);
WHEN "10010001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(148480,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(63513,18);
WHEN "10010010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(149504,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(64836,18);
WHEN "10010011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(150528,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(66178,18);
WHEN "10010100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(151552,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(67537,18);
WHEN "10010101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(152576,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(68916,18);
WHEN "10010110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(153600,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(70313,18);
WHEN "10010111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(154624,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(71728,18);
WHEN "10011000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(155648,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(73163,18);
WHEN "10011001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(156672,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(74616,18);
WHEN "10011010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(157696,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(76089,18);
WHEN "10011011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(158720,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(77581,18);
WHEN "10011100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(159744,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(79092,18);
WHEN "10011101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(160768,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(80623,18);
WHEN "10011110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(161792,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(82173,18);
WHEN "10011111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(162816,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(83744,18);
WHEN "10100000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(163840,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(85334,18);
WHEN "10100001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(164864,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(86944,18);
WHEN "10100010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(165888,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(88574,18);
WHEN "10100011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(166912,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(90224,18);
WHEN "10100100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(167936,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(91895,18);
WHEN "10100101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(168960,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(93586,18);
WHEN "10100110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(169984,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(95298,18);
WHEN "10100111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(171008,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(97031,18);
WHEN "10101000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(172032,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(98784,18);
WHEN "10101001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(173056,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(100559,18);
WHEN "10101010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(174080,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(102354,18);
WHEN "10101011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(175104,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(104171,18);
WHEN "10101100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(176128,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(106010,18);
WHEN "10101101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(177152,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(107869,18);
WHEN "10101110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(178176,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(109751,18);
WHEN "10101111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(179200,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(111654,18);
WHEN "10110000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(180224,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(113579,18);
WHEN "10110001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(181248,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(115526,18);
WHEN "10110010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(182272,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(117495,18);
WHEN "10110011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(183296,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(119487,18);
WHEN "10110100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(184320,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(121500,18);
WHEN "10110101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(185344,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(123537,18);
WHEN "10110110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(186368,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(125596,18);
WHEN "10110111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(187392,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(127677,18);
WHEN "10111000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(188416,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(129782,18);
WHEN "10111001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(189440,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(131909,18);
WHEN "10111010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(190464,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(134060,18);
WHEN "10111011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(191488,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(136234,18);
WHEN "10111100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(192512,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(138431,18);
WHEN "10111101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(193536,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(140652,18);
WHEN "10111110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(194560,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(142896,18);
WHEN "10111111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(195584,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(145164,18);
WHEN "11000000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(196608,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(147457,18);
WHEN "11000001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(197632,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(149773,18);
WHEN "11000010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(198656,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(152113,18);
WHEN "11000011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(199680,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(154477,18);
WHEN "11000100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(200704,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(156866,18);
WHEN "11000101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(201728,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(159279,18);
WHEN "11000110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(202752,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(161717,18);
WHEN "11000111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(203776,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(164180,18);
WHEN "11001000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(204800,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(166667,18);
WHEN "11001001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(205824,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(169180,18);
WHEN "11001010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(206848,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(171717,18);
WHEN "11001011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(207872,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(174280,18);
WHEN "11001100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(208896,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(176869,18);
WHEN "11001101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(209920,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(179482,18);
WHEN "11001110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(210944,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(182122,18);
WHEN "11001111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(211968,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(184787,18);
WHEN "11010000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(212992,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(187478,18);
WHEN "11010001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(214016,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(190195,18);
WHEN "11010010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(215040,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(192938,18);
WHEN "11010011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(216064,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(195708,18);
WHEN "11010100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(217088,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(198503,18);
WHEN "11010101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(218112,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(201326,18);
WHEN "11010110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(219136,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(204175,18);
WHEN "11010111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(220160,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(207050,18);
WHEN "11011000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(221184,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(209953,18);
WHEN "11011001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(222208,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(212882,18);
WHEN "11011010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(223232,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(215839,18);
WHEN "11011011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(224256,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(218823,18);
WHEN "11011100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(225280,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(221834,18);
WHEN "11011101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(226304,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(224873,18);
WHEN "11011110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(227328,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(227940,18);
WHEN "11011111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(228352,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(231034,18);
WHEN "11100000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(229376,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(234156,18);
WHEN "11100001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(230400,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(237306,18);
WHEN "11100010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(231424,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(240484,18);
WHEN "11100011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(232448,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(243690,18);
WHEN "11100100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(233472,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(246925,18);
WHEN "11100101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(234496,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(250188,18);
WHEN "11100110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(235520,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(253480,18);
WHEN "11100111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(236544,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(256801,18);
WHEN "11101000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(237568,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(260151,18);
WHEN "11101001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(238593,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(1385,18);
WHEN "11101010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(239617,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(4793,18);
WHEN "11101011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(240641,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(8230,18);
WHEN "11101100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(241665,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(11696,18);
WHEN "11101101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(242689,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(15192,18);
WHEN "11101110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(243713,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(18717,18);
WHEN "11101111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(244737,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(22272,18);
WHEN "11110000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(245761,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(25858,18);
WHEN "11110001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(246785,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(29473,18);
WHEN "11110010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(247809,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(33118,18);
WHEN "11110011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(248833,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(36793,18);
WHEN "11110100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(249857,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(40499,18);
WHEN "11110101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(250881,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(44235,18);
WHEN "11110110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(251905,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(48002,18);
WHEN "11110111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(252929,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(51800,18);
WHEN "11111000" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(253953,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(55628,18);
WHEN "11111001" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(254977,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(59488,18);
WHEN "11111010" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(256001,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(63379,18);
WHEN "11111011" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(257025,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(67301,18);
WHEN "11111100" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(258049,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(71254,18);
WHEN "11111101" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(259073,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(75239,18);
WHEN "11111110" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(260097,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(79255,18);
WHEN "11111111" =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(261121,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(83303,18);
WHEN others =>
tanfraction(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
tanfraction(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/dp_adds.vhd | 10 | 2500 |
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_ADDS.VHD ***
--*** ***
--*** Function: Synthesizable Fixed Point Adder ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_adds IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_adds;
ARCHITECTURE syn of dp_adds IS
component lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
cin : IN STD_LOGIC ;
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0)
);
end component;
BEGIN
addtwo: lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES",
lpm_pipeline => pipes,
lpm_type => "LPM_ADD_SUB",
lpm_width => width
)
PORT MAP (
dataa => aa,
datab => bb,
cin => carryin,
clken => enable,
aclr => reset,
clock => sysclk,
result => cc
);
END syn;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/dp_adds.vhd | 10 | 2500 |
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_ADDS.VHD ***
--*** ***
--*** Function: Synthesizable Fixed Point Adder ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_adds IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_adds;
ARCHITECTURE syn of dp_adds IS
component lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
cin : IN STD_LOGIC ;
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0)
);
end component;
BEGIN
addtwo: lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES",
lpm_pipeline => pipes,
lpm_type => "LPM_ADD_SUB",
lpm_width => width
)
PORT MAP (
dataa => aa,
datab => bb,
cin => carryin,
clken => enable,
aclr => reset,
clock => sysclk,
result => cc
);
END syn;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/hcc_cntuspipe64.vhd | 10 | 6914 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSPIPE64.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntuspipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
frac : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntuspipe64;
ARCHITECTURE rtl of hcc_cntuspipe64 IS
type positiontype IS ARRAY (11 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionff, positionmux : positiontype;
signal zerogroup, firstzeroff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
component hcc_usgnpos
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 11 LOOP
FOR j IN 1 TO 6 LOOP
positionff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
firstzeroff(1) <= zerogroup(1);
firstzeroff(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzeroff(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzeroff(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzeroff(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzeroff(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND zerogroup(6);
firstzeroff(7) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND zerogroup(7);
firstzeroff(8) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND zerogroup(8);
firstzeroff(9) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND zerogroup(9);
firstzeroff(10) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND zerogroup(10);
firstzeroff(11) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND NOT(zerogroup(10)) AND zerogroup(11);
FOR k IN 1 TO 11 LOOP
positionff(k)(6 DOWNTO 1) <= position(k)(6 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
zerogroup(1) <= frac(63) OR frac(62) OR frac(61) OR frac(60) OR frac(59) OR frac(58);
zerogroup(2) <= frac(57) OR frac(56) OR frac(55) OR frac(54) OR frac(53) OR frac(52);
zerogroup(3) <= frac(51) OR frac(50) OR frac(49) OR frac(48) OR frac(47) OR frac(46);
zerogroup(4) <= frac(45) OR frac(44) OR frac(43) OR frac(42) OR frac(41) OR frac(40);
zerogroup(5) <= frac(39) OR frac(38) OR frac(37) OR frac(36) OR frac(35) OR frac(34);
zerogroup(6) <= frac(33) OR frac(32) OR frac(31) OR frac(30) OR frac(29) OR frac(28);
zerogroup(7) <= frac(27) OR frac(26) OR frac(25) OR frac(24) OR frac(23) OR frac(22);
zerogroup(8) <= frac(21) OR frac(20) OR frac(19) OR frac(18) OR frac(17) OR frac(16);
zerogroup(9) <= frac(15) OR frac(14) OR frac(13) OR frac(12) OR frac(11) OR frac(10);
zerogroup(10) <= frac(9) OR frac(8) OR frac(7) OR frac(6) OR frac(5) OR frac(4);
zerogroup(11) <= frac(3) OR frac(2) OR frac(1);
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(63 DOWNTO 58),position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(57 DOWNTO 52),position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(51 DOWNTO 46),position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(45 DOWNTO 40),position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(39 DOWNTO 34),position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>frac(33 DOWNTO 28),position=>position(6)(6 DOWNTO 1));
psev: hcc_usgnpos
GENERIC MAP (start=>36)
PORT MAP (ingroup=>frac(27 DOWNTO 22),position=>position(7)(6 DOWNTO 1));
pegt: hcc_usgnpos
GENERIC MAP (start=>42)
PORT MAP (ingroup=>frac(21 DOWNTO 16),position=>position(8)(6 DOWNTO 1));
pnin: hcc_usgnpos
GENERIC MAP (start=>48)
PORT MAP (ingroup=>frac(15 DOWNTO 10),position=>position(9)(6 DOWNTO 1));
pten: hcc_usgnpos
GENERIC MAP (start=>54)
PORT MAP (ingroup=>frac(9 DOWNTO 4),position=>position(10)(6 DOWNTO 1));
pelv: hcc_usgnpos
GENERIC MAP (start=>60)
PORT MAP (ingroup=>lastfrac,position=>position(11)(6 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & "000";
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= positionff(1)(k) AND firstzeroff(1);
gmb: FOR j IN 2 TO 11 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (positionff(j)(k) AND firstzeroff(j));
END GENERATE;
END GENERATE;
count <= positionmux(11)(6 DOWNTO 1);
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/dspba_library_package.vhd | 22 | 1323 | -- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/dp_rsft64x64.vhd | 10 | 5109 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_RSFT64X64.VHD ***
--*** ***
--*** Function: Combinatorial Right Shift ***
--*** (max 64.0 to 1.52) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 29/07/09 - signed number problem fixed ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsft64x64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_rsft64x64;
ARCHITECTURE rtl of dp_rsft64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
BEGIN
levzip <= inbus;
-- unsigned input
gla: FOR k IN 1 TO 113 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
-- 29/07/65 always shift 116, else will fill with zeros
-- fixed here and other lines
levone(114) <= (levzip(114) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(115) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(115) <= (levzip(115) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(116) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(116) <= levzip(116);
glba: FOR k IN 1 TO 104 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 105 TO 108 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbc: FOR k IN 109 TO 112 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(116) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbd: FOR k IN 113 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(116) AND (shift(4) OR shift(3)));
END GENERATE;
glca: FOR k IN 1 TO 66 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
glcb: FOR k IN 67 TO 84 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(116) AND shift(6) AND shift(5));
END GENERATE;
glcc: FOR k IN 85 TO 100 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(116) AND shift(6) AND NOT(shift(5))) OR
(levtwo(116) AND shift(6) AND shift(5));
END GENERATE;
glcd: FOR k IN 101 TO 116 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(116) AND (shift(6) OR shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/dp_explutneg.vhd | 10 | 140760 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUTNEG.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explutneg IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END dp_explutneg;
ARCHITECTURE rtl OF dp_explutneg IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= conv_std_logic_vector(1023,11);
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(7910755,24);
manlo <= conv_std_logic_vector(103608120,28);
exponent <= conv_std_logic_vector(1021,11);
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(1387178,24);
manlo <= conv_std_logic_vector(62882252,28);
exponent <= conv_std_logic_vector(1020,11);
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(9952012,24);
manlo <= conv_std_logic_vector(214872239,28);
exponent <= conv_std_logic_vector(1018,11);
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(2889051,24);
manlo <= conv_std_logic_vector(136396020,28);
exponent <= conv_std_logic_vector(1017,11);
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(12162046,24);
manlo <= conv_std_logic_vector(873334,28);
exponent <= conv_std_logic_vector(1015,11);
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(4515103,24);
manlo <= conv_std_logic_vector(18076886,28);
exponent <= conv_std_logic_vector(1014,11);
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(14554809,24);
manlo <= conv_std_logic_vector(203729295,28);
exponent <= conv_std_logic_vector(1012,11);
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(6275600,24);
manlo <= conv_std_logic_vector(68167597,28);
exponent <= conv_std_logic_vector(1011,11);
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(184098,24);
manlo <= conv_std_logic_vector(86398042,28);
exponent <= conv_std_logic_vector(1010,11);
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(8181659,24);
manlo <= conv_std_logic_vector(90471578,28);
exponent <= conv_std_logic_vector(1008,11);
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(1586498,24);
manlo <= conv_std_logic_vector(59729764,28);
exponent <= conv_std_logic_vector(1007,11);
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(10245315,24);
manlo <= conv_std_logic_vector(188988555,28);
exponent <= conv_std_logic_vector(1005,11);
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(3104851,24);
manlo <= conv_std_logic_vector(194518424,28);
exponent <= conv_std_logic_vector(1004,11);
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(12479599,24);
manlo <= conv_std_logic_vector(229643794,28);
exponent <= conv_std_logic_vector(1002,11);
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(4748746,24);
manlo <= conv_std_logic_vector(36170808,28);
exponent <= conv_std_logic_vector(1001,11);
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(14898619,24);
manlo <= conv_std_logic_vector(183403979,28);
exponent <= conv_std_logic_vector(999,11);
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(6528561,24);
manlo <= conv_std_logic_vector(123365533,28);
exponent <= conv_std_logic_vector(998,11);
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(370216,24);
manlo <= conv_std_logic_vector(208248737,28);
exponent <= conv_std_logic_vector(997,11);
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(8455535,24);
manlo <= conv_std_logic_vector(254564210,28);
exponent <= conv_std_logic_vector(995,11);
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(1788005,24);
manlo <= conv_std_logic_vector(99840615,28);
exponent <= conv_std_logic_vector(994,11);
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(10541837,24);
manlo <= conv_std_logic_vector(14529516,28);
exponent <= conv_std_logic_vector(992,11);
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(3323019,24);
manlo <= conv_std_logic_vector(252804514,28);
exponent <= conv_std_logic_vector(991,11);
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(12800638,24);
manlo <= conv_std_logic_vector(70515377,28);
exponent <= conv_std_logic_vector(989,11);
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(4984952,24);
manlo <= conv_std_logic_vector(266936970,28);
exponent <= conv_std_logic_vector(988,11);
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(15246202,24);
manlo <= conv_std_logic_vector(73384750,28);
exponent <= conv_std_logic_vector(986,11);
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(6784298,24);
manlo <= conv_std_logic_vector(117472834,28);
exponent <= conv_std_logic_vector(985,11);
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(558377,24);
manlo <= conv_std_logic_vector(141983386,28);
exponent <= conv_std_logic_vector(984,11);
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(8732417,24);
manlo <= conv_std_logic_vector(225268666,28);
exponent <= conv_std_logic_vector(982,11);
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(1991723,24);
manlo <= conv_std_logic_vector(183207072,28);
exponent <= conv_std_logic_vector(981,11);
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(10841612,24);
manlo <= conv_std_logic_vector(44859253,28);
exponent <= conv_std_logic_vector(979,11);
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(3543582,24);
manlo <= conv_std_logic_vector(38615994,28);
exponent <= conv_std_logic_vector(978,11);
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(13125199,24);
manlo <= conv_std_logic_vector(123823208,28);
exponent <= conv_std_logic_vector(976,11);
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(5223751,24);
manlo <= conv_std_logic_vector(209149352,28);
exponent <= conv_std_logic_vector(975,11);
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(15597598,24);
manlo <= conv_std_logic_vector(248916640,28);
exponent <= conv_std_logic_vector(973,11);
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(7042841,24);
manlo <= conv_std_logic_vector(173666528,28);
exponent <= conv_std_logic_vector(972,11);
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(748602,24);
manlo <= conv_std_logic_vector(266199140,28);
exponent <= conv_std_logic_vector(971,11);
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(9012337,24);
manlo <= conv_std_logic_vector(264921173,28);
exponent <= conv_std_logic_vector(969,11);
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(2197677,24);
manlo <= conv_std_logic_vector(112079619,28);
exponent <= conv_std_logic_vector(968,11);
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(11144676,24);
manlo <= conv_std_logic_vector(200497976,28);
exponent <= conv_std_logic_vector(966,11);
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(3766564,24);
manlo <= conv_std_logic_vector(161159716,28);
exponent <= conv_std_logic_vector(965,11);
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(13453322,24);
manlo <= conv_std_logic_vector(28788768,28);
exponent <= conv_std_logic_vector(963,11);
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(5465170,24);
manlo <= conv_std_logic_vector(249755484,28);
exponent <= conv_std_logic_vector(962,11);
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(15952851,24);
manlo <= conv_std_logic_vector(133443390,28);
exponent <= conv_std_logic_vector(960,11);
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(7304221,24);
manlo <= conv_std_logic_vector(236407020,28);
exponent <= conv_std_logic_vector(959,11);
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(940915,24);
manlo <= conv_std_logic_vector(220198205,28);
exponent <= conv_std_logic_vector(958,11);
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(9295329,24);
manlo <= conv_std_logic_vector(196124030,28);
exponent <= conv_std_logic_vector(956,11);
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(2405891,24);
manlo <= conv_std_logic_vector(28613594,28);
exponent <= conv_std_logic_vector(955,11);
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(11451066,24);
manlo <= conv_std_logic_vector(238698933,28);
exponent <= conv_std_logic_vector(953,11);
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(3991993,24);
manlo <= conv_std_logic_vector(233279365,28);
exponent <= conv_std_logic_vector(952,11);
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(13785045,24);
manlo <= conv_std_logic_vector(75368511,28);
exponent <= conv_std_logic_vector(950,11);
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(5709239,24);
manlo <= conv_std_logic_vector(54173026,28);
exponent <= conv_std_logic_vector(949,11);
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(16312002,24);
manlo <= conv_std_logic_vector(78993710,28);
exponent <= conv_std_logic_vector(947,11);
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(7568470,24);
manlo <= conv_std_logic_vector(72422582,28);
exponent <= conv_std_logic_vector(946,11);
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(1135338,24);
manlo <= conv_std_logic_vector(246889480,28);
exponent <= conv_std_logic_vector(945,11);
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(9581426,24);
manlo <= conv_std_logic_vector(208117876,28);
exponent <= conv_std_logic_vector(943,11);
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(2616389,24);
manlo <= conv_std_logic_vector(147217980,28);
exponent <= conv_std_logic_vector(942,11);
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(11760819,24);
manlo <= conv_std_logic_vector(23037889,28);
exponent <= conv_std_logic_vector(940,11);
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(4219896,24);
manlo <= conv_std_logic_vector(214481816,28);
exponent <= conv_std_logic_vector(939,11);
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(14120408,24);
manlo <= conv_std_logic_vector(131761485,28);
exponent <= conv_std_logic_vector(937,11);
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(5955985,24);
manlo <= conv_std_logic_vector(177821786,28);
exponent <= conv_std_logic_vector(936,11);
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(16675094,24);
manlo <= conv_std_logic_vector(25356748,28);
exponent <= conv_std_logic_vector(934,11);
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(7835618,24);
manlo <= conv_std_logic_vector(77011020,28);
exponent <= conv_std_logic_vector(933,11);
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1331895,24);
manlo <= conv_std_logic_vector(119779026,28);
exponent <= conv_std_logic_vector(932,11);
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(9870663,24);
manlo <= conv_std_logic_vector(52552908,28);
exponent <= conv_std_logic_vector(930,11);
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(2829197,24);
manlo <= conv_std_logic_vector(218477336,28);
exponent <= conv_std_logic_vector(929,11);
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(12073970,24);
manlo <= conv_std_logic_vector(61450731,28);
exponent <= conv_std_logic_vector(927,11);
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(4450300,24);
manlo <= conv_std_logic_vector(143360086,28);
exponent <= conv_std_logic_vector(926,11);
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(14459451,24);
manlo <= conv_std_logic_vector(182543396,28);
exponent <= conv_std_logic_vector(924,11);
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(6205439,24);
manlo <= conv_std_logic_vector(188004913,28);
exponent <= conv_std_logic_vector(923,11);
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(132477,24);
manlo <= conv_std_logic_vector(19160299,28);
exponent <= conv_std_logic_vector(922,11);
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(8105697,24);
manlo <= conv_std_logic_vector(201304075,28);
exponent <= conv_std_logic_vector(920,11);
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1530608,24);
manlo <= conv_std_logic_vector(217452229,28);
exponent <= conv_std_logic_vector(919,11);
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(10163073,24);
manlo <= conv_std_logic_vector(118320126,28);
exponent <= conv_std_logic_vector(917,11);
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(3044341,24);
manlo <= conv_std_logic_vector(66824260,28);
exponent <= conv_std_logic_vector(916,11);
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(12390557,24);
manlo <= conv_std_logic_vector(165235674,28);
exponent <= conv_std_logic_vector(914,11);
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(4683232,24);
manlo <= conv_std_logic_vector(138461149,28);
exponent <= conv_std_logic_vector(913,11);
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(14802215,24);
manlo <= conv_std_logic_vector(61508170,28);
exponent <= conv_std_logic_vector(911,11);
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(6457631,24);
manlo <= conv_std_logic_vector(7025744,28);
exponent <= conv_std_logic_vector(910,11);
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(318029,24);
manlo <= conv_std_logic_vector(21309721,28);
exponent <= conv_std_logic_vector(909,11);
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(8378740,24);
manlo <= conv_std_logic_vector(221720132,28);
exponent <= conv_std_logic_vector(907,11);
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1731502,24);
manlo <= conv_std_logic_vector(182144977,28);
exponent <= conv_std_logic_vector(906,11);
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(10458692,24);
manlo <= conv_std_logic_vector(90475423,28);
exponent <= conv_std_logic_vector(904,11);
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(3261845,24);
manlo <= conv_std_logic_vector(128220642,28);
exponent <= conv_std_logic_vector(903,11);
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(12710618,24);
manlo <= conv_std_logic_vector(255552070,28);
exponent <= conv_std_logic_vector(901,11);
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(4918720,24);
manlo <= conv_std_logic_vector(130727832,28);
exponent <= conv_std_logic_vector(900,11);
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(15148739,24);
manlo <= conv_std_logic_vector(258265342,28);
exponent <= conv_std_logic_vector(898,11);
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(6712589,24);
manlo <= conv_std_logic_vector(181573149,28);
exponent <= conv_std_logic_vector(897,11);
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(505617,24);
manlo <= conv_std_logic_vector(45883390,28);
exponent <= conv_std_logic_vector(896,11);
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(8654780,24);
manlo <= conv_std_logic_vector(9428106,28);
exponent <= conv_std_logic_vector(894,11);
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1934600,24);
manlo <= conv_std_logic_vector(262677610,28);
exponent <= conv_std_logic_vector(893,11);
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(10757555,24);
manlo <= conv_std_logic_vector(25094861,28);
exponent <= conv_std_logic_vector(891,11);
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(3481736,24);
manlo <= conv_std_logic_vector(108799619,28);
exponent <= conv_std_logic_vector(890,11);
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(13034192,24);
manlo <= conv_std_logic_vector(96190464,28);
exponent <= conv_std_logic_vector(888,11);
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(5156792,24);
manlo <= conv_std_logic_vector(132821234,28);
exponent <= conv_std_logic_vector(887,11);
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(15499067,24);
manlo <= conv_std_logic_vector(40497064,28);
exponent <= conv_std_logic_vector(885,11);
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(6970346,24);
manlo <= conv_std_logic_vector(4633646,28);
exponent <= conv_std_logic_vector(884,11);
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(695263,24);
manlo <= conv_std_logic_vector(184734272,28);
exponent <= conv_std_logic_vector(883,11);
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(8933848,24);
manlo <= conv_std_logic_vector(68258056,28);
exponent <= conv_std_logic_vector(881,11);
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(2139927,24);
manlo <= conv_std_logic_vector(241478077,28);
exponent <= conv_std_logic_vector(880,11);
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(11059697,24);
manlo <= conv_std_logic_vector(81964893,28);
exponent <= conv_std_logic_vector(878,11);
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(3704040,24);
manlo <= conv_std_logic_vector(59435624,28);
exponent <= conv_std_logic_vector(877,11);
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(13361316,24);
manlo <= conv_std_logic_vector(100097713,28);
exponent <= conv_std_logic_vector(875,11);
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(5397476,24);
manlo <= conv_std_logic_vector(240017437,28);
exponent <= conv_std_logic_vector(874,11);
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(15853238,24);
manlo <= conv_std_logic_vector(139632179,28);
exponent <= conv_std_logic_vector(872,11);
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(7230930,24);
manlo <= conv_std_logic_vector(200816807,28);
exponent <= conv_std_logic_vector(871,11);
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(886991,24);
manlo <= conv_std_logic_vector(58654941,28);
exponent <= conv_std_logic_vector(870,11);
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(9215978,24);
manlo <= conv_std_logic_vector(193575030,28);
exponent <= conv_std_logic_vector(868,11);
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(2347507,24);
manlo <= conv_std_logic_vector(240661664,28);
exponent <= conv_std_logic_vector(867,11);
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(11365154,24);
manlo <= conv_std_logic_vector(257284930,28);
exponent <= conv_std_logic_vector(865,11);
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(3928783,24);
manlo <= conv_std_logic_vector(108146246,28);
exponent <= conv_std_logic_vector(864,11);
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(13692029,24);
manlo <= conv_std_logic_vector(256867284,28);
exponent <= conv_std_logic_vector(862,11);
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(5640802,24);
manlo <= conv_std_logic_vector(94243132,28);
exponent <= conv_std_logic_vector(861,11);
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(16211296,24);
manlo <= conv_std_logic_vector(67825654,28);
exponent <= conv_std_logic_vector(859,11);
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(7494374,24);
manlo <= conv_std_logic_vector(242982196,28);
exponent <= conv_std_logic_vector(858,11);
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1080822,24);
manlo <= conv_std_logic_vector(160277009,28);
exponent <= conv_std_logic_vector(857,11);
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(9501205,24);
manlo <= conv_std_logic_vector(10212621,28);
exponent <= conv_std_logic_vector(855,11);
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2557365,24);
manlo <= conv_std_logic_vector(185941944,28);
exponent <= conv_std_logic_vector(854,11);
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(11673964,24);
manlo <= conv_std_logic_vector(116382402,28);
exponent <= conv_std_logic_vector(852,11);
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(4155992,24);
manlo <= conv_std_logic_vector(192503267,28);
exponent <= conv_std_logic_vector(851,11);
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(14026372,24);
manlo <= conv_std_logic_vector(133984890,28);
exponent <= conv_std_logic_vector(849,11);
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(5886797,24);
manlo <= conv_std_logic_vector(227169396,28);
exponent <= conv_std_logic_vector(848,11);
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(16573282,24);
manlo <= conv_std_logic_vector(266790864,28);
exponent <= conv_std_logic_vector(846,11);
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(7760709,24);
manlo <= conv_std_logic_vector(232279832,28);
exponent <= conv_std_logic_vector(845,11);
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(1276780,24);
manlo <= conv_std_logic_vector(244188460,28);
exponent <= conv_std_logic_vector(844,11);
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(9789561,24);
manlo <= conv_std_logic_vector(47289108,28);
exponent <= conv_std_logic_vector(842,11);
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2769526,24);
manlo <= conv_std_logic_vector(75856665,28);
exponent <= conv_std_logic_vector(841,11);
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(11986162,24);
manlo <= conv_std_logic_vector(137053172,28);
exponent <= conv_std_logic_vector(839,11);
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(4385695,24);
manlo <= conv_std_logic_vector(60488459,28);
exponent <= conv_std_logic_vector(838,11);
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(14364383,24);
manlo <= conv_std_logic_vector(220265084,28);
exponent <= conv_std_logic_vector(836,11);
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(6135492,24);
manlo <= conv_std_logic_vector(182090040,28);
exponent <= conv_std_logic_vector(835,11);
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(81012,24);
manlo <= conv_std_logic_vector(249275143,28);
exponent <= conv_std_logic_vector(834,11);
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(8029967,24);
manlo <= conv_std_logic_vector(93846972,28);
exponent <= conv_std_logic_vector(832,11);
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(1474889,24);
manlo <= conv_std_logic_vector(132978099,28);
exponent <= conv_std_logic_vector(831,11);
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(10081081,24);
manlo <= conv_std_logic_vector(128680817,28);
exponent <= conv_std_logic_vector(829,11);
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2984014,24);
manlo <= conv_std_logic_vector(251002315,28);
exponent <= conv_std_logic_vector(828,11);
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(12301786,24);
manlo <= conv_std_logic_vector(100124707,28);
exponent <= conv_std_logic_vector(826,11);
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(4617918,24);
manlo <= conv_std_logic_vector(76665129,28);
exponent <= conv_std_logic_vector(825,11);
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(14706104,24);
manlo <= conv_std_logic_vector(48076192,28);
exponent <= conv_std_logic_vector(823,11);
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(6386916,24);
manlo <= conv_std_logic_vector(125471070,28);
exponent <= conv_std_logic_vector(822,11);
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(266000,24);
manlo <= conv_std_logic_vector(57624675,28);
exponent <= conv_std_logic_vector(821,11);
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(8302179,24);
manlo <= conv_std_logic_vector(114693198,28);
exponent <= conv_std_logic_vector(819,11);
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(1675171,24);
manlo <= conv_std_logic_vector(254852645,28);
exponent <= conv_std_logic_vector(818,11);
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(10375800,24);
manlo <= conv_std_logic_vector(179426511,28);
exponent <= conv_std_logic_vector(816,11);
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(3200857,24);
manlo <= conv_std_logic_vector(52664716,28);
exponent <= conv_std_logic_vector(815,11);
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(12620873,24);
manlo <= conv_std_logic_vector(164386702,28);
exponent <= conv_std_logic_vector(813,11);
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(4852689,24);
manlo <= conv_std_logic_vector(149310968,28);
exponent <= conv_std_logic_vector(812,11);
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(15051574,24);
manlo <= conv_std_logic_vector(73675604,28);
exponent <= conv_std_logic_vector(810,11);
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(6641099,24);
manlo <= conv_std_logic_vector(42591307,28);
exponent <= conv_std_logic_vector(809,11);
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(453017,24);
manlo <= conv_std_logic_vector(104016801,28);
exponent <= conv_std_logic_vector(808,11);
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(8577378,24);
manlo <= conv_std_logic_vector(139419332,28);
exponent <= conv_std_logic_vector(806,11);
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(1877652,24);
manlo <= conv_std_logic_vector(33778363,28);
exponent <= conv_std_logic_vector(805,11);
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(10673753,24);
manlo <= conv_std_logic_vector(226837452,28);
exponent <= conv_std_logic_vector(803,11);
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(3420078,24);
manlo <= conv_std_logic_vector(239554874,28);
exponent <= conv_std_logic_vector(802,11);
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(12943462,24);
manlo <= conv_std_logic_vector(62486566,28);
exponent <= conv_std_logic_vector(800,11);
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(5090036,24);
manlo <= conv_std_logic_vector(268173235,28);
exponent <= conv_std_logic_vector(799,11);
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(15400835,24);
manlo <= conv_std_logic_vector(67898261,28);
exponent <= conv_std_logic_vector(797,11);
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(6898071,24);
manlo <= conv_std_logic_vector(6935226,28);
exponent <= conv_std_logic_vector(796,11);
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(642086,24);
manlo <= conv_std_logic_vector(193616024,28);
exponent <= conv_std_logic_vector(795,11);
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(8855597,24);
manlo <= conv_std_logic_vector(108124901,28);
exponent <= conv_std_logic_vector(793,11);
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2082354,24);
manlo <= conv_std_logic_vector(37727361,28);
exponent <= conv_std_logic_vector(792,11);
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(10974976,24);
manlo <= conv_std_logic_vector(133184200,28);
exponent <= conv_std_logic_vector(790,11);
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(3641706,24);
manlo <= conv_std_logic_vector(35844662,28);
exponent <= conv_std_logic_vector(789,11);
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(13269590,24);
manlo <= conv_std_logic_vector(175886280,28);
exponent <= conv_std_logic_vector(787,11);
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(5329988,24);
manlo <= conv_std_logic_vector(236927280,28);
exponent <= conv_std_logic_vector(786,11);
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(15753928,24);
manlo <= conv_std_logic_vector(191213976,28);
exponent <= conv_std_logic_vector(784,11);
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(7157862,24);
manlo <= conv_std_logic_vector(181160855,28);
exponent <= conv_std_logic_vector(783,11);
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(833230,24);
manlo <= conv_std_logic_vector(197197075,28);
exponent <= conv_std_logic_vector(782,11);
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(9136869,24);
manlo <= conv_std_logic_vector(57456047,28);
exponent <= conv_std_logic_vector(780,11);
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(2289302,24);
manlo <= conv_std_logic_vector(100400411,28);
exponent <= conv_std_logic_vector(779,11);
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(11279504,24);
manlo <= conv_std_logic_vector(133702078,28);
exponent <= conv_std_logic_vector(777,11);
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3865765,24);
manlo <= conv_std_logic_vector(84791606,28);
exponent <= conv_std_logic_vector(776,11);
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(13599297,24);
manlo <= conv_std_logic_vector(193913492,28);
exponent <= conv_std_logic_vector(774,11);
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(5572573,24);
manlo <= conv_std_logic_vector(210951234,28);
exponent <= conv_std_logic_vector(773,11);
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(16110896,24);
manlo <= conv_std_logic_vector(189751005,28);
exponent <= conv_std_logic_vector(771,11);
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(7420505,24);
manlo <= conv_std_logic_vector(12771910,28);
exponent <= conv_std_logic_vector(770,11);
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(1026472,24);
manlo <= conv_std_logic_vector(51864863,28);
exponent <= conv_std_logic_vector(769,11);
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(9421227,24);
manlo <= conv_std_logic_vector(121664951,28);
exponent <= conv_std_logic_vector(767,11);
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(2498521,24);
manlo <= conv_std_logic_vector(127312793,28);
exponent <= conv_std_logic_vector(766,11);
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(11587374,24);
manlo <= conv_std_logic_vector(32431827,28);
exponent <= conv_std_logic_vector(764,11);
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(4092283,24);
manlo <= conv_std_logic_vector(33663701,28);
exponent <= conv_std_logic_vector(763,11);
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(13932622,24);
manlo <= conv_std_logic_vector(188745186,28);
exponent <= conv_std_logic_vector(761,11);
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(5817820,24);
manlo <= conv_std_logic_vector(161368804,28);
exponent <= conv_std_logic_vector(760,11);
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(16471781,24);
manlo <= conv_std_logic_vector(201946939,28);
exponent <= conv_std_logic_vector(758,11);
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(7686029,24);
manlo <= conv_std_logic_vector(114155240,28);
exponent <= conv_std_logic_vector(757,11);
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(1221834,24);
manlo <= conv_std_logic_vector(30217784,28);
exponent <= conv_std_logic_vector(756,11);
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(9708705,24);
manlo <= conv_std_logic_vector(265245416,28);
exponent <= conv_std_logic_vector(754,11);
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(2710036,24);
manlo <= conv_std_logic_vector(96582323,28);
exponent <= conv_std_logic_vector(753,11);
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(11898622,24);
manlo <= conv_std_logic_vector(8685564,28);
exponent <= conv_std_logic_vector(751,11);
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(4321286,24);
manlo <= conv_std_logic_vector(145205332,28);
exponent <= conv_std_logic_vector(750,11);
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(14269605,24);
manlo <= conv_std_logic_vector(79792252,28);
exponent <= conv_std_logic_vector(748,11);
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(6065758,24);
manlo <= conv_std_logic_vector(144408455,28);
exponent <= conv_std_logic_vector(747,11);
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(29705,24);
manlo <= conv_std_logic_vector(111518540,28);
exponent <= conv_std_logic_vector(746,11);
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(7954467,24);
manlo <= conv_std_logic_vector(116097284,28);
exponent <= conv_std_logic_vector(744,11);
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(1419339,24);
manlo <= conv_std_logic_vector(204212637,28);
exponent <= conv_std_logic_vector(743,11);
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(9999339,24);
manlo <= conv_std_logic_vector(15580207,28);
exponent <= conv_std_logic_vector(741,11);
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(2923872,24);
manlo <= conv_std_logic_vector(59726033,28);
exponent <= conv_std_logic_vector(740,11);
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(12213285,24);
manlo <= conv_std_logic_vector(81348195,28);
exponent <= conv_std_logic_vector(738,11);
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(4552802,24);
manlo <= conv_std_logic_vector(224758002,28);
exponent <= conv_std_logic_vector(737,11);
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(14610285,24);
manlo <= conv_std_logic_vector(171839647,28);
exponent <= conv_std_logic_vector(735,11);
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(6316417,24);
manlo <= conv_std_logic_vector(33901818,28);
exponent <= conv_std_logic_vector(734,11);
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(214129,24);
manlo <= conv_std_logic_vector(187432044,28);
exponent <= conv_std_logic_vector(733,11);
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(8225851,24);
manlo <= conv_std_logic_vector(10972428,28);
exponent <= conv_std_logic_vector(731,11);
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(1619012,24);
manlo <= conv_std_logic_vector(177473085,28);
exponent <= conv_std_logic_vector(730,11);
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(10293161,24);
manlo <= conv_std_logic_vector(74648462,28);
exponent <= conv_std_logic_vector(728,11);
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3140054,24);
manlo <= conv_std_logic_vector(142465582,28);
exponent <= conv_std_logic_vector(727,11);
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(12531401,24);
manlo <= conv_std_logic_vector(110062606,28);
exponent <= conv_std_logic_vector(725,11);
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(4786859,24);
manlo <= conv_std_logic_vector(158003247,28);
exponent <= conv_std_logic_vector(724,11);
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(14954704,24);
manlo <= conv_std_logic_vector(82587752,28);
exponent <= conv_std_logic_vector(722,11);
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(6569826,24);
manlo <= conv_std_logic_vector(59098716,28);
exponent <= conv_std_logic_vector(721,11);
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(400577,24);
manlo <= conv_std_logic_vector(185198176,28);
exponent <= conv_std_logic_vector(720,11);
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(8500212,24);
manlo <= conv_std_logic_vector(153765179,28);
exponent <= conv_std_logic_vector(718,11);
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(1820876,24);
manlo <= conv_std_logic_vector(159783545,28);
exponent <= conv_std_logic_vector(717,11);
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(10590207,24);
manlo <= conv_std_logic_vector(172648734,28);
exponent <= conv_std_logic_vector(715,11);
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3358609,24);
manlo <= conv_std_logic_vector(8670608,28);
exponent <= conv_std_logic_vector(714,11);
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(12853008,24);
manlo <= conv_std_logic_vector(64863304,28);
exponent <= conv_std_logic_vector(712,11);
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(5023484,24);
manlo <= conv_std_logic_vector(180279682,28);
exponent <= conv_std_logic_vector(711,11);
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(15302902,24);
manlo <= conv_std_logic_vector(86126918,28);
exponent <= conv_std_logic_vector(709,11);
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(6826016,24);
manlo <= conv_std_logic_vector(315265,28);
exponent <= conv_std_logic_vector(708,11);
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(589071,24);
manlo <= conv_std_logic_vector(160219440,28);
exponent <= conv_std_logic_vector(707,11);
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(8777584,24);
manlo <= conv_std_logic_vector(189361726,28);
exponent <= conv_std_logic_vector(705,11);
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(2024955,24);
manlo <= conv_std_logic_vector(162543151,28);
exponent <= conv_std_logic_vector(704,11);
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(10890513,24);
manlo <= conv_std_logic_vector(142859647,28);
exponent <= conv_std_logic_vector(702,11);
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(3579561,24);
manlo <= conv_std_logic_vector(203359193,28);
exponent <= conv_std_logic_vector(701,11);
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(13178144,24);
manlo <= conv_std_logic_vector(27387766,28);
exponent <= conv_std_logic_vector(699,11);
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(5262706,24);
manlo <= conv_std_logic_vector(72167880,28);
exponent <= conv_std_logic_vector(698,11);
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(15654921,24);
manlo <= conv_std_logic_vector(40507130,28);
exponent <= conv_std_logic_vector(696,11);
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(7085016,24);
manlo <= conv_std_logic_vector(263640644,28);
exponent <= conv_std_logic_vector(695,11);
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(779633,24);
manlo <= conv_std_logic_vector(233308885,28);
exponent <= conv_std_logic_vector(694,11);
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(9058000,24);
manlo <= conv_std_logic_vector(127336500,28);
exponent <= conv_std_logic_vector(692,11);
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(2231273,24);
manlo <= conv_std_logic_vector(267969878,28);
exponent <= conv_std_logic_vector(691,11);
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(11194114,24);
manlo <= conv_std_logic_vector(191206462,28);
exponent <= conv_std_logic_vector(689,11);
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(3802939,24);
manlo <= conv_std_logic_vector(6046440,28);
exponent <= conv_std_logic_vector(688,11);
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(13506847,24);
manlo <= conv_std_logic_vector(192101060,28);
exponent <= conv_std_logic_vector(686,11);
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(5504552,24);
manlo <= conv_std_logic_vector(234133234,28);
exponent <= conv_std_logic_vector(685,11);
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(16010802,24);
manlo <= conv_std_logic_vector(194370273,28);
exponent <= conv_std_logic_vector(683,11);
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(7346860,24);
manlo <= conv_std_logic_vector(2864438,28);
exponent <= conv_std_logic_vector(682,11);
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(972287,24);
manlo <= conv_std_logic_vector(54536955,28);
exponent <= conv_std_logic_vector(681,11);
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(9341493,24);
manlo <= conv_std_logic_vector(74572905,28);
exponent <= conv_std_logic_vector(679,11);
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(2439856,24);
manlo <= conv_std_logic_vector(93006730,28);
exponent <= conv_std_logic_vector(678,11);
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(11501047,24);
manlo <= conv_std_logic_vector(92098230,28);
exponent <= conv_std_logic_vector(676,11);
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4028767,24);
manlo <= conv_std_logic_vector(115940390,28);
exponent <= conv_std_logic_vector(675,11);
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(13839158,24);
manlo <= conv_std_logic_vector(62227559,28);
exponent <= conv_std_logic_vector(673,11);
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(5749053,24);
manlo <= conv_std_logic_vector(76824142,28);
exponent <= conv_std_logic_vector(672,11);
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(16370589,24);
manlo <= conv_std_logic_vector(114548734,28);
exponent <= conv_std_logic_vector(670,11);
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(7611576,24);
manlo <= conv_std_logic_vector(73252889,28);
exponent <= conv_std_logic_vector(669,11);
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(1167054,24);
manlo <= conv_std_logic_vector(146134399,28);
exponent <= conv_std_logic_vector(668,11);
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(9628096,24);
manlo <= conv_std_logic_vector(236331104,28);
exponent <= conv_std_logic_vector(666,11);
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(2650727,24);
manlo <= conv_std_logic_vector(132284651,28);
exponent <= conv_std_logic_vector(665,11);
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(11811347,24);
manlo <= conv_std_logic_vector(263325685,28);
exponent <= conv_std_logic_vector(663,11);
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4257073,24);
manlo <= conv_std_logic_vector(236873507,28);
exponent <= conv_std_logic_vector(662,11);
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(14175115,24);
manlo <= conv_std_logic_vector(61615323,28);
exponent <= conv_std_logic_vector(660,11);
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(5996236,24);
manlo <= conv_std_logic_vector(169476567,28);
exponent <= conv_std_logic_vector(659,11);
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(16734324,24);
manlo <= conv_std_logic_vector(29597837,28);
exponent <= conv_std_logic_vector(657,11);
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(7879197,24);
manlo <= conv_std_logic_vector(79755942,28);
exponent <= conv_std_logic_vector(656,11);
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(1363959,24);
manlo <= conv_std_logic_vector(24177677,28);
exponent <= conv_std_logic_vector(655,11);
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(9917845,24);
manlo <= conv_std_logic_vector(112021148,28);
exponent <= conv_std_logic_vector(653,11);
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(2863912,24);
manlo <= conv_std_logic_vector(148304045,28);
exponent <= conv_std_logic_vector(652,11);
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(12125053,24);
manlo <= conv_std_logic_vector(156617262,28);
exponent <= conv_std_logic_vector(650,11);
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4487885,24);
manlo <= conv_std_logic_vector(151904422,28);
exponent <= conv_std_logic_vector(649,11);
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(14514758,24);
manlo <= conv_std_logic_vector(193824214,28);
exponent <= conv_std_logic_vector(647,11);
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(6246132,24);
manlo <= conv_std_logic_vector(93361418,28);
exponent <= conv_std_logic_vector(646,11);
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(162417,24);
manlo <= conv_std_logic_vector(12929741,28);
exponent <= conv_std_logic_vector(645,11);
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(8149754,24);
manlo <= conv_std_logic_vector(257063442,28);
exponent <= conv_std_logic_vector(643,11);
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(1563024,24);
manlo <= conv_std_logic_vector(78378796,28);
exponent <= conv_std_logic_vector(642,11);
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(10210773,24);
manlo <= conv_std_logic_vector(106907060,28);
exponent <= conv_std_logic_vector(640,11);
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(3079436,24);
manlo <= conv_std_logic_vector(245979562,28);
exponent <= conv_std_logic_vector(639,11);
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(12442201,24);
manlo <= conv_std_logic_vector(137868870,28);
exponent <= conv_std_logic_vector(637,11);
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(4721229,24);
manlo <= conv_std_logic_vector(261058204,28);
exponent <= conv_std_logic_vector(636,11);
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(14858129,24);
manlo <= conv_std_logic_vector(43405174,28);
exponent <= conv_std_logic_vector(634,11);
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(6498770,24);
manlo <= conv_std_logic_vector(53338521,28);
exponent <= conv_std_logic_vector(633,11);
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(348297,24);
manlo <= conv_std_logic_vector(158641329,28);
exponent <= conv_std_logic_vector(632,11);
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(8423281,24);
manlo <= conv_std_logic_vector(128446906,28);
exponent <= conv_std_logic_vector(630,11);
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(1764273,24);
manlo <= conv_std_logic_vector(230657816,28);
exponent <= conv_std_logic_vector(629,11);
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(10506915,24);
manlo <= conv_std_logic_vector(191032874,28);
exponent <= conv_std_logic_vector(627,11);
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(3297326,24);
manlo <= conv_std_logic_vector(68145509,28);
exponent <= conv_std_logic_vector(626,11);
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(12762829,24);
manlo <= conv_std_logic_vector(146161159,28);
exponent <= conv_std_logic_vector(624,11);
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(4957134,24);
manlo <= conv_std_logic_vector(240027976,28);
exponent <= conv_std_logic_vector(623,11);
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(15205267,24);
manlo <= conv_std_logic_vector(119370809,28);
exponent <= conv_std_logic_vector(621,11);
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(6754180,24);
manlo <= conv_std_logic_vector(73501816,28);
exponent <= conv_std_logic_vector(620,11);
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(536217,24);
manlo <= conv_std_logic_vector(220758658,28);
exponent <= conv_std_logic_vector(619,11);
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(8699809,24);
manlo <= conv_std_logic_vector(117402516,28);
exponent <= conv_std_logic_vector(617,11);
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(1967731,24);
manlo <= conv_std_logic_vector(204336317,28);
exponent <= conv_std_logic_vector(616,11);
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(10806307,24);
manlo <= conv_std_logic_vector(168773516,28);
exponent <= conv_std_logic_vector(614,11);
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(3517606,24);
manlo <= conv_std_logic_vector(138553816,28);
exponent <= conv_std_logic_vector(613,11);
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(13086975,24);
manlo <= conv_std_logic_vector(231838082,28);
exponent <= conv_std_logic_vector(611,11);
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5195628,24);
manlo <= conv_std_logic_vector(114805284,28);
exponent <= conv_std_logic_vector(610,11);
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(15556214,24);
manlo <= conv_std_logic_vector(245890169,28);
exponent <= conv_std_logic_vector(608,11);
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(7012392,24);
manlo <= conv_std_logic_vector(266576824,28);
exponent <= conv_std_logic_vector(607,11);
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(726200,24);
manlo <= conv_std_logic_vector(33318175,28);
exponent <= conv_std_logic_vector(606,11);
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(8979371,24);
manlo <= conv_std_logic_vector(206515377,28);
exponent <= conv_std_logic_vector(604,11);
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(2173422,24);
manlo <= conv_std_logic_vector(61774637,28);
exponent <= conv_std_logic_vector(603,11);
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(11108984,24);
manlo <= conv_std_logic_vector(216833386,28);
exponent <= conv_std_logic_vector(601,11);
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(3740303,24);
manlo <= conv_std_logic_vector(252090990,28);
exponent <= conv_std_logic_vector(600,11);
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(13414679,24);
manlo <= conv_std_logic_vector(20856890,28);
exponent <= conv_std_logic_vector(598,11);
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5436738,24);
manlo <= conv_std_logic_vector(262578382,28);
exponent <= conv_std_logic_vector(597,11);
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(15911013,24);
manlo <= conv_std_logic_vector(100481506,28);
exponent <= conv_std_logic_vector(595,11);
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(7273439,24);
manlo <= conv_std_logic_vector(29586843,28);
exponent <= conv_std_logic_vector(594,11);
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(918267,24);
manlo <= conv_std_logic_vector(33154287,28);
exponent <= conv_std_logic_vector(593,11);
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(9262001,24);
manlo <= conv_std_logic_vector(206947959,28);
exponent <= conv_std_logic_vector(591,11);
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(2381369,24);
manlo <= conv_std_logic_vector(205146615,28);
exponent <= conv_std_logic_vector(590,11);
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(11414983,24);
manlo <= conv_std_logic_vector(80080029,28);
exponent <= conv_std_logic_vector(588,11);
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(3965445,24);
manlo <= conv_std_logic_vector(12487826,28);
exponent <= conv_std_logic_vector(587,11);
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(13745978,24);
manlo <= conv_std_logic_vector(58199715,28);
exponent <= conv_std_logic_vector(585,11);
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5680495,24);
manlo <= conv_std_logic_vector(70463110,28);
exponent <= conv_std_logic_vector(584,11);
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(16269705,24);
manlo <= conv_std_logic_vector(20654997,28);
exponent <= conv_std_logic_vector(582,11);
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(7537349,24);
manlo <= conv_std_logic_vector(192319832,28);
exponent <= conv_std_logic_vector(581,11);
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(1112441,24);
manlo <= conv_std_logic_vector(186880957,28);
exponent <= conv_std_logic_vector(580,11);
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(9547733,24);
manlo <= conv_std_logic_vector(27940083,28);
exponent <= conv_std_logic_vector(578,11);
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(2591599,24);
manlo <= conv_std_logic_vector(35045549,28);
exponent <= conv_std_logic_vector(577,11);
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(11724339,24);
manlo <= conv_std_logic_vector(146438512,28);
exponent <= conv_std_logic_vector(575,11);
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(4193056,24);
manlo <= conv_std_logic_vector(175344679,28);
exponent <= conv_std_logic_vector(574,11);
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(14080912,24);
manlo <= conv_std_logic_vector(198508677,28);
exponent <= conv_std_logic_vector(572,11);
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5926926,24);
manlo <= conv_std_logic_vector(83904648,28);
exponent <= conv_std_logic_vector(571,11);
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(16632332,24);
manlo <= conv_std_logic_vector(199957404,28);
exponent <= conv_std_logic_vector(569,11);
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(7804156,24);
manlo <= conv_std_logic_vector(65532420,28);
exponent <= conv_std_logic_vector(568,11);
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(1308746,24);
manlo <= conv_std_logic_vector(260058525,28);
exponent <= conv_std_logic_vector(567,11);
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(9836599,24);
manlo <= conv_std_logic_vector(214756046,28);
exponent <= conv_std_logic_vector(565,11);
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(2804135,24);
manlo <= conv_std_logic_vector(98759674,28);
exponent <= conv_std_logic_vector(564,11);
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(12037090,24);
manlo <= conv_std_logic_vector(105879341,28);
exponent <= conv_std_logic_vector(562,11);
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(4423165,24);
manlo <= conv_std_logic_vector(233069674,28);
exponent <= conv_std_logic_vector(561,11);
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(14419522,24);
manlo <= conv_std_logic_vector(144218340,28);
exponent <= conv_std_logic_vector(559,11);
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6176061,24);
manlo <= conv_std_logic_vector(128557517,28);
exponent <= conv_std_logic_vector(558,11);
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(110861,24);
manlo <= conv_std_logic_vector(210451229,28);
exponent <= conv_std_logic_vector(557,11);
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(8073890,24);
manlo <= conv_std_logic_vector(126309403,28);
exponent <= conv_std_logic_vector(555,11);
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(1507206,24);
manlo <= conv_std_logic_vector(86368556,28);
exponent <= conv_std_logic_vector(554,11);
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(10128636,24);
manlo <= conv_std_logic_vector(70724454,28);
exponent <= conv_std_logic_vector(552,11);
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(3019003,24);
manlo <= conv_std_logic_vector(212024500,28);
exponent <= conv_std_logic_vector(551,11);
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(12353273,24);
manlo <= conv_std_logic_vector(25338267,28);
exponent <= conv_std_logic_vector(549,11);
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(4655800,24);
manlo <= conv_std_logic_vector(26358145,28);
exponent <= conv_std_logic_vector(548,11);
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(14761847,24);
manlo <= conv_std_logic_vector(252137457,28);
exponent <= conv_std_logic_vector(546,11);
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6427930,24);
manlo <= conv_std_logic_vector(116530320,28);
exponent <= conv_std_logic_vector(545,11);
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(296176,24);
manlo <= conv_std_logic_vector(162393576,28);
exponent <= conv_std_logic_vector(544,11);
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(8346584,24);
manlo <= conv_std_logic_vector(140031506,28);
exponent <= conv_std_logic_vector(542,11);
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(1707843,24);
manlo <= conv_std_logic_vector(105232250,28);
exponent <= conv_std_logic_vector(541,11);
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(10423877,24);
manlo <= conv_std_logic_vector(74257288,28);
exponent <= conv_std_logic_vector(539,11);
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(3236229,24);
manlo <= conv_std_logic_vector(265138481,28);
exponent <= conv_std_logic_vector(538,11);
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(12672925,24);
manlo <= conv_std_logic_vector(81471742,28);
exponent <= conv_std_logic_vector(536,11);
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(4890987,24);
manlo <= conv_std_logic_vector(13504322,28);
exponent <= conv_std_logic_vector(535,11);
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(15107929,24);
manlo <= conv_std_logic_vector(192561070,28);
exponent <= conv_std_logic_vector(533,11);
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6682563,24);
manlo <= conv_std_logic_vector(47334412,28);
exponent <= conv_std_logic_vector(532,11);
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(483524,24);
manlo <= conv_std_logic_vector(243414774,28);
exponent <= conv_std_logic_vector(531,11);
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(8622270,24);
manlo <= conv_std_logic_vector(235144322,28);
exponent <= conv_std_logic_vector(529,11);
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(1910682,24);
manlo <= conv_std_logic_vector(20388866,28);
exponent <= conv_std_logic_vector(528,11);
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(10722358,24);
manlo <= conv_std_logic_vector(913747,28);
exponent <= conv_std_logic_vector(526,11);
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(3455839,24);
manlo <= conv_std_logic_vector(223781205,28);
exponent <= conv_std_logic_vector(525,11);
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(12996085,24);
manlo <= conv_std_logic_vector(24989984,28);
exponent <= conv_std_logic_vector(523,11);
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(5128754,24);
manlo <= conv_std_logic_vector(197545335,28);
exponent <= conv_std_logic_vector(522,11);
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(15457809,24);
manlo <= conv_std_logic_vector(24315860,28);
exponent <= conv_std_logic_vector(520,11);
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6939990,24);
manlo <= conv_std_logic_vector(8842978,28);
exponent <= conv_std_logic_vector(519,11);
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(672929,24);
manlo <= conv_std_logic_vector(830489,28);
exponent <= conv_std_logic_vector(518,11);
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(8900982,24);
manlo <= conv_std_logic_vector(98890321,28);
exponent <= conv_std_logic_vector(516,11);
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(2115746,24);
manlo <= conv_std_logic_vector(142837003,28);
exponent <= conv_std_logic_vector(515,11);
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(11024113,24);
manlo <= conv_std_logic_vector(266701758,28);
exponent <= conv_std_logic_vector(513,11);
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(3677859,24);
manlo <= conv_std_logic_vector(129840563,28);
exponent <= conv_std_logic_vector(512,11);
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(13322790,24);
manlo <= conv_std_logic_vector(255615990,28);
exponent <= conv_std_logic_vector(510,11);
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(5369131,24);
manlo <= conv_std_logic_vector(127156783,28);
exponent <= conv_std_logic_vector(509,11);
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(15811527,24);
manlo <= conv_std_logic_vector(196077973,28);
exponent <= conv_std_logic_vector(507,11);
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7200241,24);
manlo <= conv_std_logic_vector(178260644,28);
exponent <= conv_std_logic_vector(506,11);
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(864411,24);
manlo <= conv_std_logic_vector(121424610,28);
exponent <= conv_std_logic_vector(505,11);
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(9182752,24);
manlo <= conv_std_logic_vector(52100447,28);
exponent <= conv_std_logic_vector(503,11);
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(2323061,24);
manlo <= conv_std_logic_vector(49429697,28);
exponent <= conv_std_logic_vector(502,11);
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(11329181,24);
manlo <= conv_std_logic_vector(50166358,28);
exponent <= conv_std_logic_vector(500,11);
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(3902315,24);
manlo <= conv_std_logic_vector(102248985,28);
exponent <= conv_std_logic_vector(499,11);
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(13653081,24);
manlo <= conv_std_logic_vector(212703346,28);
exponent <= conv_std_logic_vector(497,11);
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(5612145,24);
manlo <= conv_std_logic_vector(239735388,28);
exponent <= conv_std_logic_vector(496,11);
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(16169127,24);
manlo <= conv_std_logic_vector(205528034,28);
exponent <= conv_std_logic_vector(494,11);
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7463349,24);
manlo <= conv_std_logic_vector(17797346,28);
exponent <= conv_std_logic_vector(493,11);
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(1057995,24);
manlo <= conv_std_logic_vector(16251369,28);
exponent <= conv_std_logic_vector(492,11);
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(9467613,24);
manlo <= conv_std_logic_vector(244949044,28);
exponent <= conv_std_logic_vector(490,11);
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(2532650,24);
manlo <= conv_std_logic_vector(194268012,28);
exponent <= conv_std_logic_vector(489,11);
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(11637595,24);
manlo <= conv_std_logic_vector(246328755,28);
exponent <= conv_std_logic_vector(487,11);
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(4129234,24);
manlo <= conv_std_logic_vector(69393408,28);
exponent <= conv_std_logic_vector(486,11);
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(13986996,24);
manlo <= conv_std_logic_vector(255528468,28);
exponent <= conv_std_logic_vector(484,11);
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(5857826,24);
manlo <= conv_std_logic_vector(251701587,28);
exponent <= conv_std_logic_vector(483,11);
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(16530651,24);
manlo <= conv_std_logic_vector(211310789,28);
exponent <= conv_std_logic_vector(481,11);
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7729343,24);
manlo <= conv_std_logic_vector(154707528,28);
exponent <= conv_std_logic_vector(480,11);
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(1253702,24);
manlo <= conv_std_logic_vector(237283577,28);
exponent <= conv_std_logic_vector(479,11);
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(9755601,24);
manlo <= conv_std_logic_vector(121155884,28);
exponent <= conv_std_logic_vector(477,11);
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(2744540,24);
manlo <= conv_std_logic_vector(30442277,28);
exponent <= conv_std_logic_vector(476,11);
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(11949394,24);
manlo <= conv_std_logic_vector(246622503,28);
exponent <= conv_std_logic_vector(474,11);
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(4358643,24);
manlo <= conv_std_logic_vector(38405425,28);
exponent <= conv_std_logic_vector(473,11);
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(14324576,24);
manlo <= conv_std_logic_vector(53935566,28);
exponent <= conv_std_logic_vector(471,11);
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(6106203,24);
manlo <= conv_std_logic_vector(233166714,28);
exponent <= conv_std_logic_vector(470,11);
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(59463,24);
manlo <= conv_std_logic_vector(114545214,28);
exponent <= conv_std_logic_vector(469,11);
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7998256,24);
manlo <= conv_std_logic_vector(234808364,28);
exponent <= conv_std_logic_vector(467,11);
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(1451558,24);
manlo <= conv_std_logic_vector(62230667,28);
exponent <= conv_std_logic_vector(466,11);
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(10046749,24);
manlo <= conv_std_logic_vector(29683609,28);
exponent <= conv_std_logic_vector(464,11);
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(2958754,24);
manlo <= conv_std_logic_vector(158313814,28);
exponent <= conv_std_logic_vector(463,11);
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(12264615,24);
manlo <= conv_std_logic_vector(87551554,28);
exponent <= conv_std_logic_vector(461,11);
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(4590569,24);
manlo <= conv_std_logic_vector(96025360,28);
exponent <= conv_std_logic_vector(460,11);
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(14665859,24);
manlo <= conv_std_logic_vector(200220878,28);
exponent <= conv_std_logic_vector(458,11);
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(6357306,24);
manlo <= conv_std_logic_vector(71997608,28);
exponent <= conv_std_logic_vector(457,11);
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(244214,24);
manlo <= conv_std_logic_vector(66463607,28);
exponent <= conv_std_logic_vector(456,11);
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(8270120,24);
manlo <= conv_std_logic_vector(265669912,28);
exponent <= conv_std_logic_vector(454,11);
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(1651584,24);
manlo <= conv_std_logic_vector(179638473,28);
exponent <= conv_std_logic_vector(453,11);
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(10341091,24);
manlo <= conv_std_logic_vector(152092530,28);
exponent <= conv_std_logic_vector(451,11);
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(3175319,24);
manlo <= conv_std_logic_vector(178838140,28);
exponent <= conv_std_logic_vector(450,11);
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(12583294,24);
manlo <= conv_std_logic_vector(183442082,28);
exponent <= conv_std_logic_vector(448,11);
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(4825040,24);
manlo <= conv_std_logic_vector(141040370,28);
exponent <= conv_std_logic_vector(447,11);
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(15010888,24);
manlo <= conv_std_logic_vector(62934477,28);
exponent <= conv_std_logic_vector(445,11);
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(6611164,24);
manlo <= conv_std_logic_vector(11633311,28);
exponent <= conv_std_logic_vector(444,11);
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(430992,24);
manlo <= conv_std_logic_vector(96770068,28);
exponent <= conv_std_logic_vector(443,11);
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8544968,24);
manlo <= conv_std_logic_vector(80768180,28);
exponent <= conv_std_logic_vector(441,11);
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(1853806,24);
manlo <= conv_std_logic_vector(5288079,28);
exponent <= conv_std_logic_vector(440,11);
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(10638663,24);
manlo <= conv_std_logic_vector(235213815,28);
exponent <= conv_std_logic_vector(438,11);
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(3394261,24);
manlo <= conv_std_logic_vector(36557939,28);
exponent <= conv_std_logic_vector(437,11);
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(12905470,24);
manlo <= conv_std_logic_vector(253900977,28);
exponent <= conv_std_logic_vector(435,11);
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(5062084,24);
manlo <= conv_std_logic_vector(153603034,28);
exponent <= conv_std_logic_vector(434,11);
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(15359702,24);
manlo <= conv_std_logic_vector(204098933,28);
exponent <= conv_std_logic_vector(432,11);
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(6867807,24);
manlo <= conv_std_logic_vector(115170312,28);
exponent <= conv_std_logic_vector(431,11);
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(619820,24);
manlo <= conv_std_logic_vector(2986045,28);
exponent <= conv_std_logic_vector(430,11);
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8822831,24);
manlo <= conv_std_logic_vector(145826716,28);
exponent <= conv_std_logic_vector(428,11);
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(2058246,24);
manlo <= conv_std_logic_vector(98876593,28);
exponent <= conv_std_logic_vector(427,11);
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(10939501,24);
manlo <= conv_std_logic_vector(129141213,28);
exponent <= conv_std_logic_vector(425,11);
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(3615605,24);
manlo <= conv_std_logic_vector(20427716,28);
exponent <= conv_std_logic_vector(424,11);
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(13231182,24);
manlo <= conv_std_logic_vector(130335695,28);
exponent <= conv_std_logic_vector(422,11);
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(5301729,24);
manlo <= conv_std_logic_vector(196124198,28);
exponent <= conv_std_logic_vector(421,11);
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(15712344,24);
manlo <= conv_std_logic_vector(233039482,28);
exponent <= conv_std_logic_vector(419,11);
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(7127266,24);
manlo <= conv_std_logic_vector(266329205,28);
exponent <= conv_std_logic_vector(418,11);
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(810719,24);
manlo <= conv_std_logic_vector(185030259,28);
exponent <= conv_std_logic_vector(417,11);
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(9103743,24);
manlo <= conv_std_logic_vector(217685905,28);
exponent <= conv_std_logic_vector(415,11);
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(2264930,24);
manlo <= conv_std_logic_vector(17303531,28);
exponent <= conv_std_logic_vector(414,11);
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(11243640,24);
manlo <= conv_std_logic_vector(56799625,28);
exponent <= conv_std_logic_vector(412,11);
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(3839377,24);
manlo <= conv_std_logic_vector(227776580,28);
exponent <= conv_std_logic_vector(411,11);
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(13560468,24);
manlo <= conv_std_logic_vector(25616516,28);
exponent <= conv_std_logic_vector(409,11);
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(5544004,24);
manlo <= conv_std_logic_vector(145740137,28);
exponent <= conv_std_logic_vector(408,11);
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(16068856,24);
manlo <= conv_std_logic_vector(149889545,28);
exponent <= conv_std_logic_vector(406,11);
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(7389573,24);
manlo <= conv_std_logic_vector(170431948,28);
exponent <= conv_std_logic_vector(405,11);
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(1003714,24);
manlo <= conv_std_logic_vector(35324999,28);
exponent <= conv_std_logic_vector(404,11);
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(9387738,24);
manlo <= conv_std_logic_vector(150667400,28);
exponent <= conv_std_logic_vector(402,11);
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(2473881,24);
manlo <= conv_std_logic_vector(194497484,28);
exponent <= conv_std_logic_vector(401,11);
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(11551116,24);
manlo <= conv_std_logic_vector(78219737,28);
exponent <= conv_std_logic_vector(399,11);
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(4065606,24);
manlo <= conv_std_logic_vector(28280174,28);
exponent <= conv_std_logic_vector(398,11);
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(13893366,24);
manlo <= conv_std_logic_vector(266881350,28);
exponent <= conv_std_logic_vector(396,11);
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(5788937,24);
manlo <= conv_std_logic_vector(232096008,28);
exponent <= conv_std_logic_vector(395,11);
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(16429280,24);
manlo <= conv_std_logic_vector(78498076,28);
exponent <= conv_std_logic_vector(393,11);
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(7654758,24);
manlo <= conv_std_logic_vector(160696217,28);
exponent <= conv_std_logic_vector(392,11);
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(1198826,24);
manlo <= conv_std_logic_vector(87006684,28);
exponent <= conv_std_logic_vector(391,11);
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(9674849,24);
manlo <= conv_std_logic_vector(166079254,28);
exponent <= conv_std_logic_vector(389,11);
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(2685126,24);
manlo <= conv_std_logic_vector(63154951,28);
exponent <= conv_std_logic_vector(388,11);
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(11861966,24);
manlo <= conv_std_logic_vector(91696135,28);
exponent <= conv_std_logic_vector(386,11);
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(4294316,24);
manlo <= conv_std_logic_vector(212296424,28);
exponent <= conv_std_logic_vector(385,11);
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(14229918,24);
manlo <= conv_std_logic_vector(223047784,28);
exponent <= conv_std_logic_vector(383,11);
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(6036558,24);
manlo <= conv_std_logic_vector(232962025,28);
exponent <= conv_std_logic_vector(382,11);
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(8221,24);
manlo <= conv_std_logic_vector(133893557,28);
exponent <= conv_std_logic_vector(381,11);
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(7922853,24);
manlo <= conv_std_logic_vector(125492404,28);
exponent <= conv_std_logic_vector(379,11);
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(1396079,24);
manlo <= conv_std_logic_vector(135612572,28);
exponent <= conv_std_logic_vector(378,11);
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9965111,24);
manlo <= conv_std_logic_vector(47990958,28);
exponent <= conv_std_logic_vector(376,11);
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(2898688,24);
manlo <= conv_std_logic_vector(203019642,28);
exponent <= conv_std_logic_vector(375,11);
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(12176227,24);
manlo <= conv_std_logic_vector(103393586,28);
exponent <= conv_std_logic_vector(373,11);
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(4525537,24);
manlo <= conv_std_logic_vector(38936964,28);
exponent <= conv_std_logic_vector(372,11);
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(14570163,24);
manlo <= conv_std_logic_vector(185128905,28);
exponent <= conv_std_logic_vector(370,11);
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(6286897,24);
manlo <= conv_std_logic_vector(12037044,28);
exponent <= conv_std_logic_vector(369,11);
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(192410,24);
manlo <= conv_std_logic_vector(9691196,28);
exponent <= conv_std_logic_vector(368,11);
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(8193890,24);
manlo <= conv_std_logic_vector(46224319,28);
exponent <= conv_std_logic_vector(366,11);
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(1595497,24);
manlo <= conv_std_logic_vector(45130080,28);
exponent <= conv_std_logic_vector(365,11);
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(10258557,24);
manlo <= conv_std_logic_vector(218068546,28);
exponent <= conv_std_logic_vector(363,11);
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(3114594,24);
manlo <= conv_std_logic_vector(194203222,28);
exponent <= conv_std_logic_vector(362,11);
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(12493936,24);
manlo <= conv_std_logic_vector(228530713,28);
exponent <= conv_std_logic_vector(360,11);
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(4759294,24);
manlo <= conv_std_logic_vector(189728046,28);
exponent <= conv_std_logic_vector(359,11);
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(14914142,24);
manlo <= conv_std_logic_vector(25337562,28);
exponent <= conv_std_logic_vector(357,11);
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(6539982,24);
manlo <= conv_std_logic_vector(56762382,28);
exponent <= conv_std_logic_vector(356,11);
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(378619,24);
manlo <= conv_std_logic_vector(186677702,28);
exponent <= conv_std_logic_vector(355,11);
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(8467900,24);
manlo <= conv_std_logic_vector(266785510,28);
exponent <= conv_std_logic_vector(353,11);
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(1797103,24);
manlo <= conv_std_logic_vector(17183357,28);
exponent <= conv_std_logic_vector(352,11);
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(10555224,24);
manlo <= conv_std_logic_vector(126067134,28);
exponent <= conv_std_logic_vector(350,11);
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(3332869,24);
manlo <= conv_std_logic_vector(228611260,28);
exponent <= conv_std_logic_vector(349,11);
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(12815132,24);
manlo <= conv_std_logic_vector(155705738,28);
exponent <= conv_std_logic_vector(347,11);
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(4995617,24);
manlo <= conv_std_logic_vector(85136440,28);
exponent <= conv_std_logic_vector(346,11);
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(15261895,24);
manlo <= conv_std_logic_vector(3688335,28);
exponent <= conv_std_logic_vector(344,11);
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(6795844,24);
manlo <= conv_std_logic_vector(137097782,28);
exponent <= conv_std_logic_vector(343,11);
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(566872,24);
manlo <= conv_std_logic_vector(175764875,28);
exponent <= conv_std_logic_vector(342,11);
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(8744918,24);
manlo <= conv_std_logic_vector(152414052,28);
exponent <= conv_std_logic_vector(340,11);
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(2000921,24);
manlo <= conv_std_logic_vector(54921723,28);
exponent <= conv_std_logic_vector(339,11);
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(10855146,24);
manlo <= conv_std_logic_vector(129996510,28);
exponent <= conv_std_logic_vector(337,11);
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(3553540,24);
manlo <= conv_std_logic_vector(37023540,28);
exponent <= conv_std_logic_vector(336,11);
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(13139852,24);
manlo <= conv_std_logic_vector(221848100,28);
exponent <= conv_std_logic_vector(334,11);
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(5234533,24);
manlo <= conv_std_logic_vector(32943194,28);
exponent <= conv_std_logic_vector(333,11);
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(15613463,24);
manlo <= conv_std_logic_vector(232436445,28);
exponent <= conv_std_logic_vector(331,11);
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(7054514,24);
manlo <= conv_std_logic_vector(111791498,28);
exponent <= conv_std_logic_vector(330,11);
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(757191,24);
manlo <= conv_std_logic_vector(90062360,28);
exponent <= conv_std_logic_vector(329,11);
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(9024975,24);
manlo <= conv_std_logic_vector(238219590,28);
exponent <= conv_std_logic_vector(327,11);
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(2206975,24);
manlo <= conv_std_logic_vector(232222812,28);
exponent <= conv_std_logic_vector(326,11);
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(11158359,24);
manlo <= conv_std_logic_vector(155073518,28);
exponent <= conv_std_logic_vector(324,11);
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(3776631,24);
manlo <= conv_std_logic_vector(232102510,28);
exponent <= conv_std_logic_vector(323,11);
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(13468136,24);
manlo <= conv_std_logic_vector(71264246,28);
exponent <= conv_std_logic_vector(321,11);
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(5476070,24);
manlo <= conv_std_logic_vector(155401688,28);
exponent <= conv_std_logic_vector(320,11);
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(15968890,24);
manlo <= conv_std_logic_vector(140531032,28);
exponent <= conv_std_logic_vector(318,11);
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(7316022,24);
manlo <= conv_std_logic_vector(197790036,28);
exponent <= conv_std_logic_vector(317,11);
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(949598,24);
manlo <= conv_std_logic_vector(108723575,28);
exponent <= conv_std_logic_vector(316,11);
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(9308106,24);
manlo <= conv_std_logic_vector(82754530,28);
exponent <= conv_std_logic_vector(314,11);
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(2415291,24);
manlo <= conv_std_logic_vector(157597766,28);
exponent <= conv_std_logic_vector(313,11);
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(11464899,24);
manlo <= conv_std_logic_vector(231735034,28);
exponent <= conv_std_logic_vector(311,11);
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(4002171,24);
manlo <= conv_std_logic_vector(161749904,28);
exponent <= conv_std_logic_vector(310,11);
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(13800021,24);
manlo <= conv_std_logic_vector(267486845,28);
exponent <= conv_std_logic_vector(308,11);
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(5720258,24);
manlo <= conv_std_logic_vector(121711942,28);
exponent <= conv_std_logic_vector(307,11);
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(16328217,24);
manlo <= conv_std_logic_vector(85566619,28);
exponent <= conv_std_logic_vector(305,11);
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(7580400,24);
manlo <= conv_std_logic_vector(165916765,28);
exponent <= conv_std_logic_vector(304,11);
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(1144116,24);
manlo <= conv_std_logic_vector(209234965,28);
exponent <= conv_std_logic_vector(303,11);
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(9594343,24);
manlo <= conv_std_logic_vector(148128653,28);
exponent <= conv_std_logic_vector(301,11);
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(2625893,24);
manlo <= conv_std_logic_vector(48717694,28);
exponent <= conv_std_logic_vector(300,11);
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(11774803,24);
manlo <= conv_std_logic_vector(228357100,28);
exponent <= conv_std_logic_vector(298,11);
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(4230186,24);
manlo <= conv_std_logic_vector(57439900,28);
exponent <= conv_std_logic_vector(297,11);
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(14135549,24);
manlo <= conv_std_logic_vector(147041206,28);
exponent <= conv_std_logic_vector(295,11);
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(5967125,24);
manlo <= conv_std_logic_vector(222682176,28);
exponent <= conv_std_logic_vector(294,11);
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(16691487,24);
manlo <= conv_std_logic_vector(12959237,28);
exponent <= conv_std_logic_vector(292,11);
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(7847679,24);
manlo <= conv_std_logic_vector(147174066,28);
exponent <= conv_std_logic_vector(291,11);
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(1340769,24);
manlo <= conv_std_logic_vector(168148656,28);
exponent <= conv_std_logic_vector(290,11);
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(9883721,24);
manlo <= conv_std_logic_vector(190474495,28);
exponent <= conv_std_logic_vector(288,11);
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(2838805,24);
manlo <= conv_std_logic_vector(196335986,28);
exponent <= conv_std_logic_vector(287,11);
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(12088108,24);
manlo <= conv_std_logic_vector(120857634,28);
exponent <= conv_std_logic_vector(285,11);
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(4460702,24);
manlo <= conv_std_logic_vector(229771569,28);
exponent <= conv_std_logic_vector(284,11);
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(14474758,24);
manlo <= conv_std_logic_vector(236628147,28);
exponent <= conv_std_logic_vector(282,11);
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(6216702,24);
manlo <= conv_std_logic_vector(29481361,28);
exponent <= conv_std_logic_vector(281,11);
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(140763,24);
manlo <= conv_std_logic_vector(131310533,28);
exponent <= conv_std_logic_vector(280,11);
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(8117891,24);
manlo <= conv_std_logic_vector(96879140,28);
exponent <= conv_std_logic_vector(278,11);
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(1539580,24);
manlo <= conv_std_logic_vector(98694067,28);
exponent <= conv_std_logic_vector(277,11);
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(10176275,24);
manlo <= conv_std_logic_vector(66343668,28);
exponent <= conv_std_logic_vector(275,11);
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(3054054,24);
manlo <= conv_std_logic_vector(159783892,28);
exponent <= conv_std_logic_vector(274,11);
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(12404850,24);
manlo <= conv_std_logic_vector(262311967,28);
exponent <= conv_std_logic_vector(272,11);
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(4693748,24);
manlo <= conv_std_logic_vector(264030756,28);
exponent <= conv_std_logic_vector(271,11);
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(14817690,24);
manlo <= conv_std_logic_vector(106917994,28);
exponent <= conv_std_logic_vector(269,11);
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(6469017,24);
manlo <= conv_std_logic_vector(5191992,28);
exponent <= conv_std_logic_vector(268,11);
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(326406,24);
manlo <= conv_std_logic_vector(114083215,28);
exponent <= conv_std_logic_vector(267,11);
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(8391068,24);
manlo <= conv_std_logic_vector(64117214,28);
exponent <= conv_std_logic_vector(265,11);
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(1740572,24);
manlo <= conv_std_logic_vector(183091279,28);
exponent <= conv_std_logic_vector(264,11);
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(10472039,24);
manlo <= conv_std_logic_vector(2244224,28);
exponent <= conv_std_logic_vector(262,11);
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(3271665,24);
manlo <= conv_std_logic_vector(109958542,28);
exponent <= conv_std_logic_vector(261,11);
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(12725069,24);
manlo <= conv_std_logic_vector(41968573,28);
exponent <= conv_std_logic_vector(259,11);
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(4929352,24);
manlo <= conv_std_logic_vector(94809674,28);
exponent <= conv_std_logic_vector(258,11);
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(15164384,24);
manlo <= conv_std_logic_vector(252890425,28);
exponent <= conv_std_logic_vector(256,11);
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(6724100,24);
manlo <= conv_std_logic_vector(163583158,28);
exponent <= conv_std_logic_vector(255,11);
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(514086,24);
manlo <= conv_std_logic_vector(118679222,28);
exponent <= conv_std_logic_vector(254,11);
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(8667242,24);
manlo <= conv_std_logic_vector(192770478,28);
exponent <= conv_std_logic_vector(252,11);
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(1943770,24);
manlo <= conv_std_logic_vector(136437165,28);
exponent <= conv_std_logic_vector(251,11);
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(10771048,24);
manlo <= conv_std_logic_vector(58883744,28);
exponent <= conv_std_logic_vector(249,11);
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(3491664,24);
manlo <= conv_std_logic_vector(24836209,28);
exponent <= conv_std_logic_vector(248,11);
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(13048801,24);
manlo <= conv_std_logic_vector(33938829,28);
exponent <= conv_std_logic_vector(246,11);
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(5167541,24);
manlo <= conv_std_logic_vector(6894318,28);
exponent <= conv_std_logic_vector(245,11);
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(15514883,24);
manlo <= conv_std_logic_vector(216092120,28);
exponent <= conv_std_logic_vector(243,11);
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(6981983,24);
manlo <= conv_std_logic_vector(70071320,28);
exponent <= conv_std_logic_vector(242,11);
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(703825,24);
manlo <= conv_std_logic_vector(239890498,28);
exponent <= conv_std_logic_vector(241,11);
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(8946447,24);
manlo <= conv_std_logic_vector(185687386,28);
exponent <= conv_std_logic_vector(239,11);
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(2149198,24);
manlo <= conv_std_logic_vector(12777107,28);
exponent <= conv_std_logic_vector(238,11);
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11073338,24);
manlo <= conv_std_logic_vector(132295567,28);
exponent <= conv_std_logic_vector(236,11);
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(3714076,24);
manlo <= conv_std_logic_vector(227171857,28);
exponent <= conv_std_logic_vector(235,11);
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(13376085,24);
manlo <= conv_std_logic_vector(119368169,28);
exponent <= conv_std_logic_vector(233,11);
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(5408343,24);
manlo <= conv_std_logic_vector(99290689,28);
exponent <= conv_std_logic_vector(232,11);
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(15869228,24);
manlo <= conv_std_logic_vector(196569651,28);
exponent <= conv_std_logic_vector(230,11);
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(7242695,24);
manlo <= conv_std_logic_vector(184868911,28);
exponent <= conv_std_logic_vector(229,11);
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(895647,24);
manlo <= conv_std_logic_vector(101480846,28);
exponent <= conv_std_logic_vector(228,11);
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(9228716,24);
manlo <= conv_std_logic_vector(111040654,28);
exponent <= conv_std_logic_vector(226,11);
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(2356879,24);
manlo <= conv_std_logic_vector(205878747,28);
exponent <= conv_std_logic_vector(225,11);
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(11378945,24);
manlo <= conv_std_logic_vector(223412824,28);
exponent <= conv_std_logic_vector(223,11);
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(3938930,24);
manlo <= conv_std_logic_vector(43159582,28);
exponent <= conv_std_logic_vector(222,11);
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(13706961,24);
manlo <= conv_std_logic_vector(24539717,28);
exponent <= conv_std_logic_vector(220,11);
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(5651788,24);
manlo <= conv_std_logic_vector(17696328,28);
exponent <= conv_std_logic_vector(219,11);
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(16227461,24);
manlo <= conv_std_logic_vector(248897772,28);
exponent <= conv_std_logic_vector(217,11);
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(7506268,24);
manlo <= conv_std_logic_vector(253353585,28);
exponent <= conv_std_logic_vector(216,11);
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(1089573,24);
manlo <= conv_std_logic_vector(199085712,28);
exponent <= conv_std_logic_vector(215,11);
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(9514082,24);
manlo <= conv_std_logic_vector(134954983,28);
exponent <= conv_std_logic_vector(213,11);
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(2566840,24);
manlo <= conv_std_logic_vector(107836942,28);
exponent <= conv_std_logic_vector(212,11);
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(11687906,24);
manlo <= conv_std_logic_vector(170784064,28);
exponent <= conv_std_logic_vector(210,11);
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(4166250,24);
manlo <= conv_std_logic_vector(219198631,28);
exponent <= conv_std_logic_vector(209,11);
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(14041467,24);
manlo <= conv_std_logic_vector(127426909,28);
exponent <= conv_std_logic_vector(207,11);
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(5897904,24);
manlo <= conv_std_logic_vector(29159081,28);
exponent <= conv_std_logic_vector(206,11);
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(16589626,24);
manlo <= conv_std_logic_vector(15093248,28);
exponent <= conv_std_logic_vector(204,11);
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(7772734,24);
manlo <= conv_std_logic_vector(112367334,28);
exponent <= conv_std_logic_vector(203,11);
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(1285628,24);
manlo <= conv_std_logic_vector(21894417,28);
exponent <= conv_std_logic_vector(202,11);
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(9802579,24);
manlo <= conv_std_logic_vector(254146435,28);
exponent <= conv_std_logic_vector(200,11);
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(2779104,24);
manlo <= conv_std_logic_vector(257348234,28);
exponent <= conv_std_logic_vector(199,11);
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12000257,24);
manlo <= conv_std_logic_vector(188607876,28);
exponent <= conv_std_logic_vector(197,11);
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(4396065,24);
manlo <= conv_std_logic_vector(238395052,28);
exponent <= conv_std_logic_vector(196,11);
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(14379644,24);
manlo <= conv_std_logic_vector(116776141,28);
exponent <= conv_std_logic_vector(194,11);
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(6146720,24);
manlo <= conv_std_logic_vector(217697734,28);
exponent <= conv_std_logic_vector(193,11);
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(89274,24);
manlo <= conv_std_logic_vector(34078121,28);
exponent <= conv_std_logic_vector(192,11);
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(8042123,24);
manlo <= conv_std_logic_vector(228091050,28);
exponent <= conv_std_logic_vector(190,11);
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(1483833,24);
manlo <= conv_std_logic_vector(200872250,28);
exponent <= conv_std_logic_vector(189,11);
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(10094243,24);
manlo <= conv_std_logic_vector(28573613,28);
exponent <= conv_std_logic_vector(187,11);
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(2993698,24);
manlo <= conv_std_logic_vector(193026703,28);
exponent <= conv_std_logic_vector(186,11);
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12316036,24);
manlo <= conv_std_logic_vector(62602992,28);
exponent <= conv_std_logic_vector(184,11);
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(4628402,24);
manlo <= conv_std_logic_vector(200475490,28);
exponent <= conv_std_logic_vector(183,11);
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(14721532,24);
manlo <= conv_std_logic_vector(67122338,28);
exponent <= conv_std_logic_vector(181,11);
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(6398267,24);
manlo <= conv_std_logic_vector(216803728,28);
exponent <= conv_std_logic_vector(180,11);
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(274352,24);
manlo <= conv_std_logic_vector(17200594,28);
exponent <= conv_std_logic_vector(179,11);
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(8314469,24);
manlo <= conv_std_logic_vector(86446456,28);
exponent <= conv_std_logic_vector(177,11);
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(1684214,24);
manlo <= conv_std_logic_vector(93587914,28);
exponent <= conv_std_logic_vector(176,11);
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(10389106,24);
manlo <= conv_std_logic_vector(193148951,28);
exponent <= conv_std_logic_vector(174,11);
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(3210647,24);
manlo <= conv_std_logic_vector(64824977,28);
exponent <= conv_std_logic_vector(173,11);
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(12635279,24);
manlo <= conv_std_logic_vector(224939505,28);
exponent <= conv_std_logic_vector(171,11);
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(4863289,24);
manlo <= conv_std_logic_vector(17355920,28);
exponent <= conv_std_logic_vector(170,11);
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(15067171,24);
manlo <= conv_std_logic_vector(171641236,28);
exponent <= conv_std_logic_vector(168,11);
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(6652575,24);
manlo <= conv_std_logic_vector(15694991,28);
exponent <= conv_std_logic_vector(167,11);
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(461460,24);
manlo <= conv_std_logic_vector(236949593,28);
exponent <= conv_std_logic_vector(166,11);
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(8589803,24);
manlo <= conv_std_logic_vector(73170085,28);
exponent <= conv_std_logic_vector(164,11);
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(1886793,24);
manlo <= conv_std_logic_vector(200887360,28);
exponent <= conv_std_logic_vector(163,11);
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(10687205,24);
manlo <= conv_std_logic_vector(242930225,28);
exponent <= conv_std_logic_vector(161,11);
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(3429976,24);
manlo <= conv_std_logic_vector(97980458,28);
exponent <= conv_std_logic_vector(160,11);
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(12958026,24);
manlo <= conv_std_logic_vector(144828568,28);
exponent <= conv_std_logic_vector(158,11);
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(5100752,24);
manlo <= conv_std_logic_vector(219332721,28);
exponent <= conv_std_logic_vector(157,11);
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(15416603,24);
manlo <= conv_std_logic_vector(206580322,28);
exponent <= conv_std_logic_vector(155,11);
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(6909672,24);
manlo <= conv_std_logic_vector(228709240,28);
exponent <= conv_std_logic_vector(154,11);
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(650622,24);
manlo <= conv_std_logic_vector(232984198,28);
exponent <= conv_std_logic_vector(153,11);
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(8868158,24);
manlo <= conv_std_logic_vector(132673062,28);
exponent <= conv_std_logic_vector(151,11);
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(2091596,24);
manlo <= conv_std_logic_vector(20173170,28);
exponent <= conv_std_logic_vector(150,11);
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(10988576,24);
manlo <= conv_std_logic_vector(44856082,28);
exponent <= conv_std_logic_vector(148,11);
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(3651712,24);
manlo <= conv_std_logic_vector(56970522,28);
exponent <= conv_std_logic_vector(147,11);
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13284314,24);
manlo <= conv_std_logic_vector(208786223,28);
exponent <= conv_std_logic_vector(145,11);
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(5340822,24);
manlo <= conv_std_logic_vector(76928898,28);
exponent <= conv_std_logic_vector(144,11);
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(15769870,24);
manlo <= conv_std_logic_vector(69445892,28);
exponent <= conv_std_logic_vector(142,11);
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(7169591,24);
manlo <= conv_std_logic_vector(217224162,28);
exponent <= conv_std_logic_vector(141,11);
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(841860,24);
manlo <= conv_std_logic_vector(147476782,28);
exponent <= conv_std_logic_vector(140,11);
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(9149568,24);
manlo <= conv_std_logic_vector(37524984,28);
exponent <= conv_std_logic_vector(138,11);
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(2298645,24);
manlo <= conv_std_logic_vector(193659590,28);
exponent <= conv_std_logic_vector(137,11);
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(11293253,24);
manlo <= conv_std_logic_vector(107316618,28);
exponent <= conv_std_logic_vector(135,11);
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(3875881,24);
manlo <= conv_std_logic_vector(51654059,28);
exponent <= conv_std_logic_vector(134,11);
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13614183,24);
manlo <= conv_std_logic_vector(111249634,28);
exponent <= conv_std_logic_vector(132,11);
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(5583526,24);
manlo <= conv_std_logic_vector(17717412,28);
exponent <= conv_std_logic_vector(131,11);
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(16127013,24);
manlo <= conv_std_logic_vector(48769099,28);
exponent <= conv_std_logic_vector(129,11);
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(7432362,24);
manlo <= conv_std_logic_vector(238120049,28);
exponent <= conv_std_logic_vector(128,11);
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(1035196,24);
manlo <= conv_std_logic_vector(188962402,28);
exponent <= conv_std_logic_vector(127,11);
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(9434065,24);
manlo <= conv_std_logic_vector(194820226,28);
exponent <= conv_std_logic_vector(125,11);
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(2507967,24);
manlo <= conv_std_logic_vector(93233285,28);
exponent <= conv_std_logic_vector(124,11);
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(11601273,24);
manlo <= conv_std_logic_vector(239123672,28);
exponent <= conv_std_logic_vector(122,11);
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(4102510,24);
manlo <= conv_std_logic_vector(1244898,28);
exponent <= conv_std_logic_vector(121,11);
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(13947671,24);
manlo <= conv_std_logic_vector(197996828,28);
exponent <= conv_std_logic_vector(119,11);
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(5828893,24);
manlo <= conv_std_logic_vector(16622593,28);
exponent <= conv_std_logic_vector(118,11);
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(16488075,24);
manlo <= conv_std_logic_vector(20144764,28);
exponent <= conv_std_logic_vector(116,11);
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(7698017,24);
manlo <= conv_std_logic_vector(102592250,28);
exponent <= conv_std_logic_vector(115,11);
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(1230654,24);
manlo <= conv_std_logic_vector(96196092,28);
exponent <= conv_std_logic_vector(114,11);
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(9721685,24);
manlo <= conv_std_logic_vector(36636777,28);
exponent <= conv_std_logic_vector(112,11);
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(2719585,24);
manlo <= conv_std_logic_vector(237160861,28);
exponent <= conv_std_logic_vector(111,11);
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(11912674,24);
manlo <= conv_std_logic_vector(87541902,28);
exponent <= conv_std_logic_vector(109,11);
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(4331625,24);
manlo <= conv_std_logic_vector(172036325,28);
exponent <= conv_std_logic_vector(108,11);
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14284819,24);
manlo <= conv_std_logic_vector(125225503,28);
exponent <= conv_std_logic_vector(106,11);
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(6076952,24);
manlo <= conv_std_logic_vector(133715238,28);
exponent <= conv_std_logic_vector(105,11);
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(37941,24);
manlo <= conv_std_logic_vector(126448851,28);
exponent <= conv_std_logic_vector(104,11);
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(7966586,24);
manlo <= conv_std_logic_vector(250893596,28);
exponent <= conv_std_logic_vector(102,11);
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(1428256,24);
manlo <= conv_std_logic_vector(212630882,28);
exponent <= conv_std_logic_vector(101,11);
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(10012460,24);
manlo <= conv_std_logic_vector(168603206,28);
exponent <= conv_std_logic_vector(99,11);
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(2933526,24);
manlo <= conv_std_logic_vector(143402282,28);
exponent <= conv_std_logic_vector(98,11);
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(12227491,24);
manlo <= conv_std_logic_vector(213203509,28);
exponent <= conv_std_logic_vector(96,11);
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(4563255,24);
manlo <= conv_std_logic_vector(104522224,28);
exponent <= conv_std_logic_vector(95,11);
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14625666,24);
manlo <= conv_std_logic_vector(203000190,28);
exponent <= conv_std_logic_vector(93,11);
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(6327733,24);
manlo <= conv_std_logic_vector(246711469,28);
exponent <= conv_std_logic_vector(92,11);
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(222456,24);
manlo <= conv_std_logic_vector(34640152,28);
exponent <= conv_std_logic_vector(91,11);
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(8238103,24);
manlo <= conv_std_logic_vector(142733230,28);
exponent <= conv_std_logic_vector(89,11);
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(1628027,24);
manlo <= conv_std_logic_vector(144984792,28);
exponent <= conv_std_logic_vector(88,11);
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(10306426,24);
manlo <= conv_std_logic_vector(223510234,28);
exponent <= conv_std_logic_vector(86,11);
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(3149814,24);
manlo <= conv_std_logic_vector(209464872,28);
exponent <= conv_std_logic_vector(85,11);
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(12545763,24);
manlo <= conv_std_logic_vector(212245812,28);
exponent <= conv_std_logic_vector(83,11);
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(4797426,24);
manlo <= conv_std_logic_vector(224882259,28);
exponent <= conv_std_logic_vector(82,11);
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14970254,24);
manlo <= conv_std_logic_vector(54358776,28);
exponent <= conv_std_logic_vector(80,11);
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(6581267,24);
manlo <= conv_std_logic_vector(51917314,28);
exponent <= conv_std_logic_vector(79,11);
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(408995,24);
manlo <= conv_std_logic_vector(130890803,28);
exponent <= conv_std_logic_vector(78,11);
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(8512599,24);
manlo <= conv_std_logic_vector(137347476,28);
exponent <= conv_std_logic_vector(76,11);
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(1829990,24);
manlo <= conv_std_logic_vector(106170554,28);
exponent <= conv_std_logic_vector(75,11);
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(10603618,24);
manlo <= conv_std_logic_vector(204595238,28);
exponent <= conv_std_logic_vector(73,11);
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(3368476,24);
manlo <= conv_std_logic_vector(102605239,28);
exponent <= conv_std_logic_vector(72,11);
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(12867528,24);
manlo <= conv_std_logic_vector(59687307,28);
exponent <= conv_std_logic_vector(70,11);
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(5034167,24);
manlo <= conv_std_logic_vector(235251142,28);
exponent <= conv_std_logic_vector(69,11);
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15318622,24);
manlo <= conv_std_logic_vector(227223140,28);
exponent <= conv_std_logic_vector(67,11);
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(6837582,24);
manlo <= conv_std_logic_vector(138925467,28);
exponent <= conv_std_logic_vector(66,11);
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(597581,24);
manlo <= conv_std_logic_vector(205088968,28);
exponent <= conv_std_logic_vector(65,11);
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(8790107,24);
manlo <= conv_std_logic_vector(152356460,28);
exponent <= conv_std_logic_vector(63,11);
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(2034169,24);
manlo <= conv_std_logic_vector(110749946,28);
exponent <= conv_std_logic_vector(62,11);
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(10904071,24);
manlo <= conv_std_logic_vector(218226183,28);
exponent <= conv_std_logic_vector(60,11);
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(3589537,24);
manlo <= conv_std_logic_vector(102830143,28);
exponent <= conv_std_logic_vector(59,11);
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(13192823,24);
manlo <= conv_std_logic_vector(110639602,28);
exponent <= conv_std_logic_vector(57,11);
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(5273506,24);
manlo <= conv_std_logic_vector(188352155,28);
exponent <= conv_std_logic_vector(56,11);
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15670814,24);
manlo <= conv_std_logic_vector(48227643,28);
exponent <= conv_std_logic_vector(54,11);
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(7096710,24);
manlo <= conv_std_logic_vector(112532514,28);
exponent <= conv_std_logic_vector(53,11);
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(788237,24);
manlo <= conv_std_logic_vector(112565412,28);
exponent <= conv_std_logic_vector(52,11);
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(9070660,24);
manlo <= conv_std_logic_vector(201680253,28);
exponent <= conv_std_logic_vector(50,11);
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(2240588,24);
manlo <= conv_std_logic_vector(244138286,28);
exponent <= conv_std_logic_vector(49,11);
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(11207821,24);
manlo <= conv_std_logic_vector(206597824,28);
exponent <= conv_std_logic_vector(47,11);
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(3813024,24);
manlo <= conv_std_logic_vector(29987310,28);
exponent <= conv_std_logic_vector(46,11);
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(13521688,24);
manlo <= conv_std_logic_vector(27790821,28);
exponent <= conv_std_logic_vector(44,11);
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(5515471,24);
manlo <= conv_std_logic_vector(219963166,28);
exponent <= conv_std_logic_vector(43,11);
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(16026870,24);
manlo <= conv_std_logic_vector(39964772,28);
exponent <= conv_std_logic_vector(41,11);
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(7358681,24);
manlo <= conv_std_logic_vector(204327682,28);
exponent <= conv_std_logic_vector(40,11);
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(980985,24);
manlo <= conv_std_logic_vector(43247066,28);
exponent <= conv_std_logic_vector(39,11);
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(9354292,24);
manlo <= conv_std_logic_vector(128160132,28);
exponent <= conv_std_logic_vector(37,11);
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(2449273,24);
manlo <= conv_std_logic_vector(126511008,28);
exponent <= conv_std_logic_vector(36,11);
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(11514904,24);
manlo <= conv_std_logic_vector(217311246,28);
exponent <= conv_std_logic_vector(34,11);
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(4038963,24);
manlo <= conv_std_logic_vector(49913566,28);
exponent <= conv_std_logic_vector(33,11);
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(13854161,24);
manlo <= conv_std_logic_vector(124821568,28);
exponent <= conv_std_logic_vector(31,11);
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(5760092,24);
manlo <= conv_std_logic_vector(12957085,28);
exponent <= conv_std_logic_vector(30,11);
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16386833,24);
manlo <= conv_std_logic_vector(43278038,28);
exponent <= conv_std_logic_vector(28,11);
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(7623527,24);
manlo <= conv_std_logic_vector(199937734,28);
exponent <= conv_std_logic_vector(27,11);
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(1175847,24);
manlo <= conv_std_logic_vector(253947561,28);
exponent <= conv_std_logic_vector(26,11);
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(9641036,24);
manlo <= conv_std_logic_vector(141497796,28);
exponent <= conv_std_logic_vector(24,11);
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(2660247,24);
manlo <= conv_std_logic_vector(255766959,28);
exponent <= conv_std_logic_vector(23,11);
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(11825357,24);
manlo <= conv_std_logic_vector(136095046,28);
exponent <= conv_std_logic_vector(21,11);
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(4267381,24);
manlo <= conv_std_logic_vector(138414926,28);
exponent <= conv_std_logic_vector(20,11);
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(14190283,24);
manlo <= conv_std_logic_vector(25479908,28);
exponent <= conv_std_logic_vector(18,11);
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(6007396,24);
manlo <= conv_std_logic_vector(140400514,28);
exponent <= conv_std_logic_vector(17,11);
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16750746,24);
manlo <= conv_std_logic_vector(23924155,28);
exponent <= conv_std_logic_vector(15,11);
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(7891279,24);
manlo <= conv_std_logic_vector(245330892,28);
exponent <= conv_std_logic_vector(14,11);
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(1372848,24);
manlo <= conv_std_logic_vector(263794815,28);
exponent <= conv_std_logic_vector(13,11);
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(9930927,24);
manlo <= conv_std_logic_vector(14029030,28);
exponent <= conv_std_logic_vector(11,11);
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(2873537,24);
manlo <= conv_std_logic_vector(129274844,28);
exponent <= conv_std_logic_vector(10,11);
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(12139216,24);
manlo <= conv_std_logic_vector(224845565,28);
exponent <= conv_std_logic_vector(8,11);
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(4498306,24);
manlo <= conv_std_logic_vector(82126943,28);
exponent <= conv_std_logic_vector(7,11);
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(14530093,24);
manlo <= conv_std_logic_vector(7024665,28);
exponent <= conv_std_logic_vector(5,11);
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(6257414,24);
manlo <= conv_std_logic_vector(187437029,28);
exponent <= conv_std_logic_vector(4,11);
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(170718,24);
manlo <= conv_std_logic_vector(36971864,28);
exponent <= conv_std_logic_vector(3,11);
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(8161970,24);
manlo <= conv_std_logic_vector(42518955,28);
exponent <= conv_std_logic_vector(1,11);
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(1572011,24);
manlo <= conv_std_logic_vector(197150320,28);
exponent <= conv_std_logic_vector(0,11);
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/dp_explutneg.vhd | 10 | 140760 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUTNEG.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explutneg IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END dp_explutneg;
ARCHITECTURE rtl OF dp_explutneg IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= conv_std_logic_vector(1023,11);
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(7910755,24);
manlo <= conv_std_logic_vector(103608120,28);
exponent <= conv_std_logic_vector(1021,11);
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(1387178,24);
manlo <= conv_std_logic_vector(62882252,28);
exponent <= conv_std_logic_vector(1020,11);
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(9952012,24);
manlo <= conv_std_logic_vector(214872239,28);
exponent <= conv_std_logic_vector(1018,11);
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(2889051,24);
manlo <= conv_std_logic_vector(136396020,28);
exponent <= conv_std_logic_vector(1017,11);
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(12162046,24);
manlo <= conv_std_logic_vector(873334,28);
exponent <= conv_std_logic_vector(1015,11);
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(4515103,24);
manlo <= conv_std_logic_vector(18076886,28);
exponent <= conv_std_logic_vector(1014,11);
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(14554809,24);
manlo <= conv_std_logic_vector(203729295,28);
exponent <= conv_std_logic_vector(1012,11);
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(6275600,24);
manlo <= conv_std_logic_vector(68167597,28);
exponent <= conv_std_logic_vector(1011,11);
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(184098,24);
manlo <= conv_std_logic_vector(86398042,28);
exponent <= conv_std_logic_vector(1010,11);
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(8181659,24);
manlo <= conv_std_logic_vector(90471578,28);
exponent <= conv_std_logic_vector(1008,11);
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(1586498,24);
manlo <= conv_std_logic_vector(59729764,28);
exponent <= conv_std_logic_vector(1007,11);
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(10245315,24);
manlo <= conv_std_logic_vector(188988555,28);
exponent <= conv_std_logic_vector(1005,11);
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(3104851,24);
manlo <= conv_std_logic_vector(194518424,28);
exponent <= conv_std_logic_vector(1004,11);
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(12479599,24);
manlo <= conv_std_logic_vector(229643794,28);
exponent <= conv_std_logic_vector(1002,11);
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(4748746,24);
manlo <= conv_std_logic_vector(36170808,28);
exponent <= conv_std_logic_vector(1001,11);
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(14898619,24);
manlo <= conv_std_logic_vector(183403979,28);
exponent <= conv_std_logic_vector(999,11);
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(6528561,24);
manlo <= conv_std_logic_vector(123365533,28);
exponent <= conv_std_logic_vector(998,11);
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(370216,24);
manlo <= conv_std_logic_vector(208248737,28);
exponent <= conv_std_logic_vector(997,11);
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(8455535,24);
manlo <= conv_std_logic_vector(254564210,28);
exponent <= conv_std_logic_vector(995,11);
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(1788005,24);
manlo <= conv_std_logic_vector(99840615,28);
exponent <= conv_std_logic_vector(994,11);
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(10541837,24);
manlo <= conv_std_logic_vector(14529516,28);
exponent <= conv_std_logic_vector(992,11);
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(3323019,24);
manlo <= conv_std_logic_vector(252804514,28);
exponent <= conv_std_logic_vector(991,11);
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(12800638,24);
manlo <= conv_std_logic_vector(70515377,28);
exponent <= conv_std_logic_vector(989,11);
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(4984952,24);
manlo <= conv_std_logic_vector(266936970,28);
exponent <= conv_std_logic_vector(988,11);
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(15246202,24);
manlo <= conv_std_logic_vector(73384750,28);
exponent <= conv_std_logic_vector(986,11);
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(6784298,24);
manlo <= conv_std_logic_vector(117472834,28);
exponent <= conv_std_logic_vector(985,11);
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(558377,24);
manlo <= conv_std_logic_vector(141983386,28);
exponent <= conv_std_logic_vector(984,11);
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(8732417,24);
manlo <= conv_std_logic_vector(225268666,28);
exponent <= conv_std_logic_vector(982,11);
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(1991723,24);
manlo <= conv_std_logic_vector(183207072,28);
exponent <= conv_std_logic_vector(981,11);
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(10841612,24);
manlo <= conv_std_logic_vector(44859253,28);
exponent <= conv_std_logic_vector(979,11);
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(3543582,24);
manlo <= conv_std_logic_vector(38615994,28);
exponent <= conv_std_logic_vector(978,11);
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(13125199,24);
manlo <= conv_std_logic_vector(123823208,28);
exponent <= conv_std_logic_vector(976,11);
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(5223751,24);
manlo <= conv_std_logic_vector(209149352,28);
exponent <= conv_std_logic_vector(975,11);
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(15597598,24);
manlo <= conv_std_logic_vector(248916640,28);
exponent <= conv_std_logic_vector(973,11);
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(7042841,24);
manlo <= conv_std_logic_vector(173666528,28);
exponent <= conv_std_logic_vector(972,11);
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(748602,24);
manlo <= conv_std_logic_vector(266199140,28);
exponent <= conv_std_logic_vector(971,11);
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(9012337,24);
manlo <= conv_std_logic_vector(264921173,28);
exponent <= conv_std_logic_vector(969,11);
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(2197677,24);
manlo <= conv_std_logic_vector(112079619,28);
exponent <= conv_std_logic_vector(968,11);
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(11144676,24);
manlo <= conv_std_logic_vector(200497976,28);
exponent <= conv_std_logic_vector(966,11);
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(3766564,24);
manlo <= conv_std_logic_vector(161159716,28);
exponent <= conv_std_logic_vector(965,11);
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(13453322,24);
manlo <= conv_std_logic_vector(28788768,28);
exponent <= conv_std_logic_vector(963,11);
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(5465170,24);
manlo <= conv_std_logic_vector(249755484,28);
exponent <= conv_std_logic_vector(962,11);
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(15952851,24);
manlo <= conv_std_logic_vector(133443390,28);
exponent <= conv_std_logic_vector(960,11);
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(7304221,24);
manlo <= conv_std_logic_vector(236407020,28);
exponent <= conv_std_logic_vector(959,11);
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(940915,24);
manlo <= conv_std_logic_vector(220198205,28);
exponent <= conv_std_logic_vector(958,11);
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(9295329,24);
manlo <= conv_std_logic_vector(196124030,28);
exponent <= conv_std_logic_vector(956,11);
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(2405891,24);
manlo <= conv_std_logic_vector(28613594,28);
exponent <= conv_std_logic_vector(955,11);
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(11451066,24);
manlo <= conv_std_logic_vector(238698933,28);
exponent <= conv_std_logic_vector(953,11);
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(3991993,24);
manlo <= conv_std_logic_vector(233279365,28);
exponent <= conv_std_logic_vector(952,11);
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(13785045,24);
manlo <= conv_std_logic_vector(75368511,28);
exponent <= conv_std_logic_vector(950,11);
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(5709239,24);
manlo <= conv_std_logic_vector(54173026,28);
exponent <= conv_std_logic_vector(949,11);
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(16312002,24);
manlo <= conv_std_logic_vector(78993710,28);
exponent <= conv_std_logic_vector(947,11);
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(7568470,24);
manlo <= conv_std_logic_vector(72422582,28);
exponent <= conv_std_logic_vector(946,11);
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(1135338,24);
manlo <= conv_std_logic_vector(246889480,28);
exponent <= conv_std_logic_vector(945,11);
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(9581426,24);
manlo <= conv_std_logic_vector(208117876,28);
exponent <= conv_std_logic_vector(943,11);
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(2616389,24);
manlo <= conv_std_logic_vector(147217980,28);
exponent <= conv_std_logic_vector(942,11);
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(11760819,24);
manlo <= conv_std_logic_vector(23037889,28);
exponent <= conv_std_logic_vector(940,11);
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(4219896,24);
manlo <= conv_std_logic_vector(214481816,28);
exponent <= conv_std_logic_vector(939,11);
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(14120408,24);
manlo <= conv_std_logic_vector(131761485,28);
exponent <= conv_std_logic_vector(937,11);
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(5955985,24);
manlo <= conv_std_logic_vector(177821786,28);
exponent <= conv_std_logic_vector(936,11);
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(16675094,24);
manlo <= conv_std_logic_vector(25356748,28);
exponent <= conv_std_logic_vector(934,11);
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(7835618,24);
manlo <= conv_std_logic_vector(77011020,28);
exponent <= conv_std_logic_vector(933,11);
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1331895,24);
manlo <= conv_std_logic_vector(119779026,28);
exponent <= conv_std_logic_vector(932,11);
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(9870663,24);
manlo <= conv_std_logic_vector(52552908,28);
exponent <= conv_std_logic_vector(930,11);
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(2829197,24);
manlo <= conv_std_logic_vector(218477336,28);
exponent <= conv_std_logic_vector(929,11);
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(12073970,24);
manlo <= conv_std_logic_vector(61450731,28);
exponent <= conv_std_logic_vector(927,11);
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(4450300,24);
manlo <= conv_std_logic_vector(143360086,28);
exponent <= conv_std_logic_vector(926,11);
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(14459451,24);
manlo <= conv_std_logic_vector(182543396,28);
exponent <= conv_std_logic_vector(924,11);
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(6205439,24);
manlo <= conv_std_logic_vector(188004913,28);
exponent <= conv_std_logic_vector(923,11);
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(132477,24);
manlo <= conv_std_logic_vector(19160299,28);
exponent <= conv_std_logic_vector(922,11);
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(8105697,24);
manlo <= conv_std_logic_vector(201304075,28);
exponent <= conv_std_logic_vector(920,11);
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1530608,24);
manlo <= conv_std_logic_vector(217452229,28);
exponent <= conv_std_logic_vector(919,11);
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(10163073,24);
manlo <= conv_std_logic_vector(118320126,28);
exponent <= conv_std_logic_vector(917,11);
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(3044341,24);
manlo <= conv_std_logic_vector(66824260,28);
exponent <= conv_std_logic_vector(916,11);
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(12390557,24);
manlo <= conv_std_logic_vector(165235674,28);
exponent <= conv_std_logic_vector(914,11);
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(4683232,24);
manlo <= conv_std_logic_vector(138461149,28);
exponent <= conv_std_logic_vector(913,11);
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(14802215,24);
manlo <= conv_std_logic_vector(61508170,28);
exponent <= conv_std_logic_vector(911,11);
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(6457631,24);
manlo <= conv_std_logic_vector(7025744,28);
exponent <= conv_std_logic_vector(910,11);
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(318029,24);
manlo <= conv_std_logic_vector(21309721,28);
exponent <= conv_std_logic_vector(909,11);
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(8378740,24);
manlo <= conv_std_logic_vector(221720132,28);
exponent <= conv_std_logic_vector(907,11);
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1731502,24);
manlo <= conv_std_logic_vector(182144977,28);
exponent <= conv_std_logic_vector(906,11);
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(10458692,24);
manlo <= conv_std_logic_vector(90475423,28);
exponent <= conv_std_logic_vector(904,11);
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(3261845,24);
manlo <= conv_std_logic_vector(128220642,28);
exponent <= conv_std_logic_vector(903,11);
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(12710618,24);
manlo <= conv_std_logic_vector(255552070,28);
exponent <= conv_std_logic_vector(901,11);
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(4918720,24);
manlo <= conv_std_logic_vector(130727832,28);
exponent <= conv_std_logic_vector(900,11);
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(15148739,24);
manlo <= conv_std_logic_vector(258265342,28);
exponent <= conv_std_logic_vector(898,11);
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(6712589,24);
manlo <= conv_std_logic_vector(181573149,28);
exponent <= conv_std_logic_vector(897,11);
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(505617,24);
manlo <= conv_std_logic_vector(45883390,28);
exponent <= conv_std_logic_vector(896,11);
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(8654780,24);
manlo <= conv_std_logic_vector(9428106,28);
exponent <= conv_std_logic_vector(894,11);
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1934600,24);
manlo <= conv_std_logic_vector(262677610,28);
exponent <= conv_std_logic_vector(893,11);
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(10757555,24);
manlo <= conv_std_logic_vector(25094861,28);
exponent <= conv_std_logic_vector(891,11);
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(3481736,24);
manlo <= conv_std_logic_vector(108799619,28);
exponent <= conv_std_logic_vector(890,11);
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(13034192,24);
manlo <= conv_std_logic_vector(96190464,28);
exponent <= conv_std_logic_vector(888,11);
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(5156792,24);
manlo <= conv_std_logic_vector(132821234,28);
exponent <= conv_std_logic_vector(887,11);
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(15499067,24);
manlo <= conv_std_logic_vector(40497064,28);
exponent <= conv_std_logic_vector(885,11);
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(6970346,24);
manlo <= conv_std_logic_vector(4633646,28);
exponent <= conv_std_logic_vector(884,11);
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(695263,24);
manlo <= conv_std_logic_vector(184734272,28);
exponent <= conv_std_logic_vector(883,11);
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(8933848,24);
manlo <= conv_std_logic_vector(68258056,28);
exponent <= conv_std_logic_vector(881,11);
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(2139927,24);
manlo <= conv_std_logic_vector(241478077,28);
exponent <= conv_std_logic_vector(880,11);
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(11059697,24);
manlo <= conv_std_logic_vector(81964893,28);
exponent <= conv_std_logic_vector(878,11);
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(3704040,24);
manlo <= conv_std_logic_vector(59435624,28);
exponent <= conv_std_logic_vector(877,11);
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(13361316,24);
manlo <= conv_std_logic_vector(100097713,28);
exponent <= conv_std_logic_vector(875,11);
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(5397476,24);
manlo <= conv_std_logic_vector(240017437,28);
exponent <= conv_std_logic_vector(874,11);
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(15853238,24);
manlo <= conv_std_logic_vector(139632179,28);
exponent <= conv_std_logic_vector(872,11);
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(7230930,24);
manlo <= conv_std_logic_vector(200816807,28);
exponent <= conv_std_logic_vector(871,11);
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(886991,24);
manlo <= conv_std_logic_vector(58654941,28);
exponent <= conv_std_logic_vector(870,11);
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(9215978,24);
manlo <= conv_std_logic_vector(193575030,28);
exponent <= conv_std_logic_vector(868,11);
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(2347507,24);
manlo <= conv_std_logic_vector(240661664,28);
exponent <= conv_std_logic_vector(867,11);
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(11365154,24);
manlo <= conv_std_logic_vector(257284930,28);
exponent <= conv_std_logic_vector(865,11);
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(3928783,24);
manlo <= conv_std_logic_vector(108146246,28);
exponent <= conv_std_logic_vector(864,11);
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(13692029,24);
manlo <= conv_std_logic_vector(256867284,28);
exponent <= conv_std_logic_vector(862,11);
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(5640802,24);
manlo <= conv_std_logic_vector(94243132,28);
exponent <= conv_std_logic_vector(861,11);
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(16211296,24);
manlo <= conv_std_logic_vector(67825654,28);
exponent <= conv_std_logic_vector(859,11);
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(7494374,24);
manlo <= conv_std_logic_vector(242982196,28);
exponent <= conv_std_logic_vector(858,11);
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1080822,24);
manlo <= conv_std_logic_vector(160277009,28);
exponent <= conv_std_logic_vector(857,11);
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(9501205,24);
manlo <= conv_std_logic_vector(10212621,28);
exponent <= conv_std_logic_vector(855,11);
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2557365,24);
manlo <= conv_std_logic_vector(185941944,28);
exponent <= conv_std_logic_vector(854,11);
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(11673964,24);
manlo <= conv_std_logic_vector(116382402,28);
exponent <= conv_std_logic_vector(852,11);
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(4155992,24);
manlo <= conv_std_logic_vector(192503267,28);
exponent <= conv_std_logic_vector(851,11);
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(14026372,24);
manlo <= conv_std_logic_vector(133984890,28);
exponent <= conv_std_logic_vector(849,11);
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(5886797,24);
manlo <= conv_std_logic_vector(227169396,28);
exponent <= conv_std_logic_vector(848,11);
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(16573282,24);
manlo <= conv_std_logic_vector(266790864,28);
exponent <= conv_std_logic_vector(846,11);
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(7760709,24);
manlo <= conv_std_logic_vector(232279832,28);
exponent <= conv_std_logic_vector(845,11);
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(1276780,24);
manlo <= conv_std_logic_vector(244188460,28);
exponent <= conv_std_logic_vector(844,11);
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(9789561,24);
manlo <= conv_std_logic_vector(47289108,28);
exponent <= conv_std_logic_vector(842,11);
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2769526,24);
manlo <= conv_std_logic_vector(75856665,28);
exponent <= conv_std_logic_vector(841,11);
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(11986162,24);
manlo <= conv_std_logic_vector(137053172,28);
exponent <= conv_std_logic_vector(839,11);
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(4385695,24);
manlo <= conv_std_logic_vector(60488459,28);
exponent <= conv_std_logic_vector(838,11);
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(14364383,24);
manlo <= conv_std_logic_vector(220265084,28);
exponent <= conv_std_logic_vector(836,11);
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(6135492,24);
manlo <= conv_std_logic_vector(182090040,28);
exponent <= conv_std_logic_vector(835,11);
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(81012,24);
manlo <= conv_std_logic_vector(249275143,28);
exponent <= conv_std_logic_vector(834,11);
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(8029967,24);
manlo <= conv_std_logic_vector(93846972,28);
exponent <= conv_std_logic_vector(832,11);
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(1474889,24);
manlo <= conv_std_logic_vector(132978099,28);
exponent <= conv_std_logic_vector(831,11);
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(10081081,24);
manlo <= conv_std_logic_vector(128680817,28);
exponent <= conv_std_logic_vector(829,11);
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2984014,24);
manlo <= conv_std_logic_vector(251002315,28);
exponent <= conv_std_logic_vector(828,11);
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(12301786,24);
manlo <= conv_std_logic_vector(100124707,28);
exponent <= conv_std_logic_vector(826,11);
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(4617918,24);
manlo <= conv_std_logic_vector(76665129,28);
exponent <= conv_std_logic_vector(825,11);
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(14706104,24);
manlo <= conv_std_logic_vector(48076192,28);
exponent <= conv_std_logic_vector(823,11);
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(6386916,24);
manlo <= conv_std_logic_vector(125471070,28);
exponent <= conv_std_logic_vector(822,11);
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(266000,24);
manlo <= conv_std_logic_vector(57624675,28);
exponent <= conv_std_logic_vector(821,11);
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(8302179,24);
manlo <= conv_std_logic_vector(114693198,28);
exponent <= conv_std_logic_vector(819,11);
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(1675171,24);
manlo <= conv_std_logic_vector(254852645,28);
exponent <= conv_std_logic_vector(818,11);
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(10375800,24);
manlo <= conv_std_logic_vector(179426511,28);
exponent <= conv_std_logic_vector(816,11);
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(3200857,24);
manlo <= conv_std_logic_vector(52664716,28);
exponent <= conv_std_logic_vector(815,11);
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(12620873,24);
manlo <= conv_std_logic_vector(164386702,28);
exponent <= conv_std_logic_vector(813,11);
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(4852689,24);
manlo <= conv_std_logic_vector(149310968,28);
exponent <= conv_std_logic_vector(812,11);
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(15051574,24);
manlo <= conv_std_logic_vector(73675604,28);
exponent <= conv_std_logic_vector(810,11);
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(6641099,24);
manlo <= conv_std_logic_vector(42591307,28);
exponent <= conv_std_logic_vector(809,11);
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(453017,24);
manlo <= conv_std_logic_vector(104016801,28);
exponent <= conv_std_logic_vector(808,11);
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(8577378,24);
manlo <= conv_std_logic_vector(139419332,28);
exponent <= conv_std_logic_vector(806,11);
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(1877652,24);
manlo <= conv_std_logic_vector(33778363,28);
exponent <= conv_std_logic_vector(805,11);
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(10673753,24);
manlo <= conv_std_logic_vector(226837452,28);
exponent <= conv_std_logic_vector(803,11);
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(3420078,24);
manlo <= conv_std_logic_vector(239554874,28);
exponent <= conv_std_logic_vector(802,11);
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(12943462,24);
manlo <= conv_std_logic_vector(62486566,28);
exponent <= conv_std_logic_vector(800,11);
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(5090036,24);
manlo <= conv_std_logic_vector(268173235,28);
exponent <= conv_std_logic_vector(799,11);
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(15400835,24);
manlo <= conv_std_logic_vector(67898261,28);
exponent <= conv_std_logic_vector(797,11);
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(6898071,24);
manlo <= conv_std_logic_vector(6935226,28);
exponent <= conv_std_logic_vector(796,11);
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(642086,24);
manlo <= conv_std_logic_vector(193616024,28);
exponent <= conv_std_logic_vector(795,11);
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(8855597,24);
manlo <= conv_std_logic_vector(108124901,28);
exponent <= conv_std_logic_vector(793,11);
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2082354,24);
manlo <= conv_std_logic_vector(37727361,28);
exponent <= conv_std_logic_vector(792,11);
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(10974976,24);
manlo <= conv_std_logic_vector(133184200,28);
exponent <= conv_std_logic_vector(790,11);
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(3641706,24);
manlo <= conv_std_logic_vector(35844662,28);
exponent <= conv_std_logic_vector(789,11);
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(13269590,24);
manlo <= conv_std_logic_vector(175886280,28);
exponent <= conv_std_logic_vector(787,11);
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(5329988,24);
manlo <= conv_std_logic_vector(236927280,28);
exponent <= conv_std_logic_vector(786,11);
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(15753928,24);
manlo <= conv_std_logic_vector(191213976,28);
exponent <= conv_std_logic_vector(784,11);
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(7157862,24);
manlo <= conv_std_logic_vector(181160855,28);
exponent <= conv_std_logic_vector(783,11);
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(833230,24);
manlo <= conv_std_logic_vector(197197075,28);
exponent <= conv_std_logic_vector(782,11);
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(9136869,24);
manlo <= conv_std_logic_vector(57456047,28);
exponent <= conv_std_logic_vector(780,11);
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(2289302,24);
manlo <= conv_std_logic_vector(100400411,28);
exponent <= conv_std_logic_vector(779,11);
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(11279504,24);
manlo <= conv_std_logic_vector(133702078,28);
exponent <= conv_std_logic_vector(777,11);
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3865765,24);
manlo <= conv_std_logic_vector(84791606,28);
exponent <= conv_std_logic_vector(776,11);
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(13599297,24);
manlo <= conv_std_logic_vector(193913492,28);
exponent <= conv_std_logic_vector(774,11);
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(5572573,24);
manlo <= conv_std_logic_vector(210951234,28);
exponent <= conv_std_logic_vector(773,11);
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(16110896,24);
manlo <= conv_std_logic_vector(189751005,28);
exponent <= conv_std_logic_vector(771,11);
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(7420505,24);
manlo <= conv_std_logic_vector(12771910,28);
exponent <= conv_std_logic_vector(770,11);
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(1026472,24);
manlo <= conv_std_logic_vector(51864863,28);
exponent <= conv_std_logic_vector(769,11);
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(9421227,24);
manlo <= conv_std_logic_vector(121664951,28);
exponent <= conv_std_logic_vector(767,11);
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(2498521,24);
manlo <= conv_std_logic_vector(127312793,28);
exponent <= conv_std_logic_vector(766,11);
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(11587374,24);
manlo <= conv_std_logic_vector(32431827,28);
exponent <= conv_std_logic_vector(764,11);
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(4092283,24);
manlo <= conv_std_logic_vector(33663701,28);
exponent <= conv_std_logic_vector(763,11);
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(13932622,24);
manlo <= conv_std_logic_vector(188745186,28);
exponent <= conv_std_logic_vector(761,11);
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(5817820,24);
manlo <= conv_std_logic_vector(161368804,28);
exponent <= conv_std_logic_vector(760,11);
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(16471781,24);
manlo <= conv_std_logic_vector(201946939,28);
exponent <= conv_std_logic_vector(758,11);
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(7686029,24);
manlo <= conv_std_logic_vector(114155240,28);
exponent <= conv_std_logic_vector(757,11);
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(1221834,24);
manlo <= conv_std_logic_vector(30217784,28);
exponent <= conv_std_logic_vector(756,11);
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(9708705,24);
manlo <= conv_std_logic_vector(265245416,28);
exponent <= conv_std_logic_vector(754,11);
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(2710036,24);
manlo <= conv_std_logic_vector(96582323,28);
exponent <= conv_std_logic_vector(753,11);
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(11898622,24);
manlo <= conv_std_logic_vector(8685564,28);
exponent <= conv_std_logic_vector(751,11);
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(4321286,24);
manlo <= conv_std_logic_vector(145205332,28);
exponent <= conv_std_logic_vector(750,11);
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(14269605,24);
manlo <= conv_std_logic_vector(79792252,28);
exponent <= conv_std_logic_vector(748,11);
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(6065758,24);
manlo <= conv_std_logic_vector(144408455,28);
exponent <= conv_std_logic_vector(747,11);
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(29705,24);
manlo <= conv_std_logic_vector(111518540,28);
exponent <= conv_std_logic_vector(746,11);
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(7954467,24);
manlo <= conv_std_logic_vector(116097284,28);
exponent <= conv_std_logic_vector(744,11);
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(1419339,24);
manlo <= conv_std_logic_vector(204212637,28);
exponent <= conv_std_logic_vector(743,11);
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(9999339,24);
manlo <= conv_std_logic_vector(15580207,28);
exponent <= conv_std_logic_vector(741,11);
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(2923872,24);
manlo <= conv_std_logic_vector(59726033,28);
exponent <= conv_std_logic_vector(740,11);
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(12213285,24);
manlo <= conv_std_logic_vector(81348195,28);
exponent <= conv_std_logic_vector(738,11);
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(4552802,24);
manlo <= conv_std_logic_vector(224758002,28);
exponent <= conv_std_logic_vector(737,11);
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(14610285,24);
manlo <= conv_std_logic_vector(171839647,28);
exponent <= conv_std_logic_vector(735,11);
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(6316417,24);
manlo <= conv_std_logic_vector(33901818,28);
exponent <= conv_std_logic_vector(734,11);
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(214129,24);
manlo <= conv_std_logic_vector(187432044,28);
exponent <= conv_std_logic_vector(733,11);
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(8225851,24);
manlo <= conv_std_logic_vector(10972428,28);
exponent <= conv_std_logic_vector(731,11);
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(1619012,24);
manlo <= conv_std_logic_vector(177473085,28);
exponent <= conv_std_logic_vector(730,11);
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(10293161,24);
manlo <= conv_std_logic_vector(74648462,28);
exponent <= conv_std_logic_vector(728,11);
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3140054,24);
manlo <= conv_std_logic_vector(142465582,28);
exponent <= conv_std_logic_vector(727,11);
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(12531401,24);
manlo <= conv_std_logic_vector(110062606,28);
exponent <= conv_std_logic_vector(725,11);
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(4786859,24);
manlo <= conv_std_logic_vector(158003247,28);
exponent <= conv_std_logic_vector(724,11);
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(14954704,24);
manlo <= conv_std_logic_vector(82587752,28);
exponent <= conv_std_logic_vector(722,11);
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(6569826,24);
manlo <= conv_std_logic_vector(59098716,28);
exponent <= conv_std_logic_vector(721,11);
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(400577,24);
manlo <= conv_std_logic_vector(185198176,28);
exponent <= conv_std_logic_vector(720,11);
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(8500212,24);
manlo <= conv_std_logic_vector(153765179,28);
exponent <= conv_std_logic_vector(718,11);
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(1820876,24);
manlo <= conv_std_logic_vector(159783545,28);
exponent <= conv_std_logic_vector(717,11);
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(10590207,24);
manlo <= conv_std_logic_vector(172648734,28);
exponent <= conv_std_logic_vector(715,11);
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3358609,24);
manlo <= conv_std_logic_vector(8670608,28);
exponent <= conv_std_logic_vector(714,11);
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(12853008,24);
manlo <= conv_std_logic_vector(64863304,28);
exponent <= conv_std_logic_vector(712,11);
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(5023484,24);
manlo <= conv_std_logic_vector(180279682,28);
exponent <= conv_std_logic_vector(711,11);
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(15302902,24);
manlo <= conv_std_logic_vector(86126918,28);
exponent <= conv_std_logic_vector(709,11);
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(6826016,24);
manlo <= conv_std_logic_vector(315265,28);
exponent <= conv_std_logic_vector(708,11);
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(589071,24);
manlo <= conv_std_logic_vector(160219440,28);
exponent <= conv_std_logic_vector(707,11);
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(8777584,24);
manlo <= conv_std_logic_vector(189361726,28);
exponent <= conv_std_logic_vector(705,11);
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(2024955,24);
manlo <= conv_std_logic_vector(162543151,28);
exponent <= conv_std_logic_vector(704,11);
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(10890513,24);
manlo <= conv_std_logic_vector(142859647,28);
exponent <= conv_std_logic_vector(702,11);
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(3579561,24);
manlo <= conv_std_logic_vector(203359193,28);
exponent <= conv_std_logic_vector(701,11);
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(13178144,24);
manlo <= conv_std_logic_vector(27387766,28);
exponent <= conv_std_logic_vector(699,11);
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(5262706,24);
manlo <= conv_std_logic_vector(72167880,28);
exponent <= conv_std_logic_vector(698,11);
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(15654921,24);
manlo <= conv_std_logic_vector(40507130,28);
exponent <= conv_std_logic_vector(696,11);
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(7085016,24);
manlo <= conv_std_logic_vector(263640644,28);
exponent <= conv_std_logic_vector(695,11);
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(779633,24);
manlo <= conv_std_logic_vector(233308885,28);
exponent <= conv_std_logic_vector(694,11);
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(9058000,24);
manlo <= conv_std_logic_vector(127336500,28);
exponent <= conv_std_logic_vector(692,11);
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(2231273,24);
manlo <= conv_std_logic_vector(267969878,28);
exponent <= conv_std_logic_vector(691,11);
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(11194114,24);
manlo <= conv_std_logic_vector(191206462,28);
exponent <= conv_std_logic_vector(689,11);
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(3802939,24);
manlo <= conv_std_logic_vector(6046440,28);
exponent <= conv_std_logic_vector(688,11);
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(13506847,24);
manlo <= conv_std_logic_vector(192101060,28);
exponent <= conv_std_logic_vector(686,11);
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(5504552,24);
manlo <= conv_std_logic_vector(234133234,28);
exponent <= conv_std_logic_vector(685,11);
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(16010802,24);
manlo <= conv_std_logic_vector(194370273,28);
exponent <= conv_std_logic_vector(683,11);
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(7346860,24);
manlo <= conv_std_logic_vector(2864438,28);
exponent <= conv_std_logic_vector(682,11);
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(972287,24);
manlo <= conv_std_logic_vector(54536955,28);
exponent <= conv_std_logic_vector(681,11);
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(9341493,24);
manlo <= conv_std_logic_vector(74572905,28);
exponent <= conv_std_logic_vector(679,11);
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(2439856,24);
manlo <= conv_std_logic_vector(93006730,28);
exponent <= conv_std_logic_vector(678,11);
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(11501047,24);
manlo <= conv_std_logic_vector(92098230,28);
exponent <= conv_std_logic_vector(676,11);
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4028767,24);
manlo <= conv_std_logic_vector(115940390,28);
exponent <= conv_std_logic_vector(675,11);
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(13839158,24);
manlo <= conv_std_logic_vector(62227559,28);
exponent <= conv_std_logic_vector(673,11);
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(5749053,24);
manlo <= conv_std_logic_vector(76824142,28);
exponent <= conv_std_logic_vector(672,11);
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(16370589,24);
manlo <= conv_std_logic_vector(114548734,28);
exponent <= conv_std_logic_vector(670,11);
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(7611576,24);
manlo <= conv_std_logic_vector(73252889,28);
exponent <= conv_std_logic_vector(669,11);
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(1167054,24);
manlo <= conv_std_logic_vector(146134399,28);
exponent <= conv_std_logic_vector(668,11);
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(9628096,24);
manlo <= conv_std_logic_vector(236331104,28);
exponent <= conv_std_logic_vector(666,11);
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(2650727,24);
manlo <= conv_std_logic_vector(132284651,28);
exponent <= conv_std_logic_vector(665,11);
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(11811347,24);
manlo <= conv_std_logic_vector(263325685,28);
exponent <= conv_std_logic_vector(663,11);
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4257073,24);
manlo <= conv_std_logic_vector(236873507,28);
exponent <= conv_std_logic_vector(662,11);
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(14175115,24);
manlo <= conv_std_logic_vector(61615323,28);
exponent <= conv_std_logic_vector(660,11);
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(5996236,24);
manlo <= conv_std_logic_vector(169476567,28);
exponent <= conv_std_logic_vector(659,11);
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(16734324,24);
manlo <= conv_std_logic_vector(29597837,28);
exponent <= conv_std_logic_vector(657,11);
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(7879197,24);
manlo <= conv_std_logic_vector(79755942,28);
exponent <= conv_std_logic_vector(656,11);
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(1363959,24);
manlo <= conv_std_logic_vector(24177677,28);
exponent <= conv_std_logic_vector(655,11);
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(9917845,24);
manlo <= conv_std_logic_vector(112021148,28);
exponent <= conv_std_logic_vector(653,11);
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(2863912,24);
manlo <= conv_std_logic_vector(148304045,28);
exponent <= conv_std_logic_vector(652,11);
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(12125053,24);
manlo <= conv_std_logic_vector(156617262,28);
exponent <= conv_std_logic_vector(650,11);
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4487885,24);
manlo <= conv_std_logic_vector(151904422,28);
exponent <= conv_std_logic_vector(649,11);
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(14514758,24);
manlo <= conv_std_logic_vector(193824214,28);
exponent <= conv_std_logic_vector(647,11);
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(6246132,24);
manlo <= conv_std_logic_vector(93361418,28);
exponent <= conv_std_logic_vector(646,11);
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(162417,24);
manlo <= conv_std_logic_vector(12929741,28);
exponent <= conv_std_logic_vector(645,11);
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(8149754,24);
manlo <= conv_std_logic_vector(257063442,28);
exponent <= conv_std_logic_vector(643,11);
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(1563024,24);
manlo <= conv_std_logic_vector(78378796,28);
exponent <= conv_std_logic_vector(642,11);
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(10210773,24);
manlo <= conv_std_logic_vector(106907060,28);
exponent <= conv_std_logic_vector(640,11);
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(3079436,24);
manlo <= conv_std_logic_vector(245979562,28);
exponent <= conv_std_logic_vector(639,11);
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(12442201,24);
manlo <= conv_std_logic_vector(137868870,28);
exponent <= conv_std_logic_vector(637,11);
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(4721229,24);
manlo <= conv_std_logic_vector(261058204,28);
exponent <= conv_std_logic_vector(636,11);
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(14858129,24);
manlo <= conv_std_logic_vector(43405174,28);
exponent <= conv_std_logic_vector(634,11);
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(6498770,24);
manlo <= conv_std_logic_vector(53338521,28);
exponent <= conv_std_logic_vector(633,11);
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(348297,24);
manlo <= conv_std_logic_vector(158641329,28);
exponent <= conv_std_logic_vector(632,11);
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(8423281,24);
manlo <= conv_std_logic_vector(128446906,28);
exponent <= conv_std_logic_vector(630,11);
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(1764273,24);
manlo <= conv_std_logic_vector(230657816,28);
exponent <= conv_std_logic_vector(629,11);
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(10506915,24);
manlo <= conv_std_logic_vector(191032874,28);
exponent <= conv_std_logic_vector(627,11);
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(3297326,24);
manlo <= conv_std_logic_vector(68145509,28);
exponent <= conv_std_logic_vector(626,11);
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(12762829,24);
manlo <= conv_std_logic_vector(146161159,28);
exponent <= conv_std_logic_vector(624,11);
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(4957134,24);
manlo <= conv_std_logic_vector(240027976,28);
exponent <= conv_std_logic_vector(623,11);
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(15205267,24);
manlo <= conv_std_logic_vector(119370809,28);
exponent <= conv_std_logic_vector(621,11);
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(6754180,24);
manlo <= conv_std_logic_vector(73501816,28);
exponent <= conv_std_logic_vector(620,11);
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(536217,24);
manlo <= conv_std_logic_vector(220758658,28);
exponent <= conv_std_logic_vector(619,11);
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(8699809,24);
manlo <= conv_std_logic_vector(117402516,28);
exponent <= conv_std_logic_vector(617,11);
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(1967731,24);
manlo <= conv_std_logic_vector(204336317,28);
exponent <= conv_std_logic_vector(616,11);
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(10806307,24);
manlo <= conv_std_logic_vector(168773516,28);
exponent <= conv_std_logic_vector(614,11);
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(3517606,24);
manlo <= conv_std_logic_vector(138553816,28);
exponent <= conv_std_logic_vector(613,11);
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(13086975,24);
manlo <= conv_std_logic_vector(231838082,28);
exponent <= conv_std_logic_vector(611,11);
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5195628,24);
manlo <= conv_std_logic_vector(114805284,28);
exponent <= conv_std_logic_vector(610,11);
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(15556214,24);
manlo <= conv_std_logic_vector(245890169,28);
exponent <= conv_std_logic_vector(608,11);
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(7012392,24);
manlo <= conv_std_logic_vector(266576824,28);
exponent <= conv_std_logic_vector(607,11);
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(726200,24);
manlo <= conv_std_logic_vector(33318175,28);
exponent <= conv_std_logic_vector(606,11);
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(8979371,24);
manlo <= conv_std_logic_vector(206515377,28);
exponent <= conv_std_logic_vector(604,11);
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(2173422,24);
manlo <= conv_std_logic_vector(61774637,28);
exponent <= conv_std_logic_vector(603,11);
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(11108984,24);
manlo <= conv_std_logic_vector(216833386,28);
exponent <= conv_std_logic_vector(601,11);
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(3740303,24);
manlo <= conv_std_logic_vector(252090990,28);
exponent <= conv_std_logic_vector(600,11);
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(13414679,24);
manlo <= conv_std_logic_vector(20856890,28);
exponent <= conv_std_logic_vector(598,11);
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5436738,24);
manlo <= conv_std_logic_vector(262578382,28);
exponent <= conv_std_logic_vector(597,11);
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(15911013,24);
manlo <= conv_std_logic_vector(100481506,28);
exponent <= conv_std_logic_vector(595,11);
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(7273439,24);
manlo <= conv_std_logic_vector(29586843,28);
exponent <= conv_std_logic_vector(594,11);
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(918267,24);
manlo <= conv_std_logic_vector(33154287,28);
exponent <= conv_std_logic_vector(593,11);
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(9262001,24);
manlo <= conv_std_logic_vector(206947959,28);
exponent <= conv_std_logic_vector(591,11);
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(2381369,24);
manlo <= conv_std_logic_vector(205146615,28);
exponent <= conv_std_logic_vector(590,11);
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(11414983,24);
manlo <= conv_std_logic_vector(80080029,28);
exponent <= conv_std_logic_vector(588,11);
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(3965445,24);
manlo <= conv_std_logic_vector(12487826,28);
exponent <= conv_std_logic_vector(587,11);
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(13745978,24);
manlo <= conv_std_logic_vector(58199715,28);
exponent <= conv_std_logic_vector(585,11);
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5680495,24);
manlo <= conv_std_logic_vector(70463110,28);
exponent <= conv_std_logic_vector(584,11);
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(16269705,24);
manlo <= conv_std_logic_vector(20654997,28);
exponent <= conv_std_logic_vector(582,11);
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(7537349,24);
manlo <= conv_std_logic_vector(192319832,28);
exponent <= conv_std_logic_vector(581,11);
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(1112441,24);
manlo <= conv_std_logic_vector(186880957,28);
exponent <= conv_std_logic_vector(580,11);
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(9547733,24);
manlo <= conv_std_logic_vector(27940083,28);
exponent <= conv_std_logic_vector(578,11);
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(2591599,24);
manlo <= conv_std_logic_vector(35045549,28);
exponent <= conv_std_logic_vector(577,11);
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(11724339,24);
manlo <= conv_std_logic_vector(146438512,28);
exponent <= conv_std_logic_vector(575,11);
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(4193056,24);
manlo <= conv_std_logic_vector(175344679,28);
exponent <= conv_std_logic_vector(574,11);
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(14080912,24);
manlo <= conv_std_logic_vector(198508677,28);
exponent <= conv_std_logic_vector(572,11);
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5926926,24);
manlo <= conv_std_logic_vector(83904648,28);
exponent <= conv_std_logic_vector(571,11);
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(16632332,24);
manlo <= conv_std_logic_vector(199957404,28);
exponent <= conv_std_logic_vector(569,11);
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(7804156,24);
manlo <= conv_std_logic_vector(65532420,28);
exponent <= conv_std_logic_vector(568,11);
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(1308746,24);
manlo <= conv_std_logic_vector(260058525,28);
exponent <= conv_std_logic_vector(567,11);
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(9836599,24);
manlo <= conv_std_logic_vector(214756046,28);
exponent <= conv_std_logic_vector(565,11);
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(2804135,24);
manlo <= conv_std_logic_vector(98759674,28);
exponent <= conv_std_logic_vector(564,11);
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(12037090,24);
manlo <= conv_std_logic_vector(105879341,28);
exponent <= conv_std_logic_vector(562,11);
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(4423165,24);
manlo <= conv_std_logic_vector(233069674,28);
exponent <= conv_std_logic_vector(561,11);
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(14419522,24);
manlo <= conv_std_logic_vector(144218340,28);
exponent <= conv_std_logic_vector(559,11);
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6176061,24);
manlo <= conv_std_logic_vector(128557517,28);
exponent <= conv_std_logic_vector(558,11);
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(110861,24);
manlo <= conv_std_logic_vector(210451229,28);
exponent <= conv_std_logic_vector(557,11);
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(8073890,24);
manlo <= conv_std_logic_vector(126309403,28);
exponent <= conv_std_logic_vector(555,11);
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(1507206,24);
manlo <= conv_std_logic_vector(86368556,28);
exponent <= conv_std_logic_vector(554,11);
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(10128636,24);
manlo <= conv_std_logic_vector(70724454,28);
exponent <= conv_std_logic_vector(552,11);
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(3019003,24);
manlo <= conv_std_logic_vector(212024500,28);
exponent <= conv_std_logic_vector(551,11);
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(12353273,24);
manlo <= conv_std_logic_vector(25338267,28);
exponent <= conv_std_logic_vector(549,11);
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(4655800,24);
manlo <= conv_std_logic_vector(26358145,28);
exponent <= conv_std_logic_vector(548,11);
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(14761847,24);
manlo <= conv_std_logic_vector(252137457,28);
exponent <= conv_std_logic_vector(546,11);
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6427930,24);
manlo <= conv_std_logic_vector(116530320,28);
exponent <= conv_std_logic_vector(545,11);
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(296176,24);
manlo <= conv_std_logic_vector(162393576,28);
exponent <= conv_std_logic_vector(544,11);
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(8346584,24);
manlo <= conv_std_logic_vector(140031506,28);
exponent <= conv_std_logic_vector(542,11);
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(1707843,24);
manlo <= conv_std_logic_vector(105232250,28);
exponent <= conv_std_logic_vector(541,11);
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(10423877,24);
manlo <= conv_std_logic_vector(74257288,28);
exponent <= conv_std_logic_vector(539,11);
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(3236229,24);
manlo <= conv_std_logic_vector(265138481,28);
exponent <= conv_std_logic_vector(538,11);
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(12672925,24);
manlo <= conv_std_logic_vector(81471742,28);
exponent <= conv_std_logic_vector(536,11);
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(4890987,24);
manlo <= conv_std_logic_vector(13504322,28);
exponent <= conv_std_logic_vector(535,11);
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(15107929,24);
manlo <= conv_std_logic_vector(192561070,28);
exponent <= conv_std_logic_vector(533,11);
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6682563,24);
manlo <= conv_std_logic_vector(47334412,28);
exponent <= conv_std_logic_vector(532,11);
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(483524,24);
manlo <= conv_std_logic_vector(243414774,28);
exponent <= conv_std_logic_vector(531,11);
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(8622270,24);
manlo <= conv_std_logic_vector(235144322,28);
exponent <= conv_std_logic_vector(529,11);
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(1910682,24);
manlo <= conv_std_logic_vector(20388866,28);
exponent <= conv_std_logic_vector(528,11);
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(10722358,24);
manlo <= conv_std_logic_vector(913747,28);
exponent <= conv_std_logic_vector(526,11);
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(3455839,24);
manlo <= conv_std_logic_vector(223781205,28);
exponent <= conv_std_logic_vector(525,11);
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(12996085,24);
manlo <= conv_std_logic_vector(24989984,28);
exponent <= conv_std_logic_vector(523,11);
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(5128754,24);
manlo <= conv_std_logic_vector(197545335,28);
exponent <= conv_std_logic_vector(522,11);
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(15457809,24);
manlo <= conv_std_logic_vector(24315860,28);
exponent <= conv_std_logic_vector(520,11);
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6939990,24);
manlo <= conv_std_logic_vector(8842978,28);
exponent <= conv_std_logic_vector(519,11);
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(672929,24);
manlo <= conv_std_logic_vector(830489,28);
exponent <= conv_std_logic_vector(518,11);
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(8900982,24);
manlo <= conv_std_logic_vector(98890321,28);
exponent <= conv_std_logic_vector(516,11);
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(2115746,24);
manlo <= conv_std_logic_vector(142837003,28);
exponent <= conv_std_logic_vector(515,11);
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(11024113,24);
manlo <= conv_std_logic_vector(266701758,28);
exponent <= conv_std_logic_vector(513,11);
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(3677859,24);
manlo <= conv_std_logic_vector(129840563,28);
exponent <= conv_std_logic_vector(512,11);
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(13322790,24);
manlo <= conv_std_logic_vector(255615990,28);
exponent <= conv_std_logic_vector(510,11);
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(5369131,24);
manlo <= conv_std_logic_vector(127156783,28);
exponent <= conv_std_logic_vector(509,11);
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(15811527,24);
manlo <= conv_std_logic_vector(196077973,28);
exponent <= conv_std_logic_vector(507,11);
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7200241,24);
manlo <= conv_std_logic_vector(178260644,28);
exponent <= conv_std_logic_vector(506,11);
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(864411,24);
manlo <= conv_std_logic_vector(121424610,28);
exponent <= conv_std_logic_vector(505,11);
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(9182752,24);
manlo <= conv_std_logic_vector(52100447,28);
exponent <= conv_std_logic_vector(503,11);
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(2323061,24);
manlo <= conv_std_logic_vector(49429697,28);
exponent <= conv_std_logic_vector(502,11);
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(11329181,24);
manlo <= conv_std_logic_vector(50166358,28);
exponent <= conv_std_logic_vector(500,11);
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(3902315,24);
manlo <= conv_std_logic_vector(102248985,28);
exponent <= conv_std_logic_vector(499,11);
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(13653081,24);
manlo <= conv_std_logic_vector(212703346,28);
exponent <= conv_std_logic_vector(497,11);
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(5612145,24);
manlo <= conv_std_logic_vector(239735388,28);
exponent <= conv_std_logic_vector(496,11);
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(16169127,24);
manlo <= conv_std_logic_vector(205528034,28);
exponent <= conv_std_logic_vector(494,11);
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7463349,24);
manlo <= conv_std_logic_vector(17797346,28);
exponent <= conv_std_logic_vector(493,11);
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(1057995,24);
manlo <= conv_std_logic_vector(16251369,28);
exponent <= conv_std_logic_vector(492,11);
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(9467613,24);
manlo <= conv_std_logic_vector(244949044,28);
exponent <= conv_std_logic_vector(490,11);
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(2532650,24);
manlo <= conv_std_logic_vector(194268012,28);
exponent <= conv_std_logic_vector(489,11);
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(11637595,24);
manlo <= conv_std_logic_vector(246328755,28);
exponent <= conv_std_logic_vector(487,11);
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(4129234,24);
manlo <= conv_std_logic_vector(69393408,28);
exponent <= conv_std_logic_vector(486,11);
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(13986996,24);
manlo <= conv_std_logic_vector(255528468,28);
exponent <= conv_std_logic_vector(484,11);
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(5857826,24);
manlo <= conv_std_logic_vector(251701587,28);
exponent <= conv_std_logic_vector(483,11);
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(16530651,24);
manlo <= conv_std_logic_vector(211310789,28);
exponent <= conv_std_logic_vector(481,11);
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7729343,24);
manlo <= conv_std_logic_vector(154707528,28);
exponent <= conv_std_logic_vector(480,11);
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(1253702,24);
manlo <= conv_std_logic_vector(237283577,28);
exponent <= conv_std_logic_vector(479,11);
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(9755601,24);
manlo <= conv_std_logic_vector(121155884,28);
exponent <= conv_std_logic_vector(477,11);
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(2744540,24);
manlo <= conv_std_logic_vector(30442277,28);
exponent <= conv_std_logic_vector(476,11);
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(11949394,24);
manlo <= conv_std_logic_vector(246622503,28);
exponent <= conv_std_logic_vector(474,11);
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(4358643,24);
manlo <= conv_std_logic_vector(38405425,28);
exponent <= conv_std_logic_vector(473,11);
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(14324576,24);
manlo <= conv_std_logic_vector(53935566,28);
exponent <= conv_std_logic_vector(471,11);
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(6106203,24);
manlo <= conv_std_logic_vector(233166714,28);
exponent <= conv_std_logic_vector(470,11);
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(59463,24);
manlo <= conv_std_logic_vector(114545214,28);
exponent <= conv_std_logic_vector(469,11);
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7998256,24);
manlo <= conv_std_logic_vector(234808364,28);
exponent <= conv_std_logic_vector(467,11);
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(1451558,24);
manlo <= conv_std_logic_vector(62230667,28);
exponent <= conv_std_logic_vector(466,11);
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(10046749,24);
manlo <= conv_std_logic_vector(29683609,28);
exponent <= conv_std_logic_vector(464,11);
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(2958754,24);
manlo <= conv_std_logic_vector(158313814,28);
exponent <= conv_std_logic_vector(463,11);
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(12264615,24);
manlo <= conv_std_logic_vector(87551554,28);
exponent <= conv_std_logic_vector(461,11);
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(4590569,24);
manlo <= conv_std_logic_vector(96025360,28);
exponent <= conv_std_logic_vector(460,11);
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(14665859,24);
manlo <= conv_std_logic_vector(200220878,28);
exponent <= conv_std_logic_vector(458,11);
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(6357306,24);
manlo <= conv_std_logic_vector(71997608,28);
exponent <= conv_std_logic_vector(457,11);
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(244214,24);
manlo <= conv_std_logic_vector(66463607,28);
exponent <= conv_std_logic_vector(456,11);
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(8270120,24);
manlo <= conv_std_logic_vector(265669912,28);
exponent <= conv_std_logic_vector(454,11);
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(1651584,24);
manlo <= conv_std_logic_vector(179638473,28);
exponent <= conv_std_logic_vector(453,11);
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(10341091,24);
manlo <= conv_std_logic_vector(152092530,28);
exponent <= conv_std_logic_vector(451,11);
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(3175319,24);
manlo <= conv_std_logic_vector(178838140,28);
exponent <= conv_std_logic_vector(450,11);
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(12583294,24);
manlo <= conv_std_logic_vector(183442082,28);
exponent <= conv_std_logic_vector(448,11);
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(4825040,24);
manlo <= conv_std_logic_vector(141040370,28);
exponent <= conv_std_logic_vector(447,11);
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(15010888,24);
manlo <= conv_std_logic_vector(62934477,28);
exponent <= conv_std_logic_vector(445,11);
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(6611164,24);
manlo <= conv_std_logic_vector(11633311,28);
exponent <= conv_std_logic_vector(444,11);
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(430992,24);
manlo <= conv_std_logic_vector(96770068,28);
exponent <= conv_std_logic_vector(443,11);
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8544968,24);
manlo <= conv_std_logic_vector(80768180,28);
exponent <= conv_std_logic_vector(441,11);
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(1853806,24);
manlo <= conv_std_logic_vector(5288079,28);
exponent <= conv_std_logic_vector(440,11);
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(10638663,24);
manlo <= conv_std_logic_vector(235213815,28);
exponent <= conv_std_logic_vector(438,11);
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(3394261,24);
manlo <= conv_std_logic_vector(36557939,28);
exponent <= conv_std_logic_vector(437,11);
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(12905470,24);
manlo <= conv_std_logic_vector(253900977,28);
exponent <= conv_std_logic_vector(435,11);
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(5062084,24);
manlo <= conv_std_logic_vector(153603034,28);
exponent <= conv_std_logic_vector(434,11);
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(15359702,24);
manlo <= conv_std_logic_vector(204098933,28);
exponent <= conv_std_logic_vector(432,11);
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(6867807,24);
manlo <= conv_std_logic_vector(115170312,28);
exponent <= conv_std_logic_vector(431,11);
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(619820,24);
manlo <= conv_std_logic_vector(2986045,28);
exponent <= conv_std_logic_vector(430,11);
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8822831,24);
manlo <= conv_std_logic_vector(145826716,28);
exponent <= conv_std_logic_vector(428,11);
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(2058246,24);
manlo <= conv_std_logic_vector(98876593,28);
exponent <= conv_std_logic_vector(427,11);
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(10939501,24);
manlo <= conv_std_logic_vector(129141213,28);
exponent <= conv_std_logic_vector(425,11);
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(3615605,24);
manlo <= conv_std_logic_vector(20427716,28);
exponent <= conv_std_logic_vector(424,11);
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(13231182,24);
manlo <= conv_std_logic_vector(130335695,28);
exponent <= conv_std_logic_vector(422,11);
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(5301729,24);
manlo <= conv_std_logic_vector(196124198,28);
exponent <= conv_std_logic_vector(421,11);
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(15712344,24);
manlo <= conv_std_logic_vector(233039482,28);
exponent <= conv_std_logic_vector(419,11);
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(7127266,24);
manlo <= conv_std_logic_vector(266329205,28);
exponent <= conv_std_logic_vector(418,11);
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(810719,24);
manlo <= conv_std_logic_vector(185030259,28);
exponent <= conv_std_logic_vector(417,11);
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(9103743,24);
manlo <= conv_std_logic_vector(217685905,28);
exponent <= conv_std_logic_vector(415,11);
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(2264930,24);
manlo <= conv_std_logic_vector(17303531,28);
exponent <= conv_std_logic_vector(414,11);
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(11243640,24);
manlo <= conv_std_logic_vector(56799625,28);
exponent <= conv_std_logic_vector(412,11);
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(3839377,24);
manlo <= conv_std_logic_vector(227776580,28);
exponent <= conv_std_logic_vector(411,11);
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(13560468,24);
manlo <= conv_std_logic_vector(25616516,28);
exponent <= conv_std_logic_vector(409,11);
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(5544004,24);
manlo <= conv_std_logic_vector(145740137,28);
exponent <= conv_std_logic_vector(408,11);
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(16068856,24);
manlo <= conv_std_logic_vector(149889545,28);
exponent <= conv_std_logic_vector(406,11);
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(7389573,24);
manlo <= conv_std_logic_vector(170431948,28);
exponent <= conv_std_logic_vector(405,11);
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(1003714,24);
manlo <= conv_std_logic_vector(35324999,28);
exponent <= conv_std_logic_vector(404,11);
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(9387738,24);
manlo <= conv_std_logic_vector(150667400,28);
exponent <= conv_std_logic_vector(402,11);
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(2473881,24);
manlo <= conv_std_logic_vector(194497484,28);
exponent <= conv_std_logic_vector(401,11);
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(11551116,24);
manlo <= conv_std_logic_vector(78219737,28);
exponent <= conv_std_logic_vector(399,11);
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(4065606,24);
manlo <= conv_std_logic_vector(28280174,28);
exponent <= conv_std_logic_vector(398,11);
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(13893366,24);
manlo <= conv_std_logic_vector(266881350,28);
exponent <= conv_std_logic_vector(396,11);
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(5788937,24);
manlo <= conv_std_logic_vector(232096008,28);
exponent <= conv_std_logic_vector(395,11);
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(16429280,24);
manlo <= conv_std_logic_vector(78498076,28);
exponent <= conv_std_logic_vector(393,11);
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(7654758,24);
manlo <= conv_std_logic_vector(160696217,28);
exponent <= conv_std_logic_vector(392,11);
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(1198826,24);
manlo <= conv_std_logic_vector(87006684,28);
exponent <= conv_std_logic_vector(391,11);
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(9674849,24);
manlo <= conv_std_logic_vector(166079254,28);
exponent <= conv_std_logic_vector(389,11);
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(2685126,24);
manlo <= conv_std_logic_vector(63154951,28);
exponent <= conv_std_logic_vector(388,11);
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(11861966,24);
manlo <= conv_std_logic_vector(91696135,28);
exponent <= conv_std_logic_vector(386,11);
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(4294316,24);
manlo <= conv_std_logic_vector(212296424,28);
exponent <= conv_std_logic_vector(385,11);
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(14229918,24);
manlo <= conv_std_logic_vector(223047784,28);
exponent <= conv_std_logic_vector(383,11);
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(6036558,24);
manlo <= conv_std_logic_vector(232962025,28);
exponent <= conv_std_logic_vector(382,11);
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(8221,24);
manlo <= conv_std_logic_vector(133893557,28);
exponent <= conv_std_logic_vector(381,11);
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(7922853,24);
manlo <= conv_std_logic_vector(125492404,28);
exponent <= conv_std_logic_vector(379,11);
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(1396079,24);
manlo <= conv_std_logic_vector(135612572,28);
exponent <= conv_std_logic_vector(378,11);
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9965111,24);
manlo <= conv_std_logic_vector(47990958,28);
exponent <= conv_std_logic_vector(376,11);
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(2898688,24);
manlo <= conv_std_logic_vector(203019642,28);
exponent <= conv_std_logic_vector(375,11);
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(12176227,24);
manlo <= conv_std_logic_vector(103393586,28);
exponent <= conv_std_logic_vector(373,11);
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(4525537,24);
manlo <= conv_std_logic_vector(38936964,28);
exponent <= conv_std_logic_vector(372,11);
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(14570163,24);
manlo <= conv_std_logic_vector(185128905,28);
exponent <= conv_std_logic_vector(370,11);
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(6286897,24);
manlo <= conv_std_logic_vector(12037044,28);
exponent <= conv_std_logic_vector(369,11);
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(192410,24);
manlo <= conv_std_logic_vector(9691196,28);
exponent <= conv_std_logic_vector(368,11);
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(8193890,24);
manlo <= conv_std_logic_vector(46224319,28);
exponent <= conv_std_logic_vector(366,11);
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(1595497,24);
manlo <= conv_std_logic_vector(45130080,28);
exponent <= conv_std_logic_vector(365,11);
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(10258557,24);
manlo <= conv_std_logic_vector(218068546,28);
exponent <= conv_std_logic_vector(363,11);
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(3114594,24);
manlo <= conv_std_logic_vector(194203222,28);
exponent <= conv_std_logic_vector(362,11);
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(12493936,24);
manlo <= conv_std_logic_vector(228530713,28);
exponent <= conv_std_logic_vector(360,11);
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(4759294,24);
manlo <= conv_std_logic_vector(189728046,28);
exponent <= conv_std_logic_vector(359,11);
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(14914142,24);
manlo <= conv_std_logic_vector(25337562,28);
exponent <= conv_std_logic_vector(357,11);
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(6539982,24);
manlo <= conv_std_logic_vector(56762382,28);
exponent <= conv_std_logic_vector(356,11);
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(378619,24);
manlo <= conv_std_logic_vector(186677702,28);
exponent <= conv_std_logic_vector(355,11);
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(8467900,24);
manlo <= conv_std_logic_vector(266785510,28);
exponent <= conv_std_logic_vector(353,11);
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(1797103,24);
manlo <= conv_std_logic_vector(17183357,28);
exponent <= conv_std_logic_vector(352,11);
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(10555224,24);
manlo <= conv_std_logic_vector(126067134,28);
exponent <= conv_std_logic_vector(350,11);
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(3332869,24);
manlo <= conv_std_logic_vector(228611260,28);
exponent <= conv_std_logic_vector(349,11);
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(12815132,24);
manlo <= conv_std_logic_vector(155705738,28);
exponent <= conv_std_logic_vector(347,11);
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(4995617,24);
manlo <= conv_std_logic_vector(85136440,28);
exponent <= conv_std_logic_vector(346,11);
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(15261895,24);
manlo <= conv_std_logic_vector(3688335,28);
exponent <= conv_std_logic_vector(344,11);
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(6795844,24);
manlo <= conv_std_logic_vector(137097782,28);
exponent <= conv_std_logic_vector(343,11);
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(566872,24);
manlo <= conv_std_logic_vector(175764875,28);
exponent <= conv_std_logic_vector(342,11);
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(8744918,24);
manlo <= conv_std_logic_vector(152414052,28);
exponent <= conv_std_logic_vector(340,11);
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(2000921,24);
manlo <= conv_std_logic_vector(54921723,28);
exponent <= conv_std_logic_vector(339,11);
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(10855146,24);
manlo <= conv_std_logic_vector(129996510,28);
exponent <= conv_std_logic_vector(337,11);
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(3553540,24);
manlo <= conv_std_logic_vector(37023540,28);
exponent <= conv_std_logic_vector(336,11);
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(13139852,24);
manlo <= conv_std_logic_vector(221848100,28);
exponent <= conv_std_logic_vector(334,11);
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(5234533,24);
manlo <= conv_std_logic_vector(32943194,28);
exponent <= conv_std_logic_vector(333,11);
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(15613463,24);
manlo <= conv_std_logic_vector(232436445,28);
exponent <= conv_std_logic_vector(331,11);
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(7054514,24);
manlo <= conv_std_logic_vector(111791498,28);
exponent <= conv_std_logic_vector(330,11);
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(757191,24);
manlo <= conv_std_logic_vector(90062360,28);
exponent <= conv_std_logic_vector(329,11);
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(9024975,24);
manlo <= conv_std_logic_vector(238219590,28);
exponent <= conv_std_logic_vector(327,11);
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(2206975,24);
manlo <= conv_std_logic_vector(232222812,28);
exponent <= conv_std_logic_vector(326,11);
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(11158359,24);
manlo <= conv_std_logic_vector(155073518,28);
exponent <= conv_std_logic_vector(324,11);
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(3776631,24);
manlo <= conv_std_logic_vector(232102510,28);
exponent <= conv_std_logic_vector(323,11);
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(13468136,24);
manlo <= conv_std_logic_vector(71264246,28);
exponent <= conv_std_logic_vector(321,11);
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(5476070,24);
manlo <= conv_std_logic_vector(155401688,28);
exponent <= conv_std_logic_vector(320,11);
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(15968890,24);
manlo <= conv_std_logic_vector(140531032,28);
exponent <= conv_std_logic_vector(318,11);
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(7316022,24);
manlo <= conv_std_logic_vector(197790036,28);
exponent <= conv_std_logic_vector(317,11);
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(949598,24);
manlo <= conv_std_logic_vector(108723575,28);
exponent <= conv_std_logic_vector(316,11);
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(9308106,24);
manlo <= conv_std_logic_vector(82754530,28);
exponent <= conv_std_logic_vector(314,11);
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(2415291,24);
manlo <= conv_std_logic_vector(157597766,28);
exponent <= conv_std_logic_vector(313,11);
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(11464899,24);
manlo <= conv_std_logic_vector(231735034,28);
exponent <= conv_std_logic_vector(311,11);
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(4002171,24);
manlo <= conv_std_logic_vector(161749904,28);
exponent <= conv_std_logic_vector(310,11);
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(13800021,24);
manlo <= conv_std_logic_vector(267486845,28);
exponent <= conv_std_logic_vector(308,11);
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(5720258,24);
manlo <= conv_std_logic_vector(121711942,28);
exponent <= conv_std_logic_vector(307,11);
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(16328217,24);
manlo <= conv_std_logic_vector(85566619,28);
exponent <= conv_std_logic_vector(305,11);
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(7580400,24);
manlo <= conv_std_logic_vector(165916765,28);
exponent <= conv_std_logic_vector(304,11);
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(1144116,24);
manlo <= conv_std_logic_vector(209234965,28);
exponent <= conv_std_logic_vector(303,11);
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(9594343,24);
manlo <= conv_std_logic_vector(148128653,28);
exponent <= conv_std_logic_vector(301,11);
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(2625893,24);
manlo <= conv_std_logic_vector(48717694,28);
exponent <= conv_std_logic_vector(300,11);
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(11774803,24);
manlo <= conv_std_logic_vector(228357100,28);
exponent <= conv_std_logic_vector(298,11);
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(4230186,24);
manlo <= conv_std_logic_vector(57439900,28);
exponent <= conv_std_logic_vector(297,11);
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(14135549,24);
manlo <= conv_std_logic_vector(147041206,28);
exponent <= conv_std_logic_vector(295,11);
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(5967125,24);
manlo <= conv_std_logic_vector(222682176,28);
exponent <= conv_std_logic_vector(294,11);
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(16691487,24);
manlo <= conv_std_logic_vector(12959237,28);
exponent <= conv_std_logic_vector(292,11);
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(7847679,24);
manlo <= conv_std_logic_vector(147174066,28);
exponent <= conv_std_logic_vector(291,11);
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(1340769,24);
manlo <= conv_std_logic_vector(168148656,28);
exponent <= conv_std_logic_vector(290,11);
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(9883721,24);
manlo <= conv_std_logic_vector(190474495,28);
exponent <= conv_std_logic_vector(288,11);
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(2838805,24);
manlo <= conv_std_logic_vector(196335986,28);
exponent <= conv_std_logic_vector(287,11);
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(12088108,24);
manlo <= conv_std_logic_vector(120857634,28);
exponent <= conv_std_logic_vector(285,11);
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(4460702,24);
manlo <= conv_std_logic_vector(229771569,28);
exponent <= conv_std_logic_vector(284,11);
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(14474758,24);
manlo <= conv_std_logic_vector(236628147,28);
exponent <= conv_std_logic_vector(282,11);
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(6216702,24);
manlo <= conv_std_logic_vector(29481361,28);
exponent <= conv_std_logic_vector(281,11);
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(140763,24);
manlo <= conv_std_logic_vector(131310533,28);
exponent <= conv_std_logic_vector(280,11);
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(8117891,24);
manlo <= conv_std_logic_vector(96879140,28);
exponent <= conv_std_logic_vector(278,11);
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(1539580,24);
manlo <= conv_std_logic_vector(98694067,28);
exponent <= conv_std_logic_vector(277,11);
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(10176275,24);
manlo <= conv_std_logic_vector(66343668,28);
exponent <= conv_std_logic_vector(275,11);
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(3054054,24);
manlo <= conv_std_logic_vector(159783892,28);
exponent <= conv_std_logic_vector(274,11);
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(12404850,24);
manlo <= conv_std_logic_vector(262311967,28);
exponent <= conv_std_logic_vector(272,11);
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(4693748,24);
manlo <= conv_std_logic_vector(264030756,28);
exponent <= conv_std_logic_vector(271,11);
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(14817690,24);
manlo <= conv_std_logic_vector(106917994,28);
exponent <= conv_std_logic_vector(269,11);
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(6469017,24);
manlo <= conv_std_logic_vector(5191992,28);
exponent <= conv_std_logic_vector(268,11);
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(326406,24);
manlo <= conv_std_logic_vector(114083215,28);
exponent <= conv_std_logic_vector(267,11);
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(8391068,24);
manlo <= conv_std_logic_vector(64117214,28);
exponent <= conv_std_logic_vector(265,11);
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(1740572,24);
manlo <= conv_std_logic_vector(183091279,28);
exponent <= conv_std_logic_vector(264,11);
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(10472039,24);
manlo <= conv_std_logic_vector(2244224,28);
exponent <= conv_std_logic_vector(262,11);
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(3271665,24);
manlo <= conv_std_logic_vector(109958542,28);
exponent <= conv_std_logic_vector(261,11);
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(12725069,24);
manlo <= conv_std_logic_vector(41968573,28);
exponent <= conv_std_logic_vector(259,11);
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(4929352,24);
manlo <= conv_std_logic_vector(94809674,28);
exponent <= conv_std_logic_vector(258,11);
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(15164384,24);
manlo <= conv_std_logic_vector(252890425,28);
exponent <= conv_std_logic_vector(256,11);
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(6724100,24);
manlo <= conv_std_logic_vector(163583158,28);
exponent <= conv_std_logic_vector(255,11);
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(514086,24);
manlo <= conv_std_logic_vector(118679222,28);
exponent <= conv_std_logic_vector(254,11);
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(8667242,24);
manlo <= conv_std_logic_vector(192770478,28);
exponent <= conv_std_logic_vector(252,11);
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(1943770,24);
manlo <= conv_std_logic_vector(136437165,28);
exponent <= conv_std_logic_vector(251,11);
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(10771048,24);
manlo <= conv_std_logic_vector(58883744,28);
exponent <= conv_std_logic_vector(249,11);
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(3491664,24);
manlo <= conv_std_logic_vector(24836209,28);
exponent <= conv_std_logic_vector(248,11);
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(13048801,24);
manlo <= conv_std_logic_vector(33938829,28);
exponent <= conv_std_logic_vector(246,11);
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(5167541,24);
manlo <= conv_std_logic_vector(6894318,28);
exponent <= conv_std_logic_vector(245,11);
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(15514883,24);
manlo <= conv_std_logic_vector(216092120,28);
exponent <= conv_std_logic_vector(243,11);
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(6981983,24);
manlo <= conv_std_logic_vector(70071320,28);
exponent <= conv_std_logic_vector(242,11);
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(703825,24);
manlo <= conv_std_logic_vector(239890498,28);
exponent <= conv_std_logic_vector(241,11);
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(8946447,24);
manlo <= conv_std_logic_vector(185687386,28);
exponent <= conv_std_logic_vector(239,11);
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(2149198,24);
manlo <= conv_std_logic_vector(12777107,28);
exponent <= conv_std_logic_vector(238,11);
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11073338,24);
manlo <= conv_std_logic_vector(132295567,28);
exponent <= conv_std_logic_vector(236,11);
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(3714076,24);
manlo <= conv_std_logic_vector(227171857,28);
exponent <= conv_std_logic_vector(235,11);
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(13376085,24);
manlo <= conv_std_logic_vector(119368169,28);
exponent <= conv_std_logic_vector(233,11);
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(5408343,24);
manlo <= conv_std_logic_vector(99290689,28);
exponent <= conv_std_logic_vector(232,11);
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(15869228,24);
manlo <= conv_std_logic_vector(196569651,28);
exponent <= conv_std_logic_vector(230,11);
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(7242695,24);
manlo <= conv_std_logic_vector(184868911,28);
exponent <= conv_std_logic_vector(229,11);
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(895647,24);
manlo <= conv_std_logic_vector(101480846,28);
exponent <= conv_std_logic_vector(228,11);
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(9228716,24);
manlo <= conv_std_logic_vector(111040654,28);
exponent <= conv_std_logic_vector(226,11);
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(2356879,24);
manlo <= conv_std_logic_vector(205878747,28);
exponent <= conv_std_logic_vector(225,11);
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(11378945,24);
manlo <= conv_std_logic_vector(223412824,28);
exponent <= conv_std_logic_vector(223,11);
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(3938930,24);
manlo <= conv_std_logic_vector(43159582,28);
exponent <= conv_std_logic_vector(222,11);
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(13706961,24);
manlo <= conv_std_logic_vector(24539717,28);
exponent <= conv_std_logic_vector(220,11);
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(5651788,24);
manlo <= conv_std_logic_vector(17696328,28);
exponent <= conv_std_logic_vector(219,11);
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(16227461,24);
manlo <= conv_std_logic_vector(248897772,28);
exponent <= conv_std_logic_vector(217,11);
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(7506268,24);
manlo <= conv_std_logic_vector(253353585,28);
exponent <= conv_std_logic_vector(216,11);
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(1089573,24);
manlo <= conv_std_logic_vector(199085712,28);
exponent <= conv_std_logic_vector(215,11);
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(9514082,24);
manlo <= conv_std_logic_vector(134954983,28);
exponent <= conv_std_logic_vector(213,11);
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(2566840,24);
manlo <= conv_std_logic_vector(107836942,28);
exponent <= conv_std_logic_vector(212,11);
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(11687906,24);
manlo <= conv_std_logic_vector(170784064,28);
exponent <= conv_std_logic_vector(210,11);
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(4166250,24);
manlo <= conv_std_logic_vector(219198631,28);
exponent <= conv_std_logic_vector(209,11);
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(14041467,24);
manlo <= conv_std_logic_vector(127426909,28);
exponent <= conv_std_logic_vector(207,11);
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(5897904,24);
manlo <= conv_std_logic_vector(29159081,28);
exponent <= conv_std_logic_vector(206,11);
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(16589626,24);
manlo <= conv_std_logic_vector(15093248,28);
exponent <= conv_std_logic_vector(204,11);
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(7772734,24);
manlo <= conv_std_logic_vector(112367334,28);
exponent <= conv_std_logic_vector(203,11);
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(1285628,24);
manlo <= conv_std_logic_vector(21894417,28);
exponent <= conv_std_logic_vector(202,11);
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(9802579,24);
manlo <= conv_std_logic_vector(254146435,28);
exponent <= conv_std_logic_vector(200,11);
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(2779104,24);
manlo <= conv_std_logic_vector(257348234,28);
exponent <= conv_std_logic_vector(199,11);
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12000257,24);
manlo <= conv_std_logic_vector(188607876,28);
exponent <= conv_std_logic_vector(197,11);
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(4396065,24);
manlo <= conv_std_logic_vector(238395052,28);
exponent <= conv_std_logic_vector(196,11);
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(14379644,24);
manlo <= conv_std_logic_vector(116776141,28);
exponent <= conv_std_logic_vector(194,11);
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(6146720,24);
manlo <= conv_std_logic_vector(217697734,28);
exponent <= conv_std_logic_vector(193,11);
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(89274,24);
manlo <= conv_std_logic_vector(34078121,28);
exponent <= conv_std_logic_vector(192,11);
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(8042123,24);
manlo <= conv_std_logic_vector(228091050,28);
exponent <= conv_std_logic_vector(190,11);
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(1483833,24);
manlo <= conv_std_logic_vector(200872250,28);
exponent <= conv_std_logic_vector(189,11);
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(10094243,24);
manlo <= conv_std_logic_vector(28573613,28);
exponent <= conv_std_logic_vector(187,11);
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(2993698,24);
manlo <= conv_std_logic_vector(193026703,28);
exponent <= conv_std_logic_vector(186,11);
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12316036,24);
manlo <= conv_std_logic_vector(62602992,28);
exponent <= conv_std_logic_vector(184,11);
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(4628402,24);
manlo <= conv_std_logic_vector(200475490,28);
exponent <= conv_std_logic_vector(183,11);
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(14721532,24);
manlo <= conv_std_logic_vector(67122338,28);
exponent <= conv_std_logic_vector(181,11);
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(6398267,24);
manlo <= conv_std_logic_vector(216803728,28);
exponent <= conv_std_logic_vector(180,11);
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(274352,24);
manlo <= conv_std_logic_vector(17200594,28);
exponent <= conv_std_logic_vector(179,11);
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(8314469,24);
manlo <= conv_std_logic_vector(86446456,28);
exponent <= conv_std_logic_vector(177,11);
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(1684214,24);
manlo <= conv_std_logic_vector(93587914,28);
exponent <= conv_std_logic_vector(176,11);
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(10389106,24);
manlo <= conv_std_logic_vector(193148951,28);
exponent <= conv_std_logic_vector(174,11);
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(3210647,24);
manlo <= conv_std_logic_vector(64824977,28);
exponent <= conv_std_logic_vector(173,11);
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(12635279,24);
manlo <= conv_std_logic_vector(224939505,28);
exponent <= conv_std_logic_vector(171,11);
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(4863289,24);
manlo <= conv_std_logic_vector(17355920,28);
exponent <= conv_std_logic_vector(170,11);
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(15067171,24);
manlo <= conv_std_logic_vector(171641236,28);
exponent <= conv_std_logic_vector(168,11);
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(6652575,24);
manlo <= conv_std_logic_vector(15694991,28);
exponent <= conv_std_logic_vector(167,11);
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(461460,24);
manlo <= conv_std_logic_vector(236949593,28);
exponent <= conv_std_logic_vector(166,11);
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(8589803,24);
manlo <= conv_std_logic_vector(73170085,28);
exponent <= conv_std_logic_vector(164,11);
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(1886793,24);
manlo <= conv_std_logic_vector(200887360,28);
exponent <= conv_std_logic_vector(163,11);
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(10687205,24);
manlo <= conv_std_logic_vector(242930225,28);
exponent <= conv_std_logic_vector(161,11);
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(3429976,24);
manlo <= conv_std_logic_vector(97980458,28);
exponent <= conv_std_logic_vector(160,11);
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(12958026,24);
manlo <= conv_std_logic_vector(144828568,28);
exponent <= conv_std_logic_vector(158,11);
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(5100752,24);
manlo <= conv_std_logic_vector(219332721,28);
exponent <= conv_std_logic_vector(157,11);
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(15416603,24);
manlo <= conv_std_logic_vector(206580322,28);
exponent <= conv_std_logic_vector(155,11);
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(6909672,24);
manlo <= conv_std_logic_vector(228709240,28);
exponent <= conv_std_logic_vector(154,11);
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(650622,24);
manlo <= conv_std_logic_vector(232984198,28);
exponent <= conv_std_logic_vector(153,11);
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(8868158,24);
manlo <= conv_std_logic_vector(132673062,28);
exponent <= conv_std_logic_vector(151,11);
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(2091596,24);
manlo <= conv_std_logic_vector(20173170,28);
exponent <= conv_std_logic_vector(150,11);
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(10988576,24);
manlo <= conv_std_logic_vector(44856082,28);
exponent <= conv_std_logic_vector(148,11);
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(3651712,24);
manlo <= conv_std_logic_vector(56970522,28);
exponent <= conv_std_logic_vector(147,11);
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13284314,24);
manlo <= conv_std_logic_vector(208786223,28);
exponent <= conv_std_logic_vector(145,11);
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(5340822,24);
manlo <= conv_std_logic_vector(76928898,28);
exponent <= conv_std_logic_vector(144,11);
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(15769870,24);
manlo <= conv_std_logic_vector(69445892,28);
exponent <= conv_std_logic_vector(142,11);
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(7169591,24);
manlo <= conv_std_logic_vector(217224162,28);
exponent <= conv_std_logic_vector(141,11);
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(841860,24);
manlo <= conv_std_logic_vector(147476782,28);
exponent <= conv_std_logic_vector(140,11);
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(9149568,24);
manlo <= conv_std_logic_vector(37524984,28);
exponent <= conv_std_logic_vector(138,11);
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(2298645,24);
manlo <= conv_std_logic_vector(193659590,28);
exponent <= conv_std_logic_vector(137,11);
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(11293253,24);
manlo <= conv_std_logic_vector(107316618,28);
exponent <= conv_std_logic_vector(135,11);
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(3875881,24);
manlo <= conv_std_logic_vector(51654059,28);
exponent <= conv_std_logic_vector(134,11);
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13614183,24);
manlo <= conv_std_logic_vector(111249634,28);
exponent <= conv_std_logic_vector(132,11);
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(5583526,24);
manlo <= conv_std_logic_vector(17717412,28);
exponent <= conv_std_logic_vector(131,11);
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(16127013,24);
manlo <= conv_std_logic_vector(48769099,28);
exponent <= conv_std_logic_vector(129,11);
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(7432362,24);
manlo <= conv_std_logic_vector(238120049,28);
exponent <= conv_std_logic_vector(128,11);
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(1035196,24);
manlo <= conv_std_logic_vector(188962402,28);
exponent <= conv_std_logic_vector(127,11);
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(9434065,24);
manlo <= conv_std_logic_vector(194820226,28);
exponent <= conv_std_logic_vector(125,11);
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(2507967,24);
manlo <= conv_std_logic_vector(93233285,28);
exponent <= conv_std_logic_vector(124,11);
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(11601273,24);
manlo <= conv_std_logic_vector(239123672,28);
exponent <= conv_std_logic_vector(122,11);
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(4102510,24);
manlo <= conv_std_logic_vector(1244898,28);
exponent <= conv_std_logic_vector(121,11);
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(13947671,24);
manlo <= conv_std_logic_vector(197996828,28);
exponent <= conv_std_logic_vector(119,11);
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(5828893,24);
manlo <= conv_std_logic_vector(16622593,28);
exponent <= conv_std_logic_vector(118,11);
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(16488075,24);
manlo <= conv_std_logic_vector(20144764,28);
exponent <= conv_std_logic_vector(116,11);
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(7698017,24);
manlo <= conv_std_logic_vector(102592250,28);
exponent <= conv_std_logic_vector(115,11);
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(1230654,24);
manlo <= conv_std_logic_vector(96196092,28);
exponent <= conv_std_logic_vector(114,11);
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(9721685,24);
manlo <= conv_std_logic_vector(36636777,28);
exponent <= conv_std_logic_vector(112,11);
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(2719585,24);
manlo <= conv_std_logic_vector(237160861,28);
exponent <= conv_std_logic_vector(111,11);
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(11912674,24);
manlo <= conv_std_logic_vector(87541902,28);
exponent <= conv_std_logic_vector(109,11);
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(4331625,24);
manlo <= conv_std_logic_vector(172036325,28);
exponent <= conv_std_logic_vector(108,11);
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14284819,24);
manlo <= conv_std_logic_vector(125225503,28);
exponent <= conv_std_logic_vector(106,11);
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(6076952,24);
manlo <= conv_std_logic_vector(133715238,28);
exponent <= conv_std_logic_vector(105,11);
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(37941,24);
manlo <= conv_std_logic_vector(126448851,28);
exponent <= conv_std_logic_vector(104,11);
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(7966586,24);
manlo <= conv_std_logic_vector(250893596,28);
exponent <= conv_std_logic_vector(102,11);
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(1428256,24);
manlo <= conv_std_logic_vector(212630882,28);
exponent <= conv_std_logic_vector(101,11);
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(10012460,24);
manlo <= conv_std_logic_vector(168603206,28);
exponent <= conv_std_logic_vector(99,11);
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(2933526,24);
manlo <= conv_std_logic_vector(143402282,28);
exponent <= conv_std_logic_vector(98,11);
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(12227491,24);
manlo <= conv_std_logic_vector(213203509,28);
exponent <= conv_std_logic_vector(96,11);
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(4563255,24);
manlo <= conv_std_logic_vector(104522224,28);
exponent <= conv_std_logic_vector(95,11);
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14625666,24);
manlo <= conv_std_logic_vector(203000190,28);
exponent <= conv_std_logic_vector(93,11);
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(6327733,24);
manlo <= conv_std_logic_vector(246711469,28);
exponent <= conv_std_logic_vector(92,11);
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(222456,24);
manlo <= conv_std_logic_vector(34640152,28);
exponent <= conv_std_logic_vector(91,11);
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(8238103,24);
manlo <= conv_std_logic_vector(142733230,28);
exponent <= conv_std_logic_vector(89,11);
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(1628027,24);
manlo <= conv_std_logic_vector(144984792,28);
exponent <= conv_std_logic_vector(88,11);
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(10306426,24);
manlo <= conv_std_logic_vector(223510234,28);
exponent <= conv_std_logic_vector(86,11);
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(3149814,24);
manlo <= conv_std_logic_vector(209464872,28);
exponent <= conv_std_logic_vector(85,11);
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(12545763,24);
manlo <= conv_std_logic_vector(212245812,28);
exponent <= conv_std_logic_vector(83,11);
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(4797426,24);
manlo <= conv_std_logic_vector(224882259,28);
exponent <= conv_std_logic_vector(82,11);
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14970254,24);
manlo <= conv_std_logic_vector(54358776,28);
exponent <= conv_std_logic_vector(80,11);
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(6581267,24);
manlo <= conv_std_logic_vector(51917314,28);
exponent <= conv_std_logic_vector(79,11);
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(408995,24);
manlo <= conv_std_logic_vector(130890803,28);
exponent <= conv_std_logic_vector(78,11);
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(8512599,24);
manlo <= conv_std_logic_vector(137347476,28);
exponent <= conv_std_logic_vector(76,11);
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(1829990,24);
manlo <= conv_std_logic_vector(106170554,28);
exponent <= conv_std_logic_vector(75,11);
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(10603618,24);
manlo <= conv_std_logic_vector(204595238,28);
exponent <= conv_std_logic_vector(73,11);
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(3368476,24);
manlo <= conv_std_logic_vector(102605239,28);
exponent <= conv_std_logic_vector(72,11);
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(12867528,24);
manlo <= conv_std_logic_vector(59687307,28);
exponent <= conv_std_logic_vector(70,11);
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(5034167,24);
manlo <= conv_std_logic_vector(235251142,28);
exponent <= conv_std_logic_vector(69,11);
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15318622,24);
manlo <= conv_std_logic_vector(227223140,28);
exponent <= conv_std_logic_vector(67,11);
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(6837582,24);
manlo <= conv_std_logic_vector(138925467,28);
exponent <= conv_std_logic_vector(66,11);
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(597581,24);
manlo <= conv_std_logic_vector(205088968,28);
exponent <= conv_std_logic_vector(65,11);
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(8790107,24);
manlo <= conv_std_logic_vector(152356460,28);
exponent <= conv_std_logic_vector(63,11);
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(2034169,24);
manlo <= conv_std_logic_vector(110749946,28);
exponent <= conv_std_logic_vector(62,11);
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(10904071,24);
manlo <= conv_std_logic_vector(218226183,28);
exponent <= conv_std_logic_vector(60,11);
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(3589537,24);
manlo <= conv_std_logic_vector(102830143,28);
exponent <= conv_std_logic_vector(59,11);
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(13192823,24);
manlo <= conv_std_logic_vector(110639602,28);
exponent <= conv_std_logic_vector(57,11);
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(5273506,24);
manlo <= conv_std_logic_vector(188352155,28);
exponent <= conv_std_logic_vector(56,11);
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15670814,24);
manlo <= conv_std_logic_vector(48227643,28);
exponent <= conv_std_logic_vector(54,11);
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(7096710,24);
manlo <= conv_std_logic_vector(112532514,28);
exponent <= conv_std_logic_vector(53,11);
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(788237,24);
manlo <= conv_std_logic_vector(112565412,28);
exponent <= conv_std_logic_vector(52,11);
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(9070660,24);
manlo <= conv_std_logic_vector(201680253,28);
exponent <= conv_std_logic_vector(50,11);
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(2240588,24);
manlo <= conv_std_logic_vector(244138286,28);
exponent <= conv_std_logic_vector(49,11);
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(11207821,24);
manlo <= conv_std_logic_vector(206597824,28);
exponent <= conv_std_logic_vector(47,11);
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(3813024,24);
manlo <= conv_std_logic_vector(29987310,28);
exponent <= conv_std_logic_vector(46,11);
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(13521688,24);
manlo <= conv_std_logic_vector(27790821,28);
exponent <= conv_std_logic_vector(44,11);
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(5515471,24);
manlo <= conv_std_logic_vector(219963166,28);
exponent <= conv_std_logic_vector(43,11);
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(16026870,24);
manlo <= conv_std_logic_vector(39964772,28);
exponent <= conv_std_logic_vector(41,11);
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(7358681,24);
manlo <= conv_std_logic_vector(204327682,28);
exponent <= conv_std_logic_vector(40,11);
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(980985,24);
manlo <= conv_std_logic_vector(43247066,28);
exponent <= conv_std_logic_vector(39,11);
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(9354292,24);
manlo <= conv_std_logic_vector(128160132,28);
exponent <= conv_std_logic_vector(37,11);
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(2449273,24);
manlo <= conv_std_logic_vector(126511008,28);
exponent <= conv_std_logic_vector(36,11);
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(11514904,24);
manlo <= conv_std_logic_vector(217311246,28);
exponent <= conv_std_logic_vector(34,11);
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(4038963,24);
manlo <= conv_std_logic_vector(49913566,28);
exponent <= conv_std_logic_vector(33,11);
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(13854161,24);
manlo <= conv_std_logic_vector(124821568,28);
exponent <= conv_std_logic_vector(31,11);
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(5760092,24);
manlo <= conv_std_logic_vector(12957085,28);
exponent <= conv_std_logic_vector(30,11);
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16386833,24);
manlo <= conv_std_logic_vector(43278038,28);
exponent <= conv_std_logic_vector(28,11);
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(7623527,24);
manlo <= conv_std_logic_vector(199937734,28);
exponent <= conv_std_logic_vector(27,11);
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(1175847,24);
manlo <= conv_std_logic_vector(253947561,28);
exponent <= conv_std_logic_vector(26,11);
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(9641036,24);
manlo <= conv_std_logic_vector(141497796,28);
exponent <= conv_std_logic_vector(24,11);
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(2660247,24);
manlo <= conv_std_logic_vector(255766959,28);
exponent <= conv_std_logic_vector(23,11);
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(11825357,24);
manlo <= conv_std_logic_vector(136095046,28);
exponent <= conv_std_logic_vector(21,11);
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(4267381,24);
manlo <= conv_std_logic_vector(138414926,28);
exponent <= conv_std_logic_vector(20,11);
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(14190283,24);
manlo <= conv_std_logic_vector(25479908,28);
exponent <= conv_std_logic_vector(18,11);
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(6007396,24);
manlo <= conv_std_logic_vector(140400514,28);
exponent <= conv_std_logic_vector(17,11);
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16750746,24);
manlo <= conv_std_logic_vector(23924155,28);
exponent <= conv_std_logic_vector(15,11);
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(7891279,24);
manlo <= conv_std_logic_vector(245330892,28);
exponent <= conv_std_logic_vector(14,11);
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(1372848,24);
manlo <= conv_std_logic_vector(263794815,28);
exponent <= conv_std_logic_vector(13,11);
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(9930927,24);
manlo <= conv_std_logic_vector(14029030,28);
exponent <= conv_std_logic_vector(11,11);
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(2873537,24);
manlo <= conv_std_logic_vector(129274844,28);
exponent <= conv_std_logic_vector(10,11);
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(12139216,24);
manlo <= conv_std_logic_vector(224845565,28);
exponent <= conv_std_logic_vector(8,11);
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(4498306,24);
manlo <= conv_std_logic_vector(82126943,28);
exponent <= conv_std_logic_vector(7,11);
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(14530093,24);
manlo <= conv_std_logic_vector(7024665,28);
exponent <= conv_std_logic_vector(5,11);
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(6257414,24);
manlo <= conv_std_logic_vector(187437029,28);
exponent <= conv_std_logic_vector(4,11);
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(170718,24);
manlo <= conv_std_logic_vector(36971864,28);
exponent <= conv_std_logic_vector(3,11);
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(8161970,24);
manlo <= conv_std_logic_vector(42518955,28);
exponent <= conv_std_logic_vector(1,11);
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(1572011,24);
manlo <= conv_std_logic_vector(197150320,28);
exponent <= conv_std_logic_vector(0,11);
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/dp_log.vhd | 10 | 10521 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** DP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 DP LN() ***
--*** ***
--*** 11/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 27 + 7*DoubleSpeed + ***
--*** RoundConvert*(1+DoubleSpeed) ***
--*** DoubleSpeed = 0, RoundConvert = 0 : 27 ***
--*** DoubleSpeed = 1, RoundConvert = 0 : 34 ***
--*** DoubleSpeed = 0, RoundConvert = 1 : 28 ***
--*** DoubleSpeed = 1, RoundConvert = 1 : 36 ***
--*** ***
--***************************************************
ENTITY dp_log IS
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_log;
ARCHITECTURE rtl OF dp_log IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
constant coredepth : positive := 26 + 7*doublespeed;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component dp_ln_core
GENERIC (
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (53 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component dp_lnnornd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component dp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component dp_lnrndpipe
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: dp_ln_core
GENERIC MAP (doublespeed=>doublespeed,device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
gra: IF (roundconvert = 0) GENERATE
norndout: dp_lnnornd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END GENERATE;
grb: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
rndout: dp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END GENERATE;
grc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
rndoutpipe: dp_lnrndpipe
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END GENERATE;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_mul54usb.vhd | 10 | 3839 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_MUL54USB.VHD ***
--*** ***
--*** Function: 4/5/6 pipeline stage unsigned ***
--*** 54 bit multiplier (behavioral) ***
--*** ***
--*** 24/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 31/01/08 ML see below ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul54usb IS
GENERIC (
latency : positive := 5; -- 4/5/6
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
prune : integer := 0 -- 0 = pruned multiplier, 1 = normal multiplier
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
END fp_mul54usb;
ARCHITECTURE rtl OF fp_mul54usb IS
constant delaydepth : integer := latency - 2;
type muldelfftype IS ARRAY (delaydepth DOWNTO 1) OF STD_LOGIC_VECTOR (72 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal mulff : STD_LOGIC_VECTOR (108 DOWNTO 1);
signal muldelff : muldelfftype;
signal mulnode : STD_LOGIC_VECTOR (108 DOWNTO 1);
signal mulonenode, multwonode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multhrnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO 72 GENERATE
zerovec(k) <= '0';
END GENERATE;
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
mulff(k) <= '0';
END LOOP;
FOR k IN 1 TO 108 LOOP
mulff(k) <= '0';
END LOOP;
FOR k IN 1 TO delaydepth LOOP
FOR j IN 1 TO 72 LOOP
muldelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
mulff <= mulnode;
muldelff(1)(72 DOWNTO 1) <= mulff(108 DOWNTO 37);
FOR k IN 2 TO delaydepth LOOP
muldelff(k)(72 DOWNTO 1) <= muldelff(k-1)(72 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- full multiplier
gpa: IF (prune = 1) GENERATE
mulonenode <= zerovec(54 DOWNTO 1);
multwonode <= zerovec(54 DOWNTO 1);
multhrnode <= zerovec(72 DOWNTO 1);
mulnode <= aaff * bbff;
END GENERATE;
-- pruned multiplier (18x18 LSB contribution missing)
gpb: IF (prune = 0) GENERATE
mulonenode <= aaff(18 DOWNTO 1) * bbff(54 DOWNTO 19);
multwonode <= bbff(18 DOWNTO 1) * aaff(54 DOWNTO 19);
multhrnode <= aaff(54 DOWNTO 19) * bbff(54 DOWNTO 19);
mulnode <= (multhrnode & zerovec(36 DOWNTO 1)) +
(zerovec(36 DOWNTO 1) & mulonenode & zerovec(18 DOWNTO 1)) +
(zerovec(36 DOWNTO 1) & multwonode & zerovec(18 DOWNTO 1));
END GENERATE;
cc <= muldelff(delaydepth)(72 DOWNTO 1);
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/hcc_lsftcomb36.vhd | 10 | 3820 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftcomb36;
ARCHITECTURE rtl OF hcc_lsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/hcc_lsftcomb36.vhd | 10 | 3820 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial left shift, 36 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_lsftcomb36;
ARCHITECTURE rtl OF hcc_lsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 36 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 36 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 36 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_divrnd.vhd | 10 | 6587 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION DIVIDER - OUTPUT STAGE ***
--*** ***
--*** FP_DIVRND.VHD ***
--*** ***
--*** Function: Output Stage, Rounding ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 2 ***
--***************************************************
ENTITY fp_divrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (24 DOWNTO 1); -- includes roundbit
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END fp_divrnd;
ARCHITECTURE rtl OF fp_divrnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal dividebyzeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal overflowbitff : STD_LOGIC;
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
signal setmanzeroff, setmanmaxff : STD_LOGIC;
signal setexpzeroff, setexpmaxff : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= "00";
nanff <= "00";
dividebyzeroff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
overflowbitff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff(1) <= signin;
signff(2) <= signff(1);
nanff(1) <= nanin;
nanff(2) <= nanff(1);
dividebyzeroff(1) <= dividebyzeroin;
dividebyzeroff(2) <= dividebyzeroff(1);
roundmantissaff <= mantissadiv(manwidth+1 DOWNTO 2) + (zerovec & mantissadiv(1));
overflowbitff <= manoverflow(manwidth+1);
-- nan takes precedence (set max)
-- nan takes precedence (set max)
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND setmanzero) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= exponentdiv(expwidth+2 DOWNTO 1);
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND setexpzero) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & overflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissadiv(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissadiv(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- infinity if exponent >= 255
infinitygen(1) <= exponentnode(1);
gia: FOR k IN 2 TO expwidth GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentnode(k);
END GENERATE;
infinitygen(expwidth+1) <= infinitygen(expwidth) OR
(exponentnode(expwidth+1) AND
NOT(exponentnode(expwidth+2))); -- ;1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentnode(1);
gza: FOR k IN 2 TO expwidth GENERATE
zerogen(k) <= zerogen(k-1) OR exponentnode(k);
END GENERATE;
zerogen(expwidth+1) <= zerogen(expwidth) AND
NOT(exponentnode(expwidth+2)); -- '0' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(infinitygen(expwidth+1)) AND zerogen(expwidth+1) AND NOT(dividebyzeroff(1));
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= zerogen(expwidth+1);
-- set exponent to "11..11" when nan, infinity, or divide by 0
setexpmax <= nanff(1) OR infinitygen(expwidth+1) OR dividebyzeroff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff(expwidth DOWNTO 1);
-----------------------------------------------
nanout <= nanff(2);
invalidout <= nanff(2);
dividebyzeroout <= dividebyzeroff(2);
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/dp_lsftpipe64.vhd | 10 | 4808 |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL **
--*** ***
--*** DP_LSFTPIPE64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift 64 Bits ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_lsftpipe64;
ARCHITECTURE rtl of dp_lsftpipe64 IS
signal levzip, levone, levtwo, levtwoff, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/fp_sqr.vhd | 10 | 9456 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** FP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 FP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 28 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY fp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END fp_sqr;
ARCHITECTURE rtl OF fp_sqr IS
constant manwidth : positive := 23;
constant expwidth : positive := 8;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 25
-- top latency = core + 1 (input) + 2 (output) = 28
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/hcc_alufp1x_sv.vhd | 10 | 12097 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1X.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add NAN support ***
--*** 04/05/10 - optimized structure ***
--*** 15/10/10 - bug in shiftcheckbit ***
--*** ***
--***************************************************
ENTITY hcc_alufp1x IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_alufp1x;
ARCHITECTURE rtl OF hcc_alufp1x IS
type exponentbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
-- input registers and nodes
signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal aananff, bbnanff : STD_LOGIC;
signal addsubff : STD_LOGIC;
signal aanode, bbnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatnode, aazipnode, bbsatnode, bbzipnode : STD_LOGIC;
signal aanannode, bbnannode : STD_LOGIC;
signal addsubnode : STD_LOGIC;
signal addsubctlff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal mantissaleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissarightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissaleftdelayff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal exponentshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentbaseff : exponentbasefftype;
signal invertleftff, invertrightff : STD_LOGIC_VECTOR (2+shiftspeed DOWNTO 1);
signal shiftcheckff, shiftcheckdelayff : STD_LOGIC;
signal aluleftff, alurightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal mantissaleftnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zeroaluright : STD_LOGIC;
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal alucarrybitnode : STD_LOGIC;
signal subexponentone, subexponenttwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal shiftcheck : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal shiftcheckbit : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pin: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
aananff <= '0';
bbsatff <= '0';
bbzipff <= '0';
bbnanff <= '0';
addsubff <= addsub_resetval;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
aananff <= aanan;
bbnanff <= bbnan;
addsubff <= addsub;
END IF;
END IF;
END PROCESS;
gina: IF (outputpipe = 1) GENERATE
aanode <= aaff;
bbnode <= bbff;
aasatnode <= aasatff;
bbsatnode <= bbsatff;
aazipnode <= aazipff;
bbzipnode <= bbzipff;
aanannode <= aananff;
bbnannode <= bbnanff;
addsubnode <= addsubff;
END GENERATE;
ginb: IF (outputpipe = 0) GENERATE
aanode <= aa;
bbnode <= bb;
aasatnode <= aasat;
bbsatnode <= bbsat;
aazipnode <= aazip;
bbzipnode <= bbzip;
aanannode <= aanan;
bbnannode <= bbnan;
addsubnode <= addsub;
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3+shiftspeed LOOP
addsubctlff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= '0';
mantissarightff(k) <= '0';
mantissaleftdelayff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
exponentbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2+shiftspeed LOOP
invertleftff(k) <= '0';
invertrightff(k) <= '0';
END LOOP;
shiftcheckff <= '0';
shiftcheckdelayff <= '0';
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
alurightff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
ccnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
addsubctlff(1) <= addsubnode;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubctlff(k) <= addsubctlff(k-1);
END LOOP;
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= (aanode(k+10) AND NOT(switch)) OR (bbnode(k+10) AND switch);
mantissarightff(k) <= (bbnode(k+10) AND NOT(switch)) OR (aanode(k+10) AND switch);
END LOOP;
-- only use if shiftspeed = 1
mantissaleftdelayff <= mantissaleftff;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= (subexponentone(k) AND NOT(switch)) OR (subexponenttwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentbaseff(1)(k) <= (aanode(k) AND NOT(switch)) OR (bbnode(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
exponentbaseff(k)(10 DOWNTO 1) <= exponentbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff(1) <= addsubnode AND switch;
invertrightff(1) <= addsubnode AND NOT(switch);
FOR k IN 2 TO 2+shiftspeed LOOP
invertleftff(k) <= invertleftff(k-1);
invertrightff(k) <= invertrightff(k-1);
END LOOP;
shiftcheckff <= shiftcheckbit;
shiftcheckdelayff <= shiftcheckff;
aluleftff <= mantissaleftnode;
alurightff <= shiftbusnode;
aluff <= aluleftnode + alurightnode + alucarrybitnode;
ccsatff(1) <= aasatnode OR bbsatnode;
cczipff(1) <= aazipnode AND bbzipnode;
-- add/sub infinity is invalid OP, NAN out
ccnanff(1) <= aanannode OR bbnannode OR aasatnode OR bbsatnode;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
ccnanff(k) <= ccnanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gmsa: IF (shiftspeed = 0) GENERATE
mantissaleftnode <= mantissaleftff;
zeroaluright <= shiftcheckff;
END GENERATE;
gmsb: IF (shiftspeed = 1) GENERATE
mantissaleftnode <= mantissaleftdelayff;
zeroaluright <= shiftcheckdelayff;
END GENERATE;
gma: FOR k IN 1 TO mantissa GENERATE
aluleftnode(k) <= aluleftff(k) XOR invertleftff(2+shiftspeed);
alurightnode(k) <= (alurightff(k) XOR invertrightff(2+shiftspeed)) AND NOT(zeroaluright);
END GENERATE;
alucarrybitnode <= addsubctlff(2+shiftspeed);
subexponentone <= aanode(10 DOWNTO 1) - bbnode(10 DOWNTO 1);
subexponenttwo <= bbnode(10 DOWNTO 1) - aanode(10 DOWNTO 1);
switch <= subexponentone(10);
gsa: IF (mantissa = 32) GENERATE
-- 31 ok, 32 not
shiftcheck <= "0000000000";
-- if '1', then zero right bus
-- 15/10/10 - was down to exponentshiftff(5) - zeroed any shift >= 16. Old design was ok because it
-- used shiftcheck subtract 31, not caught because unlikely to cause differences for small designs
shiftcheckbit <= exponentshiftff(10) OR exponentshiftff(9) OR exponentshiftff(8) OR
exponentshiftff(7) OR exponentshiftff(6);
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
-- 35 ok, 36 not
shiftcheck <= exponentshiftff - "0000100100";
-- if '1', then zero right bus
shiftcheckbit <= NOT(shiftcheck(10));
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & exponentbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
ccnan <= ccnanff(3+shiftspeed);
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= exponentbaseff(3+shiftspeed)(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= aluff;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/dp_explut20.vhd | 10 | 142711 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT20.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut20 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1)
);
END dp_explut20;
ARCHITECTURE rtl OF dp_explut20 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16,24);
manlo <= conv_std_logic_vector(2048,28);
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32,24);
manlo <= conv_std_logic_vector(8192,28);
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(48,24);
manlo <= conv_std_logic_vector(18432,28);
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(64,24);
manlo <= conv_std_logic_vector(32768,28);
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(80,24);
manlo <= conv_std_logic_vector(51200,28);
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(96,24);
manlo <= conv_std_logic_vector(73728,28);
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(112,24);
manlo <= conv_std_logic_vector(100352,28);
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(128,24);
manlo <= conv_std_logic_vector(131072,28);
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(144,24);
manlo <= conv_std_logic_vector(165888,28);
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(160,24);
manlo <= conv_std_logic_vector(204801,28);
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(176,24);
manlo <= conv_std_logic_vector(247809,28);
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(192,24);
manlo <= conv_std_logic_vector(294913,28);
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(208,24);
manlo <= conv_std_logic_vector(346113,28);
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(224,24);
manlo <= conv_std_logic_vector(401410,28);
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(240,24);
manlo <= conv_std_logic_vector(460802,28);
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(256,24);
manlo <= conv_std_logic_vector(524291,28);
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(272,24);
manlo <= conv_std_logic_vector(591875,28);
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(288,24);
manlo <= conv_std_logic_vector(663556,28);
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(304,24);
manlo <= conv_std_logic_vector(739332,28);
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(320,24);
manlo <= conv_std_logic_vector(819205,28);
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(336,24);
manlo <= conv_std_logic_vector(903174,28);
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(352,24);
manlo <= conv_std_logic_vector(991239,28);
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(368,24);
manlo <= conv_std_logic_vector(1083400,28);
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(384,24);
manlo <= conv_std_logic_vector(1179657,28);
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(400,24);
manlo <= conv_std_logic_vector(1280010,28);
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(416,24);
manlo <= conv_std_logic_vector(1384459,28);
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(432,24);
manlo <= conv_std_logic_vector(1493005,28);
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(448,24);
manlo <= conv_std_logic_vector(1605646,28);
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(464,24);
manlo <= conv_std_logic_vector(1722384,28);
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(480,24);
manlo <= conv_std_logic_vector(1843218,28);
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(496,24);
manlo <= conv_std_logic_vector(1968147,28);
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(512,24);
manlo <= conv_std_logic_vector(2097173,28);
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(528,24);
manlo <= conv_std_logic_vector(2230295,28);
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(544,24);
manlo <= conv_std_logic_vector(2367514,28);
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(560,24);
manlo <= conv_std_logic_vector(2508828,28);
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(576,24);
manlo <= conv_std_logic_vector(2654238,28);
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(592,24);
manlo <= conv_std_logic_vector(2803745,28);
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(608,24);
manlo <= conv_std_logic_vector(2957348,28);
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(624,24);
manlo <= conv_std_logic_vector(3115047,28);
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(640,24);
manlo <= conv_std_logic_vector(3276842,28);
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(656,24);
manlo <= conv_std_logic_vector(3442733,28);
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(672,24);
manlo <= conv_std_logic_vector(3612720,28);
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(688,24);
manlo <= conv_std_logic_vector(3786804,28);
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(704,24);
manlo <= conv_std_logic_vector(3964983,28);
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(720,24);
manlo <= conv_std_logic_vector(4147259,28);
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(736,24);
manlo <= conv_std_logic_vector(4333631,28);
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(752,24);
manlo <= conv_std_logic_vector(4524100,28);
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(768,24);
manlo <= conv_std_logic_vector(4718664,28);
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(784,24);
manlo <= conv_std_logic_vector(4917325,28);
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(800,24);
manlo <= conv_std_logic_vector(5120081,28);
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(816,24);
manlo <= conv_std_logic_vector(5326934,28);
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(832,24);
manlo <= conv_std_logic_vector(5537884,28);
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(848,24);
manlo <= conv_std_logic_vector(5752929,28);
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(864,24);
manlo <= conv_std_logic_vector(5972071,28);
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(880,24);
manlo <= conv_std_logic_vector(6195308,28);
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(896,24);
manlo <= conv_std_logic_vector(6422642,28);
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(912,24);
manlo <= conv_std_logic_vector(6654073,28);
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(928,24);
manlo <= conv_std_logic_vector(6889599,28);
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(944,24);
manlo <= conv_std_logic_vector(7129222,28);
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(960,24);
manlo <= conv_std_logic_vector(7372941,28);
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(976,24);
manlo <= conv_std_logic_vector(7620756,28);
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(992,24);
manlo <= conv_std_logic_vector(7872667,28);
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1008,24);
manlo <= conv_std_logic_vector(8128675,28);
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1024,24);
manlo <= conv_std_logic_vector(8388779,28);
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1040,24);
manlo <= conv_std_logic_vector(8652979,28);
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1056,24);
manlo <= conv_std_logic_vector(8921275,28);
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1072,24);
manlo <= conv_std_logic_vector(9193668,28);
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1088,24);
manlo <= conv_std_logic_vector(9470157,28);
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1104,24);
manlo <= conv_std_logic_vector(9750742,28);
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1120,24);
manlo <= conv_std_logic_vector(10035423,28);
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1136,24);
manlo <= conv_std_logic_vector(10324201,28);
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1152,24);
manlo <= conv_std_logic_vector(10617075,28);
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1168,24);
manlo <= conv_std_logic_vector(10914045,28);
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1184,24);
manlo <= conv_std_logic_vector(11215112,28);
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1200,24);
manlo <= conv_std_logic_vector(11520275,28);
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1216,24);
manlo <= conv_std_logic_vector(11829534,28);
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1232,24);
manlo <= conv_std_logic_vector(12142889,28);
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1248,24);
manlo <= conv_std_logic_vector(12460341,28);
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1264,24);
manlo <= conv_std_logic_vector(12781889,28);
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1280,24);
manlo <= conv_std_logic_vector(13107533,28);
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1296,24);
manlo <= conv_std_logic_vector(13437274,28);
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1312,24);
manlo <= conv_std_logic_vector(13771111,28);
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1328,24);
manlo <= conv_std_logic_vector(14109044,28);
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1344,24);
manlo <= conv_std_logic_vector(14451074,28);
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1360,24);
manlo <= conv_std_logic_vector(14797200,28);
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1376,24);
manlo <= conv_std_logic_vector(15147422,28);
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1392,24);
manlo <= conv_std_logic_vector(15501741,28);
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1408,24);
manlo <= conv_std_logic_vector(15860156,28);
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1424,24);
manlo <= conv_std_logic_vector(16222667,28);
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1440,24);
manlo <= conv_std_logic_vector(16589275,28);
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1456,24);
manlo <= conv_std_logic_vector(16959979,28);
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1472,24);
manlo <= conv_std_logic_vector(17334779,28);
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1488,24);
manlo <= conv_std_logic_vector(17713676,28);
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1504,24);
manlo <= conv_std_logic_vector(18096669,28);
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1520,24);
manlo <= conv_std_logic_vector(18483758,28);
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1536,24);
manlo <= conv_std_logic_vector(18874944,28);
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1552,24);
manlo <= conv_std_logic_vector(19270226,28);
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1568,24);
manlo <= conv_std_logic_vector(19669605,28);
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1584,24);
manlo <= conv_std_logic_vector(20073080,28);
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1600,24);
manlo <= conv_std_logic_vector(20480651,28);
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1616,24);
manlo <= conv_std_logic_vector(20892319,28);
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1632,24);
manlo <= conv_std_logic_vector(21308083,28);
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1648,24);
manlo <= conv_std_logic_vector(21727943,28);
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1664,24);
manlo <= conv_std_logic_vector(22151900,28);
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1680,24);
manlo <= conv_std_logic_vector(22579954,28);
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1696,24);
manlo <= conv_std_logic_vector(23012103,28);
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1712,24);
manlo <= conv_std_logic_vector(23448350,28);
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1728,24);
manlo <= conv_std_logic_vector(23888692,28);
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1744,24);
manlo <= conv_std_logic_vector(24333131,28);
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1760,24);
manlo <= conv_std_logic_vector(24781667,28);
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1776,24);
manlo <= conv_std_logic_vector(25234298,28);
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1792,24);
manlo <= conv_std_logic_vector(25691027,28);
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1808,24);
manlo <= conv_std_logic_vector(26151851,28);
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1824,24);
manlo <= conv_std_logic_vector(26616773,28);
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1840,24);
manlo <= conv_std_logic_vector(27085790,28);
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(1856,24);
manlo <= conv_std_logic_vector(27558904,28);
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(1872,24);
manlo <= conv_std_logic_vector(28036115,28);
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(1888,24);
manlo <= conv_std_logic_vector(28517422,28);
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(1904,24);
manlo <= conv_std_logic_vector(29002825,28);
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(1920,24);
manlo <= conv_std_logic_vector(29492325,28);
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(1936,24);
manlo <= conv_std_logic_vector(29985921,28);
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(1952,24);
manlo <= conv_std_logic_vector(30483614,28);
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(1968,24);
manlo <= conv_std_logic_vector(30985404,28);
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(1984,24);
manlo <= conv_std_logic_vector(31491289,28);
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2000,24);
manlo <= conv_std_logic_vector(32001272,28);
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2016,24);
manlo <= conv_std_logic_vector(32515350,28);
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2032,24);
manlo <= conv_std_logic_vector(33033526,28);
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2048,24);
manlo <= conv_std_logic_vector(33555797,28);
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2064,24);
manlo <= conv_std_logic_vector(34082166,28);
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2080,24);
manlo <= conv_std_logic_vector(34612630,28);
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2096,24);
manlo <= conv_std_logic_vector(35147192,28);
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2112,24);
manlo <= conv_std_logic_vector(35685849,28);
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2128,24);
manlo <= conv_std_logic_vector(36228604,28);
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2144,24);
manlo <= conv_std_logic_vector(36775455,28);
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2160,24);
manlo <= conv_std_logic_vector(37326402,28);
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2176,24);
manlo <= conv_std_logic_vector(37881446,28);
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2192,24);
manlo <= conv_std_logic_vector(38440586,28);
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2208,24);
manlo <= conv_std_logic_vector(39003823,28);
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2224,24);
manlo <= conv_std_logic_vector(39571157,28);
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2240,24);
manlo <= conv_std_logic_vector(40142587,28);
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2256,24);
manlo <= conv_std_logic_vector(40718113,28);
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2272,24);
manlo <= conv_std_logic_vector(41297736,28);
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2288,24);
manlo <= conv_std_logic_vector(41881456,28);
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2304,24);
manlo <= conv_std_logic_vector(42469272,28);
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2320,24);
manlo <= conv_std_logic_vector(43061185,28);
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2336,24);
manlo <= conv_std_logic_vector(43657194,28);
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2352,24);
manlo <= conv_std_logic_vector(44257300,28);
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2368,24);
manlo <= conv_std_logic_vector(44861503,28);
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2384,24);
manlo <= conv_std_logic_vector(45469802,28);
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2400,24);
manlo <= conv_std_logic_vector(46082197,28);
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2416,24);
manlo <= conv_std_logic_vector(46698690,28);
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2432,24);
manlo <= conv_std_logic_vector(47319278,28);
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2448,24);
manlo <= conv_std_logic_vector(47943964,28);
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2464,24);
manlo <= conv_std_logic_vector(48572746,28);
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2480,24);
manlo <= conv_std_logic_vector(49205624,28);
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2496,24);
manlo <= conv_std_logic_vector(49842600,28);
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2512,24);
manlo <= conv_std_logic_vector(50483672,28);
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2528,24);
manlo <= conv_std_logic_vector(51128840,28);
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2544,24);
manlo <= conv_std_logic_vector(51778105,28);
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2560,24);
manlo <= conv_std_logic_vector(52431467,28);
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2576,24);
manlo <= conv_std_logic_vector(53088925,28);
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2592,24);
manlo <= conv_std_logic_vector(53750480,28);
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2608,24);
manlo <= conv_std_logic_vector(54416132,28);
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2624,24);
manlo <= conv_std_logic_vector(55085880,28);
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2640,24);
manlo <= conv_std_logic_vector(55759725,28);
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2656,24);
manlo <= conv_std_logic_vector(56437666,28);
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2672,24);
manlo <= conv_std_logic_vector(57119704,28);
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2688,24);
manlo <= conv_std_logic_vector(57805839,28);
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(2704,24);
manlo <= conv_std_logic_vector(58496071,28);
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(2720,24);
manlo <= conv_std_logic_vector(59190399,28);
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(2736,24);
manlo <= conv_std_logic_vector(59888823,28);
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(2752,24);
manlo <= conv_std_logic_vector(60591345,28);
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(2768,24);
manlo <= conv_std_logic_vector(61297963,28);
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(2784,24);
manlo <= conv_std_logic_vector(62008678,28);
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(2800,24);
manlo <= conv_std_logic_vector(62723489,28);
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(2816,24);
manlo <= conv_std_logic_vector(63442397,28);
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(2832,24);
manlo <= conv_std_logic_vector(64165402,28);
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(2848,24);
manlo <= conv_std_logic_vector(64892504,28);
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(2864,24);
manlo <= conv_std_logic_vector(65623702,28);
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(2880,24);
manlo <= conv_std_logic_vector(66358997,28);
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(2896,24);
manlo <= conv_std_logic_vector(67098389,28);
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(2912,24);
manlo <= conv_std_logic_vector(67841877,28);
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(2928,24);
manlo <= conv_std_logic_vector(68589462,28);
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(2944,24);
manlo <= conv_std_logic_vector(69341144,28);
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(2960,24);
manlo <= conv_std_logic_vector(70096922,28);
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(2976,24);
manlo <= conv_std_logic_vector(70856798,28);
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(2992,24);
manlo <= conv_std_logic_vector(71620769,28);
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3008,24);
manlo <= conv_std_logic_vector(72388838,28);
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3024,24);
manlo <= conv_std_logic_vector(73161004,28);
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3040,24);
manlo <= conv_std_logic_vector(73937266,28);
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3056,24);
manlo <= conv_std_logic_vector(74717625,28);
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3072,24);
manlo <= conv_std_logic_vector(75502080,28);
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3088,24);
manlo <= conv_std_logic_vector(76290633,28);
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3104,24);
manlo <= conv_std_logic_vector(77083282,28);
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3120,24);
manlo <= conv_std_logic_vector(77880028,28);
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3136,24);
manlo <= conv_std_logic_vector(78680870,28);
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3152,24);
manlo <= conv_std_logic_vector(79485810,28);
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3168,24);
manlo <= conv_std_logic_vector(80294846,28);
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3184,24);
manlo <= conv_std_logic_vector(81107979,28);
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3200,24);
manlo <= conv_std_logic_vector(81925209,28);
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3216,24);
manlo <= conv_std_logic_vector(82746535,28);
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3232,24);
manlo <= conv_std_logic_vector(83571958,28);
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3248,24);
manlo <= conv_std_logic_vector(84401479,28);
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3264,24);
manlo <= conv_std_logic_vector(85235095,28);
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3280,24);
manlo <= conv_std_logic_vector(86072809,28);
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3296,24);
manlo <= conv_std_logic_vector(86914620,28);
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3312,24);
manlo <= conv_std_logic_vector(87760527,28);
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3328,24);
manlo <= conv_std_logic_vector(88610531,28);
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3344,24);
manlo <= conv_std_logic_vector(89464632,28);
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3360,24);
manlo <= conv_std_logic_vector(90322830,28);
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3376,24);
manlo <= conv_std_logic_vector(91185124,28);
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3392,24);
manlo <= conv_std_logic_vector(92051516,28);
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3408,24);
manlo <= conv_std_logic_vector(92922004,28);
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3424,24);
manlo <= conv_std_logic_vector(93796589,28);
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3440,24);
manlo <= conv_std_logic_vector(94675271,28);
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3456,24);
manlo <= conv_std_logic_vector(95558049,28);
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3472,24);
manlo <= conv_std_logic_vector(96444925,28);
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3488,24);
manlo <= conv_std_logic_vector(97335897,28);
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(3504,24);
manlo <= conv_std_logic_vector(98230967,28);
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(3520,24);
manlo <= conv_std_logic_vector(99130133,28);
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(3536,24);
manlo <= conv_std_logic_vector(100033396,28);
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(3552,24);
manlo <= conv_std_logic_vector(100940755,28);
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(3568,24);
manlo <= conv_std_logic_vector(101852212,28);
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(3584,24);
manlo <= conv_std_logic_vector(102767766,28);
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(3600,24);
manlo <= conv_std_logic_vector(103687416,28);
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(3616,24);
manlo <= conv_std_logic_vector(104611163,28);
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(3632,24);
manlo <= conv_std_logic_vector(105539008,28);
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(3648,24);
manlo <= conv_std_logic_vector(106470949,28);
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(3664,24);
manlo <= conv_std_logic_vector(107406987,28);
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(3680,24);
manlo <= conv_std_logic_vector(108347122,28);
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(3696,24);
manlo <= conv_std_logic_vector(109291353,28);
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(3712,24);
manlo <= conv_std_logic_vector(110239682,28);
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(3728,24);
manlo <= conv_std_logic_vector(111192108,28);
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(3744,24);
manlo <= conv_std_logic_vector(112148630,28);
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(3760,24);
manlo <= conv_std_logic_vector(113109250,28);
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(3776,24);
manlo <= conv_std_logic_vector(114073966,28);
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(3792,24);
manlo <= conv_std_logic_vector(115042779,28);
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(3808,24);
manlo <= conv_std_logic_vector(116015689,28);
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(3824,24);
manlo <= conv_std_logic_vector(116992696,28);
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(3840,24);
manlo <= conv_std_logic_vector(117973801,28);
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(3856,24);
manlo <= conv_std_logic_vector(118959001,28);
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(3872,24);
manlo <= conv_std_logic_vector(119948299,28);
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(3888,24);
manlo <= conv_std_logic_vector(120941694,28);
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(3904,24);
manlo <= conv_std_logic_vector(121939186,28);
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(3920,24);
manlo <= conv_std_logic_vector(122940775,28);
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(3936,24);
manlo <= conv_std_logic_vector(123946461,28);
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(3952,24);
manlo <= conv_std_logic_vector(124956243,28);
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(3968,24);
manlo <= conv_std_logic_vector(125970123,28);
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(3984,24);
manlo <= conv_std_logic_vector(126988100,28);
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4000,24);
manlo <= conv_std_logic_vector(128010173,28);
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4016,24);
manlo <= conv_std_logic_vector(129036344,28);
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4032,24);
manlo <= conv_std_logic_vector(130066611,28);
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4048,24);
manlo <= conv_std_logic_vector(131100976,28);
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4064,24);
manlo <= conv_std_logic_vector(132139437,28);
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4080,24);
manlo <= conv_std_logic_vector(133181996,28);
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4096,24);
manlo <= conv_std_logic_vector(134228651,28);
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4112,24);
manlo <= conv_std_logic_vector(135279404,28);
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4128,24);
manlo <= conv_std_logic_vector(136334253,28);
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4144,24);
manlo <= conv_std_logic_vector(137393200,28);
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4160,24);
manlo <= conv_std_logic_vector(138456243,28);
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4176,24);
manlo <= conv_std_logic_vector(139523384,28);
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4192,24);
manlo <= conv_std_logic_vector(140594622,28);
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4208,24);
manlo <= conv_std_logic_vector(141669956,28);
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4224,24);
manlo <= conv_std_logic_vector(142749388,28);
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4240,24);
manlo <= conv_std_logic_vector(143832916,28);
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4256,24);
manlo <= conv_std_logic_vector(144920542,28);
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4272,24);
manlo <= conv_std_logic_vector(146012265,28);
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(4288,24);
manlo <= conv_std_logic_vector(147108085,28);
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(4304,24);
manlo <= conv_std_logic_vector(148208001,28);
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(4320,24);
manlo <= conv_std_logic_vector(149312015,28);
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(4336,24);
manlo <= conv_std_logic_vector(150420126,28);
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(4352,24);
manlo <= conv_std_logic_vector(151532334,28);
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(4368,24);
manlo <= conv_std_logic_vector(152648639,28);
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(4384,24);
manlo <= conv_std_logic_vector(153769041,28);
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(4400,24);
manlo <= conv_std_logic_vector(154893541,28);
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(4416,24);
manlo <= conv_std_logic_vector(156022137,28);
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(4432,24);
manlo <= conv_std_logic_vector(157154830,28);
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(4448,24);
manlo <= conv_std_logic_vector(158291621,28);
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(4464,24);
manlo <= conv_std_logic_vector(159432508,28);
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(4480,24);
manlo <= conv_std_logic_vector(160577493,28);
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(4496,24);
manlo <= conv_std_logic_vector(161726574,28);
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(4512,24);
manlo <= conv_std_logic_vector(162879753,28);
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(4528,24);
manlo <= conv_std_logic_vector(164037029,28);
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(4544,24);
manlo <= conv_std_logic_vector(165198402,28);
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(4560,24);
manlo <= conv_std_logic_vector(166363872,28);
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(4576,24);
manlo <= conv_std_logic_vector(167533439,28);
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(4592,24);
manlo <= conv_std_logic_vector(168707104,28);
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(4608,24);
manlo <= conv_std_logic_vector(169884865,28);
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(4624,24);
manlo <= conv_std_logic_vector(171066724,28);
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(4640,24);
manlo <= conv_std_logic_vector(172252679,28);
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(4656,24);
manlo <= conv_std_logic_vector(173442732,28);
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(4672,24);
manlo <= conv_std_logic_vector(174636882,28);
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(4688,24);
manlo <= conv_std_logic_vector(175835129,28);
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(4704,24);
manlo <= conv_std_logic_vector(177037474,28);
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(4720,24);
manlo <= conv_std_logic_vector(178243915,28);
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(4736,24);
manlo <= conv_std_logic_vector(179454454,28);
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(4752,24);
manlo <= conv_std_logic_vector(180669089,28);
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(4768,24);
manlo <= conv_std_logic_vector(181887822,28);
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(4784,24);
manlo <= conv_std_logic_vector(183110652,28);
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(4800,24);
manlo <= conv_std_logic_vector(184337579,28);
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(4816,24);
manlo <= conv_std_logic_vector(185568604,28);
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(4832,24);
manlo <= conv_std_logic_vector(186803725,28);
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(4848,24);
manlo <= conv_std_logic_vector(188042944,28);
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(4864,24);
manlo <= conv_std_logic_vector(189286260,28);
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(4880,24);
manlo <= conv_std_logic_vector(190533673,28);
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(4896,24);
manlo <= conv_std_logic_vector(191785183,28);
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(4912,24);
manlo <= conv_std_logic_vector(193040791,28);
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(4928,24);
manlo <= conv_std_logic_vector(194300496,28);
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(4944,24);
manlo <= conv_std_logic_vector(195564298,28);
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(4960,24);
manlo <= conv_std_logic_vector(196832197,28);
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(4976,24);
manlo <= conv_std_logic_vector(198104193,28);
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(4992,24);
manlo <= conv_std_logic_vector(199380286,28);
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5008,24);
manlo <= conv_std_logic_vector(200660477,28);
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(5024,24);
manlo <= conv_std_logic_vector(201944765,28);
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(5040,24);
manlo <= conv_std_logic_vector(203233150,28);
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(5056,24);
manlo <= conv_std_logic_vector(204525633,28);
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(5072,24);
manlo <= conv_std_logic_vector(205822213,28);
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(5088,24);
manlo <= conv_std_logic_vector(207122889,28);
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(5104,24);
manlo <= conv_std_logic_vector(208427664,28);
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(5120,24);
manlo <= conv_std_logic_vector(209736535,28);
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(5136,24);
manlo <= conv_std_logic_vector(211049504,28);
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(5152,24);
manlo <= conv_std_logic_vector(212366570,28);
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(5168,24);
manlo <= conv_std_logic_vector(213687733,28);
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(5184,24);
manlo <= conv_std_logic_vector(215012993,28);
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(5200,24);
manlo <= conv_std_logic_vector(216342351,28);
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(5216,24);
manlo <= conv_std_logic_vector(217675806,28);
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(5232,24);
manlo <= conv_std_logic_vector(219013358,28);
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(5248,24);
manlo <= conv_std_logic_vector(220355007,28);
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(5264,24);
manlo <= conv_std_logic_vector(221700754,28);
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(5280,24);
manlo <= conv_std_logic_vector(223050598,28);
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(5296,24);
manlo <= conv_std_logic_vector(224404540,28);
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(5312,24);
manlo <= conv_std_logic_vector(225762578,28);
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(5328,24);
manlo <= conv_std_logic_vector(227124714,28);
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(5344,24);
manlo <= conv_std_logic_vector(228490948,28);
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(5360,24);
manlo <= conv_std_logic_vector(229861278,28);
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(5376,24);
manlo <= conv_std_logic_vector(231235706,28);
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(5392,24);
manlo <= conv_std_logic_vector(232614231,28);
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(5408,24);
manlo <= conv_std_logic_vector(233996854,28);
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(5424,24);
manlo <= conv_std_logic_vector(235383573,28);
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(5440,24);
manlo <= conv_std_logic_vector(236774391,28);
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(5456,24);
manlo <= conv_std_logic_vector(238169305,28);
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(5472,24);
manlo <= conv_std_logic_vector(239568317,28);
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(5488,24);
manlo <= conv_std_logic_vector(240971426,28);
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(5504,24);
manlo <= conv_std_logic_vector(242378633,28);
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(5520,24);
manlo <= conv_std_logic_vector(243789936,28);
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(5536,24);
manlo <= conv_std_logic_vector(245205338,28);
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(5552,24);
manlo <= conv_std_logic_vector(246624836,28);
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(5568,24);
manlo <= conv_std_logic_vector(248048432,28);
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(5584,24);
manlo <= conv_std_logic_vector(249476125,28);
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(5600,24);
manlo <= conv_std_logic_vector(250907916,28);
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(5616,24);
manlo <= conv_std_logic_vector(252343804,28);
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(5632,24);
manlo <= conv_std_logic_vector(253783789,28);
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(5648,24);
manlo <= conv_std_logic_vector(255227872,28);
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(5664,24);
manlo <= conv_std_logic_vector(256676052,28);
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(5680,24);
manlo <= conv_std_logic_vector(258128329,28);
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(5696,24);
manlo <= conv_std_logic_vector(259584704,28);
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(5712,24);
manlo <= conv_std_logic_vector(261045176,28);
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(5728,24);
manlo <= conv_std_logic_vector(262509746,28);
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(5744,24);
manlo <= conv_std_logic_vector(263978413,28);
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(5760,24);
manlo <= conv_std_logic_vector(265451178,28);
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(5776,24);
manlo <= conv_std_logic_vector(266928039,28);
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(5792,24);
manlo <= conv_std_logic_vector(268408999,28);
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(5809,24);
manlo <= conv_std_logic_vector(1458599,28);
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(5825,24);
manlo <= conv_std_logic_vector(2947754,28);
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(5841,24);
manlo <= conv_std_logic_vector(4441005,28);
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(5857,24);
manlo <= conv_std_logic_vector(5938354,28);
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(5873,24);
manlo <= conv_std_logic_vector(7439800,28);
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(5889,24);
manlo <= conv_std_logic_vector(8945344,28);
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(5905,24);
manlo <= conv_std_logic_vector(10454985,28);
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(5921,24);
manlo <= conv_std_logic_vector(11968724,28);
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(5937,24);
manlo <= conv_std_logic_vector(13486560,28);
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(5953,24);
manlo <= conv_std_logic_vector(15008494,28);
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(5969,24);
manlo <= conv_std_logic_vector(16534525,28);
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(5985,24);
manlo <= conv_std_logic_vector(18064653,28);
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(6001,24);
manlo <= conv_std_logic_vector(19598879,28);
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(6017,24);
manlo <= conv_std_logic_vector(21137203,28);
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(6033,24);
manlo <= conv_std_logic_vector(22679624,28);
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(6049,24);
manlo <= conv_std_logic_vector(24226142,28);
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(6065,24);
manlo <= conv_std_logic_vector(25776758,28);
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(6081,24);
manlo <= conv_std_logic_vector(27331471,28);
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(6097,24);
manlo <= conv_std_logic_vector(28890282,28);
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(6113,24);
manlo <= conv_std_logic_vector(30453190,28);
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(6129,24);
manlo <= conv_std_logic_vector(32020196,28);
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(6145,24);
manlo <= conv_std_logic_vector(33591299,28);
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(6161,24);
manlo <= conv_std_logic_vector(35166500,28);
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(6177,24);
manlo <= conv_std_logic_vector(36745798,28);
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(6193,24);
manlo <= conv_std_logic_vector(38329194,28);
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(6209,24);
manlo <= conv_std_logic_vector(39916688,28);
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(6225,24);
manlo <= conv_std_logic_vector(41508278,28);
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(6241,24);
manlo <= conv_std_logic_vector(43103967,28);
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(6257,24);
manlo <= conv_std_logic_vector(44703753,28);
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(6273,24);
manlo <= conv_std_logic_vector(46307636,28);
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(6289,24);
manlo <= conv_std_logic_vector(47915617,28);
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(6305,24);
manlo <= conv_std_logic_vector(49527695,28);
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(6321,24);
manlo <= conv_std_logic_vector(51143871,28);
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(6337,24);
manlo <= conv_std_logic_vector(52764145,28);
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(6353,24);
manlo <= conv_std_logic_vector(54388516,28);
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(6369,24);
manlo <= conv_std_logic_vector(56016985,28);
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(6385,24);
manlo <= conv_std_logic_vector(57649551,28);
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(6401,24);
manlo <= conv_std_logic_vector(59286215,28);
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(6417,24);
manlo <= conv_std_logic_vector(60926976,28);
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(6433,24);
manlo <= conv_std_logic_vector(62571835,28);
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(6449,24);
manlo <= conv_std_logic_vector(64220791,28);
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(6465,24);
manlo <= conv_std_logic_vector(65873845,28);
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(6481,24);
manlo <= conv_std_logic_vector(67530997,28);
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(6497,24);
manlo <= conv_std_logic_vector(69192246,28);
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(6513,24);
manlo <= conv_std_logic_vector(70857593,28);
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(6529,24);
manlo <= conv_std_logic_vector(72527037,28);
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(6545,24);
manlo <= conv_std_logic_vector(74200579,28);
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(6561,24);
manlo <= conv_std_logic_vector(75878219,28);
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(6577,24);
manlo <= conv_std_logic_vector(77559956,28);
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(6593,24);
manlo <= conv_std_logic_vector(79245791,28);
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(6609,24);
manlo <= conv_std_logic_vector(80935723,28);
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(6625,24);
manlo <= conv_std_logic_vector(82629753,28);
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(6641,24);
manlo <= conv_std_logic_vector(84327881,28);
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(6657,24);
manlo <= conv_std_logic_vector(86030106,28);
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(6673,24);
manlo <= conv_std_logic_vector(87736429,28);
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(6689,24);
manlo <= conv_std_logic_vector(89446849,28);
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(6705,24);
manlo <= conv_std_logic_vector(91161367,28);
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(6721,24);
manlo <= conv_std_logic_vector(92879983,28);
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(6737,24);
manlo <= conv_std_logic_vector(94602697,28);
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(6753,24);
manlo <= conv_std_logic_vector(96329508,28);
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(6769,24);
manlo <= conv_std_logic_vector(98060416,28);
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(6785,24);
manlo <= conv_std_logic_vector(99795423,28);
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(6801,24);
manlo <= conv_std_logic_vector(101534527,28);
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(6817,24);
manlo <= conv_std_logic_vector(103277728,28);
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(6833,24);
manlo <= conv_std_logic_vector(105025028,28);
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(6849,24);
manlo <= conv_std_logic_vector(106776425,28);
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(6865,24);
manlo <= conv_std_logic_vector(108531919,28);
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(6881,24);
manlo <= conv_std_logic_vector(110291512,28);
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(6897,24);
manlo <= conv_std_logic_vector(112055202,28);
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(6913,24);
manlo <= conv_std_logic_vector(113822989,28);
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(6929,24);
manlo <= conv_std_logic_vector(115594875,28);
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(6945,24);
manlo <= conv_std_logic_vector(117370858,28);
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(6961,24);
manlo <= conv_std_logic_vector(119150939,28);
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(6977,24);
manlo <= conv_std_logic_vector(120935117,28);
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(6993,24);
manlo <= conv_std_logic_vector(122723393,28);
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(7009,24);
manlo <= conv_std_logic_vector(124515767,28);
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(7025,24);
manlo <= conv_std_logic_vector(126312239,28);
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(7041,24);
manlo <= conv_std_logic_vector(128112808,28);
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(7057,24);
manlo <= conv_std_logic_vector(129917475,28);
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(7073,24);
manlo <= conv_std_logic_vector(131726240,28);
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(7089,24);
manlo <= conv_std_logic_vector(133539102,28);
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(7105,24);
manlo <= conv_std_logic_vector(135356063,28);
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(7121,24);
manlo <= conv_std_logic_vector(137177121,28);
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(7137,24);
manlo <= conv_std_logic_vector(139002276,28);
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(7153,24);
manlo <= conv_std_logic_vector(140831530,28);
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(7169,24);
manlo <= conv_std_logic_vector(142664881,28);
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(7185,24);
manlo <= conv_std_logic_vector(144502330,28);
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(7201,24);
manlo <= conv_std_logic_vector(146343877,28);
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(7217,24);
manlo <= conv_std_logic_vector(148189521,28);
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(7233,24);
manlo <= conv_std_logic_vector(150039263,28);
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(7249,24);
manlo <= conv_std_logic_vector(151893103,28);
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(7265,24);
manlo <= conv_std_logic_vector(153751041,28);
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(7281,24);
manlo <= conv_std_logic_vector(155613076,28);
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(7297,24);
manlo <= conv_std_logic_vector(157479210,28);
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(7313,24);
manlo <= conv_std_logic_vector(159349441,28);
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(7329,24);
manlo <= conv_std_logic_vector(161223770,28);
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(7345,24);
manlo <= conv_std_logic_vector(163102196,28);
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(7361,24);
manlo <= conv_std_logic_vector(164984721,28);
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(7377,24);
manlo <= conv_std_logic_vector(166871343,28);
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(7393,24);
manlo <= conv_std_logic_vector(168762063,28);
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(7409,24);
manlo <= conv_std_logic_vector(170656881,28);
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(7425,24);
manlo <= conv_std_logic_vector(172555797,28);
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(7441,24);
manlo <= conv_std_logic_vector(174458810,28);
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(7457,24);
manlo <= conv_std_logic_vector(176365921,28);
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(7473,24);
manlo <= conv_std_logic_vector(178277130,28);
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(7489,24);
manlo <= conv_std_logic_vector(180192437,28);
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(7505,24);
manlo <= conv_std_logic_vector(182111842,28);
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(7521,24);
manlo <= conv_std_logic_vector(184035345,28);
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(7537,24);
manlo <= conv_std_logic_vector(185962945,28);
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(7553,24);
manlo <= conv_std_logic_vector(187894643,28);
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(7569,24);
manlo <= conv_std_logic_vector(189830439,28);
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(7585,24);
manlo <= conv_std_logic_vector(191770333,28);
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(7601,24);
manlo <= conv_std_logic_vector(193714325,28);
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(7617,24);
manlo <= conv_std_logic_vector(195662415,28);
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(7633,24);
manlo <= conv_std_logic_vector(197614602,28);
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(7649,24);
manlo <= conv_std_logic_vector(199570888,28);
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(7665,24);
manlo <= conv_std_logic_vector(201531271,28);
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(7681,24);
manlo <= conv_std_logic_vector(203495752,28);
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(7697,24);
manlo <= conv_std_logic_vector(205464331,28);
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(7713,24);
manlo <= conv_std_logic_vector(207437008,28);
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(7729,24);
manlo <= conv_std_logic_vector(209413783,28);
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(7745,24);
manlo <= conv_std_logic_vector(211394656,28);
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(7761,24);
manlo <= conv_std_logic_vector(213379626,28);
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(7777,24);
manlo <= conv_std_logic_vector(215368695,28);
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(7793,24);
manlo <= conv_std_logic_vector(217361861,28);
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(7809,24);
manlo <= conv_std_logic_vector(219359125,28);
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(7825,24);
manlo <= conv_std_logic_vector(221360487,28);
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(7841,24);
manlo <= conv_std_logic_vector(223365947,28);
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(7857,24);
manlo <= conv_std_logic_vector(225375505,28);
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(7873,24);
manlo <= conv_std_logic_vector(227389161,28);
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(7889,24);
manlo <= conv_std_logic_vector(229406915,28);
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(7905,24);
manlo <= conv_std_logic_vector(231428767,28);
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(7921,24);
manlo <= conv_std_logic_vector(233454716,28);
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(7937,24);
manlo <= conv_std_logic_vector(235484764,28);
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(7953,24);
manlo <= conv_std_logic_vector(237518910,28);
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(7969,24);
manlo <= conv_std_logic_vector(239557153,28);
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(7985,24);
manlo <= conv_std_logic_vector(241599495,28);
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(8001,24);
manlo <= conv_std_logic_vector(243645934,28);
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(8017,24);
manlo <= conv_std_logic_vector(245696471,28);
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(8033,24);
manlo <= conv_std_logic_vector(247751107,28);
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(8049,24);
manlo <= conv_std_logic_vector(249809840,28);
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(8065,24);
manlo <= conv_std_logic_vector(251872671,28);
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(8081,24);
manlo <= conv_std_logic_vector(253939600,28);
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(8097,24);
manlo <= conv_std_logic_vector(256010627,28);
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(8113,24);
manlo <= conv_std_logic_vector(258085753,28);
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(8129,24);
manlo <= conv_std_logic_vector(260164976,28);
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(8145,24);
manlo <= conv_std_logic_vector(262248297,28);
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(8161,24);
manlo <= conv_std_logic_vector(264335716,28);
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(8177,24);
manlo <= conv_std_logic_vector(266427233,28);
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(8194,24);
manlo <= conv_std_logic_vector(87392,28);
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(8210,24);
manlo <= conv_std_logic_vector(2187105,28);
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(8226,24);
manlo <= conv_std_logic_vector(4290916,28);
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(8242,24);
manlo <= conv_std_logic_vector(6398825,28);
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(8258,24);
manlo <= conv_std_logic_vector(8510832,28);
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(8274,24);
manlo <= conv_std_logic_vector(10626938,28);
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(8290,24);
manlo <= conv_std_logic_vector(12747141,28);
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(8306,24);
manlo <= conv_std_logic_vector(14871442,28);
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(8322,24);
manlo <= conv_std_logic_vector(16999841,28);
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(8338,24);
manlo <= conv_std_logic_vector(19132338,28);
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(8354,24);
manlo <= conv_std_logic_vector(21268934,28);
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(8370,24);
manlo <= conv_std_logic_vector(23409627,28);
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(8386,24);
manlo <= conv_std_logic_vector(25554418,28);
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(8402,24);
manlo <= conv_std_logic_vector(27703308,28);
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(8418,24);
manlo <= conv_std_logic_vector(29856295,28);
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(8434,24);
manlo <= conv_std_logic_vector(32013381,28);
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(8450,24);
manlo <= conv_std_logic_vector(34174564,28);
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(8466,24);
manlo <= conv_std_logic_vector(36339846,28);
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(8482,24);
manlo <= conv_std_logic_vector(38509225,28);
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(8498,24);
manlo <= conv_std_logic_vector(40682703,28);
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(8514,24);
manlo <= conv_std_logic_vector(42860279,28);
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(8530,24);
manlo <= conv_std_logic_vector(45041953,28);
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(8546,24);
manlo <= conv_std_logic_vector(47227725,28);
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(8562,24);
manlo <= conv_std_logic_vector(49417595,28);
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(8578,24);
manlo <= conv_std_logic_vector(51611563,28);
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(8594,24);
manlo <= conv_std_logic_vector(53809629,28);
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(8610,24);
manlo <= conv_std_logic_vector(56011794,28);
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(8626,24);
manlo <= conv_std_logic_vector(58218056,28);
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(8642,24);
manlo <= conv_std_logic_vector(60428417,28);
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(8658,24);
manlo <= conv_std_logic_vector(62642876,28);
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(8674,24);
manlo <= conv_std_logic_vector(64861432,28);
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(8690,24);
manlo <= conv_std_logic_vector(67084087,28);
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(8706,24);
manlo <= conv_std_logic_vector(69310840,28);
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(8722,24);
manlo <= conv_std_logic_vector(71541691,28);
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(8738,24);
manlo <= conv_std_logic_vector(73776641,28);
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(8754,24);
manlo <= conv_std_logic_vector(76015688,28);
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(8770,24);
manlo <= conv_std_logic_vector(78258834,28);
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(8786,24);
manlo <= conv_std_logic_vector(80506077,28);
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(8802,24);
manlo <= conv_std_logic_vector(82757419,28);
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(8818,24);
manlo <= conv_std_logic_vector(85012859,28);
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(8834,24);
manlo <= conv_std_logic_vector(87272397,28);
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(8850,24);
manlo <= conv_std_logic_vector(89536034,28);
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(8866,24);
manlo <= conv_std_logic_vector(91803768,28);
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(8882,24);
manlo <= conv_std_logic_vector(94075601,28);
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(8898,24);
manlo <= conv_std_logic_vector(96351532,28);
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(8914,24);
manlo <= conv_std_logic_vector(98631561,28);
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(8930,24);
manlo <= conv_std_logic_vector(100915688,28);
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(8946,24);
manlo <= conv_std_logic_vector(103203913,28);
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(8962,24);
manlo <= conv_std_logic_vector(105496237,28);
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(8978,24);
manlo <= conv_std_logic_vector(107792658,28);
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(8994,24);
manlo <= conv_std_logic_vector(110093178,28);
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(9010,24);
manlo <= conv_std_logic_vector(112397796,28);
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(9026,24);
manlo <= conv_std_logic_vector(114706513,28);
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(9042,24);
manlo <= conv_std_logic_vector(117019327,28);
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(9058,24);
manlo <= conv_std_logic_vector(119336240,28);
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(9074,24);
manlo <= conv_std_logic_vector(121657251,28);
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(9090,24);
manlo <= conv_std_logic_vector(123982360,28);
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(9106,24);
manlo <= conv_std_logic_vector(126311567,28);
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(9122,24);
manlo <= conv_std_logic_vector(128644873,28);
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(9138,24);
manlo <= conv_std_logic_vector(130982277,28);
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(9154,24);
manlo <= conv_std_logic_vector(133323779,28);
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(9170,24);
manlo <= conv_std_logic_vector(135669379,28);
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(9186,24);
manlo <= conv_std_logic_vector(138019077,28);
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(9202,24);
manlo <= conv_std_logic_vector(140372874,28);
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(9218,24);
manlo <= conv_std_logic_vector(142730769,28);
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(9234,24);
manlo <= conv_std_logic_vector(145092762,28);
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(9250,24);
manlo <= conv_std_logic_vector(147458854,28);
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(9266,24);
manlo <= conv_std_logic_vector(149829044,28);
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(9282,24);
manlo <= conv_std_logic_vector(152203332,28);
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(9298,24);
manlo <= conv_std_logic_vector(154581718,28);
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(9314,24);
manlo <= conv_std_logic_vector(156964202,28);
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(9330,24);
manlo <= conv_std_logic_vector(159350785,28);
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(9346,24);
manlo <= conv_std_logic_vector(161741466,28);
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(9362,24);
manlo <= conv_std_logic_vector(164136246,28);
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(9378,24);
manlo <= conv_std_logic_vector(166535123,28);
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(9394,24);
manlo <= conv_std_logic_vector(168938099,28);
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(9410,24);
manlo <= conv_std_logic_vector(171345174,28);
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(9426,24);
manlo <= conv_std_logic_vector(173756346,28);
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(9442,24);
manlo <= conv_std_logic_vector(176171617,28);
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(9458,24);
manlo <= conv_std_logic_vector(178590986,28);
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(9474,24);
manlo <= conv_std_logic_vector(181014454,28);
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(9490,24);
manlo <= conv_std_logic_vector(183442020,28);
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(9506,24);
manlo <= conv_std_logic_vector(185873684,28);
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(9522,24);
manlo <= conv_std_logic_vector(188309446,28);
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(9538,24);
manlo <= conv_std_logic_vector(190749307,28);
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(9554,24);
manlo <= conv_std_logic_vector(193193266,28);
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(9570,24);
manlo <= conv_std_logic_vector(195641323,28);
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(9586,24);
manlo <= conv_std_logic_vector(198093479,28);
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(9602,24);
manlo <= conv_std_logic_vector(200549733,28);
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(9618,24);
manlo <= conv_std_logic_vector(203010086,28);
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(9634,24);
manlo <= conv_std_logic_vector(205474536,28);
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(9650,24);
manlo <= conv_std_logic_vector(207943085,28);
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(9666,24);
manlo <= conv_std_logic_vector(210415733,28);
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(9682,24);
manlo <= conv_std_logic_vector(212892479,28);
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(9698,24);
manlo <= conv_std_logic_vector(215373323,28);
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(9714,24);
manlo <= conv_std_logic_vector(217858266,28);
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(9730,24);
manlo <= conv_std_logic_vector(220347307,28);
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(9746,24);
manlo <= conv_std_logic_vector(222840446,28);
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(9762,24);
manlo <= conv_std_logic_vector(225337684,28);
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(9778,24);
manlo <= conv_std_logic_vector(227839020,28);
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(9794,24);
manlo <= conv_std_logic_vector(230344454,28);
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(9810,24);
manlo <= conv_std_logic_vector(232853987,28);
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(9826,24);
manlo <= conv_std_logic_vector(235367618,28);
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(9842,24);
manlo <= conv_std_logic_vector(237885348,28);
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(9858,24);
manlo <= conv_std_logic_vector(240407176,28);
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(9874,24);
manlo <= conv_std_logic_vector(242933102,28);
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(9890,24);
manlo <= conv_std_logic_vector(245463127,28);
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(9906,24);
manlo <= conv_std_logic_vector(247997251,28);
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(9922,24);
manlo <= conv_std_logic_vector(250535472,28);
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(9938,24);
manlo <= conv_std_logic_vector(253077793,28);
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(9954,24);
manlo <= conv_std_logic_vector(255624211,28);
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(9970,24);
manlo <= conv_std_logic_vector(258174728,28);
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(9986,24);
manlo <= conv_std_logic_vector(260729344,28);
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(10002,24);
manlo <= conv_std_logic_vector(263288057,28);
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(10018,24);
manlo <= conv_std_logic_vector(265850870,28);
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(10034,24);
manlo <= conv_std_logic_vector(268417780,28);
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(10051,24);
manlo <= conv_std_logic_vector(2553334,28);
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(10067,24);
manlo <= conv_std_logic_vector(5128441,28);
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(10083,24);
manlo <= conv_std_logic_vector(7707647,28);
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(10099,24);
manlo <= conv_std_logic_vector(10290952,28);
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(10115,24);
manlo <= conv_std_logic_vector(12878355,28);
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(10131,24);
manlo <= conv_std_logic_vector(15469857,28);
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(10147,24);
manlo <= conv_std_logic_vector(18065457,28);
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(10163,24);
manlo <= conv_std_logic_vector(20665155,28);
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(10179,24);
manlo <= conv_std_logic_vector(23268952,28);
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(10195,24);
manlo <= conv_std_logic_vector(25876847,28);
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(10211,24);
manlo <= conv_std_logic_vector(28488841,28);
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(10227,24);
manlo <= conv_std_logic_vector(31104934,28);
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(10243,24);
manlo <= conv_std_logic_vector(33725125,28);
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(10259,24);
manlo <= conv_std_logic_vector(36349414,28);
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(10275,24);
manlo <= conv_std_logic_vector(38977802,28);
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(10291,24);
manlo <= conv_std_logic_vector(41610288,28);
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(10307,24);
manlo <= conv_std_logic_vector(44246873,28);
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(10323,24);
manlo <= conv_std_logic_vector(46887557,28);
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(10339,24);
manlo <= conv_std_logic_vector(49532339,28);
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(10355,24);
manlo <= conv_std_logic_vector(52181219,28);
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(10371,24);
manlo <= conv_std_logic_vector(54834198,28);
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(10387,24);
manlo <= conv_std_logic_vector(57491276,28);
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(10403,24);
manlo <= conv_std_logic_vector(60152452,28);
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(10419,24);
manlo <= conv_std_logic_vector(62817727,28);
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(10435,24);
manlo <= conv_std_logic_vector(65487100,28);
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(10451,24);
manlo <= conv_std_logic_vector(68160572,28);
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(10467,24);
manlo <= conv_std_logic_vector(70838142,28);
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(10483,24);
manlo <= conv_std_logic_vector(73519811,28);
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(10499,24);
manlo <= conv_std_logic_vector(76205578,28);
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(10515,24);
manlo <= conv_std_logic_vector(78895444,28);
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(10531,24);
manlo <= conv_std_logic_vector(81589409,28);
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(10547,24);
manlo <= conv_std_logic_vector(84287472,28);
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(10563,24);
manlo <= conv_std_logic_vector(86989633,28);
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(10579,24);
manlo <= conv_std_logic_vector(89695894,28);
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(10595,24);
manlo <= conv_std_logic_vector(92406252,28);
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(10611,24);
manlo <= conv_std_logic_vector(95120710,28);
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(10627,24);
manlo <= conv_std_logic_vector(97839266,28);
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(10643,24);
manlo <= conv_std_logic_vector(100561920,28);
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(10659,24);
manlo <= conv_std_logic_vector(103288674,28);
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(10675,24);
manlo <= conv_std_logic_vector(106019525,28);
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(10691,24);
manlo <= conv_std_logic_vector(108754476,28);
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(10707,24);
manlo <= conv_std_logic_vector(111493525,28);
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(10723,24);
manlo <= conv_std_logic_vector(114236673,28);
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(10739,24);
manlo <= conv_std_logic_vector(116983919,28);
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(10755,24);
manlo <= conv_std_logic_vector(119735264,28);
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(10771,24);
manlo <= conv_std_logic_vector(122490707,28);
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(10787,24);
manlo <= conv_std_logic_vector(125250249,28);
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(10803,24);
manlo <= conv_std_logic_vector(128013890,28);
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(10819,24);
manlo <= conv_std_logic_vector(130781629,28);
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(10835,24);
manlo <= conv_std_logic_vector(133553468,28);
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(10851,24);
manlo <= conv_std_logic_vector(136329404,28);
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(10867,24);
manlo <= conv_std_logic_vector(139109440,28);
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(10883,24);
manlo <= conv_std_logic_vector(141893574,28);
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(10899,24);
manlo <= conv_std_logic_vector(144681806,28);
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(10915,24);
manlo <= conv_std_logic_vector(147474137,28);
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(10931,24);
manlo <= conv_std_logic_vector(150270567,28);
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(10947,24);
manlo <= conv_std_logic_vector(153071096,28);
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(10963,24);
manlo <= conv_std_logic_vector(155875723,28);
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(10979,24);
manlo <= conv_std_logic_vector(158684449,28);
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(10995,24);
manlo <= conv_std_logic_vector(161497274,28);
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(11011,24);
manlo <= conv_std_logic_vector(164314197,28);
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(11027,24);
manlo <= conv_std_logic_vector(167135219,28);
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(11043,24);
manlo <= conv_std_logic_vector(169960340,28);
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(11059,24);
manlo <= conv_std_logic_vector(172789560,28);
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(11075,24);
manlo <= conv_std_logic_vector(175622878,28);
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(11091,24);
manlo <= conv_std_logic_vector(178460295,28);
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(11107,24);
manlo <= conv_std_logic_vector(181301810,28);
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(11123,24);
manlo <= conv_std_logic_vector(184147424,28);
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(11139,24);
manlo <= conv_std_logic_vector(186997137,28);
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(11155,24);
manlo <= conv_std_logic_vector(189850949,28);
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(11171,24);
manlo <= conv_std_logic_vector(192708860,28);
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(11187,24);
manlo <= conv_std_logic_vector(195570869,28);
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(11203,24);
manlo <= conv_std_logic_vector(198436977,28);
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(11219,24);
manlo <= conv_std_logic_vector(201307183,28);
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(11235,24);
manlo <= conv_std_logic_vector(204181489,28);
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(11251,24);
manlo <= conv_std_logic_vector(207059893,28);
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(11267,24);
manlo <= conv_std_logic_vector(209942395,28);
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(11283,24);
manlo <= conv_std_logic_vector(212828997,28);
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(11299,24);
manlo <= conv_std_logic_vector(215719697,28);
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(11315,24);
manlo <= conv_std_logic_vector(218614497,28);
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(11331,24);
manlo <= conv_std_logic_vector(221513394,28);
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(11347,24);
manlo <= conv_std_logic_vector(224416391,28);
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(11363,24);
manlo <= conv_std_logic_vector(227323486,28);
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(11379,24);
manlo <= conv_std_logic_vector(230234681,28);
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(11395,24);
manlo <= conv_std_logic_vector(233149974,28);
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(11411,24);
manlo <= conv_std_logic_vector(236069365,28);
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(11427,24);
manlo <= conv_std_logic_vector(238992856,28);
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(11443,24);
manlo <= conv_std_logic_vector(241920445,28);
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(11459,24);
manlo <= conv_std_logic_vector(244852133,28);
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(11475,24);
manlo <= conv_std_logic_vector(247787920,28);
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(11491,24);
manlo <= conv_std_logic_vector(250727806,28);
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(11507,24);
manlo <= conv_std_logic_vector(253671790,28);
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(11523,24);
manlo <= conv_std_logic_vector(256619874,28);
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(11539,24);
manlo <= conv_std_logic_vector(259572056,28);
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(11555,24);
manlo <= conv_std_logic_vector(262528337,28);
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(11571,24);
manlo <= conv_std_logic_vector(265488717,28);
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(11588,24);
manlo <= conv_std_logic_vector(17739,28);
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(11604,24);
manlo <= conv_std_logic_vector(2986317,28);
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(11620,24);
manlo <= conv_std_logic_vector(5958993,28);
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(11636,24);
manlo <= conv_std_logic_vector(8935768,28);
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(11652,24);
manlo <= conv_std_logic_vector(11916642,28);
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(11668,24);
manlo <= conv_std_logic_vector(14901615,28);
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(11684,24);
manlo <= conv_std_logic_vector(17890686,28);
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(11700,24);
manlo <= conv_std_logic_vector(20883857,28);
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(11716,24);
manlo <= conv_std_logic_vector(23881126,28);
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(11732,24);
manlo <= conv_std_logic_vector(26882494,28);
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(11748,24);
manlo <= conv_std_logic_vector(29887961,28);
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(11764,24);
manlo <= conv_std_logic_vector(32897527,28);
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(11780,24);
manlo <= conv_std_logic_vector(35911192,28);
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(11796,24);
manlo <= conv_std_logic_vector(38928956,28);
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(11812,24);
manlo <= conv_std_logic_vector(41950818,28);
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(11828,24);
manlo <= conv_std_logic_vector(44976780,28);
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(11844,24);
manlo <= conv_std_logic_vector(48006840,28);
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(11860,24);
manlo <= conv_std_logic_vector(51040999,28);
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(11876,24);
manlo <= conv_std_logic_vector(54079258,28);
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(11892,24);
manlo <= conv_std_logic_vector(57121615,28);
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(11908,24);
manlo <= conv_std_logic_vector(60168071,28);
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(11924,24);
manlo <= conv_std_logic_vector(63218625,28);
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(11940,24);
manlo <= conv_std_logic_vector(66273279,28);
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(11956,24);
manlo <= conv_std_logic_vector(69332032,28);
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(11972,24);
manlo <= conv_std_logic_vector(72394883,28);
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(11988,24);
manlo <= conv_std_logic_vector(75461834,28);
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(12004,24);
manlo <= conv_std_logic_vector(78532883,28);
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(12020,24);
manlo <= conv_std_logic_vector(81608032,28);
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(12036,24);
manlo <= conv_std_logic_vector(84687279,28);
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(12052,24);
manlo <= conv_std_logic_vector(87770625,28);
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(12068,24);
manlo <= conv_std_logic_vector(90858070,28);
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(12084,24);
manlo <= conv_std_logic_vector(93949615,28);
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(12100,24);
manlo <= conv_std_logic_vector(97045258,28);
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(12116,24);
manlo <= conv_std_logic_vector(100145000,28);
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(12132,24);
manlo <= conv_std_logic_vector(103248841,28);
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(12148,24);
manlo <= conv_std_logic_vector(106356781,28);
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(12164,24);
manlo <= conv_std_logic_vector(109468819,28);
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(12180,24);
manlo <= conv_std_logic_vector(112584957,28);
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(12196,24);
manlo <= conv_std_logic_vector(115705194,28);
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(12212,24);
manlo <= conv_std_logic_vector(118829530,28);
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(12228,24);
manlo <= conv_std_logic_vector(121957965,28);
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(12244,24);
manlo <= conv_std_logic_vector(125090499,28);
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(12260,24);
manlo <= conv_std_logic_vector(128227131,28);
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(12276,24);
manlo <= conv_std_logic_vector(131367863,28);
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(12292,24);
manlo <= conv_std_logic_vector(134512694,28);
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(12308,24);
manlo <= conv_std_logic_vector(137661624,28);
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(12324,24);
manlo <= conv_std_logic_vector(140814653,28);
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(12340,24);
manlo <= conv_std_logic_vector(143971780,28);
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(12356,24);
manlo <= conv_std_logic_vector(147133007,28);
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(12372,24);
manlo <= conv_std_logic_vector(150298333,28);
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(12388,24);
manlo <= conv_std_logic_vector(153467758,28);
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(12404,24);
manlo <= conv_std_logic_vector(156641282,28);
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(12420,24);
manlo <= conv_std_logic_vector(159818905,28);
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(12436,24);
manlo <= conv_std_logic_vector(163000627,28);
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(12452,24);
manlo <= conv_std_logic_vector(166186448,28);
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(12468,24);
manlo <= conv_std_logic_vector(169376368,28);
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(12484,24);
manlo <= conv_std_logic_vector(172570387,28);
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(12500,24);
manlo <= conv_std_logic_vector(175768505,28);
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(12516,24);
manlo <= conv_std_logic_vector(178970722,28);
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(12532,24);
manlo <= conv_std_logic_vector(182177038,28);
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(12548,24);
manlo <= conv_std_logic_vector(185387453,28);
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(12564,24);
manlo <= conv_std_logic_vector(188601968,28);
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(12580,24);
manlo <= conv_std_logic_vector(191820581,28);
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(12596,24);
manlo <= conv_std_logic_vector(195043294,28);
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(12612,24);
manlo <= conv_std_logic_vector(198270105,28);
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(12628,24);
manlo <= conv_std_logic_vector(201501016,28);
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(12644,24);
manlo <= conv_std_logic_vector(204736025,28);
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(12660,24);
manlo <= conv_std_logic_vector(207975134,28);
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(12676,24);
manlo <= conv_std_logic_vector(211218342,28);
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(12692,24);
manlo <= conv_std_logic_vector(214465649,28);
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(12708,24);
manlo <= conv_std_logic_vector(217717055,28);
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(12724,24);
manlo <= conv_std_logic_vector(220972560,28);
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(12740,24);
manlo <= conv_std_logic_vector(224232165,28);
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(12756,24);
manlo <= conv_std_logic_vector(227495868,28);
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(12772,24);
manlo <= conv_std_logic_vector(230763671,28);
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(12788,24);
manlo <= conv_std_logic_vector(234035572,28);
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(12804,24);
manlo <= conv_std_logic_vector(237311573,28);
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(12820,24);
manlo <= conv_std_logic_vector(240591673,28);
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(12836,24);
manlo <= conv_std_logic_vector(243875872,28);
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(12852,24);
manlo <= conv_std_logic_vector(247164170,28);
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(12868,24);
manlo <= conv_std_logic_vector(250456567,28);
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(12884,24);
manlo <= conv_std_logic_vector(253753064,28);
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(12900,24);
manlo <= conv_std_logic_vector(257053659,28);
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(12916,24);
manlo <= conv_std_logic_vector(260358354,28);
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(12932,24);
manlo <= conv_std_logic_vector(263667148,28);
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(12948,24);
manlo <= conv_std_logic_vector(266980041,28);
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(12965,24);
manlo <= conv_std_logic_vector(1861577,28);
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(12981,24);
manlo <= conv_std_logic_vector(5182668,28);
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(12997,24);
manlo <= conv_std_logic_vector(8507859,28);
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(13013,24);
manlo <= conv_std_logic_vector(11837149,28);
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(13029,24);
manlo <= conv_std_logic_vector(15170538,28);
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(13045,24);
manlo <= conv_std_logic_vector(18508026,28);
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(13061,24);
manlo <= conv_std_logic_vector(21849613,28);
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(13077,24);
manlo <= conv_std_logic_vector(25195299,28);
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(13093,24);
manlo <= conv_std_logic_vector(28545085,28);
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(13109,24);
manlo <= conv_std_logic_vector(31898970,28);
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(13125,24);
manlo <= conv_std_logic_vector(35256954,28);
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(13141,24);
manlo <= conv_std_logic_vector(38619037,28);
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(13157,24);
manlo <= conv_std_logic_vector(41985219,28);
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(13173,24);
manlo <= conv_std_logic_vector(45355501,28);
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(13189,24);
manlo <= conv_std_logic_vector(48729882,28);
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(13205,24);
manlo <= conv_std_logic_vector(52108362,28);
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(13221,24);
manlo <= conv_std_logic_vector(55490941,28);
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(13237,24);
manlo <= conv_std_logic_vector(58877620,28);
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(13253,24);
manlo <= conv_std_logic_vector(62268398,28);
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(13269,24);
manlo <= conv_std_logic_vector(65663275,28);
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(13285,24);
manlo <= conv_std_logic_vector(69062251,28);
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(13301,24);
manlo <= conv_std_logic_vector(72465326,28);
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(13317,24);
manlo <= conv_std_logic_vector(75872501,28);
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(13333,24);
manlo <= conv_std_logic_vector(79283775,28);
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(13349,24);
manlo <= conv_std_logic_vector(82699148,28);
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(13365,24);
manlo <= conv_std_logic_vector(86118621,28);
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(13381,24);
manlo <= conv_std_logic_vector(89542193,28);
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(13397,24);
manlo <= conv_std_logic_vector(92969864,28);
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(13413,24);
manlo <= conv_std_logic_vector(96401634,28);
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(13429,24);
manlo <= conv_std_logic_vector(99837503,28);
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(13445,24);
manlo <= conv_std_logic_vector(103277472,28);
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(13461,24);
manlo <= conv_std_logic_vector(106721540,28);
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(13477,24);
manlo <= conv_std_logic_vector(110169708,28);
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(13493,24);
manlo <= conv_std_logic_vector(113621975,28);
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(13509,24);
manlo <= conv_std_logic_vector(117078341,28);
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(13525,24);
manlo <= conv_std_logic_vector(120538806,28);
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(13541,24);
manlo <= conv_std_logic_vector(124003370,28);
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(13557,24);
manlo <= conv_std_logic_vector(127472034,28);
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(13573,24);
manlo <= conv_std_logic_vector(130944798,28);
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(13589,24);
manlo <= conv_std_logic_vector(134421660,28);
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(13605,24);
manlo <= conv_std_logic_vector(137902622,28);
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(13621,24);
manlo <= conv_std_logic_vector(141387683,28);
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(13637,24);
manlo <= conv_std_logic_vector(144876844,28);
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(13653,24);
manlo <= conv_std_logic_vector(148370104,28);
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(13669,24);
manlo <= conv_std_logic_vector(151867463,28);
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(13685,24);
manlo <= conv_std_logic_vector(155368921,28);
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(13701,24);
manlo <= conv_std_logic_vector(158874479,28);
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(13717,24);
manlo <= conv_std_logic_vector(162384136,28);
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(13733,24);
manlo <= conv_std_logic_vector(165897893,28);
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(13749,24);
manlo <= conv_std_logic_vector(169415749,28);
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(13765,24);
manlo <= conv_std_logic_vector(172937704,28);
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(13781,24);
manlo <= conv_std_logic_vector(176463758,28);
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(13797,24);
manlo <= conv_std_logic_vector(179993912,28);
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(13813,24);
manlo <= conv_std_logic_vector(183528166,28);
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(13829,24);
manlo <= conv_std_logic_vector(187066519,28);
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(13845,24);
manlo <= conv_std_logic_vector(190608971,28);
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(13861,24);
manlo <= conv_std_logic_vector(194155522,28);
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(13877,24);
manlo <= conv_std_logic_vector(197706173,28);
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(13893,24);
manlo <= conv_std_logic_vector(201260923,28);
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(13909,24);
manlo <= conv_std_logic_vector(204819773,28);
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(13925,24);
manlo <= conv_std_logic_vector(208382722,28);
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(13941,24);
manlo <= conv_std_logic_vector(211949770,28);
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(13957,24);
manlo <= conv_std_logic_vector(215520918,28);
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(13973,24);
manlo <= conv_std_logic_vector(219096165,28);
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(13989,24);
manlo <= conv_std_logic_vector(222675512,28);
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(14005,24);
manlo <= conv_std_logic_vector(226258958,28);
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(14021,24);
manlo <= conv_std_logic_vector(229846504,28);
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(14037,24);
manlo <= conv_std_logic_vector(233438148,28);
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(14053,24);
manlo <= conv_std_logic_vector(237033893,28);
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(14069,24);
manlo <= conv_std_logic_vector(240633737,28);
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(14085,24);
manlo <= conv_std_logic_vector(244237680,28);
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(14101,24);
manlo <= conv_std_logic_vector(247845722,28);
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(14117,24);
manlo <= conv_std_logic_vector(251457864,28);
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(14133,24);
manlo <= conv_std_logic_vector(255074106,28);
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(14149,24);
manlo <= conv_std_logic_vector(258694447,28);
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(14165,24);
manlo <= conv_std_logic_vector(262318887,28);
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(14181,24);
manlo <= conv_std_logic_vector(265947427,28);
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(14198,24);
manlo <= conv_std_logic_vector(1144611,28);
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(14214,24);
manlo <= conv_std_logic_vector(4781350,28);
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(14230,24);
manlo <= conv_std_logic_vector(8422188,28);
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(14246,24);
manlo <= conv_std_logic_vector(12067126,28);
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(14262,24);
manlo <= conv_std_logic_vector(15716163,28);
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(14278,24);
manlo <= conv_std_logic_vector(19369300,28);
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(14294,24);
manlo <= conv_std_logic_vector(23026536,28);
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(14310,24);
manlo <= conv_std_logic_vector(26687871,28);
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(14326,24);
manlo <= conv_std_logic_vector(30353307,28);
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(14342,24);
manlo <= conv_std_logic_vector(34022841,28);
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(14358,24);
manlo <= conv_std_logic_vector(37696476,28);
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(14374,24);
manlo <= conv_std_logic_vector(41374209,28);
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(14390,24);
manlo <= conv_std_logic_vector(45056043,28);
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(14406,24);
manlo <= conv_std_logic_vector(48741975,28);
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(14422,24);
manlo <= conv_std_logic_vector(52432007,28);
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(14438,24);
manlo <= conv_std_logic_vector(56126139,28);
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(14454,24);
manlo <= conv_std_logic_vector(59824371,28);
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(14470,24);
manlo <= conv_std_logic_vector(63526701,28);
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(14486,24);
manlo <= conv_std_logic_vector(67233132,28);
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(14502,24);
manlo <= conv_std_logic_vector(70943662,28);
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(14518,24);
manlo <= conv_std_logic_vector(74658291,28);
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(14534,24);
manlo <= conv_std_logic_vector(78377020,28);
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(14550,24);
manlo <= conv_std_logic_vector(82099849,28);
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(14566,24);
manlo <= conv_std_logic_vector(85826777,28);
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(14582,24);
manlo <= conv_std_logic_vector(89557804,28);
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(14598,24);
manlo <= conv_std_logic_vector(93292931,28);
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(14614,24);
manlo <= conv_std_logic_vector(97032158,28);
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(14630,24);
manlo <= conv_std_logic_vector(100775484,28);
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(14646,24);
manlo <= conv_std_logic_vector(104522910,28);
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(14662,24);
manlo <= conv_std_logic_vector(108274436,28);
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(14678,24);
manlo <= conv_std_logic_vector(112030061,28);
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(14694,24);
manlo <= conv_std_logic_vector(115789786,28);
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(14710,24);
manlo <= conv_std_logic_vector(119553610,28);
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(14726,24);
manlo <= conv_std_logic_vector(123321534,28);
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(14742,24);
manlo <= conv_std_logic_vector(127093557,28);
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(14758,24);
manlo <= conv_std_logic_vector(130869680,28);
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(14774,24);
manlo <= conv_std_logic_vector(134649903,28);
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(14790,24);
manlo <= conv_std_logic_vector(138434225,28);
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(14806,24);
manlo <= conv_std_logic_vector(142222647,28);
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(14822,24);
manlo <= conv_std_logic_vector(146015168,28);
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(14838,24);
manlo <= conv_std_logic_vector(149811789,28);
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(14854,24);
manlo <= conv_std_logic_vector(153612510,28);
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(14870,24);
manlo <= conv_std_logic_vector(157417330,28);
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(14886,24);
manlo <= conv_std_logic_vector(161226250,28);
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(14902,24);
manlo <= conv_std_logic_vector(165039270,28);
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(14918,24);
manlo <= conv_std_logic_vector(168856389,28);
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(14934,24);
manlo <= conv_std_logic_vector(172677608,28);
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(14950,24);
manlo <= conv_std_logic_vector(176502926,28);
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(14966,24);
manlo <= conv_std_logic_vector(180332344,28);
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(14982,24);
manlo <= conv_std_logic_vector(184165862,28);
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(14998,24);
manlo <= conv_std_logic_vector(188003480,28);
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(15014,24);
manlo <= conv_std_logic_vector(191845197,28);
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(15030,24);
manlo <= conv_std_logic_vector(195691014,28);
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(15046,24);
manlo <= conv_std_logic_vector(199540930,28);
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(15062,24);
manlo <= conv_std_logic_vector(203394946,28);
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(15078,24);
manlo <= conv_std_logic_vector(207253062,28);
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(15094,24);
manlo <= conv_std_logic_vector(211115277,28);
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(15110,24);
manlo <= conv_std_logic_vector(214981593,28);
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(15126,24);
manlo <= conv_std_logic_vector(218852007,28);
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(15142,24);
manlo <= conv_std_logic_vector(222726522,28);
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(15158,24);
manlo <= conv_std_logic_vector(226605136,28);
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(15174,24);
manlo <= conv_std_logic_vector(230487850,28);
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(15190,24);
manlo <= conv_std_logic_vector(234374664,28);
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(15206,24);
manlo <= conv_std_logic_vector(238265577,28);
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(15222,24);
manlo <= conv_std_logic_vector(242160590,28);
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(15238,24);
manlo <= conv_std_logic_vector(246059703,28);
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(15254,24);
manlo <= conv_std_logic_vector(249962916,28);
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(15270,24);
manlo <= conv_std_logic_vector(253870228,28);
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(15286,24);
manlo <= conv_std_logic_vector(257781640,28);
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(15302,24);
manlo <= conv_std_logic_vector(261697152,28);
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(15318,24);
manlo <= conv_std_logic_vector(265616763,28);
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(15335,24);
manlo <= conv_std_logic_vector(1105018,28);
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(15351,24);
manlo <= conv_std_logic_vector(5032829,28);
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(15367,24);
manlo <= conv_std_logic_vector(8964740,28);
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(15383,24);
manlo <= conv_std_logic_vector(12900750,28);
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(15399,24);
manlo <= conv_std_logic_vector(16840860,28);
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(15415,24);
manlo <= conv_std_logic_vector(20785070,28);
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(15431,24);
manlo <= conv_std_logic_vector(24733380,28);
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(15447,24);
manlo <= conv_std_logic_vector(28685790,28);
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(15463,24);
manlo <= conv_std_logic_vector(32642299,28);
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(15479,24);
manlo <= conv_std_logic_vector(36602908,28);
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(15495,24);
manlo <= conv_std_logic_vector(40567617,28);
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(15511,24);
manlo <= conv_std_logic_vector(44536425,28);
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(15527,24);
manlo <= conv_std_logic_vector(48509334,28);
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(15543,24);
manlo <= conv_std_logic_vector(52486342,28);
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(15559,24);
manlo <= conv_std_logic_vector(56467450,28);
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(15575,24);
manlo <= conv_std_logic_vector(60452657,28);
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(15591,24);
manlo <= conv_std_logic_vector(64441965,28);
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(15607,24);
manlo <= conv_std_logic_vector(68435372,28);
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(15623,24);
manlo <= conv_std_logic_vector(72432880,28);
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(15639,24);
manlo <= conv_std_logic_vector(76434487,28);
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(15655,24);
manlo <= conv_std_logic_vector(80440193,28);
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(15671,24);
manlo <= conv_std_logic_vector(84450000,28);
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(15687,24);
manlo <= conv_std_logic_vector(88463906,28);
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(15703,24);
manlo <= conv_std_logic_vector(92481913,28);
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(15719,24);
manlo <= conv_std_logic_vector(96504019,28);
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(15735,24);
manlo <= conv_std_logic_vector(100530225,28);
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(15751,24);
manlo <= conv_std_logic_vector(104560531,28);
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(15767,24);
manlo <= conv_std_logic_vector(108594936,28);
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(15783,24);
manlo <= conv_std_logic_vector(112633442,28);
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(15799,24);
manlo <= conv_std_logic_vector(116676047,28);
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(15815,24);
manlo <= conv_std_logic_vector(120722752,28);
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(15831,24);
manlo <= conv_std_logic_vector(124773557,28);
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(15847,24);
manlo <= conv_std_logic_vector(128828462,28);
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(15863,24);
manlo <= conv_std_logic_vector(132887467,28);
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(15879,24);
manlo <= conv_std_logic_vector(136950572,28);
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(15895,24);
manlo <= conv_std_logic_vector(141017776,28);
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(15911,24);
manlo <= conv_std_logic_vector(145089081,28);
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(15927,24);
manlo <= conv_std_logic_vector(149164485,28);
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(15943,24);
manlo <= conv_std_logic_vector(153243989,28);
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(15959,24);
manlo <= conv_std_logic_vector(157327593,28);
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(15975,24);
manlo <= conv_std_logic_vector(161415297,28);
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(15991,24);
manlo <= conv_std_logic_vector(165507101,28);
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(16007,24);
manlo <= conv_std_logic_vector(169603005,28);
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(16023,24);
manlo <= conv_std_logic_vector(173703009,28);
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(16039,24);
manlo <= conv_std_logic_vector(177807112,28);
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(16055,24);
manlo <= conv_std_logic_vector(181915316,28);
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(16071,24);
manlo <= conv_std_logic_vector(186027619,28);
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(16087,24);
manlo <= conv_std_logic_vector(190144023,28);
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(16103,24);
manlo <= conv_std_logic_vector(194264526,28);
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(16119,24);
manlo <= conv_std_logic_vector(198389129,28);
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(16135,24);
manlo <= conv_std_logic_vector(202517832,28);
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(16151,24);
manlo <= conv_std_logic_vector(206650635,28);
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(16167,24);
manlo <= conv_std_logic_vector(210787538,28);
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(16183,24);
manlo <= conv_std_logic_vector(214928541,28);
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(16199,24);
manlo <= conv_std_logic_vector(219073644,28);
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(16215,24);
manlo <= conv_std_logic_vector(223222847,28);
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(16231,24);
manlo <= conv_std_logic_vector(227376150,28);
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(16247,24);
manlo <= conv_std_logic_vector(231533553,28);
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(16263,24);
manlo <= conv_std_logic_vector(235695056,28);
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(16279,24);
manlo <= conv_std_logic_vector(239860659,28);
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(16295,24);
manlo <= conv_std_logic_vector(244030361,28);
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(16311,24);
manlo <= conv_std_logic_vector(248204164,28);
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(16327,24);
manlo <= conv_std_logic_vector(252382067,28);
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(16343,24);
manlo <= conv_std_logic_vector(256564069,28);
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(16359,24);
manlo <= conv_std_logic_vector(260750172,28);
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(16375,24);
manlo <= conv_std_logic_vector(264940375,28);
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/hcc_castytol.vhd | 10 | 6849 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOL.VHD ***
--*** ***
--*** Function: Cast Internal Double Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castytol IS
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castytol;
ARCHITECTURE rtl OF hcc_castytol IS
signal leftshiftnum, rightshiftnum : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal midpoint, maxpoint, minpoint : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal leftshiftmax, rightshiftmin : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal leftshiftbus, rightshiftbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal selectleftbit, selectleftbitdel : STD_LOGIC;
signal satshiftbit, satshiftout : STD_LOGIC;
signal zipshiftbit, zipshiftout : STD_LOGIC;
signal satout, zipout : STD_LOGIC;
signal leftshiftbusff, rightshiftbusff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftmuxff : STD_LOGIC_VECTOR (32 DOWNTO 1);
component hcc_delaybit IS
GENERIC (delay : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
component hcc_lsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_lsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftpipe64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_rsftcomb64
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
midpoint <= conv_std_logic_vector (1054,13);
maxpoint <= conv_std_logic_vector (1118,13);
minpoint <= conv_std_logic_vector (1022,13);
leftshiftnum <= aa(13 DOWNTO 1) - midpoint; -- 1054 is 1.0 point
rightshiftnum <= midpoint - aa(13 DOWNTO 1);
-- because of 64 bit Y mantissa > 32 bit long, left shift range > right shift rangre
leftshiftmax <= aa(13 DOWNTO 1) - maxpoint; -- 1118 is the max - if +ve, saturate
rightshiftmin <= aa(13 DOWNTO 1) - minpoint; -- 1022 is the min - if -ve, zero
selectleftbit <= rightshiftnum(13);
satshiftbit <= selectleftbit AND NOT(leftshiftmax(13));
zipshiftbit <= NOT(selectleftbit) AND rightshiftmin(13);
gsa: IF (normspeed = 1) GENERATE
sftlc: hcc_lsftcomb64
PORT MAP (inbus=>aa(77 DOWNTO 14),shift=>leftshiftnum(6 DOWNTO 1),
outbus=>leftshiftbus);
sftrc: hcc_rsftcomb64
PORT MAP (inbus=>aa(77 DOWNTO 14),shift=>rightshiftnum(6 DOWNTO 1),
outbus=>rightshiftbus);
END GENERATE;
gsb: IF (normspeed > 1) GENERATE
sftlp: hcc_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>aa(77 DOWNTO 14),shift=>leftshiftnum(6 DOWNTO 1),
outbus=>leftshiftbus);
sftrp: hcc_rsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>aa(77 DOWNTO 14),shift=>rightshiftnum(6 DOWNTO 1),
outbus=>rightshiftbus);
END GENERATE;
--*** DELAY CONTROL AND CONDITION SIGNALS ***
dbmux: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>selectleftbit,cc=>selectleftbitdel);
dbsat: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aasat,cc=>satout);
dbzip: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aazip,cc=>zipout);
dbsftsat: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>satshiftbit,cc=>satshiftout);
dbsftzip: hcc_delaybit
GENERIC MAP (delay=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zipshiftbit,cc=>zipshiftout);
--*** OUTPUT MUX ***
pao: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
leftshiftbusff(k) <= '0';
rightshiftbusff(k) <= '0';
shiftmuxff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
leftshiftbusff <= leftshiftbus(64 DOWNTO 33);
rightshiftbusff <= rightshiftbus(64 DOWNTO 33);
FOR k IN 1 TO 32 LOOP
shiftmuxff(k) <= (((leftshiftbusff(k) AND selectleftbitdel) OR
(rightshiftbusff(k) AND NOT(selectleftbitdel))) OR
(satout OR satshiftout)) AND
NOT(zipout OR zipshiftout);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************
--*** OUTPUT ***
--**************
cc <= shiftmuxff;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/hcc_mullongb.vhd | 10 | 2584 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULLONGB.VHD ***
--*** ***
--*** Function: 3 pipeline stage fixed point ***
--*** (long, signed & unsigned) ***
--*** behavioral ***
--*** ***
--*** 14/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mullongb IS
GENERIC (unsigned : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_mullongb;
ARCHITECTURE rtl OF hcc_mullongb IS
signal aabit, bbbit : STD_LOGIC;
signal aaff, bbff : STD_LOGIC_VECTOR (33 DOWNTO 1);
signal mulff : STD_LOGIC_VECTOR (66 DOWNTO 1);
signal muloutff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gxa: IF (unsigned = 0) GENERATE
aabit <= aa(32);
bbbit <= bb(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
aabit <= '0';
bbbit <= '0';
END GENERATE;
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 33 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 66 LOOP
mulff(k) <= '0';
END LOOP;
FOR k IN 1 TO 32 LOOP
muloutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aabit & aa;
bbff <= bbbit & bb;
mulff <= aaff * bbff;
muloutff <= mulff(32 DOWNTO 1);
END IF;
END IF;
END PROCESS;
cc <= muloutff;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/hcc_alufp1x.vhd | 10 | 10539 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1X.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_alufp1x IS
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_alufp1x;
ARCHITECTURE rtl OF hcc_alufp1x IS
type expbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
type aluleftdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal manleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal manrightff, manalignff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal invertleftff, invertrightff : STD_LOGIC;
signal invertleftdelff, invertrightdelff : STD_LOGIC;
signal invertleftnode, invertrightnode : STD_LOGIC;
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftnode, alurightnode, alucarrynode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluleftdelff : aluleftdelfftype;
signal subexpone, subexptwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal expzerochk : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzerochkff : STD_LOGIC;
signal expzerochknode : STD_LOGIC;
signal expbaseff : expbasefftype;
signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= '0';
manrightff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
expbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
invertleftff <= '0';
invertrightff <= '0';
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
addsubff(k) <= '0';
ccsatff(k) <= '0';
cczipff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--*** LEVEL 1 ***
aaff <= aa;
bbff <= bb;
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
addsubff(1) <= addsub;
FOR k IN 2 TO 3+shiftspeed LOOP
addsubff(k) <= addsubff(k-1);
END LOOP;
--*** LEVEL 2 ***
FOR k IN 1 TO mantissa LOOP
manleftff(k) <= (aaff(k+10) AND NOT(switch)) OR (bbff(k+10) AND switch);
manrightff(k) <= (bbff(k+10) AND NOT(switch)) OR (aaff(k+10) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
expbaseff(k)(10 DOWNTO 1) <= expbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff <= addsubff(1) AND switch;
invertrightff <= addsubff(1) AND NOT(switch);
ccsatff(1) <= aasatff OR bbsatff;
cczipff(1) <= aazipff AND bbzipff;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
END LOOP;
--*** LEVEL 3 or 4 ***
FOR k IN 1 TO mantissa LOOP
manalignff(k) <= (shiftbusnode(k) XOR invertrightnode) AND expzerochknode;
END LOOP;
--*** LEVEL 4 or 5 ***
aluff <= aluleftnode + alurightnode + alucarrynode;
END IF;
END IF;
END PROCESS;
gssa: IF (shiftspeed = 0) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= manleftff(k) XOR invertleftnode;
END LOOP;
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftff;
invertrightnode <= invertrightff;
expzerochknode <= expzerochk(10);
aluleftnode <= aluleftff;
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(3);
END GENERATE;
gssb: IF (shiftspeed = 1) GENERATE
psa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
aluleftdelff(1)(k) <= '0';
aluleftdelff(2)(k) <= '0';
END LOOP;
invertleftdelff <= '0';
invertrightdelff <= '0';
expzerochkff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aluleftdelff(1)(mantissa DOWNTO 1) <= manleftff;
FOR k IN 1 TO mantissa LOOP
aluleftdelff(2)(k) <= aluleftdelff(1)(k) XOR invertleftnode;
END LOOP;
invertleftdelff <= invertleftff;
invertrightdelff <= invertrightff;
expzerochkff <= expzerochk(10);
END IF;
END IF;
END PROCESS;
invertleftnode <= invertleftdelff;
invertrightnode <= invertrightdelff;
expzerochknode <= expzerochkff;
aluleftnode <= aluleftdelff(2)(mantissa DOWNTO 1);
alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(4);
END GENERATE;
alurightnode <= manalignff;
subexpone <= aaff(10 DOWNTO 1) - bbff(10 DOWNTO 1);
subexptwo <= bbff(10 DOWNTO 1) - aaff(10 DOWNTO 1);
switch <= subexpone(10);
gsa: IF (mantissa = 32) GENERATE
expzerochk <= expshiftff - "0000100000"; -- 31 ok, 32 not
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
expzerochk <= expshiftff - "0000100100"; -- 35 ok, 36 not
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & expbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
--*** DEBUG SECTION ***
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
ccexp <= expbaseff(3+shiftspeed)(10 DOWNTO 1);
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
ccman <= aluff;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/fp_sqrt_double_s5.vhd | 10 | 321991 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sqrt_double_s5
-- VHDL created on Tue Apr 9 15:17:30 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sqrt_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sqrt_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid10_fpSqrtTest_q : std_logic_vector (51 downto 0);
signal cstAllZWE_uid11_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal sBias_uid25_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal sBiasM1_uid28_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal expRMux_uid33_fpSqrtTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid33_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal inInfAndNotNeg_uid41_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid41_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid41_fpSqrtTest_q_i : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid41_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal minReg_uid42_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal minReg_uid42_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal minReg_uid42_fpSqrtTest_q_i : std_logic_vector(0 downto 0);
signal minReg_uid42_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal minInf_uid43_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal minInf_uid43_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal minInf_uid43_fpSqrtTest_q_i : std_logic_vector(0 downto 0);
signal minInf_uid43_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid47_fpSqrtTest_q : std_logic_vector(1 downto 0);
signal fracNaN_uid52_fpSqrtTest_q : std_logic_vector (51 downto 0);
signal negZero_uid56_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal negZero_uid56_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal negZero_uid56_fpSqrtTest_q_i : std_logic_vector(0 downto 0);
signal negZero_uid56_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal rndBit_uid93_sqrtPolynomialEvaluator_q : std_logic_vector (1 downto 0);
signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a : std_logic_vector (16 downto 0);
signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0);
signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr : SIGNED (34 downto 0);
signal prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0);
signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a : std_logic_vector (23 downto 0);
signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0);
signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 : std_logic_vector (49 downto 0);
signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr : SIGNED (50 downto 0);
signal prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q : std_logic_vector (49 downto 0);
signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a : std_logic_vector (32 downto 0);
signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0);
signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 : std_logic_vector (67 downto 0);
signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr : SIGNED (68 downto 0);
signal prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q : std_logic_vector (67 downto 0);
signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0);
signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0);
signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0);
signal topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid59_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0);
signal memoryC0_uid59_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0);
signal memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid60_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0);
signal memoryC0_uid60_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid60_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid60_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0);
signal memoryC0_uid60_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0);
signal memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid62_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0);
signal memoryC1_uid62_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid62_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid62_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0);
signal memoryC1_uid62_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0);
signal memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid63_sqrtTableGenerator_lutmem_ia : std_logic_vector (8 downto 0);
signal memoryC1_uid63_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid63_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid63_sqrtTableGenerator_lutmem_iq : std_logic_vector (8 downto 0);
signal memoryC1_uid63_sqrtTableGenerator_lutmem_q : std_logic_vector (8 downto 0);
signal memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid65_sqrtTableGenerator_lutmem_ia : std_logic_vector (39 downto 0);
signal memoryC2_uid65_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid65_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid65_sqrtTableGenerator_lutmem_iq : std_logic_vector (39 downto 0);
signal memoryC2_uid65_sqrtTableGenerator_lutmem_q : std_logic_vector (39 downto 0);
signal memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC3_uid67_sqrtTableGenerator_lutmem_ia : std_logic_vector (32 downto 0);
signal memoryC3_uid67_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC3_uid67_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC3_uid67_sqrtTableGenerator_lutmem_iq : std_logic_vector (32 downto 0);
signal memoryC3_uid67_sqrtTableGenerator_lutmem_q : std_logic_vector (32 downto 0);
signal memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC4_uid69_sqrtTableGenerator_lutmem_ia : std_logic_vector (23 downto 0);
signal memoryC4_uid69_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC4_uid69_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC4_uid69_sqrtTableGenerator_lutmem_iq : std_logic_vector (23 downto 0);
signal memoryC4_uid69_sqrtTableGenerator_lutmem_q : std_logic_vector (23 downto 0);
signal memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC5_uid71_sqrtTableGenerator_lutmem_ia : std_logic_vector (16 downto 0);
signal memoryC5_uid71_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC5_uid71_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC5_uid71_sqrtTableGenerator_lutmem_iq : std_logic_vector (16 downto 0);
signal memoryC5_uid71_sqrtTableGenerator_lutmem_q : std_logic_vector (16 downto 0);
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a : signal is true;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c_type;
attribute preserve of multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c : signal is true;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l_type;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p_type;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w_type;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x_type;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y_type;
type multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s : multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s_type;
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q : std_logic_vector (36 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr : UNSIGNED (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr : UNSIGNED (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr : SIGNED (54 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr : SIGNED (54 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a : std_logic_vector(84 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b : std_logic_vector(84 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o : std_logic_vector (84 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q : std_logic_vector (83 downto 0);
signal reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q : std_logic_vector (0 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0);
signal reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q : std_logic_vector (8 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q : std_logic_vector (16 downto 0);
signal reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q : std_logic_vector (16 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0);
signal reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q : std_logic_vector (23 downto 0);
signal reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0);
signal reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0);
signal reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q : std_logic_vector (32 downto 0);
signal reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q : std_logic_vector (34 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q : std_logic_vector (39 downto 0);
signal reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q : std_logic_vector (50 downto 0);
signal reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q : std_logic_vector (42 downto 0);
signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q : std_logic_vector (39 downto 0);
signal reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q : std_logic_vector (16 downto 0);
signal reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q : std_logic_vector (56 downto 0);
signal reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q : std_logic_vector (49 downto 0);
signal reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q : std_logic_vector (1 downto 0);
signal reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q : std_logic_vector (51 downto 0);
signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q : std_logic_vector (51 downto 0);
signal ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q : std_logic_vector (10 downto 0);
signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq : std_logic;
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q : signal is true;
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 : std_logic;
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq : std_logic;
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q : std_logic_vector (5 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q : signal is true;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q : signal is true;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q : signal is true;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 : std_logic;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq : std_logic;
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (32 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic;
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq : std_logic;
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSqrtTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpSqrtTest_b : std_logic_vector (10 downto 0);
signal fracX_uid7_fpSqrtTest_in : std_logic_vector (51 downto 0);
signal fracX_uid7_fpSqrtTest_b : std_logic_vector (51 downto 0);
signal signX_uid8_fpSqrtTest_in : std_logic_vector (63 downto 0);
signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid13_fpSqrtTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid13_fpSqrtTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid15_fpSqrtTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid15_fpSqrtTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid15_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid17_fpSqrtTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid17_fpSqrtTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid18_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid26_fpSqrtTest_a : std_logic_vector(11 downto 0);
signal expEvenSig_uid26_fpSqrtTest_b : std_logic_vector(11 downto 0);
signal expEvenSig_uid26_fpSqrtTest_o : std_logic_vector (11 downto 0);
signal expEvenSig_uid26_fpSqrtTest_q : std_logic_vector (11 downto 0);
signal expOddSig_uid29_fpSqrtTest_a : std_logic_vector(11 downto 0);
signal expOddSig_uid29_fpSqrtTest_b : std_logic_vector(11 downto 0);
signal expOddSig_uid29_fpSqrtTest_o : std_logic_vector (11 downto 0);
signal expOddSig_uid29_fpSqrtTest_q : std_logic_vector (11 downto 0);
signal excRNaN_uid44_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid44_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid44_fpSqrtTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid44_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expRPostExc_uid51_fpSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid51_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal fracRPostExc_uid55_fpSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid55_fpSqrtTest_q : std_logic_vector (51 downto 0);
signal ts4_uid95_sqrtPolynomialEvaluator_a : std_logic_vector(51 downto 0);
signal ts4_uid95_sqrtPolynomialEvaluator_b : std_logic_vector(51 downto 0);
signal ts4_uid95_sqrtPolynomialEvaluator_o : std_logic_vector (51 downto 0);
signal ts4_uid95_sqrtPolynomialEvaluator_q : std_logic_vector (51 downto 0);
signal sumAHighB_uid101_sqrtPolynomialEvaluator_a : std_logic_vector(57 downto 0);
signal sumAHighB_uid101_sqrtPolynomialEvaluator_b : std_logic_vector(57 downto 0);
signal sumAHighB_uid101_sqrtPolynomialEvaluator_o : std_logic_vector (57 downto 0);
signal sumAHighB_uid101_sqrtPolynomialEvaluator_q : std_logic_vector (57 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal join_uid45_fpSqrtTest_q : std_logic_vector (2 downto 0);
signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in : std_logic_vector (49 downto 0);
signal prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in : std_logic_vector (67 downto 0);
signal prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b : std_logic_vector (33 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q : std_logic_vector (53 downto 0);
signal os_uid64_sqrtTableGenerator_q : std_logic_vector (48 downto 0);
signal os_uid61_sqrtTableGenerator_q : std_logic_vector (56 downto 0);
signal s5_uid99_uid102_sqrtPolynomialEvaluator_q : std_logic_vector (59 downto 0);
signal FracX44dto0_uid37_fpSqrtTest_in : std_logic_vector (44 downto 0);
signal FracX44dto0_uid37_fpSqrtTest_b : std_logic_vector (44 downto 0);
signal fracSelIn_uid46_fpSqrtTest_q : std_logic_vector (3 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int : std_logic_vector (82 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q : std_logic_vector (82 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int : std_logic_vector (107 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q : std_logic_vector (107 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal RSqrt_uid57_fpSqrtTest_q : std_logic_vector (63 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a : std_logic_vector(5 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b : std_logic_vector(5 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid91_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT4_uid91_sqrtPolynomialEvaluator_b : std_logic_vector (39 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b : std_logic_vector (26 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal expX0_uid31_fpSqrtTest_in : std_logic_vector (0 downto 0);
signal expX0_uid31_fpSqrtTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid35_fpSqrtTest_in : std_logic_vector (51 downto 0);
signal fracXAddr_uid35_fpSqrtTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid40_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid40_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid23_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid23_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid22_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid22_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expREven_uid27_fpSqrtTest_in : std_logic_vector (11 downto 0);
signal expREven_uid27_fpSqrtTest_b : std_logic_vector (10 downto 0);
signal expROdd_uid30_fpSqrtTest_in : std_logic_vector (11 downto 0);
signal expROdd_uid30_fpSqrtTest_b : std_logic_vector (10 downto 0);
signal s4_uid96_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0);
signal s4_uid96_sqrtPolynomialEvaluator_b : std_logic_vector (50 downto 0);
signal lowRangeB_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid76_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0);
signal highBBits_uid76_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0);
signal lowRangeB_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid82_sqrtPolynomialEvaluator_in : std_logic_vector (26 downto 0);
signal highBBits_uid82_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0);
signal lowRangeB_uid87_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid87_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid88_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0);
signal highBBits_uid88_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0);
signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (5 downto 0);
signal lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (5 downto 0);
signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (34 downto 0);
signal highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0);
signal cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q : std_logic_vector (50 downto 0);
signal fracR_uid39_fpSqrtTest_in : std_logic_vector (56 downto 0);
signal fracR_uid39_fpSqrtTest_b : std_logic_vector (51 downto 0);
signal yT1_uid73_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT1_uid73_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0);
signal yT2_uid79_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT2_uid79_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal yT3_uid85_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT3_uid85_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q : std_logic_vector (108 downto 0);
signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0);
signal xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0);
signal xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal expOddSelect_uid32_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid32_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid36_fpSqrtTest_q : std_logic_vector (7 downto 0);
signal exc_N_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b : std_logic_vector (26 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in : std_logic_vector (53 downto 0);
signal prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid77_sqrtPolynomialEvaluator_a : std_logic_vector(24 downto 0);
signal sumAHighB_uid77_sqrtPolynomialEvaluator_b : std_logic_vector(24 downto 0);
signal sumAHighB_uid77_sqrtPolynomialEvaluator_o : std_logic_vector (24 downto 0);
signal sumAHighB_uid77_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0);
signal sumAHighB_uid83_sqrtPolynomialEvaluator_a : std_logic_vector(33 downto 0);
signal sumAHighB_uid83_sqrtPolynomialEvaluator_b : std_logic_vector(33 downto 0);
signal sumAHighB_uid83_sqrtPolynomialEvaluator_o : std_logic_vector (33 downto 0);
signal sumAHighB_uid83_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0);
signal sumAHighB_uid89_sqrtPolynomialEvaluator_a : std_logic_vector(40 downto 0);
signal sumAHighB_uid89_sqrtPolynomialEvaluator_b : std_logic_vector(40 downto 0);
signal sumAHighB_uid89_sqrtPolynomialEvaluator_o : std_logic_vector (40 downto 0);
signal sumAHighB_uid89_sqrtPolynomialEvaluator_q : std_logic_vector (40 downto 0);
signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0);
signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in : std_logic_vector (95 downto 0);
signal prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b : std_logic_vector (51 downto 0);
signal pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (16 downto 0);
signal InvExc_N_uid21_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid21_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid75_uid78_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0);
signal s2_uid81_uid84_sqrtPolynomialEvaluator_q : std_logic_vector (34 downto 0);
signal s3_uid87_uid90_sqrtPolynomialEvaluator_q : std_logic_vector (41 downto 0);
signal add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0);
signal lowRangeB_uid99_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid99_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid100_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0);
signal highBBits_uid100_sqrtPolynomialEvaluator_b : std_logic_vector (49 downto 0);
signal exc_R_uid24_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid24_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid24_fpSqrtTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid24_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0);
signal yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (14 downto 0);
signal yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (14 downto 0);
signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0);
signal yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in : std_logic_vector (59 downto 0);
signal R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b : std_logic_vector (42 downto 0);
signal spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (15 downto 0);
signal pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q : std_logic_vector (17 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable(LOGICAL,408)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a <= en;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q <= not ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_a;
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor(LOGICAL,435)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q <= not (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_a or ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_b);
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top(CONSTANT,431)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q <= "011000";
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp(LOGICAL,432)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_mem_top_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q);
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q <= "1" when ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_a = ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_b else "0";
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg(REG,433)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena(REG,436)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_nor_q = "1") THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd(LOGICAL,437)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_sticky_ena_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b <= en;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_a and ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_b;
--signX_uid8_fpSqrtTest(BITSELECT,7)@0
signX_uid8_fpSqrtTest_in <= a;
signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(63 downto 63);
--cstAllZWE_uid11_fpSqrtTest(CONSTANT,10)
cstAllZWE_uid11_fpSqrtTest_q <= "00000000000";
--expX_uid6_fpSqrtTest(BITSELECT,5)@0
expX_uid6_fpSqrtTest_in <= a(62 downto 0);
expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(62 downto 52);
--expXIsZero_uid13_fpSqrtTest(LOGICAL,12)@0
expXIsZero_uid13_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b;
expXIsZero_uid13_fpSqrtTest_b <= cstAllZWE_uid11_fpSqrtTest_q;
expXIsZero_uid13_fpSqrtTest_q <= "1" when expXIsZero_uid13_fpSqrtTest_a = expXIsZero_uid13_fpSqrtTest_b else "0";
--negZero_uid56_fpSqrtTest(LOGICAL,55)@0
negZero_uid56_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q;
negZero_uid56_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b;
negZero_uid56_fpSqrtTest_q_i <= negZero_uid56_fpSqrtTest_a and negZero_uid56_fpSqrtTest_b;
negZero_uid56_fpSqrtTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negZero_uid56_fpSqrtTest_q, xin => negZero_uid56_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg(DELAY,425)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => negZero_uid56_fpSqrtTest_q, xout => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt(COUNTER,427)
-- every=1, low=0, high=24, step=1, init=1
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i = 23 THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_eq = '1') THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i - 24;
ELSE
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_i,5));
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg(REG,428)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux(MUX,429)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s <= en;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux: PROCESS (ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q, ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q)
BEGIN
CASE ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_s IS
WHEN "0" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q;
WHEN "1" => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem(DUALMEM,426)
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_inputreg_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdreg_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_rdmux_q;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 25,
width_b => 1,
widthad_b => 5,
numwords_b => 25,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq,
address_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_aa,
data_a => ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_ia
);
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_reset0 <= areset;
ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_iq(0 downto 0);
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor(LOGICAL,422)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q <= not (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_a or ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_b);
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top(CONSTANT,405)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q <= "010111";
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp(LOGICAL,406)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_mem_top_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q);
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q <= "1" when ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_a = ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_b else "0";
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg(REG,407)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena(REG,423)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd(LOGICAL,424)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_a and ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_b;
--cstAllOWE_uid9_fpSqrtTest(CONSTANT,8)
cstAllOWE_uid9_fpSqrtTest_q <= "11111111111";
--sBiasM1_uid28_fpSqrtTest(CONSTANT,27)
sBiasM1_uid28_fpSqrtTest_q <= "01111111110";
--expOddSig_uid29_fpSqrtTest(ADD,28)@0
expOddSig_uid29_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b);
expOddSig_uid29_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBiasM1_uid28_fpSqrtTest_q);
expOddSig_uid29_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid29_fpSqrtTest_a) + UNSIGNED(expOddSig_uid29_fpSqrtTest_b));
expOddSig_uid29_fpSqrtTest_q <= expOddSig_uid29_fpSqrtTest_o(11 downto 0);
--expROdd_uid30_fpSqrtTest(BITSELECT,29)@0
expROdd_uid30_fpSqrtTest_in <= expOddSig_uid29_fpSqrtTest_q;
expROdd_uid30_fpSqrtTest_b <= expROdd_uid30_fpSqrtTest_in(11 downto 1);
--sBias_uid25_fpSqrtTest(CONSTANT,24)
sBias_uid25_fpSqrtTest_q <= "01111111111";
--expEvenSig_uid26_fpSqrtTest(ADD,25)@0
expEvenSig_uid26_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b);
expEvenSig_uid26_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & sBias_uid25_fpSqrtTest_q);
expEvenSig_uid26_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid26_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid26_fpSqrtTest_b));
expEvenSig_uid26_fpSqrtTest_q <= expEvenSig_uid26_fpSqrtTest_o(11 downto 0);
--expREven_uid27_fpSqrtTest(BITSELECT,26)@0
expREven_uid27_fpSqrtTest_in <= expEvenSig_uid26_fpSqrtTest_q;
expREven_uid27_fpSqrtTest_b <= expREven_uid27_fpSqrtTest_in(11 downto 1);
--expX0_uid31_fpSqrtTest(BITSELECT,30)@0
expX0_uid31_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0);
expX0_uid31_fpSqrtTest_b <= expX0_uid31_fpSqrtTest_in(0 downto 0);
--expOddSelect_uid32_fpSqrtTest(LOGICAL,31)@0
expOddSelect_uid32_fpSqrtTest_a <= expX0_uid31_fpSqrtTest_b;
expOddSelect_uid32_fpSqrtTest_q <= not expOddSelect_uid32_fpSqrtTest_a;
--expRMux_uid33_fpSqrtTest(MUX,32)@0
expRMux_uid33_fpSqrtTest_s <= expOddSelect_uid32_fpSqrtTest_q;
expRMux_uid33_fpSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid33_fpSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid33_fpSqrtTest_s IS
WHEN "0" => expRMux_uid33_fpSqrtTest_q <= expREven_uid27_fpSqrtTest_b;
WHEN "1" => expRMux_uid33_fpSqrtTest_q <= expROdd_uid30_fpSqrtTest_b;
WHEN OTHERS => expRMux_uid33_fpSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d(DELAY,248)@1
ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRMux_uid33_fpSqrtTest_q, xout => ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b(DELAY,245)@0
ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid8_fpSqrtTest_b, xout => ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid10_fpSqrtTest(CONSTANT,9)
cstAllZWF_uid10_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000000";
--fracX_uid7_fpSqrtTest(BITSELECT,6)@0
fracX_uid7_fpSqrtTest_in <= a(51 downto 0);
fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(51 downto 0);
--fracXIsZero_uid17_fpSqrtTest(LOGICAL,16)@0
fracXIsZero_uid17_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b;
fracXIsZero_uid17_fpSqrtTest_b <= cstAllZWF_uid10_fpSqrtTest_q;
fracXIsZero_uid17_fpSqrtTest_q <= "1" when fracXIsZero_uid17_fpSqrtTest_a = fracXIsZero_uid17_fpSqrtTest_b else "0";
--InvFracXIsZero_uid19_fpSqrtTest(LOGICAL,18)@0
InvFracXIsZero_uid19_fpSqrtTest_a <= fracXIsZero_uid17_fpSqrtTest_q;
InvFracXIsZero_uid19_fpSqrtTest_q <= not InvFracXIsZero_uid19_fpSqrtTest_a;
--expXIsMax_uid15_fpSqrtTest(LOGICAL,14)@0
expXIsMax_uid15_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b;
expXIsMax_uid15_fpSqrtTest_b <= cstAllOWE_uid9_fpSqrtTest_q;
expXIsMax_uid15_fpSqrtTest_q <= "1" when expXIsMax_uid15_fpSqrtTest_a = expXIsMax_uid15_fpSqrtTest_b else "0";
--exc_N_uid20_fpSqrtTest(LOGICAL,19)@0
exc_N_uid20_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q;
exc_N_uid20_fpSqrtTest_b <= InvFracXIsZero_uid19_fpSqrtTest_q;
exc_N_uid20_fpSqrtTest_q <= exc_N_uid20_fpSqrtTest_a and exc_N_uid20_fpSqrtTest_b;
--InvExc_N_uid21_fpSqrtTest(LOGICAL,20)@0
InvExc_N_uid21_fpSqrtTest_a <= exc_N_uid20_fpSqrtTest_q;
InvExc_N_uid21_fpSqrtTest_q <= not InvExc_N_uid21_fpSqrtTest_a;
--exc_I_uid18_fpSqrtTest(LOGICAL,17)@0
exc_I_uid18_fpSqrtTest_a <= expXIsMax_uid15_fpSqrtTest_q;
exc_I_uid18_fpSqrtTest_b <= fracXIsZero_uid17_fpSqrtTest_q;
exc_I_uid18_fpSqrtTest_q <= exc_I_uid18_fpSqrtTest_a and exc_I_uid18_fpSqrtTest_b;
--InvExc_I_uid22_fpSqrtTest(LOGICAL,21)@0
InvExc_I_uid22_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q;
InvExc_I_uid22_fpSqrtTest_q <= not InvExc_I_uid22_fpSqrtTest_a;
--InvExpXIsZero_uid23_fpSqrtTest(LOGICAL,22)@0
InvExpXIsZero_uid23_fpSqrtTest_a <= expXIsZero_uid13_fpSqrtTest_q;
InvExpXIsZero_uid23_fpSqrtTest_q <= not InvExpXIsZero_uid23_fpSqrtTest_a;
--exc_R_uid24_fpSqrtTest(LOGICAL,23)@0
exc_R_uid24_fpSqrtTest_a <= InvExpXIsZero_uid23_fpSqrtTest_q;
exc_R_uid24_fpSqrtTest_b <= InvExc_I_uid22_fpSqrtTest_q;
exc_R_uid24_fpSqrtTest_c <= InvExc_N_uid21_fpSqrtTest_q;
exc_R_uid24_fpSqrtTest_q <= exc_R_uid24_fpSqrtTest_a and exc_R_uid24_fpSqrtTest_b and exc_R_uid24_fpSqrtTest_c;
--minReg_uid42_fpSqrtTest(LOGICAL,41)@0
minReg_uid42_fpSqrtTest_a <= exc_R_uid24_fpSqrtTest_q;
minReg_uid42_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b;
minReg_uid42_fpSqrtTest_q_i <= minReg_uid42_fpSqrtTest_a and minReg_uid42_fpSqrtTest_b;
minReg_uid42_fpSqrtTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => minReg_uid42_fpSqrtTest_q, xin => minReg_uid42_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset);
--minInf_uid43_fpSqrtTest(LOGICAL,42)@0
minInf_uid43_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q;
minInf_uid43_fpSqrtTest_b <= signX_uid8_fpSqrtTest_b;
minInf_uid43_fpSqrtTest_q_i <= minInf_uid43_fpSqrtTest_a and minInf_uid43_fpSqrtTest_b;
minInf_uid43_fpSqrtTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => minInf_uid43_fpSqrtTest_q, xin => minInf_uid43_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1(REG,155)@0
reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q <= exc_N_uid20_fpSqrtTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid44_fpSqrtTest(LOGICAL,43)@1
excRNaN_uid44_fpSqrtTest_a <= reg_exc_N_uid20_fpSqrtTest_0_to_excRNaN_uid44_fpSqrtTest_1_q;
excRNaN_uid44_fpSqrtTest_b <= minInf_uid43_fpSqrtTest_q;
excRNaN_uid44_fpSqrtTest_c <= minReg_uid42_fpSqrtTest_q;
excRNaN_uid44_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_a or excRNaN_uid44_fpSqrtTest_b or excRNaN_uid44_fpSqrtTest_c;
--InvSignX_uid40_fpSqrtTest(LOGICAL,39)@0
InvSignX_uid40_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b;
InvSignX_uid40_fpSqrtTest_q <= not InvSignX_uid40_fpSqrtTest_a;
--inInfAndNotNeg_uid41_fpSqrtTest(LOGICAL,40)@0
inInfAndNotNeg_uid41_fpSqrtTest_a <= exc_I_uid18_fpSqrtTest_q;
inInfAndNotNeg_uid41_fpSqrtTest_b <= InvSignX_uid40_fpSqrtTest_q;
inInfAndNotNeg_uid41_fpSqrtTest_q_i <= inInfAndNotNeg_uid41_fpSqrtTest_a and inInfAndNotNeg_uid41_fpSqrtTest_b;
inInfAndNotNeg_uid41_fpSqrtTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => inInfAndNotNeg_uid41_fpSqrtTest_q, xin => inInfAndNotNeg_uid41_fpSqrtTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0(REG,156)@0
reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q <= expXIsZero_uid13_fpSqrtTest_q;
END IF;
END IF;
END PROCESS;
--join_uid45_fpSqrtTest(BITJOIN,44)@1
join_uid45_fpSqrtTest_q <= excRNaN_uid44_fpSqrtTest_q & inInfAndNotNeg_uid41_fpSqrtTest_q & reg_expXIsZero_uid13_fpSqrtTest_0_to_join_uid45_fpSqrtTest_0_q;
--fracSelIn_uid46_fpSqrtTest(BITJOIN,45)@1
fracSelIn_uid46_fpSqrtTest_q <= ld_signX_uid8_fpSqrtTest_b_to_fracSelIn_uid46_fpSqrtTest_b_q & join_uid45_fpSqrtTest_q;
--fracSel_uid47_fpSqrtTest(LOOKUP,46)@1
fracSel_uid47_fpSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracSel_uid47_fpSqrtTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (fracSelIn_uid46_fpSqrtTest_q) IS
WHEN "0000" => fracSel_uid47_fpSqrtTest_q <= "01";
WHEN "0001" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "0010" => fracSel_uid47_fpSqrtTest_q <= "10";
WHEN "0011" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "0100" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "0101" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "0110" => fracSel_uid47_fpSqrtTest_q <= "10";
WHEN "0111" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "1000" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1001" => fracSel_uid47_fpSqrtTest_q <= "00";
WHEN "1010" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1011" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1100" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1101" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1110" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN "1111" => fracSel_uid47_fpSqrtTest_q <= "11";
WHEN OTHERS =>
fracSel_uid47_fpSqrtTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid51_fpSqrtTest(MUX,50)@2
expRPostExc_uid51_fpSqrtTest_s <= fracSel_uid47_fpSqrtTest_q;
expRPostExc_uid51_fpSqrtTest: PROCESS (expRPostExc_uid51_fpSqrtTest_s, en, cstAllZWE_uid11_fpSqrtTest_q, ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q, cstAllOWE_uid9_fpSqrtTest_q, cstAllOWE_uid9_fpSqrtTest_q)
BEGIN
CASE expRPostExc_uid51_fpSqrtTest_s IS
WHEN "00" => expRPostExc_uid51_fpSqrtTest_q <= cstAllZWE_uid11_fpSqrtTest_q;
WHEN "01" => expRPostExc_uid51_fpSqrtTest_q <= ld_expRMux_uid33_fpSqrtTest_q_to_expRPostExc_uid51_fpSqrtTest_d_q;
WHEN "10" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q;
WHEN "11" => expRPostExc_uid51_fpSqrtTest_q <= cstAllOWE_uid9_fpSqrtTest_q;
WHEN OTHERS => expRPostExc_uid51_fpSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg(DELAY,412)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid51_fpSqrtTest_q, xout => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt(COUNTER,401)
-- every=1, low=0, high=23, step=1, init=1
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i = 22 THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_eq = '1') THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i - 23;
ELSE
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_i,5));
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg(REG,402)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux(MUX,403)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s <= en;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux: PROCESS (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q, ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem(DUALMEM,413)
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_inputreg_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 24,
width_b => 11,
widthad_b => 5,
numwords_b => 24,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_iq(10 downto 0);
--fracNaN_uid52_fpSqrtTest(CONSTANT,51)
fracNaN_uid52_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000001";
--fracXAddr_uid35_fpSqrtTest(BITSELECT,34)@0
fracXAddr_uid35_fpSqrtTest_in <= fracX_uid7_fpSqrtTest_b;
fracXAddr_uid35_fpSqrtTest_b <= fracXAddr_uid35_fpSqrtTest_in(51 downto 45);
--addrTable_uid36_fpSqrtTest(BITJOIN,35)@0
addrTable_uid36_fpSqrtTest_q <= expOddSelect_uid32_fpSqrtTest_q & fracXAddr_uid35_fpSqrtTest_b;
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0(REG,161)@0
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q <= addrTable_uid36_fpSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC5_uid71_sqrtTableGenerator_lutmem(DUALMEM,139)@1
memoryC5_uid71_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC5_uid71_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC5_uid71_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q;
memoryC5_uid71_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 17,
widthad_a => 8,
numwords_a => 256,
width_b => 17,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC5_uid71_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC5_uid71_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC5_uid71_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC5_uid71_sqrtTableGenerator_lutmem_iq,
address_a => memoryC5_uid71_sqrtTableGenerator_lutmem_aa,
data_a => memoryC5_uid71_sqrtTableGenerator_lutmem_ia
);
memoryC5_uid71_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC5_uid71_sqrtTableGenerator_lutmem_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_iq(16 downto 0);
--reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1(REG,163)@3
reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q <= memoryC5_uid71_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg(DELAY,398)
ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSqrtTest_b, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a(DELAY,229)@0
ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_inputreg_q, xout => ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX44dto0_uid37_fpSqrtTest(BITSELECT,36)@3
FracX44dto0_uid37_fpSqrtTest_in <= ld_fracX_uid7_fpSqrtTest_b_to_FracX44dto0_uid37_fpSqrtTest_a_q(44 downto 0);
FracX44dto0_uid37_fpSqrtTest_b <= FracX44dto0_uid37_fpSqrtTest_in(44 downto 0);
--yT1_uid73_sqrtPolynomialEvaluator(BITSELECT,72)@3
yT1_uid73_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b;
yT1_uid73_sqrtPolynomialEvaluator_b <= yT1_uid73_sqrtPolynomialEvaluator_in(44 downto 28);
--reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0(REG,162)@3
reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q <= yT1_uid73_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator(MULT,103)@4
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a),18)) * SIGNED(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b);
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_a <= reg_yT1_uid73_sqrtPolynomialEvaluator_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_0_q;
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_b <= reg_memoryC5_uid71_sqrtTableGenerator_lutmem_0_to_prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_1_q;
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator(BITSELECT,104)@7
prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in <= prodXY_uid104_pT1_uid74_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_in(33 downto 16);
--highBBits_uid76_sqrtPolynomialEvaluator(BITSELECT,75)@7
highBBits_uid76_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b;
highBBits_uid76_sqrtPolynomialEvaluator_b <= highBBits_uid76_sqrtPolynomialEvaluator_in(17 downto 1);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a(DELAY,363)@0
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0(REG,164)@3
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid69_sqrtTableGenerator_lutmem(DUALMEM,138)@4
memoryC4_uid69_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC4_uid69_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC4_uid69_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC4_uid69_sqrtTableGenerator_lutmem_0_q;
memoryC4_uid69_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 8,
numwords_a => 256,
width_b => 24,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC4_uid69_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid69_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid69_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid69_sqrtTableGenerator_lutmem_iq,
address_a => memoryC4_uid69_sqrtTableGenerator_lutmem_aa,
data_a => memoryC4_uid69_sqrtTableGenerator_lutmem_ia
);
memoryC4_uid69_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC4_uid69_sqrtTableGenerator_lutmem_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_iq(23 downto 0);
--reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0(REG,165)@6
reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q <= memoryC4_uid69_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid77_sqrtPolynomialEvaluator(ADD,76)@7
sumAHighB_uid77_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((24 downto 24 => reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q(23)) & reg_memoryC4_uid69_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid77_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid77_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((24 downto 17 => highBBits_uid76_sqrtPolynomialEvaluator_b(16)) & highBBits_uid76_sqrtPolynomialEvaluator_b);
sumAHighB_uid77_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid77_sqrtPolynomialEvaluator_b));
sumAHighB_uid77_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_o(24 downto 0);
--lowRangeB_uid75_sqrtPolynomialEvaluator(BITSELECT,74)@7
lowRangeB_uid75_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid105_pT1_uid74_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid75_sqrtPolynomialEvaluator_b <= lowRangeB_uid75_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid75_uid78_sqrtPolynomialEvaluator(BITJOIN,77)@7
s1_uid75_uid78_sqrtPolynomialEvaluator_q <= sumAHighB_uid77_sqrtPolynomialEvaluator_q & lowRangeB_uid75_sqrtPolynomialEvaluator_b;
--reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1(REG,167)@7
reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q <= s1_uid75_uid78_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor(LOGICAL,459)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q <= not (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_a or ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_b);
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg(REG,457)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena(REG,460)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,461)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_a and ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_b;
--yT2_uid79_sqrtPolynomialEvaluator(BITSELECT,78)@3
yT2_uid79_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b;
yT2_uid79_sqrtPolynomialEvaluator_b <= yT2_uid79_sqrtPolynomialEvaluator_in(44 downto 21);
--reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0(REG,166)@3
reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q <= yT2_uid79_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg(DELAY,451)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q, xout => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,453)
-- every=1, low=0, high=1, step=1, init=1
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_i,1));
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg(REG,454)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,455)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,452)
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_inputreg_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_iq(23 downto 0);
--prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator(MULT,106)@8
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a),25)) * SIGNED(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b);
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a <= ld_reg_yT2_uid79_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_0_q_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_a_replace_mem_q;
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_b <= reg_s1_uid75_uid78_sqrtPolynomialEvaluator_0_to_prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_1_q;
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_pr,50));
END IF;
END IF;
END PROCESS;
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator(BITSELECT,107)@11
prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in <= prodXY_uid107_pT2_uid80_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_in(49 downto 23);
--highBBits_uid82_sqrtPolynomialEvaluator(BITSELECT,81)@11
highBBits_uid82_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b;
highBBits_uid82_sqrtPolynomialEvaluator_b <= highBBits_uid82_sqrtPolynomialEvaluator_in(26 downto 1);
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor(LOGICAL,485)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,481)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q <= "0100";
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,482)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg(REG,483)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena(REG,486)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,487)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg(DELAY,462)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_addrTable_uid36_fpSqrtTest_0_to_memoryC5_uid71_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,477)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,3));
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,478)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,479)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,476)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC3_uid67_sqrtTableGenerator_lutmem(DUALMEM,137)@8
memoryC3_uid67_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC3_uid67_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC3_uid67_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC3_uid67_sqrtTableGenerator_lutmem_0_q_to_memoryC3_uid67_sqrtTableGenerator_lutmem_a_replace_mem_q;
memoryC3_uid67_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 8,
numwords_a => 256,
width_b => 33,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC3_uid67_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid67_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid67_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid67_sqrtTableGenerator_lutmem_iq,
address_a => memoryC3_uid67_sqrtTableGenerator_lutmem_aa,
data_a => memoryC3_uid67_sqrtTableGenerator_lutmem_ia
);
memoryC3_uid67_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC3_uid67_sqrtTableGenerator_lutmem_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_iq(32 downto 0);
--reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0(REG,169)@10
reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q <= memoryC3_uid67_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid83_sqrtPolynomialEvaluator(ADD,82)@11
sumAHighB_uid83_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((33 downto 33 => reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q(32)) & reg_memoryC3_uid67_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid83_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid83_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((33 downto 26 => highBBits_uid82_sqrtPolynomialEvaluator_b(25)) & highBBits_uid82_sqrtPolynomialEvaluator_b);
sumAHighB_uid83_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid83_sqrtPolynomialEvaluator_b));
sumAHighB_uid83_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_o(33 downto 0);
--lowRangeB_uid81_sqrtPolynomialEvaluator(BITSELECT,80)@11
lowRangeB_uid81_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid108_pT2_uid80_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid81_sqrtPolynomialEvaluator_b <= lowRangeB_uid81_sqrtPolynomialEvaluator_in(0 downto 0);
--s2_uid81_uid84_sqrtPolynomialEvaluator(BITJOIN,83)@11
s2_uid81_uid84_sqrtPolynomialEvaluator_q <= sumAHighB_uid83_sqrtPolynomialEvaluator_q & lowRangeB_uid81_sqrtPolynomialEvaluator_b;
--reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1(REG,171)@11
reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q <= s2_uid81_uid84_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,524)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_a or ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_b);
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top(CONSTANT,520)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q <= "0101";
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp(LOGICAL,521)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_mem_top_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q);
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q <= "1" when ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_a = ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_b else "0";
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg(REG,522)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,525)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,526)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_sticky_ena_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_b;
--yT3_uid85_sqrtPolynomialEvaluator(BITSELECT,84)@3
yT3_uid85_sqrtPolynomialEvaluator_in <= FracX44dto0_uid37_fpSqrtTest_b;
yT3_uid85_sqrtPolynomialEvaluator_b <= yT3_uid85_sqrtPolynomialEvaluator_in(44 downto 12);
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,514)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => yT3_uid85_sqrtPolynomialEvaluator_b, xout => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,516)
-- every=1, low=0, high=5, step=1, init=1
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i = 4 THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_eq = '1') THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i - 5;
ELSE
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,3));
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,517)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,518)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q;
WHEN "1" => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,515)
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_inputreg_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdreg_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_rdmux_q;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 3,
numwords_a => 6,
width_b => 33,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq,
address_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_aa,
data_a => ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_ia
);
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset;
ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_iq(32 downto 0);
--reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0(REG,170)@11
reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q <= ld_yT3_uid85_sqrtPolynomialEvaluator_b_to_reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator(MULT,109)@12
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a),34)) * SIGNED(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b);
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_a <= reg_yT3_uid85_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_0_q;
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_b <= reg_s2_uid81_uid84_sqrtPolynomialEvaluator_0_to_prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_1_q;
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_pr,68));
END IF;
END IF;
END PROCESS;
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator(BITSELECT,110)@15
prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in <= prodXY_uid110_pT3_uid86_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_in(67 downto 34);
--highBBits_uid88_sqrtPolynomialEvaluator(BITSELECT,87)@15
highBBits_uid88_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b;
highBBits_uid88_sqrtPolynomialEvaluator_b <= highBBits_uid88_sqrtPolynomialEvaluator_in(33 downto 1);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,537)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_b);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,533)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01000";
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,534)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_mem_top_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_b else "0";
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,535)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,538)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,539)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,501)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid36_fpSqrtTest_q, xout => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,529)
-- every=1, low=0, high=8, step=1, init=1
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 7 THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 8;
ELSE
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4));
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,530)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,531)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,528)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0(REG,172)@11
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid65_sqrtTableGenerator_lutmem(DUALMEM,136)@12
memoryC2_uid65_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid65_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid65_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC2_uid65_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid65_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 256,
width_b => 40,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC2_uid65_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid65_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid65_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid65_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid65_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid65_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid65_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid65_sqrtTableGenerator_lutmem_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_iq(39 downto 0);
--reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0(REG,173)@14
reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q <= memoryC2_uid65_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid89_sqrtPolynomialEvaluator(ADD,88)@15
sumAHighB_uid89_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q(39)) & reg_memoryC2_uid65_sqrtTableGenerator_lutmem_0_to_sumAHighB_uid89_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid89_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((40 downto 33 => highBBits_uid88_sqrtPolynomialEvaluator_b(32)) & highBBits_uid88_sqrtPolynomialEvaluator_b);
sumAHighB_uid89_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid89_sqrtPolynomialEvaluator_b));
sumAHighB_uid89_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_o(40 downto 0);
--lowRangeB_uid87_sqrtPolynomialEvaluator(BITSELECT,86)@15
lowRangeB_uid87_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid111_pT3_uid86_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid87_sqrtPolynomialEvaluator_b <= lowRangeB_uid87_sqrtPolynomialEvaluator_in(0 downto 0);
--s3_uid87_uid90_sqrtPolynomialEvaluator(BITJOIN,89)@15
s3_uid87_uid90_sqrtPolynomialEvaluator_q <= sumAHighB_uid89_sqrtPolynomialEvaluator_q & lowRangeB_uid87_sqrtPolynomialEvaluator_b;
--yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,118)@15
yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q;
yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 24);
--reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9(REG,177)@15
reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q <= yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor(LOGICAL,448)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_b);
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,444)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q <= "01001";
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp(LOGICAL,445)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_mem_top_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg(REG,446)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena(REG,449)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,450)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b <= en;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_b;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg(DELAY,438)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => FracX44dto0_uid37_fpSqrtTest_b, xout => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,440)
-- every=1, low=0, high=9, step=1, init=1
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 8 THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 9;
ELSE
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_i,4));
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg(REG,441)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,442)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s <= en;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,439)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 4,
numwords_a => 10,
width_b => 45,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0);
--yT4_uid91_sqrtPolynomialEvaluator(BITSELECT,90)@15
yT4_uid91_sqrtPolynomialEvaluator_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_replace_mem_q;
yT4_uid91_sqrtPolynomialEvaluator_b <= yT4_uid91_sqrtPolynomialEvaluator_in(44 downto 5);
--xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,117)@15
xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b(12 downto 0);
xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_in(12 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,120)@15
pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q <= xBottomBits_uid118_pT4_uid92_sqrtPolynomialEvaluator_b & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7(REG,176)@15
reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q <= pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,116)@15
yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q(14 downto 0);
yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b <= yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_in(14 downto 0);
--spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,119)@15
spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q <= GND_q & yBottomBits_uid117_pT4_uid92_sqrtPolynomialEvaluator_b;
--pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,121)@15
pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid117_uid120_pT4_uid92_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6(REG,175)@15
reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,115)@15
xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b;
xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 22);
--reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4(REG,174)@15
reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q <= xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma(CHAINMULTADD,140)@16
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0),19));
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1),19));
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(0) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_l(1) * multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(0),38) + RESIZE(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_p(1),38);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_w(0);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_x(0);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid116_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_4_q),18);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid118_uid121_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_7_q),18);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid117_uid122_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_6_q),18);
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid119_pT4_uid92_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,123)@19
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_cma_q;
multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_in(36 downto 2);
--highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,125)@19
highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b;
highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b <= highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_in(34 downto 6);
--yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,113)@15
yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in <= s3_uid87_uid90_sqrtPolynomialEvaluator_q;
yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_in(41 downto 15);
--reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1(REG,179)@15
reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,112)@15
xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in <= yT4_uid91_sqrtPolynomialEvaluator_b;
xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_in(39 downto 13);
--reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0(REG,178)@15
reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q <= xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator(MULT,114)@16
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b);
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= (others => '0');
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= (others => '0');
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_a <= reg_xTop27Bits_uid113_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_0_q;
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_b <= reg_yTop27Bits_uid114_pT4_uid92_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_1_q;
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q <= topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator(ADD,126)@19
sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q(53)) & topProd_uid115_pT4_uid92_sqrtPolynomialEvaluator_q);
sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b(28)) & highBBits_uid126_pT4_uid92_sqrtPolynomialEvaluator_b);
sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_b));
sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_o(54 downto 0);
--lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,124)@19
lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid120_pT4_uid92_sqrtPolynomialEvaluator_b(5 downto 0);
lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b <= lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_in(5 downto 0);
--add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator(BITJOIN,127)@19
add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q <= sumAHighB_uid127_pT4_uid92_sqrtPolynomialEvaluator_q & lowRangeB_uid125_pT4_uid92_sqrtPolynomialEvaluator_b;
--R_uid129_pT4_uid92_sqrtPolynomialEvaluator(BITSELECT,128)@19
R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in <= add0_uid125_uid128_pT4_uid92_sqrtPolynomialEvaluator_q(59 downto 0);
R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_in(59 downto 17);
--reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1(REG,181)@19
reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= "0000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q <= R_uid129_pT4_uid92_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,511)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_b);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top(CONSTANT,507)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q <= "01100";
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp(LOGICAL,508)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_mem_top_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q <= "1" when ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_a = ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_b else "0";
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg(REG,509)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,512)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,513)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt(COUNTER,503)
-- every=1, low=0, high=12, step=1, init=1
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i = 11 THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i - 12;
ELSE
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_i,4));
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg(REG,504)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux(MUX,505)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux: PROCESS (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q, ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,502)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_rdmux_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 13,
width_b => 8,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0(REG,157)@15
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid63_sqrtTableGenerator_lutmem(DUALMEM,135)@16
memoryC1_uid63_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid63_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid63_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid63_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 8,
numwords_a => 256,
width_b => 9,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC1_uid63_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid63_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid63_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid63_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid63_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid63_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid63_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid63_sqrtTableGenerator_lutmem_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_iq(8 downto 0);
--reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1(REG,160)@18
reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q <= memoryC1_uid63_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid62_sqrtTableGenerator_lutmem(DUALMEM,134)@16
memoryC1_uid62_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid62_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid62_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_q;
memoryC1_uid62_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 256,
width_b => 40,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC1_uid62_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid62_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid62_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid62_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid62_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid62_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid62_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid62_sqrtTableGenerator_lutmem_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_iq(39 downto 0);
--reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0(REG,159)@18
reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q <= memoryC1_uid62_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid64_sqrtTableGenerator(BITJOIN,63)@19
os_uid64_sqrtTableGenerator_q <= reg_memoryC1_uid63_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_1_q & reg_memoryC1_uid62_sqrtTableGenerator_lutmem_0_to_os_uid64_sqrtTableGenerator_0_q;
--rndBit_uid93_sqrtPolynomialEvaluator(CONSTANT,92)
rndBit_uid93_sqrtPolynomialEvaluator_q <= "01";
--cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator(BITJOIN,93)@19
cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q <= os_uid64_sqrtTableGenerator_q & rndBit_uid93_sqrtPolynomialEvaluator_q;
--reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0(REG,180)@19
reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ts4_uid95_sqrtPolynomialEvaluator(ADD,94)@20
ts4_uid95_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((51 downto 51 => reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q(50)) & reg_cIncludingRoundingBit_uid94_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_0_q);
ts4_uid95_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((51 downto 43 => reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q(42)) & reg_R_uid129_pT4_uid92_sqrtPolynomialEvaluator_0_to_ts4_uid95_sqrtPolynomialEvaluator_1_q);
ts4_uid95_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid95_sqrtPolynomialEvaluator_a) + SIGNED(ts4_uid95_sqrtPolynomialEvaluator_b));
ts4_uid95_sqrtPolynomialEvaluator_q <= ts4_uid95_sqrtPolynomialEvaluator_o(51 downto 0);
--s4_uid96_sqrtPolynomialEvaluator(BITSELECT,95)@20
s4_uid96_sqrtPolynomialEvaluator_in <= ts4_uid95_sqrtPolynomialEvaluator_q;
s4_uid96_sqrtPolynomialEvaluator_b <= s4_uid96_sqrtPolynomialEvaluator_in(51 downto 1);
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1(BITSELECT,144)@20
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in <= STD_LOGIC_VECTOR((53 downto 51 => s4_uid96_sqrtPolynomialEvaluator_b(50)) & s4_uid96_sqrtPolynomialEvaluator_b);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_in(53 downto 27);
--reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1(REG,187)@20
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_b;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor(LOGICAL,498)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q <= not (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_a or ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_b);
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top(CONSTANT,494)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q <= "01110";
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp(LOGICAL,495)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_mem_top_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q <= "1" when ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_a = ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_b else "0";
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg(REG,496)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena(REG,499)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_nor_q = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd(LOGICAL,500)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_sticky_ena_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b <= en;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_a and ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_b;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt(COUNTER,490)
-- every=1, low=0, high=14, step=1, init=1
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i = 13 THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_eq = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i - 14;
ELSE
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_i,4));
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg(REG,491)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux(MUX,492)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s <= en;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux: PROCESS (ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q, ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q)
BEGIN
CASE ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_s IS
WHEN "0" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q;
WHEN "1" => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem(DUALMEM,489)
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_yT4_uid91_sqrtPolynomialEvaluator_a_inputreg_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdreg_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_rdmux_q;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 4,
numwords_a => 15,
width_b => 45,
widthad_b => 4,
numwords_b => 15,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq,
address_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_aa,
data_a => ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_ia
);
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_reset0 <= areset;
ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_iq(44 downto 0);
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1(BITSELECT,142)@20
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in <= STD_LOGIC_VECTOR("000000000" & ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_in(53 downto 27);
--reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0(REG,184)@20
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1(MULT,148)@21
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a(DELAY,349)@24
ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2(BITSHIFT,152)@26
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b1_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q_int(107 downto 0);
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0(BITSELECT,141)@20
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in <= ld_FracX44dto0_uid37_fpSqrtTest_b_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_a_replace_mem_q(26 downto 0);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_in(26 downto 0);
--reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0(REG,182)@20
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1(MULT,147)@21
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr <= signed(resize(UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a),28)) * SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_1_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_pr,54));
END IF;
END IF;
END PROCESS;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0(BITSELECT,143)@20
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in <= s4_uid96_sqrtPolynomialEvaluator_b(26 downto 0);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_in(26 downto 0);
--reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1(REG,183)@20
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0(MULT,146)@21
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_1_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_0_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0(ADD,149)@24
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR('0' & "00" & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a1_b0_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR((56 downto 54 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q(53)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b1_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_b));
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_o(55 downto 0);
--ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a(DELAY,348)@24
ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q, xout => ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1(BITSHIFT,151)@25
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int <= ld_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_addcol_1_add_0_0_q_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_a_q & "000000000000000000000000000";
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q_int(82 downto 0);
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0(MULT,145)@21
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr <= UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a) * UNSIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= (others => '0');
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_a <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_0_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_b <= reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_b_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_1_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1 <= STD_LOGIC_VECTOR(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0(BITSHIFT,150)@24
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_a0_b0_q;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q_int(53 downto 0);
--reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0(REG,188)@24
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0(ADD,153)@25
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_0_0_to_prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_0_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q(82)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_1_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_b));
END IF;
END PROCESS;
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_o(83 downto 0);
--prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0(ADD,154)@26
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a <= STD_LOGIC_VECTOR((108 downto 84 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q(83)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_0_0_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b <= STD_LOGIC_VECTOR((108 downto 108 => prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q(107)) & prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_align_2_q);
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_a) + SIGNED(prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_b));
prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_o(108 downto 0);
--prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator(BITSELECT,130)@26
prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in <= prodXY_uid130_pT5_uid98_sqrtPolynomialEvaluator_result_add_1_0_q(95 downto 0);
prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_in(95 downto 44);
--highBBits_uid100_sqrtPolynomialEvaluator(BITSELECT,99)@26
highBBits_uid100_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b;
highBBits_uid100_sqrtPolynomialEvaluator_b <= highBBits_uid100_sqrtPolynomialEvaluator_in(51 downto 2);
--reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1(REG,196)@26
reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q <= highBBits_uid100_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor(LOGICAL,472)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q <= not (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_a or ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_b);
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top(CONSTANT,468)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q <= "010011";
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp(LOGICAL,469)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_mem_top_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q <= "1" when ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_a = ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_b else "0";
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg(REG,470)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena(REG,473)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_nor_q = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd(LOGICAL,474)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_sticky_ena_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b <= en;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_a and ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_b;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt(COUNTER,464)
-- every=1, low=0, high=19, step=1, init=1
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i = 18 THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i - 19;
ELSE
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_i,5));
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg(REG,465)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux(MUX,466)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s <= en;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux: PROCESS (ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q, ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem(DUALMEM,463)
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_inputreg_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 20,
width_b => 8,
widthad_b => 5,
numwords_b => 20,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq,
address_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_aa,
data_a => ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_ia
);
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_iq(7 downto 0);
--memoryC0_uid60_sqrtTableGenerator_lutmem(DUALMEM,133)@23
memoryC0_uid60_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid60_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid60_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_mem_q;
memoryC0_uid60_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 17,
widthad_a => 8,
numwords_a => 256,
width_b => 17,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC0_uid60_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid60_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid60_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid60_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid60_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid60_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid60_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid60_sqrtTableGenerator_lutmem_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_iq(16 downto 0);
--reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1(REG,194)@25
reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q <= memoryC0_uid60_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,550)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_b);
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,551)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,552)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,541)
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC1_uid62_sqrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdreg_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid60_sqrtTableGenerator_lutmem_0_q_to_memoryC0_uid60_sqrtTableGenerator_lutmem_a_replace_rdmux_q;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 20,
width_b => 8,
widthad_b => 5,
numwords_b => 20,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0(REG,191)@22
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid36_fpSqrtTest_q_to_reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid59_sqrtTableGenerator_lutmem(DUALMEM,132)@23
memoryC0_uid59_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid59_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid59_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid36_fpSqrtTest_0_to_memoryC0_uid59_sqrtTableGenerator_lutmem_0_q;
memoryC0_uid59_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 256,
width_b => 40,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sqrt_double_s5_memoryC0_uid59_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid59_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid59_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid59_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid59_sqrtTableGenerator_lutmem_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_iq(39 downto 0);
--reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0(REG,193)@25
reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q <= memoryC0_uid59_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid61_sqrtTableGenerator(BITJOIN,60)@26
os_uid61_sqrtTableGenerator_q <= reg_memoryC0_uid60_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_1_q & reg_memoryC0_uid59_sqrtTableGenerator_lutmem_0_to_os_uid61_sqrtTableGenerator_0_q;
--reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0(REG,195)@26
reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q <= os_uid61_sqrtTableGenerator_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid101_sqrtPolynomialEvaluator(ADD,100)@27
sumAHighB_uid101_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((57 downto 57 => reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q(56)) & reg_os_uid61_sqrtTableGenerator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid101_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((57 downto 50 => reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q(49)) & reg_highBBits_uid100_sqrtPolynomialEvaluator_0_to_sumAHighB_uid101_sqrtPolynomialEvaluator_1_q);
sumAHighB_uid101_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid101_sqrtPolynomialEvaluator_b));
sumAHighB_uid101_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_o(57 downto 0);
--lowRangeB_uid99_sqrtPolynomialEvaluator(BITSELECT,98)@26
lowRangeB_uid99_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid131_pT5_uid98_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid99_sqrtPolynomialEvaluator_b <= lowRangeB_uid99_sqrtPolynomialEvaluator_in(1 downto 0);
--reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0(REG,197)@26
reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q <= lowRangeB_uid99_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--s5_uid99_uid102_sqrtPolynomialEvaluator(BITJOIN,101)@27
s5_uid99_uid102_sqrtPolynomialEvaluator_q <= sumAHighB_uid101_sqrtPolynomialEvaluator_q & reg_lowRangeB_uid99_sqrtPolynomialEvaluator_0_to_s5_uid99_uid102_sqrtPolynomialEvaluator_0_q;
--fracR_uid39_fpSqrtTest(BITSELECT,38)@27
fracR_uid39_fpSqrtTest_in <= s5_uid99_uid102_sqrtPolynomialEvaluator_q(56 downto 0);
fracR_uid39_fpSqrtTest_b <= fracR_uid39_fpSqrtTest_in(56 downto 5);
--reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3(REG,198)@27
reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q <= fracR_uid39_fpSqrtTest_b;
END IF;
END IF;
END PROCESS;
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor(LOGICAL,409)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_notEnable_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q <= not (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_a or ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_b);
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena(REG,410)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_nor_q = "1") THEN
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd(LOGICAL,411)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_sticky_ena_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b <= en;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_a and ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_b;
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg(DELAY,399)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => fracSel_uid47_fpSqrtTest_q, xout => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem(DUALMEM,400)
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_inputreg_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdreg_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_rdmux_q;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 24,
width_b => 2,
widthad_b => 5,
numwords_b => 24,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq,
address_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_aa,
data_a => ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_ia
);
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_reset0 <= areset;
ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_iq(1 downto 0);
--fracRPostExc_uid55_fpSqrtTest(MUX,54)@28
fracRPostExc_uid55_fpSqrtTest_s <= ld_fracSel_uid47_fpSqrtTest_q_to_fracRPostExc_uid55_fpSqrtTest_b_replace_mem_q;
fracRPostExc_uid55_fpSqrtTest: PROCESS (fracRPostExc_uid55_fpSqrtTest_s, en, cstAllZWF_uid10_fpSqrtTest_q, reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q, cstAllZWF_uid10_fpSqrtTest_q, fracNaN_uid52_fpSqrtTest_q)
BEGIN
CASE fracRPostExc_uid55_fpSqrtTest_s IS
WHEN "00" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q;
WHEN "01" => fracRPostExc_uid55_fpSqrtTest_q <= reg_fracR_uid39_fpSqrtTest_0_to_fracRPostExc_uid55_fpSqrtTest_3_q;
WHEN "10" => fracRPostExc_uid55_fpSqrtTest_q <= cstAllZWF_uid10_fpSqrtTest_q;
WHEN "11" => fracRPostExc_uid55_fpSqrtTest_q <= fracNaN_uid52_fpSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid55_fpSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid57_fpSqrtTest(BITJOIN,56)@28
RSqrt_uid57_fpSqrtTest_q <= ld_negZero_uid56_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_c_replace_mem_q & ld_expRPostExc_uid51_fpSqrtTest_q_to_RSqrt_uid57_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid55_fpSqrtTest_q;
--xOut(GPOUT,4)@28
q <= RSqrt_uid57_fpSqrtTest_q;
end normal;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_cordic_m1.vhd | 10 | 13050 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_M1.VHD ***
--*** ***
--*** Function: SIN and COS CORDIC with early ***
--*** Termination Algorithm (Multiplier) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. estimates lower iterations of cordic ***
--*** using Z value and multiplier ***
--*** 2. multiplier at level (depth-4) for best ***
--*** results try depth = width/2+4 ***
--***************************************************
ENTITY fp_cordic_m1 IS
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC; -- 0 = cos, 1 = sin
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_m1;
ARCHITECTURE rtl of fp_cordic_m1 IS
constant cordic_depth : positive := depth - 4;
type datapathtype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
type atantype IS ARRAY (cordic_depth DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal indexpointnum, startindex : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal indexbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal sincosbitff : STD_LOGIC_VECTOR (cordic_depth+3 DOWNTO 1);
signal x_start_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal radians_load_node : STD_LOGIC_VECTOR (width DOWNTO 1);
signal x_pipeff : datapathtype;
signal y_pipeff : datapathtype;
signal z_pipeff : datapathtype;
signal x_prenode, x_prenodeone, x_prenodetwo : datapathtype;
signal x_subnode, x_pipenode : datapathtype;
signal y_prenode, y_prenodeone, y_prenodetwo : datapathtype;
signal y_subnode, y_pipenode : datapathtype;
signal z_subnode, z_pipenode : datapathtype;
signal atannode : atantype;
signal multiplier_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (2*width DOWNTO 1);
signal sincosff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_input : STD_LOGIC_VECTOR (width DOWNTO 1);
signal delay_pipe : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pre_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
signal post_estimate : STD_LOGIC_VECTOR (width DOWNTO 1);
component fp_cordic_start1
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_cordic_atan1
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_sgn_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- maximum width supported = 36 (width of start table)
-- depth <= width
-- maximum indexpoint = 10 (atan_table width - 10 > maximum width)
gprma: IF (width > 36) GENERATE
assert false report "maximum width is 36" severity error;
END GENERATE;
gprmb: IF (depth > width) GENERATE
assert false report "depth cannot exceed (width-6)" severity error;
END GENERATE;
gprmc: IF (indexpoint > 10) GENERATE
assert false report "maximum indexpoint is 10" severity error;
END GENERATE;
-- max radians = 1.57 = 01100100....
-- max atan(2^-0)= 0.785 = 00110010.....
-- x start (0.607) = 0010011011....
indexpointnum <= conv_std_logic_vector (indexpoint,4);
gipa: FOR k IN 1 TO 4 GENERATE
startindex(k) <= indexpointnum(k) AND indexbit;
END GENERATE;
cxs: fp_cordic_start1
GENERIC MAP (width=>width)
PORT MAP (index=>startindex,value=>x_start_node);
gra: FOR k IN 1 TO indexpoint GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit));
END GENERATE;
grb: FOR k IN indexpoint+1 TO width GENERATE
radians_load_node(k) <= (radians(k) AND NOT(indexbit)) OR
(radians(k-indexpoint) AND indexbit);
END GENERATE;
zerovec <= x"000000000";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO cordic_depth+3 LOOP
indexbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+3 LOOP
sincosbitff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth LOOP
FOR j IN 1 TO width LOOP
x_pipeff(k)(j) <= '0';
y_pipeff(k)(j) <= '0';
z_pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
indexbitff(1) <= indexbit;
FOR k IN 2 TO cordic_depth+3 LOOP
indexbitff(k) <= indexbitff(k-1);
END LOOP;
sincosbitff(1) <= sincosbit;
FOR k IN 2 TO cordic_depth+3 LOOP
sincosbitff(k) <= sincosbitff(k-1);
END LOOP;
x_pipeff(1)(width DOWNTO 1) <= x_start_node;
y_pipeff(1)(width DOWNTO 1) <= conv_std_logic_vector(0,width);
z_pipeff(1)(width DOWNTO 1) <= radians_load_node;
-- z(1) always positive
x_pipeff(2)(width DOWNTO 1) <= x_pipeff(1)(width DOWNTO 1); -- subtraction value always 0 here anyway
y_pipeff(2)(width DOWNTO 1) <= y_pipeff(1)(width DOWNTO 1) + y_subnode(2)(width DOWNTO 1);
z_pipeff(2)(width DOWNTO 1) <= z_pipeff(1)(width DOWNTO 1) - atannode(1)(width DOWNTO 1);
FOR k IN 3 TO cordic_depth LOOP
x_pipeff(k)(width DOWNTO 1) <= x_pipenode(k)(width DOWNTO 1);
y_pipeff(k)(width DOWNTO 1) <= y_pipenode(k)(width DOWNTO 1);
z_pipeff(k)(width DOWNTO 1) <= z_pipenode(k)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gya: FOR k IN 1 TO width-indexpoint GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1)) OR (x_pipeff(1)(k+indexpoint) AND indexbitff(1));
END GENERATE;
gyb: FOR k IN (width-(indexpoint-1)) TO width GENERATE
y_subnode(2)(k) <= (x_pipeff(1)(k) AND NOT indexbitff(1));
END GENERATE;
gpa: FOR k IN 3 TO cordic_depth GENERATE
gpb: FOR j IN width+3-k TO width GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodeone(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpc: FOR j IN width+3-indexpoint-k TO width GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(width));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(width);
END GENERATE;
gpd: FOR j IN 1 TO width+2-k GENERATE
x_prenodeone(k)(j) <= NOT(y_pipeff(k-1)(j+k-2));
y_prenodeone(k)(j) <= x_pipeff(k-1)(j+k-2);
END GENERATE;
gpe: FOR j IN 1 TO width+2-indexpoint-k GENERATE
x_prenodetwo(k)(j) <= NOT(y_pipeff(k-1)(j+k-2+indexpoint));
y_prenodetwo(k)(j) <= x_pipeff(k-1)(j+k-2+indexpoint);
END GENERATE;
gpf: FOR j IN 1 TO width GENERATE
x_prenode(k)(j) <= (x_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(x_prenodetwo(k)(j) AND indexbitff(k-1));
y_prenode(k)(j) <= (y_prenodeone(k)(j) AND NOT(indexbitff(k-1))) OR
(y_prenodetwo(k)(j) AND indexbitff(k-1));
END GENERATE;
gpg: FOR j IN 1 TO width GENERATE
x_subnode(k)(j) <= x_prenode(k)(j) XOR z_pipeff(k-1)(width);
y_subnode(k)(j) <= y_prenode(k)(j) XOR z_pipeff(k-1)(width);
z_subnode(k)(j) <= NOT(atannode(k-1)(j)) XOR z_pipeff(k-1)(width);
END GENERATE;
x_pipenode(k)(width DOWNTO 1) <= x_pipeff(k-1)(width DOWNTO 1) +
x_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
y_pipenode(k)(width DOWNTO 1) <= y_pipeff(k-1)(width DOWNTO 1) +
y_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
z_pipenode(k)(width DOWNTO 1) <= z_pipeff(k-1)(width DOWNTO 1) +
z_subnode(k)(width DOWNTO 1) + z_pipeff(k-1)(width);
END GENERATE;
gata: FOR k IN 1 TO cordic_depth GENERATE
cata: fp_cordic_atan1
GENERIC MAP (start=>k,width=>width,indexpoint=>indexpoint)
PORT MAP (indexbit=>indexbitff(k),arctan=>atannode(k)(width DOWNTO 1));
END GENERATE;
gma: FOR k IN 1 TO width GENERATE
multiplier_input(k) <= (x_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth)) OR
(y_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth)));
delay_input(k) <= (x_pipeff(cordic_depth)(k) AND NOT(sincosbitff(cordic_depth))) OR
(y_pipeff(cordic_depth)(k) AND sincosbitff(cordic_depth));
END GENERATE;
cmx: fp_sgn_mul3s
GENERIC MAP (widthaa=>width,widthbb=>width,widthcc=>2*width)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multiplier_input,
databb=>z_pipeff(cordic_depth)(width DOWNTO 1),
result=>multipliernode);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
sincosff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sincosff <= delay_pipe + post_estimate + NOT(sincosbitff(cordic_depth+3));
END IF;
END IF;
END PROCESS;
pre_estimate <= multipliernode(2*width-2 DOWNTO width-1);
gea: FOR k IN 1 TO width-indexpoint GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(k+indexpoint) AND indexbitff(cordic_depth+3));
END GENERATE;
geb: FOR k IN width-indexpoint+1 TO width GENERATE
estimate(k) <= (pre_estimate(k) AND NOT(indexbitff(cordic_depth+3))) OR
(pre_estimate(width) AND indexbitff(cordic_depth+3));
END GENERATE;
-- add estimate for sin, subtract for cos
gec: FOR k IN 1 TO width GENERATE
post_estimate(k) <= estimate(k) XOR NOT(sincosbitff(cordic_depth+3));
END GENERATE;
cda: fp_del
GENERIC MAP (width=>width,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>delay_input,
cc=>delay_pipe);
sincos <= sincosff;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_cordic_atan1.vhd | 10 | 5033 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_ATAN1.VHD ***
--*** ***
--*** Function: ATAN Values Table for SIN and ***
--*** COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_atan1 IS
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_atan1;
ARCHITECTURE sft OF fp_cordic_atan1 IS
type atantype IS ARRAY (48 DOWNTO 1) OF STD_LOGIC_VECTOR (48 DOWNTO 1);
signal atannum : atantype;
BEGIN
-- "00" + 46 bits
atannum(1)(48 DOWNTO 1) <= x"3243F6A8885A";
atannum(2)(48 DOWNTO 1) <= x"1DAC670561BB";
atannum(3)(48 DOWNTO 1) <= x"0FADBAFC9640";
atannum(4)(48 DOWNTO 1) <= x"07F56EA6AB0C";
atannum(5)(48 DOWNTO 1) <= x"03FEAB76E5A0";
atannum(6)(48 DOWNTO 1) <= x"01FFD55BBA97";
atannum(7)(48 DOWNTO 1) <= x"00FFFAAADDDC";
atannum(8)(48 DOWNTO 1) <= x"007FFF5556EF";
atannum(9)(48 DOWNTO 1) <= x"003FFFEAAAB7";
atannum(10)(48 DOWNTO 1) <= x"001FFFFD5556";
atannum(11)(48 DOWNTO 1) <= x"000FFFFFAAAB";
atannum(12)(48 DOWNTO 1) <= x"0007FFFFF555";
atannum(13)(48 DOWNTO 1) <= x"0003FFFFFEAB";
atannum(14)(48 DOWNTO 1) <= x"0001FFFFFFD5";
atannum(15)(48 DOWNTO 1) <= x"0000FFFFFFFB";
atannum(16)(48 DOWNTO 1) <= x"00007FFFFFFF";
atannum(17)(48 DOWNTO 1) <= x"000040000000";
atannum(18)(48 DOWNTO 1) <= x"000020000000";
atannum(19)(48 DOWNTO 1) <= x"000010000000";
atannum(20)(48 DOWNTO 1) <= x"000008000000";
atannum(21)(48 DOWNTO 1) <= x"000004000000";
atannum(22)(48 DOWNTO 1) <= x"000002000000";
atannum(23)(48 DOWNTO 1) <= x"000001000000";
atannum(24)(48 DOWNTO 1) <= x"000000800000";
atannum(25)(48 DOWNTO 1) <= x"000000400000";
atannum(26)(48 DOWNTO 1) <= x"000000200000";
atannum(27)(48 DOWNTO 1) <= x"000000100000";
atannum(28)(48 DOWNTO 1) <= x"000000080000";
atannum(29)(48 DOWNTO 1) <= x"000000040000";
atannum(30)(48 DOWNTO 1) <= x"000000020000";
atannum(31)(48 DOWNTO 1) <= x"000000010000";
atannum(32)(48 DOWNTO 1) <= x"000000008000";
atannum(33)(48 DOWNTO 1) <= x"000000004000";
atannum(34)(48 DOWNTO 1) <= x"000000002000";
atannum(35)(48 DOWNTO 1) <= x"000000001000";
atannum(36)(48 DOWNTO 1) <= x"000000000800";
atannum(37)(48 DOWNTO 1) <= x"000000000400";
atannum(38)(48 DOWNTO 1) <= x"000000000200";
atannum(39)(48 DOWNTO 1) <= x"000000000100";
atannum(40)(48 DOWNTO 1) <= x"000000000080";
atannum(41)(48 DOWNTO 1) <= x"000000000040";
atannum(42)(48 DOWNTO 1) <= x"000000000020";
atannum(43)(48 DOWNTO 1) <= x"000000000010";
atannum(44)(48 DOWNTO 1) <= x"000000000008";
atannum(45)(48 DOWNTO 1) <= x"000000000004";
atannum(46)(48 DOWNTO 1) <= x"000000000002";
atannum(47)(48 DOWNTO 1) <= x"000000000001";
atannum(48)(48 DOWNTO 1) <= x"000000000000";
pca: PROCESS (indexbit)
BEGIN
CASE indexbit IS
WHEN '0' => arctan <= atannum(start)(48 DOWNTO 49-width);
WHEN '1' => arctan <= atannum(start+indexpoint)(48-indexpoint DOWNTO 49-indexpoint-width);
WHEN others => arctan <= atannum(48)(width DOWNTO 1);
END CASE;
END PROCESS;
END sft;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/fp_sum36x18.vhd | 10 | 18695 | -- megafunction wizard: %ALTMULT_ADD%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTMULT_ADD
-- ============================================================
-- File Name: sum36x18.vhd
-- Megafunction Name(s):
-- ALTMULT_ADD
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 8.1 Build 163 10/28/2008 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2008 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fp_sum36x18 IS
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END fp_sum36x18;
ARCHITECTURE SYN OF fp_sum36x18 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (54 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (17 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (35 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (71 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (35 DOWNTO 0);
COMPONENT altmult_add
GENERIC (
accumulator : STRING;
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
chainout_adder : STRING;
chainout_register : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_a1 : STRING;
input_aclr_b0 : STRING;
input_aclr_b1 : STRING;
input_register_a0 : STRING;
input_register_a1 : STRING;
input_register_b0 : STRING;
input_register_b1 : STRING;
input_source_a0 : STRING;
input_source_a1 : STRING;
input_source_b0 : STRING;
input_source_b1 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_aclr1 : STRING;
multiplier_register0 : STRING;
multiplier_register1 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_chainin : NATURAL;
width_result : NATURAL;
zero_chainout_output_aclr : STRING;
zero_chainout_output_register : STRING;
zero_loopback_aclr : STRING;
zero_loopback_output_aclr : STRING;
zero_loopback_output_register : STRING;
zero_loopback_pipeline_aclr : STRING;
zero_loopback_pipeline_register : STRING;
zero_loopback_register : STRING
);
PORT (
dataa : IN STD_LOGIC_VECTOR (35 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire6 <= datab_1(35 DOWNTO 0);
sub_wire3 <= dataa_1(17 DOWNTO 0);
result <= sub_wire0(54 DOWNTO 0);
sub_wire1 <= dataa_0(17 DOWNTO 0);
sub_wire2 <= sub_wire3(17 DOWNTO 0) & sub_wire1(17 DOWNTO 0);
sub_wire4 <= datab_0(35 DOWNTO 0);
sub_wire5 <= sub_wire6(35 DOWNTO 0) & sub_wire4(35 DOWNTO 0);
ALTMULT_ADD_component : ALTMULT_ADD
GENERIC MAP (
accumulator => "NO",
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
chainout_adder => "NO",
chainout_register => "UNREGISTERED",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_a1 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_aclr_b1 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_a1 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_register_b1 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_a1 => "DATAA",
input_source_b0 => "DATAB",
input_source_b1 => "DATAB",
intended_device_family => "Stratix III",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_aclr1 => "ACLR3",
multiplier_register0 => "CLOCK0",
multiplier_register1 => "CLOCK0",
number_of_multipliers => 2,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 36,
width_chainin => 1,
width_result => 55,
zero_chainout_output_aclr => "ACLR3",
zero_chainout_output_register => "CLOCK0",
zero_loopback_aclr => "ACLR3",
zero_loopback_output_aclr => "ACLR3",
zero_loopback_output_register => "CLOCK0",
zero_loopback_pipeline_aclr => "ACLR3",
zero_loopback_pipeline_register => "CLOCK0",
zero_loopback_register => "CLOCK0"
)
PORT MAP (
dataa => sub_wire2,
datab => sub_wire5,
clock0 => clock0,
aclr3 => aclr3,
ena0 => ena0,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1"
-- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1"
-- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0"
-- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0"
-- Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "1"
-- Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: HAS_MAC STRING "0"
-- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0"
-- Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0"
-- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1"
-- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1"
-- Retrieval info: PRIVATE: NUM_MULT STRING "2"
-- Retrieval info: PRIVATE: OP1 STRING "Add"
-- Retrieval info: PRIVATE: OP3 STRING "Add"
-- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0"
-- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3"
-- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0"
-- Retrieval info: PRIVATE: REG_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: RNFORMAT STRING "55"
-- Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ROTATE_REG STRING "1"
-- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15"
-- Retrieval info: PRIVATE: RTS_WIDTH STRING "55"
-- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1"
-- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1"
-- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0"
-- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1"
-- Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None"
-- Retrieval info: PRIVATE: SIGNA STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNA_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB STRING "Unsigned"
-- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: SIGNB_REG STRING "1"
-- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTHA STRING "18"
-- Retrieval info: PRIVATE: WIDTHB STRING "36"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1"
-- Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ACCUMULATOR STRING "NO"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO"
-- Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO"
-- Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "ACLR3"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB"
-- Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add"
-- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "ACLR3"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0"
-- Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0"
-- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2"
-- Retrieval info: CONSTANT: OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED"
-- Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED"
-- Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "ACLR3"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36"
-- Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "55"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "ACLR3"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0"
-- Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr3 0 0 0 0 INPUT GND "aclr3"
-- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0"
-- Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]"
-- Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]"
-- Retrieval info: USED_PORT: datab_0 0 0 36 0 INPUT GND "datab_0[35..0]"
-- Retrieval info: USED_PORT: datab_1 0 0 36 0 INPUT GND "datab_1[35..0]"
-- Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0"
-- Retrieval info: USED_PORT: result 0 0 55 0 OUTPUT GND "result[54..0]"
-- Retrieval info: CONNECT: @datab 0 0 36 36 datab_1 0 0 36 0
-- Retrieval info: CONNECT: @aclr3 0 0 0 0 aclr3 0 0 0 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 55 0 @result 0 0 55 0
-- Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0
-- Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0
-- Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0
-- Retrieval info: CONNECT: @datab 0 0 36 0 datab_0 0 0 36 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.inc FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.cmp TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.bsf FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_inst.vhd FALSE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_waveforms.html TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_wave*.jpg FALSE FALSE
-- Retrieval info: LIB_FILE: altera_mf
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/hcc_divide.vhd | 10 | 4415 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVIDE.VHD ***
--*** ***
--*** Function: Fixed point divide - used by ***
--*** single and double dividers ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_divide IS
GENERIC (
width : positive := 24;
precision : positive := 28 -- minimum width+4
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
top : IN STD_LOGIC_VECTOR (width DOWNTO 1);
bot : IN STD_LOGIC_VECTOR (width DOWNTO 1);
fpquotient : OUT STD_LOGIC_VECTOR (width+2 DOWNTO 1)
);
END hcc_divide;
ARCHITECTURE div OF hcc_divide IS
type nodetype IS ARRAY (width+2 DOWNTO 1) OF STD_LOGIC_VECTOR (precision DOWNTO 1);
type qfftype IS ARRAY (width+1 DOWNTO 1) OF STD_LOGIC_VECTOR (width+1 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (precision-1 DOWNTO 1);
signal topone, botone : STD_LOGIC_VECTOR (precision DOWNTO 1);
signal addsub, botnode : nodetype;
signal levff, botff : nodetype;
signal qff : qfftype;
signal quotientnode : STD_LOGIC_VECTOR (width+2 DOWNTO 1);
BEGIN
-- NOTES
-- non restoring divider
-- check for "0" intermediate remainder not required as both inputs 1.XXXXX format
-- 2 extra output bits - pentium compatibility requires round to nearest, not round to nearest even
-- trailing zeros optimizations do not appear to improve size or speed, removed here
zerovec <= conv_std_logic_vector (0,precision-1);
topone <= '0' & top & zerovec(precision-width-1 DOWNTO 1);
botone <= '0' & bot & zerovec(precision-width-1 DOWNTO 1);
addsub(1)(precision DOWNTO 1) <= topone - botone;
addsub(2)(precision DOWNTO 1) <= '0' & ( levff(1)(precision-1 DOWNTO 1) +
botnode(1)(precision-1 DOWNTO 1) +
(zerovec(precision-2 DOWNTO 1) & NOT(levff(1)(precision))) );
gsa: FOR k IN 3 TO width+2 GENERATE
addsub(k)(precision DOWNTO 1) <= zerovec(k-1 DOWNTO 1) & ( levff(k-1)(precision+1-k DOWNTO 1) +
botnode(k-1)(precision+1-k DOWNTO 1) +
(zerovec(precision-k DOWNTO 1) & NOT(levff(k-1)(precision+2-k))) );
END GENERATE;
gxa: FOR k IN 1 TO width+1 GENERATE
gxb: FOR j IN 1 TO precision GENERATE
botnode(k)(j) <= botff(k)(j) XOR NOT(levff(k)(precision+1-k));
END GENERATE;
END GENERATE;
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
botff(1)(precision DOWNTO 1) <= "00" & bot & zerovec(precision-width-2 DOWNTO 1);
FOR k IN 2 TO width+1 LOOP
botff(k)(precision DOWNTO 1) <= '0' & botff(k-1)(precision DOWNTO 2);
END LOOP;
FOR k IN 1 TO width+1 LOOP
levff(k)(precision DOWNTO 1) <= addsub(k)(precision DOWNTO 1);
END LOOP;
FOR k IN 1 TO width+1 LOOP
qff(k)(1) <= addsub(k)(precision+1-k);
FOR j IN 2 TO width+1 LOOP
qff(k)(j) <= qff(k)(j-1);
END LOOP;
END LOOP;
END IF;
END IF;
END PROCESS;
quotientnode(1) <= NOT(addsub(width+2)(precision-width-1));
gqo: FOR k IN 2 TO width+2 GENERATE
quotientnode(k) <= NOT(qff(width+3-k)(k-1));
END GENERATE;
fpquotient <= quotientnode;
END div;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/hcc_package.vhd | 10 | 12965 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 06/02/08 - removed divides (now a library ***
--*** function ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
GENERIC (
mantissa : positive := 36;
shiftspeed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 0; -- 0 = none, 1 = scale
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_neg1x
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (smantissa/10)
funcoutput : integer := 0 -- function output (S'1'umantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_neg2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 0 -- 1 = to another double muliplier (s/1u52/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component castytox IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/dp_neg.vhd | 10 | 3079 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_NEG.VHD ***
--*** ***
--*** Function: Single Precision Negative Value ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_neg IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_neg;
ARCHITECTURE rtl OF dp_neg IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= NOT(signin);
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(11));
expmax <= expmaxchk(11);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(52));
mannonzero <= manzerochk(52);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_sinpi_s5.vhd | 10 | 314232 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sinpi_s5
-- VHDL created on Mon Mar 11 13:59:03 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sinpi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sinpi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid9_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid10_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid11_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasPwF_uid12_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid16_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasM1_uid31_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal biasMwShift_uid33_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal shiftBias_uid36_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cst01pWShift_uid38_fpSinPiTest_q : std_logic_vector (12 downto 0);
signal ozz_uid45_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cOne_uid48_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_a : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_b : std_logic_vector(40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_o : std_logic_vector (40 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid50_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid59_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expP_uid65_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid65_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal piwFP2_uid71_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal multRightOp_uid72_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multRightOp_uid72_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_a : std_logic_vector (23 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_s1 : std_logic_vector (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_pr : UNSIGNED (48 downto 0);
signal mul2xSinRes_uid73_fpSinPiTest_q : std_logic_vector (48 downto 0);
signal regXAndInt_uid91_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal regXAndInt_uid91_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xHalfRZI_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneFracRPostExc2_uid96_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal rZOrXInt_uid98_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid107_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid108_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid148_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid149_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (28 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid168_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid216_sinPiZTableGenerator_q : std_logic_vector(28 downto 0);
signal memoryC1_uid217_sinPiZTableGenerator_q : std_logic_vector(20 downto 0);
signal memoryC2_uid218_sinPiZTableGenerator_q : std_logic_vector(13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_a : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 : std_logic_vector (27 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr : SIGNED (28 downto 0);
signal prodXY_uid232_pT1_uid220_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid235_pT2_uid226_sinPiZPolyEval_q : std_logic_vector (38 downto 0);
signal reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q : std_logic_vector (35 downto 0);
signal reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q : std_logic_vector (37 downto 0);
signal reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q : std_logic_vector (13 downto 0);
signal reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q : std_logic_vector (34 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (28 downto 0);
signal ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (24 downto 0);
signal ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (35 downto 0);
signal ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (34 downto 0);
signal ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (2 downto 0);
signal ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (30 downto 0);
signal ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (26 downto 0);
signal ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (22 downto 0);
signal ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (33 downto 0);
signal ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (32 downto 0);
signal ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q : std_logic_vector (31 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q : std_logic_vector (34 downto 0);
signal ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q : std_logic_vector (13 downto 0);
signal ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q : std_logic_vector (18 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q : std_logic_vector (34 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q : signal is true;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q : signal is true;
signal yIsZero_uid44_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid44_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRIoN_uid102_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expXP1_uid62_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXP1_uid62_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXP1_uid62_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid84_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIntExp_uid88_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXFrac_uid105_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid35_uid35_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal join_uid46_fpSinPiTest_q : std_logic_vector (35 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid7_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid7_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid8_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid8_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid18_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid20_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid22_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid23_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntExp_uid30_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xIntExp_uid30_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xIntExp_uid30_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xIntExp_uid30_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xFrac_uid32_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xFrac_uid32_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xFrac_uid32_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal shiftValue_uid37_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal shiftValue_uid37_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal shiftValue_uid37_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yIsZero_uid47_fpSinPiTest_a : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_b : std_logic_vector(35 downto 0);
signal yIsZero_uid47_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid49_fpSinPiTest_a : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_b : std_logic_vector(37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_o : std_logic_vector (37 downto 0);
signal oneMinusY_uid49_fpSinPiTest_q : std_logic_vector (37 downto 0);
signal z_uid53_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid53_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal expHardCase_uid61_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid61_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid61_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSinXNX_uid85_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIntYz_uid86_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid87_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_d : std_logic_vector(0 downto 0);
signal xRyHalf_uid90_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid92_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid95_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid97_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid101_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expRPostExc_uid104_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid104_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal yZSC_uid109_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal yZSC_uid109_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid110_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid162_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid165_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid171_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal normBit_uid74_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal normBit_uid74_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid75_fpSinPiTest_in : std_logic_vector (47 downto 0);
signal highRes_uid75_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid76_fpSinPiTest_in : std_logic_vector (46 downto 0);
signal lowRes_uid76_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal cStage_uid151_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in : std_logic_vector (27 downto 0);
signal prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b : std_logic_vector (14 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q : std_logic_vector (34 downto 0);
signal R_uid111_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid153_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal join_uid103_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal expXP1R_uid63_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXP1R_uid63_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid24_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid27_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid40_fpSinPiTest_b : std_logic_vector (5 downto 0);
signal oMyBottom_uid51_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal oMyBottom_uid51_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal zAddr_uid67_fpSinPiTest_b : std_logic_vector (6 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_in : std_logic_vector (27 downto 0);
signal zPPolyEval_uid68_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid147_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid150_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (2 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (18 downto 0);
signal X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (18 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expHardCaseR_uid64_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvXIsInt_uid106_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid167_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid169_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid173_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid175_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (20 downto 0);
signal X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (20 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (4 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid77_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal rndExpUpdate_uid79_uid80_fpSinPiTest_q : std_logic_vector (24 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid221_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid222_sinPiZPolyEval_in : std_logic_vector (14 downto 0);
signal highBBits_uid222_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid227_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid228_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid228_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal intXParity_uid42_fpSinPiTest_in : std_logic_vector (36 downto 0);
signal intXParity_uid42_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid43_fpSinPiTest_in : std_logic_vector (35 downto 0);
signal y_uid43_fpSinPiTest_b : std_logic_vector (35 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (26 downto 0);
signal LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (26 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (33 downto 0);
signal LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (33 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal alignedZLow_uid57_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal alignedZLow_uid57_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid155_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid157_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal exc_N_uid25_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid25_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal yT1_uid219_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid219_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid174_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid177_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal expFracPreRnd_uid78_uid78_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal expFracComp_uid81_fpSinPiTest_a : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_b : std_logic_vector(32 downto 0);
signal expFracComp_uid81_fpSinPiTest_o : std_logic_vector (32 downto 0);
signal expFracComp_uid81_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid223_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid229_sinPiZPolyEval_q : std_logic_vector (29 downto 0);
signal yBottom_uid52_fpSinPiTest_in : std_logic_vector (34 downto 0);
signal yBottom_uid52_fpSinPiTest_b : std_logic_vector (34 downto 0);
signal pHardCase_uid58_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid156_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid159_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal InvExc_N_uid26_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid26_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid179_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q : std_logic_vector (36 downto 0);
signal fracRComp_uid82_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid82_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRComp_uid83_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal expRComp_uid83_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal s1_uid221_uid224_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid227_uid230_sinPiZPolyEval_q : std_logic_vector (31 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid161_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid163_lzcZ_uid55_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid29_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid29_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid180_lzcZ_uid55_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (28 downto 0);
signal LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (28 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in : std_logic_vector (24 downto 0);
signal LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal fxpSinRes_uid70_fpSinPiTest_b : std_logic_vector (24 downto 0);
signal r_uid181_lzcZ_uid55_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b : std_logic_vector (1 downto 0);
begin
--xIn(GPIN,3)@0
--leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest(CONSTANT,119)
leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000000000000000000000000";
--X4dto0_uid118_fixedPointX_uid41_fpSinPiTest(BITSELECT,117)@1
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(4 downto 0);
X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_in(4 downto 0);
--leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest(CONSTANT,116)
leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest(BITJOIN,118)@1
leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q <= X4dto0_uid118_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--X20dto0_uid115_fixedPointX_uid41_fpSinPiTest(BITSELECT,114)@1
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(20 downto 0);
X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_in(20 downto 0);
--leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest(CONSTANT,113)
leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest(BITJOIN,115)@1
leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q <= X20dto0_uid115_fixedPointX_uid41_fpSinPiTest_b & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--cst01pWShift_uid38_fpSinPiTest(CONSTANT,37)
cst01pWShift_uid38_fpSinPiTest_q <= "0000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--fracX_uid7_fpSinPiTest(BITSELECT,6)@0
fracX_uid7_fpSinPiTest_in <= a(22 downto 0);
fracX_uid7_fpSinPiTest_b <= fracX_uid7_fpSinPiTest_in(22 downto 0);
--ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a(DELAY,294)@0
ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid7_fpSinPiTest_b, xout => ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracX_uid35_uid35_fpSinPiTest(BITJOIN,34)@1
oFracX_uid35_uid35_fpSinPiTest_q <= VCC_q & ld_fracX_uid7_fpSinPiTest_b_to_oFracX_uid35_uid35_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@1
extendedFracX_uid39_fpSinPiTest_q <= cst01pWShift_uid38_fpSinPiTest_q & oFracX_uid35_uid35_fpSinPiTest_q;
--shiftBias_uid36_fpSinPiTest(CONSTANT,35)
shiftBias_uid36_fpSinPiTest_q <= "01110010";
--expX_uid6_fpSinPiTest(BITSELECT,5)@0
expX_uid6_fpSinPiTest_in <= a(30 downto 0);
expX_uid6_fpSinPiTest_b <= expX_uid6_fpSinPiTest_in(30 downto 23);
--shiftValue_uid37_fpSinPiTest(SUB,36)@0
shiftValue_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSinPiTest_b);
shiftValue_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid36_fpSinPiTest_q);
shiftValue_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid37_fpSinPiTest_a) - UNSIGNED(shiftValue_uid37_fpSinPiTest_b));
shiftValue_uid37_fpSinPiTest_q <= shiftValue_uid37_fpSinPiTest_o(8 downto 0);
--fxpShifterBits_uid40_fpSinPiTest(BITSELECT,39)@0
fxpShifterBits_uid40_fpSinPiTest_in <= shiftValue_uid37_fpSinPiTest_q(5 downto 0);
fxpShifterBits_uid40_fpSinPiTest_b <= fxpShifterBits_uid40_fpSinPiTest_in(5 downto 0);
--leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest(BITSELECT,120)@0
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b;
leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1(REG,237)@0
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest(MUX,121)@1
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid121_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx1_uid116_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx2_uid119_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage0Idx3_uid120_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest(BITSELECT,129)@1
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(24 downto 0);
LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_in(24 downto 0);
--ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b(DELAY,403)@1
ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest(CONSTANT,128)
leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q <= "000000000000";
--leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest(BITJOIN,130)@2
leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage024dto0_uid130_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest(BITSELECT,126)@1
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(28 downto 0);
LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_in(28 downto 0);
--ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b(DELAY,401)@1
ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 29, depth => 1 )
PORT MAP ( xin => LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid16_fpSinPiTest(CONSTANT,15)
cstAllZWE_uid16_fpSinPiTest_q <= "00000000";
--leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest(BITJOIN,127)@2
leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage028dto0_uid127_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest(BITSELECT,123)@1
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q(32 downto 0);
LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b(DELAY,399)@1
ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest(CONSTANT,122)
leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q <= "0000";
--leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest(BITJOIN,124)@2
leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage032dto0_uid124_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2(REG,239)@1
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest(BITSELECT,131)@0
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(3 downto 0);
leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_in(3 downto 2);
--ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,516)@0
ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1(REG,238)@1
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest(MUX,132)@2
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid132_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage0_uid122_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx1_uid125_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx2_uid128_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage1Idx3_uid131_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest(BITSELECT,140)@2
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b(DELAY,415)@2
ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest(CONSTANT,139)
leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q <= "000";
--leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest(BITJOIN,141)@3
leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid141_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest(BITSELECT,137)@2
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(34 downto 0);
LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_in(34 downto 0);
--ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b(DELAY,413)@2
ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest(CONSTANT,136)
leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q <= "00";
--leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest(BITJOIN,138)@3
leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage134dto0_uid138_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest(BITSELECT,134)@2
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b <= LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_in(35 downto 0);
--ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b(DELAY,411)@2
ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 1 )
PORT MAP ( xin => LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b, xout => ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest(BITJOIN,135)@3
leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q <= ld_LeftShiftStage135dto0_uid135_fixedPointX_uid41_fpSinPiTest_b_to_leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2(REG,241)@2
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q <= leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest(BITSELECT,142)@0
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in <= fxpShifterBits_uid40_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a(DELAY,518)@0
ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1(REG,240)@2
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest(MUX,143)@3
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid143_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_1_q;
leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest: PROCESS (leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s, en, reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q, leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q, leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= reg_leftShiftStage1_uid133_fixedPointX_uid41_fpSinPiTest_0_to_leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx1_uid136_fixedPointX_uid41_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx2_uid139_fixedPointX_uid41_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= leftShiftStage2Idx3_uid142_fixedPointX_uid41_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid42_fpSinPiTest(BITSELECT,41)@3
intXParity_uid42_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q;
intXParity_uid42_fpSinPiTest_b <= intXParity_uid42_fpSinPiTest_in(36 downto 36);
--ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c(DELAY,380)@3
ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => intXParity_uid42_fpSinPiTest_b, xout => ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--biasM1_uid31_fpSinPiTest(CONSTANT,30)
biasM1_uid31_fpSinPiTest_q <= "01111110";
--xFrac_uid32_fpSinPiTest(COMPARE,31)@0
xFrac_uid32_fpSinPiTest_cin <= GND_q;
xFrac_uid32_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & biasM1_uid31_fpSinPiTest_q) & '0';
xFrac_uid32_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xFrac_uid32_fpSinPiTest_cin(0);
xFrac_uid32_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xFrac_uid32_fpSinPiTest_a) - UNSIGNED(xFrac_uid32_fpSinPiTest_b));
xFrac_uid32_fpSinPiTest_n(0) <= not xFrac_uid32_fpSinPiTest_o(10);
--ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a(DELAY,376)@0
ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xFrac_uid32_fpSinPiTest_n, xout => ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvXFrac_uid105_fpSinPiTest(LOGICAL,104)@4
InvXFrac_uid105_fpSinPiTest_a <= ld_xFrac_uid32_fpSinPiTest_n_to_InvXFrac_uid105_fpSinPiTest_a_q;
InvXFrac_uid105_fpSinPiTest_q <= not InvXFrac_uid105_fpSinPiTest_a;
--biasMwShift_uid33_fpSinPiTest(CONSTANT,32)
biasMwShift_uid33_fpSinPiTest_q <= "01110011";
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid33_fpSinPiTest_q) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_c(0) <= sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a(DELAY,343)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid84_fpSinPiTest(LOGICAL,83)@4
InvSinXIsX_uid84_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_c_to_InvSinXIsX_uid84_fpSinPiTest_a_q;
InvSinXIsX_uid84_fpSinPiTest_q <= not InvSinXIsX_uid84_fpSinPiTest_a;
--y_uid43_fpSinPiTest(BITSELECT,42)@3
y_uid43_fpSinPiTest_in <= leftShiftStage2_uid144_fixedPointX_uid41_fpSinPiTest_q(35 downto 0);
y_uid43_fpSinPiTest_b <= y_uid43_fpSinPiTest_in(35 downto 0);
--reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1(REG,242)@3
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q <= y_uid43_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--yIsZero_uid44_fpSinPiTest(LOGICAL,43)@4
yIsZero_uid44_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid44_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000" & GND_q);
yIsZero_uid44_fpSinPiTest_q <= "1" when yIsZero_uid44_fpSinPiTest_a = yIsZero_uid44_fpSinPiTest_b else "0";
--yZSinXNX_uid85_fpSinPiTest(LOGICAL,84)@4
yZSinXNX_uid85_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_b <= InvSinXIsX_uid84_fpSinPiTest_q;
yZSinXNX_uid85_fpSinPiTest_q <= yZSinXNX_uid85_fpSinPiTest_a and yZSinXNX_uid85_fpSinPiTest_b;
--cstBiasPwF_uid12_fpSinPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpSinPiTest_q <= "10010110";
--xIntExp_uid30_fpSinPiTest(COMPARE,29)@0
xIntExp_uid30_fpSinPiTest_cin <= GND_q;
xIntExp_uid30_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpSinPiTest_q) & '0';
xIntExp_uid30_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpSinPiTest_b) & xIntExp_uid30_fpSinPiTest_cin(0);
xIntExp_uid30_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xIntExp_uid30_fpSinPiTest_a) - UNSIGNED(xIntExp_uid30_fpSinPiTest_b));
xIntExp_uid30_fpSinPiTest_c(0) <= xIntExp_uid30_fpSinPiTest_o(10);
--ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a(DELAY,346)@0
ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => xIntExp_uid30_fpSinPiTest_c, xout => ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIntYz_uid86_fpSinPiTest(LOGICAL,85)@4
xIntYz_uid86_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
xIntYz_uid86_fpSinPiTest_b <= yZSinXNX_uid85_fpSinPiTest_q;
xIntYz_uid86_fpSinPiTest_q <= xIntYz_uid86_fpSinPiTest_a or xIntYz_uid86_fpSinPiTest_b;
--cstAllZWF_uid10_fpSinPiTest(CONSTANT,9)
cstAllZWF_uid10_fpSinPiTest_q <= "00000000000000000000000";
--fracXIsZero_uid22_fpSinPiTest(LOGICAL,21)@0
fracXIsZero_uid22_fpSinPiTest_a <= fracX_uid7_fpSinPiTest_b;
fracXIsZero_uid22_fpSinPiTest_b <= cstAllZWF_uid10_fpSinPiTest_q;
fracXIsZero_uid22_fpSinPiTest_q <= "1" when fracXIsZero_uid22_fpSinPiTest_a = fracXIsZero_uid22_fpSinPiTest_b else "0";
--InvFracXIsZero_uid24_fpSinPiTest(LOGICAL,23)@0
InvFracXIsZero_uid24_fpSinPiTest_a <= fracXIsZero_uid22_fpSinPiTest_q;
InvFracXIsZero_uid24_fpSinPiTest_q <= not InvFracXIsZero_uid24_fpSinPiTest_a;
--cstAllOWE_uid9_fpSinPiTest(CONSTANT,8)
cstAllOWE_uid9_fpSinPiTest_q <= "11111111";
--expXIsMax_uid20_fpSinPiTest(LOGICAL,19)@0
expXIsMax_uid20_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsMax_uid20_fpSinPiTest_b <= cstAllOWE_uid9_fpSinPiTest_q;
expXIsMax_uid20_fpSinPiTest_q <= "1" when expXIsMax_uid20_fpSinPiTest_a = expXIsMax_uid20_fpSinPiTest_b else "0";
--exc_N_uid25_fpSinPiTest(LOGICAL,24)@0
exc_N_uid25_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_b <= InvFracXIsZero_uid24_fpSinPiTest_q;
exc_N_uid25_fpSinPiTest_q <= exc_N_uid25_fpSinPiTest_a and exc_N_uid25_fpSinPiTest_b;
--InvExc_N_uid26_fpSinPiTest(LOGICAL,25)@0
InvExc_N_uid26_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
InvExc_N_uid26_fpSinPiTest_q <= not InvExc_N_uid26_fpSinPiTest_a;
--exc_I_uid23_fpSinPiTest(LOGICAL,22)@0
exc_I_uid23_fpSinPiTest_a <= expXIsMax_uid20_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_b <= fracXIsZero_uid22_fpSinPiTest_q;
exc_I_uid23_fpSinPiTest_q <= exc_I_uid23_fpSinPiTest_a and exc_I_uid23_fpSinPiTest_b;
--InvExc_I_uid27_fpSinPiTest(LOGICAL,26)@0
InvExc_I_uid27_fpSinPiTest_a <= exc_I_uid23_fpSinPiTest_q;
InvExc_I_uid27_fpSinPiTest_q <= not InvExc_I_uid27_fpSinPiTest_a;
--expXIsZero_uid18_fpSinPiTest(LOGICAL,17)@0
expXIsZero_uid18_fpSinPiTest_a <= expX_uid6_fpSinPiTest_b;
expXIsZero_uid18_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
expXIsZero_uid18_fpSinPiTest_q <= "1" when expXIsZero_uid18_fpSinPiTest_a = expXIsZero_uid18_fpSinPiTest_b else "0";
--InvExpXIsZero_uid28_fpSinPiTest(LOGICAL,27)@0
InvExpXIsZero_uid28_fpSinPiTest_a <= expXIsZero_uid18_fpSinPiTest_q;
InvExpXIsZero_uid28_fpSinPiTest_q <= not InvExpXIsZero_uid28_fpSinPiTest_a;
--exc_R_uid29_fpSinPiTest(LOGICAL,28)@0
exc_R_uid29_fpSinPiTest_a <= InvExpXIsZero_uid28_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_b <= InvExc_I_uid27_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_c <= InvExc_N_uid26_fpSinPiTest_q;
exc_R_uid29_fpSinPiTest_q <= exc_R_uid29_fpSinPiTest_a and exc_R_uid29_fpSinPiTest_b and exc_R_uid29_fpSinPiTest_c;
--ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a(DELAY,348)@0
ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => exc_R_uid29_fpSinPiTest_q, xout => ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--xIsInt_uid87_fpSinPiTest(LOGICAL,86)@4
xIsInt_uid87_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xIsInt_uid87_fpSinPiTest_b <= xIntYz_uid86_fpSinPiTest_q;
xIsInt_uid87_fpSinPiTest_q <= xIsInt_uid87_fpSinPiTest_a and xIsInt_uid87_fpSinPiTest_b;
--InvXIsInt_uid106_fpSinPiTest(LOGICAL,105)@4
InvXIsInt_uid106_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
InvXIsInt_uid106_fpSinPiTest_q <= not InvXIsInt_uid106_fpSinPiTest_a;
--signComp_uid107_fpSinPiTest(LOGICAL,106)@4
signComp_uid107_fpSinPiTest_a <= InvXIsInt_uid106_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_b <= InvXFrac_uid105_fpSinPiTest_q;
signComp_uid107_fpSinPiTest_c <= ld_intXParity_uid42_fpSinPiTest_b_to_signComp_uid107_fpSinPiTest_c_q;
signComp_uid107_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signComp_uid107_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signComp_uid107_fpSinPiTest_q <= signComp_uid107_fpSinPiTest_a and signComp_uid107_fpSinPiTest_b and signComp_uid107_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--InvYIsZero_uid108_fpSinPiTest(LOGICAL,107)@4
InvYIsZero_uid108_fpSinPiTest_a <= yIsZero_uid44_fpSinPiTest_q;
InvYIsZero_uid108_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvYIsZero_uid108_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvYIsZero_uid108_fpSinPiTest_q <= not InvYIsZero_uid108_fpSinPiTest_a;
END IF;
END PROCESS;
--yZSC_uid109_fpSinPiTest(LOGICAL,108)@5
yZSC_uid109_fpSinPiTest_a <= InvYIsZero_uid108_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_b <= signComp_uid107_fpSinPiTest_q;
yZSC_uid109_fpSinPiTest_q <= yZSC_uid109_fpSinPiTest_a and yZSC_uid109_fpSinPiTest_b;
--signX_uid8_fpSinPiTest(BITSELECT,7)@0
signX_uid8_fpSinPiTest_in <= a;
signX_uid8_fpSinPiTest_b <= signX_uid8_fpSinPiTest_in(31 downto 31);
--ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a(DELAY,384)@0
ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signX_uid8_fpSinPiTest_b, xout => ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid110_fpSinPiTest(LOGICAL,109)@5
signR_uid110_fpSinPiTest_a <= ld_signX_uid8_fpSinPiTest_b_to_signR_uid110_fpSinPiTest_a_q;
signR_uid110_fpSinPiTest_b <= yZSC_uid109_fpSinPiTest_q;
signR_uid110_fpSinPiTest_q <= signR_uid110_fpSinPiTest_a xor signR_uid110_fpSinPiTest_b;
--ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c(DELAY,388)@5
ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => signR_uid110_fpSinPiTest_q, xout => ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid11_fpSinPiTest(CONSTANT,10)
cstBias_uid11_fpSinPiTest_q <= "01111111";
--piwFP2_uid71_fpSinPiTest(CONSTANT,70)
piwFP2_uid71_fpSinPiTest_q <= "1100100100001111110110101";
--cOne_uid48_fpSinPiTest(CONSTANT,47)
cOne_uid48_fpSinPiTest_q <= "1000000000000000000000000000000000000";
--oneMinusY_uid49_fpSinPiTest(SUB,48)@4
oneMinusY_uid49_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & cOne_uid48_fpSinPiTest_q);
oneMinusY_uid49_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q);
oneMinusY_uid49_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid49_fpSinPiTest_b));
oneMinusY_uid49_fpSinPiTest_q <= oneMinusY_uid49_fpSinPiTest_o(37 downto 0);
--oMyBottom_uid51_fpSinPiTest(BITSELECT,50)@4
oMyBottom_uid51_fpSinPiTest_in <= oneMinusY_uid49_fpSinPiTest_q(34 downto 0);
oMyBottom_uid51_fpSinPiTest_b <= oMyBottom_uid51_fpSinPiTest_in(34 downto 0);
--reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3(REG,249)@4
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q <= oMyBottom_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d(DELAY,310)@5
ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q, xout => ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--yBottom_uid52_fpSinPiTest(BITSELECT,51)@3
yBottom_uid52_fpSinPiTest_in <= y_uid43_fpSinPiTest_b(34 downto 0);
yBottom_uid52_fpSinPiTest_b <= yBottom_uid52_fpSinPiTest_in(34 downto 0);
--ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a(DELAY,526)@3
ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 35, depth => 2 )
PORT MAP ( xin => yBottom_uid52_fpSinPiTest_b, xout => ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2(REG,248)@5
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q <= ld_yBottom_uid52_fpSinPiTest_b_to_reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b(DELAY,305)@3
ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 36, depth => 2 )
PORT MAP ( xin => y_uid43_fpSinPiTest_b, xout => ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0(REG,247)@4
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q <= oneMinusY_uid49_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid50_fpSinPiTest(COMPARE,49)@5
cmpYToOneMinusY_uid50_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid50_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpSinPiTest_0_to_cmpYToOneMinusY_uid50_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid50_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid43_fpSinPiTest_b_to_cmpYToOneMinusY_uid50_fpSinPiTest_b_q) & cmpYToOneMinusY_uid50_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid50_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid50_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid50_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid50_fpSinPiTest_o(40);
--z_uid53_fpSinPiTest(MUX,52)@6
z_uid53_fpSinPiTest_s <= cmpYToOneMinusY_uid50_fpSinPiTest_c;
z_uid53_fpSinPiTest: PROCESS (z_uid53_fpSinPiTest_s, en, reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q, ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q)
BEGIN
CASE z_uid53_fpSinPiTest_s IS
WHEN "0" => z_uid53_fpSinPiTest_q <= reg_yBottom_uid52_fpSinPiTest_0_to_z_uid53_fpSinPiTest_2_q;
WHEN "1" => z_uid53_fpSinPiTest_q <= ld_reg_oMyBottom_uid51_fpSinPiTest_0_to_z_uid53_fpSinPiTest_3_q_to_z_uid53_fpSinPiTest_d_q;
WHEN OTHERS => z_uid53_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid67_fpSinPiTest(BITSELECT,66)@6
zAddr_uid67_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
zAddr_uid67_fpSinPiTest_b <= zAddr_uid67_fpSinPiTest_in(34 downto 28);
--reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0(REG,261)@6
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q <= zAddr_uid67_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid218_sinPiZTableGenerator(LOOKUP,217)@7
memoryC2_uid218_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q) IS
WHEN "0000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010011";
WHEN "0000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010100";
WHEN "0000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101010111";
WHEN "0000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011001";
WHEN "0000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011011";
WHEN "0000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011100";
WHEN "0000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101011111";
WHEN "0000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100010";
WHEN "0001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101100110";
WHEN "0001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101101011";
WHEN "0001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110000";
WHEN "0001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101110101";
WHEN "0001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101101111011";
WHEN "0001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000000";
WHEN "0001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110000111";
WHEN "0001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110001110";
WHEN "0010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110010011";
WHEN "0010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110011110";
WHEN "0010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110100110";
WHEN "0010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110101111";
WHEN "0010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101110111000";
WHEN "0010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111000011";
WHEN "0010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111001100";
WHEN "0010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111010111";
WHEN "0011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111100011";
WHEN "0011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111101110";
WHEN "0011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10101111111011";
WHEN "0011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000001001";
WHEN "0011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000010101";
WHEN "0011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000100000";
WHEN "0011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110000110001";
WHEN "0011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001000000";
WHEN "0100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001001101";
WHEN "0100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001011110";
WHEN "0100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001101100";
WHEN "0100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110001111111";
WHEN "0100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010001111";
WHEN "0100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010100001";
WHEN "0100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110010110011";
WHEN "0100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011000101";
WHEN "0101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011010110";
WHEN "0101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011101011";
WHEN "0101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110011111111";
WHEN "0101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100010010";
WHEN "0101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100100101";
WHEN "0101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110100111011";
WHEN "0101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101001110";
WHEN "0101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101100111";
WHEN "0110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110101111100";
WHEN "0110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110010010";
WHEN "0110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110110100110";
WHEN "0110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111000000";
WHEN "0110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111010101";
WHEN "0110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10110111110000";
WHEN "0110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000000110";
WHEN "0110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000100010";
WHEN "0111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111000111001";
WHEN "0111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001010100";
WHEN "0111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111001101111";
WHEN "0111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010001001";
WHEN "0111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010100011";
WHEN "0111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111010111100";
WHEN "0111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011011001";
WHEN "0111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111011110111";
WHEN "1000000" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100010100";
WHEN "1000001" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111100110001";
WHEN "1000010" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101001101";
WHEN "1000011" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111101101010";
WHEN "1000100" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110001000";
WHEN "1000101" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111110100101";
WHEN "1000110" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111000101";
WHEN "1000111" => memoryC2_uid218_sinPiZTableGenerator_q <= "10111111100011";
WHEN "1001000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000000011";
WHEN "1001001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000000100011";
WHEN "1001010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001000100";
WHEN "1001011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000001100010";
WHEN "1001100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010000100";
WHEN "1001101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000010100010";
WHEN "1001110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011000110";
WHEN "1001111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000011101000";
WHEN "1010000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100001010";
WHEN "1010001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000100101101";
WHEN "1010010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101010001";
WHEN "1010011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000101110010";
WHEN "1010100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110010100";
WHEN "1010101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000110111011";
WHEN "1010110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11000111011010";
WHEN "1010111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000000001";
WHEN "1011000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001000100110";
WHEN "1011001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001001011";
WHEN "1011010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001001101101";
WHEN "1011011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010010101";
WHEN "1011100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001010111100";
WHEN "1011101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001011100000";
WHEN "1011110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100000101";
WHEN "1011111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001100101110";
WHEN "1100000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101010100";
WHEN "1100001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001101111010";
WHEN "1100010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001110100010";
WHEN "1100011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111001001";
WHEN "1100100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11001111110001";
WHEN "1100101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000010110";
WHEN "1100110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010000111111";
WHEN "1100111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010001101001";
WHEN "1101000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010010010";
WHEN "1101001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010010111101";
WHEN "1101010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010011100001";
WHEN "1101011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100001100";
WHEN "1101100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010100110111";
WHEN "1101101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010101100001";
WHEN "1101110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110001011";
WHEN "1101111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010110110011";
WHEN "1110000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11010111011111";
WHEN "1110001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000001010";
WHEN "1110010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011000110100";
WHEN "1110011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011001011111";
WHEN "1110100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010001010";
WHEN "1110101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011010110110";
WHEN "1110110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011011100011";
WHEN "1110111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100001111";
WHEN "1111000" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011100111001";
WHEN "1111001" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011101100011";
WHEN "1111010" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110010001";
WHEN "1111011" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011110111011";
WHEN "1111100" => memoryC2_uid218_sinPiZTableGenerator_q <= "11011111101000";
WHEN "1111101" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100000010101";
WHEN "1111110" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001000010";
WHEN "1111111" => memoryC2_uid218_sinPiZTableGenerator_q <= "11100001110000";
WHEN OTHERS =>
memoryC2_uid218_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid68_fpSinPiTest(BITSELECT,67)@6
zPPolyEval_uid68_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(27 downto 0);
zPPolyEval_uid68_fpSinPiTest_b <= zPPolyEval_uid68_fpSinPiTest_in(27 downto 12);
--yT1_uid219_sinPiZPolyEval(BITSELECT,218)@6
yT1_uid219_sinPiZPolyEval_in <= zPPolyEval_uid68_fpSinPiTest_b;
yT1_uid219_sinPiZPolyEval_b <= yT1_uid219_sinPiZPolyEval_in(15 downto 2);
--ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a(DELAY,540)@6
ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yT1_uid219_sinPiZPolyEval_b, xout => ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0(REG,262)@7
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q <= ld_yT1_uid219_sinPiZPolyEval_b_to_reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid232_pT1_uid220_sinPiZPolyEval(MULT,231)@8
prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_a),15)) * SIGNED(prodXY_uid232_pT1_uid220_sinPiZPolyEval_b);
prodXY_uid232_pT1_uid220_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= (others => '0');
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_a <= reg_yT1_uid219_sinPiZPolyEval_0_to_prodXY_uid232_pT1_uid220_sinPiZPolyEval_0_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_b <= memoryC2_uid218_sinPiZTableGenerator_q;
prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid232_pT1_uid220_sinPiZPolyEval_pr,28));
END IF;
END IF;
END PROCESS;
prodXY_uid232_pT1_uid220_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid232_pT1_uid220_sinPiZPolyEval_q <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval(BITSELECT,232)@11
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in <= prodXY_uid232_pT1_uid220_sinPiZPolyEval_q;
prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_in(27 downto 13);
--highBBits_uid222_sinPiZPolyEval(BITSELECT,221)@11
highBBits_uid222_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b;
highBBits_uid222_sinPiZPolyEval_b <= highBBits_uid222_sinPiZPolyEval_in(14 downto 1);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a(DELAY,494)@7
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid217_sinPiZTableGenerator(LOOKUP,216)@10
memoryC1_uid217_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC1_uid217_sinPiZTableGenerator_0_q_to_memoryC1_uid217_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "000000000000000000001";
WHEN "0000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111101011010101010";
WHEN "0000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111010110101010001";
WHEN "0000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111111000001111111100";
WHEN "0000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110101101010101010";
WHEN "0000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110011000101011101";
WHEN "0000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111110000100000010101";
WHEN "0000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101101111011010001";
WHEN "0001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101011010110010101";
WHEN "0001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111101000110001011111";
WHEN "0001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100110001100110010";
WHEN "0001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100011101000010000";
WHEN "0001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111100001000011110111";
WHEN "0001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011110011111101011";
WHEN "0001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011011111011101011";
WHEN "0001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111011001010111110111";
WHEN "0010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010110110100010101";
WHEN "0010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010100010000111100";
WHEN "0010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "111010001101101111000";
WHEN "0010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001111001011000011";
WHEN "0010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001100101000100010";
WHEN "0010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "111001010000110010001";
WHEN "0010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000111100100010111";
WHEN "0010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000101000010110001";
WHEN "0011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000010100001011111";
WHEN "0011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "111000000000000100110";
WHEN "0011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111101100000000011";
WHEN "0011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111010111111111000";
WHEN "0011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110111000100000001000";
WHEN "0011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110110000000110101";
WHEN "0011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110011100001110111";
WHEN "0011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110110001000011011000";
WHEN "0100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101110100101011010";
WHEN "0100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101100000111110101";
WHEN "0100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110101001101010110010";
WHEN "0100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100111001110001011";
WHEN "0100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100100110010001001";
WHEN "0100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110100010010110100110";
WHEN "0100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011111111011100110";
WHEN "0100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011101100001001010";
WHEN "0101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011011000111010011";
WHEN "0101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110011000101101111111";
WHEN "0101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010110010101010010";
WHEN "0101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010011111101001101";
WHEN "0101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "110010001100101110000";
WHEN "0101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001111001110111001";
WHEN "0101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001100111000110000";
WHEN "0101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001010100011001011";
WHEN "0110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "110001000001110010110";
WHEN "0110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000101111010001100";
WHEN "0110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000011100110110001";
WHEN "0110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "110000001010011111111";
WHEN "0110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111111000010000000";
WHEN "0110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111100110000101100";
WHEN "0110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111010100000001100";
WHEN "0110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101111000010000011001";
WHEN "0111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110110000001011100";
WHEN "0111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110011110011001110";
WHEN "0111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101110001100101110101";
WHEN "0111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101111011001010001";
WHEN "0111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101101001101100010";
WHEN "0111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101011000010101010";
WHEN "0111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101101000111000100101";
WHEN "0111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100110101111010111";
WHEN "1000000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100100100111000010";
WHEN "1000001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100010011111100111";
WHEN "1000010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101100000011001000111";
WHEN "1000011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011110010011100000";
WHEN "1000100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011100001110110100";
WHEN "1000101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011010001011000100";
WHEN "1000110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101011000001000001110";
WHEN "1000111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010110000110011000";
WHEN "1001000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010100000101011111";
WHEN "1001001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010010000101100100";
WHEN "1001010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101010000000110101001";
WHEN "1001011" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001110001000110000";
WHEN "1001100" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001100001011110101";
WHEN "1001101" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001010001111111111";
WHEN "1001110" => memoryC1_uid217_sinPiZTableGenerator_q <= "101001000010101000110";
WHEN "1001111" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000110011011010001";
WHEN "1010000" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000100100010100001";
WHEN "1010001" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000010101010110100";
WHEN "1010010" => memoryC1_uid217_sinPiZTableGenerator_q <= "101000000110100001011";
WHEN "1010011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111110111110101011";
WHEN "1010100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111101001010010000";
WHEN "1010101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111011010110110110";
WHEN "1010110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100111001100100101100";
WHEN "1010111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110111110011100011";
WHEN "1011000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110110000011100011";
WHEN "1011001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110100010100101110";
WHEN "1011010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110010100111000101";
WHEN "1011011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100110000111010100001";
WHEN "1011100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101111001111001000";
WHEN "1011101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101101100100111111";
WHEN "1011110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101011111100000000";
WHEN "1011111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101010010100001001";
WHEN "1100000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100101000101101100011";
WHEN "1100001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100111001000001011";
WHEN "1100010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100101100011111111";
WHEN "1100011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100100000001000010";
WHEN "1100100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100010011111010101";
WHEN "1100101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100100000111110111001";
WHEN "1100110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011111011111101010";
WHEN "1100111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011110000001101010";
WHEN "1101000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011100100100111101";
WHEN "1101001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011011001001011111";
WHEN "1101010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011001101111011010";
WHEN "1101011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100011000010110100001";
WHEN "1101100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010110111110111010";
WHEN "1101101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010101101000101000";
WHEN "1101110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010100010011101001";
WHEN "1101111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010011000000000001";
WHEN "1110000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010001101101101010";
WHEN "1110001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100010000011100100111";
WHEN "1110010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001111001100111100";
WHEN "1110011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001101111110100101";
WHEN "1110100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001100110001100100";
WHEN "1110101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001011100101111001";
WHEN "1110110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001010011011100011";
WHEN "1110111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001001010010100101";
WHEN "1111000" => memoryC1_uid217_sinPiZTableGenerator_q <= "100001000001011000000";
WHEN "1111001" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000111000100110100";
WHEN "1111010" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000101111111111100";
WHEN "1111011" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000100111100011111";
WHEN "1111100" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000011111010011000";
WHEN "1111101" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000010111001101010";
WHEN "1111110" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000001111010010101";
WHEN "1111111" => memoryC1_uid217_sinPiZTableGenerator_q <= "100000000111100011001";
WHEN OTHERS =>
memoryC1_uid217_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid223_sinPiZPolyEval(ADD,222)@11
sumAHighB_uid223_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid217_sinPiZTableGenerator_q(20)) & memoryC1_uid217_sinPiZTableGenerator_q);
sumAHighB_uid223_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 14 => highBBits_uid222_sinPiZPolyEval_b(13)) & highBBits_uid222_sinPiZPolyEval_b);
sumAHighB_uid223_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid223_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid223_sinPiZPolyEval_b));
sumAHighB_uid223_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid221_sinPiZPolyEval(BITSELECT,220)@11
lowRangeB_uid221_sinPiZPolyEval_in <= prodXYTruncFR_uid233_pT1_uid220_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid221_sinPiZPolyEval_b <= lowRangeB_uid221_sinPiZPolyEval_in(0 downto 0);
--s1_uid221_uid224_sinPiZPolyEval(BITJOIN,223)@11
s1_uid221_uid224_sinPiZPolyEval_q <= sumAHighB_uid223_sinPiZPolyEval_q & lowRangeB_uid221_sinPiZPolyEval_b;
--reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1(REG,265)@11
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q <= s1_uid221_uid224_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable(LOGICAL,560)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q <= not ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_a;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor(LOGICAL,636)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top(CONSTANT,632)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q <= "010";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp(LOGICAL,633)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg(REG,634)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena(REG,637)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd(LOGICAL,638)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0(REG,264)@6
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q <= zPPolyEval_uid68_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg(DELAY,626)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt(COUNTER,628)
-- every=1, low=0, high=2, step=1, init=1
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i = 1 THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i - 2;
ELSE
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_i,2));
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg(REG,629)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux(MUX,630)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem(DUALMEM,627)
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 2,
numwords_a => 3,
width_b => 16,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_iq(15 downto 0);
--prodXY_uid235_pT2_uid226_sinPiZPolyEval(MULT,234)@12
prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_a),17)) * SIGNED(prodXY_uid235_pT2_uid226_sinPiZPolyEval_b);
prodXY_uid235_pT2_uid226_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= (others => '0');
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid68_fpSinPiTest_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_0_q_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_b <= reg_s1_uid221_uid224_sinPiZPolyEval_0_to_prodXY_uid235_pT2_uid226_sinPiZPolyEval_1_q;
prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid235_pT2_uid226_sinPiZPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid235_pT2_uid226_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid235_pT2_uid226_sinPiZPolyEval_q <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval(BITSELECT,235)@15
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in <= prodXY_uid235_pT2_uid226_sinPiZPolyEval_q;
prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_in(38 downto 15);
--highBBits_uid228_sinPiZPolyEval(BITSELECT,227)@15
highBBits_uid228_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b;
highBBits_uid228_sinPiZPolyEval_b <= highBBits_uid228_sinPiZPolyEval_in(23 downto 2);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor(LOGICAL,623)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q <= not (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_a or ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_b);
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top(CONSTANT,619)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q <= "0100";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp(LOGICAL,620)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_mem_top_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q <= "1" when ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_a = ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_b else "0";
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg(REG,621)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena(REG,624)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd(LOGICAL,625)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_sticky_ena_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_a and ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_b;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg(DELAY,613)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_zAddr_uid67_fpSinPiTest_0_to_memoryC2_uid218_sinPiZTableGenerator_0_q, xout => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,615)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i = 3 THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg(REG,616)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux(MUX,617)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s <= en;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q, ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem(DUALMEM,614)
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_inputreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdreg_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_rdmux_q;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_ia
);
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q <= ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--memoryC0_uid216_sinPiZTableGenerator(LOOKUP,215)@14
memoryC0_uid216_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_zAddr_uid67_fpSinPiTest_0_to_memoryC0_uid216_sinPiZTableGenerator_0_q_to_memoryC0_uid216_sinPiZTableGenerator_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001111110110101110";
WHEN "0000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001110100100000010";
WHEN "0000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100001010101100000000";
WHEN "0000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100100000100001110101000";
WHEN "0000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011111011001011111101";
WHEN "0000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011101111100100000010";
WHEN "0000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011100001010110111011";
WHEN "0000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100011010000100100101111";
WHEN "0001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010111101001101100010";
WHEN "0001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010100111010001011101";
WHEN "0001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100010001110110000100111";
WHEN "0001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001110011101011001001";
WHEN "0001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100001010110000001001110";
WHEN "0001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000110101110011000000";
WHEN "0001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100100000010011000000101011";
WHEN "0001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111101101101010011101";
WHEN "0010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011111000101110000100010";
WHEN "0010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011110011011010011001011";
WHEN "0010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011101101110010010100101";
WHEN "0010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100111110101111000011";
WHEN "0010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011100001100101000110101";
WHEN "0010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011011011000000000001111";
WHEN "0010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011010100000110101100011";
WHEN "0010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011001100111001001000110";
WHEN "0011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100011000101010111011001110";
WHEN "0011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010111101100001100010000";
WHEN "0011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010110101010111100100100";
WHEN "0011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010101100111001100100010";
WHEN "0011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010100100000111100100011";
WHEN "0011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010011011000001101000000";
WHEN "0011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010010001100111110010110";
WHEN "0011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100010000111111010000111111";
WHEN "0100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001111101111000101010111";
WHEN "0100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001110011100011011111110";
WHEN "0100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001101000111010101010001";
WHEN "0100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001011101111110001110000";
WHEN "0100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001010010101110001111010";
WHEN "0100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100001000111001010110010010";
WHEN "0100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000111011010011111011001";
WHEN "0100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000101111001001101110010";
WHEN "0101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000100010101100010000001";
WHEN "0101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000010101111011100101011";
WHEN "0101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01100000001000110111110010101";
WHEN "0101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111111011100000111100110";
WHEN "0101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111101101110111001000101";
WHEN "0101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111011111111010011011011";
WHEN "0101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111010001101010111001111";
WHEN "0101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011111000011001000101001110";
WHEN "0110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110110100010011110000000";
WHEN "0110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110100101001100010010010";
WHEN "0110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110010101110010010110000";
WHEN "0110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011110000110000110000001000";
WHEN "0110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101110110000111011000111";
WHEN "0110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101100101110110100011101";
WHEN "0110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101010101010011100111001";
WHEN "0110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011101000100011110101001100";
WHEN "0111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100110011010111110000111";
WHEN "0111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100100001111111000011101";
WHEN "0111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011100010000010100101000000";
WHEN "0111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011111110011000100100100";
WHEN "0111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011101100001010111111110";
WHEN "0111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011011001101100000000011";
WHEN "0111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011011000110111011101101010";
WHEN "0111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010110011111010001101001";
WHEN "1000000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010100000100111100111000";
WHEN "1000001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011010001101000100000001111";
WHEN "1000010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001111001001111100100111";
WHEN "1000011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001100101001010010111011";
WHEN "1000100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011001010000110100100000101";
WHEN "1000101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000111100001110001000001";
WHEN "1000110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000100111010111010101011";
WHEN "1000111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01011000010010010000001111111";
WHEN "1001000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111111100111000111111011";
WHEN "1001001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111100111010001101011110";
WHEN "1001010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010111010001011010011100110";
WHEN "1001011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110111011010011011010011";
WHEN "1001100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110100100111100101100110";
WHEN "1001101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010110001110010110011011111";
WHEN "1001110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101110111100000110000001";
WHEN "1001111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101100000011011110001110";
WHEN "1010000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010101001001000111101001000";
WHEN "1010001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100110001100100011110100";
WHEN "1010010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100011001110010011010110";
WHEN "1010011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010100000001110001100110010";
WHEN "1010100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011101001100010001001111";
WHEN "1010101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010011010001000100001110100";
WHEN "1010110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010111000010111111100101";
WHEN "1010111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010011111011101011101100";
WHEN "1011000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010010000110010100111010001";
WHEN "1011001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001101100111110011011011";
WHEN "1011010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010001010011011010001010100";
WHEN "1011011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000111001101000010000111";
WHEN "1011100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000011111101000110111110";
WHEN "1011101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01010000000101011100001000010";
WHEN "1011110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111101011000010001100001";
WHEN "1011111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001111010000011011001100111";
WHEN "1100000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110110101100111010011111";
WHEN "1100001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001110011010100110101010111";
WHEN "1100010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101111111011001011011101";
WHEN "1100011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101100011111111101111111";
WHEN "1100100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001101001000011001110001011";
WHEN "1100101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100101100100111101010001";
WHEN "1100110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001100010000101001100100001";
WHEN "1100111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011110100011111101001011";
WHEN "1101000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001011011000001010000011111";
WHEN "1101001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010111011101000111101111";
WHEN "1101010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010011110111100100001011";
WHEN "1101011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001010000010000100111000111";
WHEN "1101100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001100101000010001110101";
WHEN "1101101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001001000111110100101100111";
WHEN "1101110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000101010011100011110001";
WHEN "1101111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01001000001100111001101100110";
WHEN "1110000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111101111001100100011011";
WHEN "1110001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000111010001010101001100101";
WHEN "1110010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110110011010011110010111";
WHEN "1110011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000110010101001000100001000";
WHEN "1110100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101110110110011100001101";
WHEN "1110101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000101011000010100111111100";
WHEN "1110110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100111001101101000101100";
WHEN "1110111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000100011010111011111110011";
WHEN "1111000" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011111100000001110101000";
WHEN "1111001" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000011011100111110110100010";
WHEN "1111010" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010111101110011000111010";
WHEN "1111011" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000010011110011110111000111";
WHEN "1111100" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001111111000010010100010";
WHEN "1111101" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000001011111011101100100011";
WHEN "1111110" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000111111110000110100011";
WHEN "1111111" => memoryC0_uid216_sinPiZTableGenerator_q <= "01000000011111111100001111011";
WHEN OTHERS =>
memoryC0_uid216_sinPiZTableGenerator_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid229_sinPiZPolyEval(ADD,228)@15
sumAHighB_uid229_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid216_sinPiZTableGenerator_q(28)) & memoryC0_uid216_sinPiZTableGenerator_q);
sumAHighB_uid229_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid228_sinPiZPolyEval_b(21)) & highBBits_uid228_sinPiZPolyEval_b);
sumAHighB_uid229_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid229_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid229_sinPiZPolyEval_b));
sumAHighB_uid229_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_o(29 downto 0);
--lowRangeB_uid227_sinPiZPolyEval(BITSELECT,226)@15
lowRangeB_uid227_sinPiZPolyEval_in <= prodXYTruncFR_uid236_pT2_uid226_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid227_sinPiZPolyEval_b <= lowRangeB_uid227_sinPiZPolyEval_in(1 downto 0);
--s2_uid227_uid230_sinPiZPolyEval(BITJOIN,229)@15
s2_uid227_uid230_sinPiZPolyEval_q <= sumAHighB_uid229_sinPiZPolyEval_q & lowRangeB_uid227_sinPiZPolyEval_b;
--fxpSinRes_uid70_fpSinPiTest(BITSELECT,69)@15
fxpSinRes_uid70_fpSinPiTest_in <= s2_uid227_uid230_sinPiZPolyEval_q(29 downto 0);
fxpSinRes_uid70_fpSinPiTest_b <= fxpSinRes_uid70_fpSinPiTest_in(29 downto 5);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b(DELAY,326)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multRightOp_uid72_fpSinPiTest(MUX,71)@15
multRightOp_uid72_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_multRightOp_uid72_fpSinPiTest_b_q;
multRightOp_uid72_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multRightOp_uid72_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multRightOp_uid72_fpSinPiTest_s IS
WHEN "0" => multRightOp_uid72_fpSinPiTest_q <= fxpSinRes_uid70_fpSinPiTest_b;
WHEN "1" => multRightOp_uid72_fpSinPiTest_q <= piwFP2_uid71_fpSinPiTest_q;
WHEN OTHERS => multRightOp_uid72_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor(LOGICAL,561)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q <= not (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_a or ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_b);
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top(CONSTANT,557)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q <= "01000";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp(LOGICAL,558)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_mem_top_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q <= "1" when ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_a = ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_b else "0";
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg(REG,559)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena(REG,562)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd(LOGICAL,563)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_sticky_ena_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_a and ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_b;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg(DELAY,551)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oFracX_uid35_uid35_fpSinPiTest_q, xout => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt(COUNTER,553)
-- every=1, low=0, high=8, step=1, init=1
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i = 7 THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i - 8;
ELSE
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg(REG,554)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux(MUX,555)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q, ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem(DUALMEM,552)
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_inputreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdreg_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_rdmux_q;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 9,
width_b => 24,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_ia
);
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_iq(23 downto 0);
--ozz_uid45_fpSinPiTest(CONSTANT,44)
ozz_uid45_fpSinPiTest_q <= "00000000000000000000000000000000000";
--vStage_uid150_lzcZ_uid55_fpSinPiTest(BITSELECT,149)@6
vStage_uid150_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(2 downto 0);
vStage_uid150_lzcZ_uid55_fpSinPiTest_b <= vStage_uid150_lzcZ_uid55_fpSinPiTest_in(2 downto 0);
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b(DELAY,463)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 4 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest(BITJOIN,188)@10
leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor(LOGICAL,599)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q <= not (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_a or ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_b);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg(REG,597)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena(REG,600)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_nor_q = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd(LOGICAL,601)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_sticky_ena_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_a and ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_b;
--X18dto0_uid185_alignedZ_uid56_fpSinPiTest(BITSELECT,184)@6
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in <= z_uid53_fpSinPiTest_q(18 downto 0);
X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b <= X18dto0_uid185_alignedZ_uid56_fpSinPiTest_in(18 downto 0);
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg(DELAY,591)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 19, depth => 1 )
PORT MAP ( xin => X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b, xout => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt(COUNTER,593)
-- every=1, low=0, high=1, step=1, init=1
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_i,1));
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg(REG,594)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux(MUX,595)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s <= en;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux: PROCESS (ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q, ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem(DUALMEM,592)
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_inputreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 1,
numwords_a => 2,
width_b => 19,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_ia
);
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_iq(18 downto 0);
--leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest(BITJOIN,185)@10
leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor(LOGICAL,610)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q <= not (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_a or ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_b);
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena(REG,611)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd(LOGICAL,612)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_sticky_ena_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_a and ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_b;
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg(DELAY,602)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 35, depth => 1 )
PORT MAP ( xin => z_uid53_fpSinPiTest_q, xout => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem(DUALMEM,603)
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_inputreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdreg_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab <= ld_X18dto0_uid185_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_b_replace_rdmux_q;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 35,
widthad_a => 1,
numwords_a => 2,
width_b => 35,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_iq(34 downto 0);
--rVStage_uid147_lzcZ_uid55_fpSinPiTest(BITSELECT,146)@6
rVStage_uid147_lzcZ_uid55_fpSinPiTest_in <= z_uid53_fpSinPiTest_q;
rVStage_uid147_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_in(34 downto 3);
--vCount_uid148_lzcZ_uid55_fpSinPiTest(LOGICAL,147)@6
vCount_uid148_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid147_lzcZ_uid55_fpSinPiTest_b;
vCount_uid148_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx2Pad32_uid117_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid148_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid148_lzcZ_uid55_fpSinPiTest_a = vCount_uid148_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid148_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f(DELAY,460)@7
ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid148_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b(DELAY,425)@6
ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => vStage_uid150_lzcZ_uid55_fpSinPiTest_b, xout => ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid149_lzcZ_uid55_fpSinPiTest(CONSTANT,148)
mO_uid149_lzcZ_uid55_fpSinPiTest_q <= "11111111111111111111111111111";
--cStage_uid151_lzcZ_uid55_fpSinPiTest(BITJOIN,150)@7
cStage_uid151_lzcZ_uid55_fpSinPiTest_q <= ld_vStage_uid150_lzcZ_uid55_fpSinPiTest_b_to_cStage_uid151_lzcZ_uid55_fpSinPiTest_b_q & mO_uid149_lzcZ_uid55_fpSinPiTest_q;
--ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c(DELAY,427)@6
ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid147_lzcZ_uid55_fpSinPiTest_b, xout => ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid153_lzcZ_uid55_fpSinPiTest(MUX,152)@7
vStagei_uid153_lzcZ_uid55_fpSinPiTest_s <= vCount_uid148_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid153_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid153_lzcZ_uid55_fpSinPiTest_s, en, ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q, cStage_uid151_lzcZ_uid55_fpSinPiTest_q)
BEGIN
CASE vStagei_uid153_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= ld_rVStage_uid147_lzcZ_uid55_fpSinPiTest_b_to_vStagei_uid153_lzcZ_uid55_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= cStage_uid151_lzcZ_uid55_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid153_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid155_lzcZ_uid55_fpSinPiTest(BITSELECT,154)@7
rVStage_uid155_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid155_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_in(31 downto 16);
--vCount_uid156_lzcZ_uid55_fpSinPiTest(LOGICAL,155)@7
vCount_uid156_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
vCount_uid156_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage0Idx1Pad16_uid114_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid156_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid156_lzcZ_uid55_fpSinPiTest_a = vCount_uid156_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a(DELAY,533)@7
ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid156_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4(REG,255)@8
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q <= ld_vCount_uid156_lzcZ_uid55_fpSinPiTest_q_to_reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid157_lzcZ_uid55_fpSinPiTest(BITSELECT,156)@7
vStage_uid157_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid153_lzcZ_uid55_fpSinPiTest_q(15 downto 0);
vStage_uid157_lzcZ_uid55_fpSinPiTest_b <= vStage_uid157_lzcZ_uid55_fpSinPiTest_in(15 downto 0);
--vStagei_uid159_lzcZ_uid55_fpSinPiTest(MUX,158)@7
vStagei_uid159_lzcZ_uid55_fpSinPiTest_s <= vCount_uid156_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid159_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid159_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid155_lzcZ_uid55_fpSinPiTest_b, vStage_uid157_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid159_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid155_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= vStage_uid157_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid159_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid161_lzcZ_uid55_fpSinPiTest(BITSELECT,160)@7
rVStage_uid161_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid161_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1(REG,250)@7
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q <= rVStage_uid161_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid162_lzcZ_uid55_fpSinPiTest(LOGICAL,161)@8
vCount_uid162_lzcZ_uid55_fpSinPiTest_a <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_b <= cstAllZWE_uid16_fpSinPiTest_q;
vCount_uid162_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid162_lzcZ_uid55_fpSinPiTest_a = vCount_uid162_lzcZ_uid55_fpSinPiTest_b else "0";
--ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d(DELAY,458)@8
ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid162_lzcZ_uid55_fpSinPiTest_q, xout => ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid163_lzcZ_uid55_fpSinPiTest(BITSELECT,162)@7
vStage_uid163_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid159_lzcZ_uid55_fpSinPiTest_q(7 downto 0);
vStage_uid163_lzcZ_uid55_fpSinPiTest_b <= vStage_uid163_lzcZ_uid55_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3(REG,252)@7
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid163_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid165_lzcZ_uid55_fpSinPiTest(MUX,164)@8
vStagei_uid165_lzcZ_uid55_fpSinPiTest_s <= vCount_uid162_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid165_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid165_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q, reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid165_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid161_lzcZ_uid55_fpSinPiTest_0_to_vCount_uid162_lzcZ_uid55_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid163_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid165_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid165_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid167_lzcZ_uid55_fpSinPiTest(BITSELECT,166)@8
rVStage_uid167_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid167_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_in(7 downto 4);
--vCount_uid168_lzcZ_uid55_fpSinPiTest(LOGICAL,167)@8
vCount_uid168_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
vCount_uid168_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid168_lzcZ_uid55_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid168_lzcZ_uid55_fpSinPiTest_a = vCount_uid168_lzcZ_uid55_fpSinPiTest_b) THEN
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "1";
ELSE
vCount_uid168_lzcZ_uid55_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid169_lzcZ_uid55_fpSinPiTest(BITSELECT,168)@8
vStage_uid169_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid165_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
vStage_uid169_lzcZ_uid55_fpSinPiTest_b <= vStage_uid169_lzcZ_uid55_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3(REG,254)@8
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q <= vStage_uid169_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2(REG,253)@8
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q <= rVStage_uid167_lzcZ_uid55_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid171_lzcZ_uid55_fpSinPiTest(MUX,170)@9
vStagei_uid171_lzcZ_uid55_fpSinPiTest_s <= vCount_uid168_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid171_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid171_lzcZ_uid55_fpSinPiTest_s, en, reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q, reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid171_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_rVStage_uid167_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= reg_vStage_uid169_lzcZ_uid55_fpSinPiTest_0_to_vStagei_uid171_lzcZ_uid55_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid171_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid173_lzcZ_uid55_fpSinPiTest(BITSELECT,172)@9
rVStage_uid173_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid173_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_in(3 downto 2);
--vCount_uid174_lzcZ_uid55_fpSinPiTest(LOGICAL,173)@9
vCount_uid174_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
vCount_uid174_lzcZ_uid55_fpSinPiTest_b <= leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
vCount_uid174_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid174_lzcZ_uid55_fpSinPiTest_a = vCount_uid174_lzcZ_uid55_fpSinPiTest_b else "0";
--vStage_uid175_lzcZ_uid55_fpSinPiTest(BITSELECT,174)@9
vStage_uid175_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid171_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
vStage_uid175_lzcZ_uid55_fpSinPiTest_b <= vStage_uid175_lzcZ_uid55_fpSinPiTest_in(1 downto 0);
--vStagei_uid177_lzcZ_uid55_fpSinPiTest(MUX,176)@9
vStagei_uid177_lzcZ_uid55_fpSinPiTest_s <= vCount_uid174_lzcZ_uid55_fpSinPiTest_q;
vStagei_uid177_lzcZ_uid55_fpSinPiTest: PROCESS (vStagei_uid177_lzcZ_uid55_fpSinPiTest_s, en, rVStage_uid173_lzcZ_uid55_fpSinPiTest_b, vStage_uid175_lzcZ_uid55_fpSinPiTest_b)
BEGIN
CASE vStagei_uid177_lzcZ_uid55_fpSinPiTest_s IS
WHEN "0" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= rVStage_uid173_lzcZ_uid55_fpSinPiTest_b;
WHEN "1" => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= vStage_uid175_lzcZ_uid55_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid177_lzcZ_uid55_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid179_lzcZ_uid55_fpSinPiTest(BITSELECT,178)@9
rVStage_uid179_lzcZ_uid55_fpSinPiTest_in <= vStagei_uid177_lzcZ_uid55_fpSinPiTest_q;
rVStage_uid179_lzcZ_uid55_fpSinPiTest_b <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_in(1 downto 1);
--vCount_uid180_lzcZ_uid55_fpSinPiTest(LOGICAL,179)@9
vCount_uid180_lzcZ_uid55_fpSinPiTest_a <= rVStage_uid179_lzcZ_uid55_fpSinPiTest_b;
vCount_uid180_lzcZ_uid55_fpSinPiTest_b <= GND_q;
vCount_uid180_lzcZ_uid55_fpSinPiTest_q <= "1" when vCount_uid180_lzcZ_uid55_fpSinPiTest_a = vCount_uid180_lzcZ_uid55_fpSinPiTest_b else "0";
--r_uid181_lzcZ_uid55_fpSinPiTest(BITJOIN,180)@9
r_uid181_lzcZ_uid55_fpSinPiTest_q <= ld_vCount_uid148_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_f_q & reg_vCount_uid156_lzcZ_uid55_fpSinPiTest_0_to_r_uid181_lzcZ_uid55_fpSinPiTest_4_q & ld_vCount_uid162_lzcZ_uid55_fpSinPiTest_q_to_r_uid181_lzcZ_uid55_fpSinPiTest_d_q & vCount_uid168_lzcZ_uid55_fpSinPiTest_q & vCount_uid174_lzcZ_uid55_fpSinPiTest_q & vCount_uid180_lzcZ_uid55_fpSinPiTest_q;
--leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest(BITSELECT,190)@9
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_in(5 downto 4);
--reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1(REG,256)@9
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest(MUX,191)@10
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel5Dto4_uid191_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s, en, ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q, leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q, ozz_uid45_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ld_z_uid53_fpSinPiTest_q_to_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx1_uid186_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage0Idx2_uid189_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= ozz_uid45_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest(BITSELECT,199)@10
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(22 downto 0);
LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_in(22 downto 0);
--ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b(DELAY,474)@10
ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest(BITJOIN,200)@11
leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage022dto0_uid200_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx3Pad12_uid129_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest(BITSELECT,196)@10
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(26 downto 0);
LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_in(26 downto 0);
--ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b(DELAY,472)@10
ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest(BITJOIN,197)@11
leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage026dto0_uid197_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_b_q & cstAllZWE_uid16_fpSinPiTest_q;
--LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest(BITSELECT,193)@10
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q(30 downto 0);
LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_in(30 downto 0);
--ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b(DELAY,470)@10
ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 31, depth => 1 )
PORT MAP ( xin => LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest(BITJOIN,194)@11
leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage030dto0_uid194_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage1Idx1Pad4_uid123_fixedPointX_uid41_fpSinPiTest_q;
--reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2(REG,258)@10
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest(BITSELECT,201)@9
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1(REG,257)@9
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b(DELAY,476)@10
ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest(MUX,202)@11
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s <= ld_reg_leftShiftStageSel3Dto2_uid202_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_1_q_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_b_q;
leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q, leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage0_uid192_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx1_uid195_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx2_uid198_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage1Idx3_uid201_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest(BITSELECT,210)@11
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(31 downto 0);
LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_in(31 downto 0);
--ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b(DELAY,486)@11
ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest(BITJOIN,211)@12
leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage131dto0_uid211_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx3Pad3_uid140_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest(BITSELECT,207)@11
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(32 downto 0);
LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_in(32 downto 0);
--ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b(DELAY,484)@11
ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest(BITJOIN,208)@12
leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage132dto0_uid208_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_b_q & leftShiftStage2Idx2Pad2_uid137_fixedPointX_uid41_fpSinPiTest_q;
--LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest(BITSELECT,204)@11
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q(33 downto 0);
LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b <= LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_in(33 downto 0);
--ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b(DELAY,482)@11
ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 34, depth => 1 )
PORT MAP ( xin => LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b, xout => ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest(BITJOIN,205)@12
leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q <= ld_LeftShiftStage133dto0_uid205_alignedZ_uid56_fpSinPiTest_b_to_leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2(REG,260)@11
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q <= leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest(BITSELECT,212)@9
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in <= r_uid181_lzcZ_uid55_fpSinPiTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a(DELAY,537)@9
ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1(REG,259)@11
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_b_to_reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest(MUX,213)@12
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s <= reg_leftShiftStageSel1Dto0_uid213_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_1_q;
leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest: PROCESS (leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s, en, reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q, leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q, leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= reg_leftShiftStage1_uid203_alignedZ_uid56_fpSinPiTest_0_to_leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx1_uid206_alignedZ_uid56_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx2_uid209_alignedZ_uid56_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= leftShiftStage2Idx3_uid212_alignedZ_uid56_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--alignedZLow_uid57_fpSinPiTest(BITSELECT,56)@12
alignedZLow_uid57_fpSinPiTest_in <= leftShiftStage2_uid214_alignedZ_uid56_fpSinPiTest_q;
alignedZLow_uid57_fpSinPiTest_b <= alignedZLow_uid57_fpSinPiTest_in(34 downto 12);
--pHardCase_uid58_fpSinPiTest(BITJOIN,57)@12
pHardCase_uid58_fpSinPiTest_q <= alignedZLow_uid57_fpSinPiTest_b & GND_q;
--ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b(DELAY,313)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid59_fpSinPiTest(MUX,58)@12
p_uid59_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_p_uid59_fpSinPiTest_b_q;
p_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid59_fpSinPiTest_s IS
WHEN "0" => p_uid59_fpSinPiTest_q <= pHardCase_uid58_fpSinPiTest_q;
WHEN "1" => p_uid59_fpSinPiTest_q <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => p_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg(DELAY,577)
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => p_uid59_fpSinPiTest_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a(DELAY,328)@13
ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_inputreg_q, xout => ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--mul2xSinRes_uid73_fpSinPiTest(MULT,72)@16
mul2xSinRes_uid73_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid73_fpSinPiTest_b);
mul2xSinRes_uid73_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid73_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_a <= ld_p_uid59_fpSinPiTest_q_to_mul2xSinRes_uid73_fpSinPiTest_a_q;
mul2xSinRes_uid73_fpSinPiTest_b <= multRightOp_uid72_fpSinPiTest_q;
mul2xSinRes_uid73_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid73_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid73_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid73_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid73_fpSinPiTest_q <= mul2xSinRes_uid73_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid74_fpSinPiTest(BITSELECT,73)@19
normBit_uid74_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q;
normBit_uid74_fpSinPiTest_b <= normBit_uid74_fpSinPiTest_in(48 downto 48);
--rndExpUpdate_uid79_uid80_fpSinPiTest(BITJOIN,79)@19
rndExpUpdate_uid79_uid80_fpSinPiTest_q <= normBit_uid74_fpSinPiTest_b & cstAllZWF_uid10_fpSinPiTest_q & VCC_q;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor(LOGICAL,588)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q <= not (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_a or ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_b);
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top(CONSTANT,584)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q <= "0101";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp(LOGICAL,585)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_mem_top_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_a = ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg(REG,586)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena(REG,589)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd(LOGICAL,590)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_a and ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor(LOGICAL,574)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q <= not (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_a or ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_b);
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top(CONSTANT,570)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp(LOGICAL,571)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_mem_top_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q <= "1" when ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_a = ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_b else "0";
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg(REG,572)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena(REG,575)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_nor_q = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd(LOGICAL,576)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_sticky_ena_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_a and ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_b;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg(DELAY,564)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpSinPiTest_b, xout => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt(COUNTER,566)
-- every=1, low=0, high=7, step=1, init=1
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg(REG,567)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux(MUX,568)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q, ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem(DUALMEM,565)
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_inputreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdreg_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_rdmux_q;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_ia
);
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q <= ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--expXP1_uid62_fpSinPiTest(ADD,61)@10
expXP1_uid62_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpSinPiTest_b_to_expXP1_uid62_fpSinPiTest_a_replace_mem_q);
expXP1_uid62_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & VCC_q);
expXP1_uid62_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXP1_uid62_fpSinPiTest_a) + UNSIGNED(expXP1_uid62_fpSinPiTest_b));
expXP1_uid62_fpSinPiTest_q <= expXP1_uid62_fpSinPiTest_o(8 downto 0);
--expXP1R_uid63_fpSinPiTest(BITSELECT,62)@10
expXP1R_uid63_fpSinPiTest_in <= expXP1_uid62_fpSinPiTest_q(7 downto 0);
expXP1R_uid63_fpSinPiTest_b <= expXP1R_uid63_fpSinPiTest_in(7 downto 0);
--reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1(REG,267)@9
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q <= r_uid181_lzcZ_uid55_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid61_fpSinPiTest(SUB,60)@10
expHardCase_uid61_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid31_fpSinPiTest_q);
expHardCase_uid61_fpSinPiTest_b <= STD_LOGIC_VECTOR("000" & reg_r_uid181_lzcZ_uid55_fpSinPiTest_0_to_expHardCase_uid61_fpSinPiTest_1_q);
expHardCase_uid61_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpSinPiTest_a) - UNSIGNED(expHardCase_uid61_fpSinPiTest_b));
expHardCase_uid61_fpSinPiTest_q <= expHardCase_uid61_fpSinPiTest_o(8 downto 0);
--expHardCaseR_uid64_fpSinPiTest(BITSELECT,63)@10
expHardCaseR_uid64_fpSinPiTest_in <= expHardCase_uid61_fpSinPiTest_q(7 downto 0);
expHardCaseR_uid64_fpSinPiTest_b <= expHardCaseR_uid64_fpSinPiTest_in(7 downto 0);
--ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b(DELAY,320)@0
ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_c, xout => ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expP_uid65_fpSinPiTest(MUX,64)@10
expP_uid65_fpSinPiTest_s <= ld_sinXIsX_uid34_fpSinPiTest_c_to_expP_uid65_fpSinPiTest_b_q;
expP_uid65_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid65_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid65_fpSinPiTest_s IS
WHEN "0" => expP_uid65_fpSinPiTest_q <= expHardCaseR_uid64_fpSinPiTest_b;
WHEN "1" => expP_uid65_fpSinPiTest_q <= expXP1R_uid63_fpSinPiTest_b;
WHEN OTHERS => expP_uid65_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg(DELAY,578)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expP_uid65_fpSinPiTest_q, xout => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt(COUNTER,580)
-- every=1, low=0, high=5, step=1, init=1
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i = 4 THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i - 5;
ELSE
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg(REG,581)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux(MUX,582)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem(DUALMEM,579)
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_inputreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_iq(7 downto 0);
--highRes_uid75_fpSinPiTest(BITSELECT,74)@19
highRes_uid75_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(47 downto 0);
highRes_uid75_fpSinPiTest_b <= highRes_uid75_fpSinPiTest_in(47 downto 24);
--lowRes_uid76_fpSinPiTest(BITSELECT,75)@19
lowRes_uid76_fpSinPiTest_in <= mul2xSinRes_uid73_fpSinPiTest_q(46 downto 0);
lowRes_uid76_fpSinPiTest_b <= lowRes_uid76_fpSinPiTest_in(46 downto 23);
--fracRCompPreRnd_uid77_fpSinPiTest(MUX,76)@19
fracRCompPreRnd_uid77_fpSinPiTest_s <= normBit_uid74_fpSinPiTest_b;
fracRCompPreRnd_uid77_fpSinPiTest: PROCESS (fracRCompPreRnd_uid77_fpSinPiTest_s, en, lowRes_uid76_fpSinPiTest_b, highRes_uid75_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid77_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid77_fpSinPiTest_q <= lowRes_uid76_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid77_fpSinPiTest_q <= highRes_uid75_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid77_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid78_uid78_fpSinPiTest(BITJOIN,77)@19
expFracPreRnd_uid78_uid78_fpSinPiTest_q <= ld_expP_uid65_fpSinPiTest_q_to_expFracPreRnd_uid78_uid78_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid77_fpSinPiTest_q;
--expFracComp_uid81_fpSinPiTest(ADD,80)@19
expFracComp_uid81_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracPreRnd_uid78_uid78_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndExpUpdate_uid79_uid80_fpSinPiTest_q);
expFracComp_uid81_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid81_fpSinPiTest_a) + UNSIGNED(expFracComp_uid81_fpSinPiTest_b));
expFracComp_uid81_fpSinPiTest_q <= expFracComp_uid81_fpSinPiTest_o(32 downto 0);
--expRComp_uid83_fpSinPiTest(BITSELECT,82)@19
expRComp_uid83_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(31 downto 0);
expRComp_uid83_fpSinPiTest_b <= expRComp_uid83_fpSinPiTest_in(31 downto 24);
--reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2(REG,271)@19
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q <= expRComp_uid83_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2(REG,270)@4
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q <= xIsInt_uid87_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2(REG,244)@0
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q <= expXIsZero_uid18_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b(DELAY,358)@1
ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q, xout => ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--regXAndInt_uid91_fpSinPiTest(LOGICAL,90)@4
regXAndInt_uid91_fpSinPiTest_a <= xIsInt_uid87_fpSinPiTest_q;
regXAndInt_uid91_fpSinPiTest_b <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
regXAndInt_uid91_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
regXAndInt_uid91_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
regXAndInt_uid91_fpSinPiTest_q <= regXAndInt_uid91_fpSinPiTest_a and regXAndInt_uid91_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--excRZero_uid92_fpSinPiTest(LOGICAL,91)@5
excRZero_uid92_fpSinPiTest_a <= regXAndInt_uid91_fpSinPiTest_q;
excRZero_uid92_fpSinPiTest_b <= ld_reg_expXIsZero_uid18_fpSinPiTest_0_to_excRZero_uid92_fpSinPiTest_2_q_to_excRZero_uid92_fpSinPiTest_b_q;
excRZero_uid92_fpSinPiTest_q <= excRZero_uid92_fpSinPiTest_a or excRZero_uid92_fpSinPiTest_b;
--rZOrXInt_uid98_fpSinPiTest(LOGICAL,97)@5
rZOrXInt_uid98_fpSinPiTest_a <= excRZero_uid92_fpSinPiTest_q;
rZOrXInt_uid98_fpSinPiTest_b <= reg_xIsInt_uid87_fpSinPiTest_0_to_rZOrXInt_uid98_fpSinPiTest_2_q;
rZOrXInt_uid98_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rZOrXInt_uid98_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
rZOrXInt_uid98_fpSinPiTest_q <= rZOrXInt_uid98_fpSinPiTest_a or rZOrXInt_uid98_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b(DELAY,369)@6
ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => rZOrXInt_uid98_fpSinPiTest_q, xout => ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRPostExc1_uid101_fpSinPiTest(MUX,100)@20
expRPostExc1_uid101_fpSinPiTest_s <= ld_rZOrXInt_uid98_fpSinPiTest_q_to_expRPostExc1_uid101_fpSinPiTest_b_q;
expRPostExc1_uid101_fpSinPiTest: PROCESS (expRPostExc1_uid101_fpSinPiTest_s, en, reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q, cstAllZWE_uid16_fpSinPiTest_q)
BEGIN
CASE expRPostExc1_uid101_fpSinPiTest_s IS
WHEN "0" => expRPostExc1_uid101_fpSinPiTest_q <= reg_expRComp_uid83_fpSinPiTest_0_to_expRPostExc1_uid101_fpSinPiTest_2_q;
WHEN "1" => expRPostExc1_uid101_fpSinPiTest_q <= cstAllZWE_uid16_fpSinPiTest_q;
WHEN OTHERS => expRPostExc1_uid101_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor(LOGICAL,649)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a <= ld_oFracX_uid35_uid35_fpSinPiTest_q_to_p_uid59_fpSinPiTest_d_notEnable_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q <= not (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_a or ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_b);
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top(CONSTANT,645)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q <= "01100";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp(LOGICAL,646)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_mem_top_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q <= "1" when ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_a = ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_b else "0";
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg(REG,647)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena(REG,650)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_nor_q = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd(LOGICAL,651)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_sticky_ena_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_a and ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_b;
--InvXIntExp_uid88_fpSinPiTest(LOGICAL,87)@4
InvXIntExp_uid88_fpSinPiTest_a <= ld_xIntExp_uid30_fpSinPiTest_c_to_xIntYz_uid86_fpSinPiTest_a_q;
InvXIntExp_uid88_fpSinPiTest_q <= not InvXIntExp_uid88_fpSinPiTest_a;
--join_uid46_fpSinPiTest(BITJOIN,45)@4
join_uid46_fpSinPiTest_q <= VCC_q & ozz_uid45_fpSinPiTest_q;
--yIsZero_uid47_fpSinPiTest(LOGICAL,46)@4
yIsZero_uid47_fpSinPiTest_a <= reg_y_uid43_fpSinPiTest_0_to_yIsZero_uid47_fpSinPiTest_1_q;
yIsZero_uid47_fpSinPiTest_b <= join_uid46_fpSinPiTest_q;
yIsZero_uid47_fpSinPiTest_q <= "1" when yIsZero_uid47_fpSinPiTest_a = yIsZero_uid47_fpSinPiTest_b else "0";
--xRyHalf_uid90_fpSinPiTest(LOGICAL,89)@4
xRyHalf_uid90_fpSinPiTest_a <= ld_exc_R_uid29_fpSinPiTest_q_to_xIsInt_uid87_fpSinPiTest_a_q;
xRyHalf_uid90_fpSinPiTest_b <= yIsZero_uid47_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_c <= InvSinXIsX_uid84_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_d <= InvXIntExp_uid88_fpSinPiTest_q;
xRyHalf_uid90_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_a and xRyHalf_uid90_fpSinPiTest_b and xRyHalf_uid90_fpSinPiTest_c and xRyHalf_uid90_fpSinPiTest_d;
--excRNaN_uid93_fpSinPiTest(LOGICAL,92)@0
excRNaN_uid93_fpSinPiTest_a <= exc_N_uid25_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_b <= exc_I_uid23_fpSinPiTest_q;
excRNaN_uid93_fpSinPiTest_q <= excRNaN_uid93_fpSinPiTest_a or excRNaN_uid93_fpSinPiTest_b;
--ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b(DELAY,371)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRIoN_uid102_fpSinPiTest(LOGICAL,101)@4
excRIoN_uid102_fpSinPiTest_a <= GND_q;
excRIoN_uid102_fpSinPiTest_b <= ld_excRNaN_uid93_fpSinPiTest_q_to_excRIoN_uid102_fpSinPiTest_b_q;
excRIoN_uid102_fpSinPiTest_q <= excRIoN_uid102_fpSinPiTest_a or excRIoN_uid102_fpSinPiTest_b;
--join_uid103_fpSinPiTest(BITJOIN,102)@4
join_uid103_fpSinPiTest_q <= xRyHalf_uid90_fpSinPiTest_q & excRIoN_uid102_fpSinPiTest_q;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg(DELAY,639)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => join_uid103_fpSinPiTest_q, xout => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt(COUNTER,641)
-- every=1, low=0, high=12, step=1, init=1
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i = 11 THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i - 12;
ELSE
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_i,4));
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg(REG,642)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux(MUX,643)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s <= en;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q, ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem(DUALMEM,640)
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_inputreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdreg_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_rdmux_q;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 13,
width_b => 2,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_ia
);
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_iq(1 downto 0);
--reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1(REG,272)@19
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q <= ld_join_uid103_fpSinPiTest_q_to_reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid104_fpSinPiTest(MUX,103)@20
expRPostExc_uid104_fpSinPiTest_s <= reg_join_uid103_fpSinPiTest_0_to_expRPostExc_uid104_fpSinPiTest_1_q;
expRPostExc_uid104_fpSinPiTest: PROCESS (expRPostExc_uid104_fpSinPiTest_s, en, expRPostExc1_uid101_fpSinPiTest_q, cstAllOWE_uid9_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q, cstBias_uid11_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid104_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid104_fpSinPiTest_q <= expRPostExc1_uid101_fpSinPiTest_q;
WHEN "01" => expRPostExc_uid104_fpSinPiTest_q <= cstAllOWE_uid9_fpSinPiTest_q;
WHEN "10" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid104_fpSinPiTest_q <= cstBias_uid11_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid104_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid96_fpSinPiTest(CONSTANT,95)
oneFracRPostExc2_uid96_fpSinPiTest_q <= "00000000000000000000001";
--fracRComp_uid82_fpSinPiTest(BITSELECT,81)@19
fracRComp_uid82_fpSinPiTest_in <= expFracComp_uid81_fpSinPiTest_q(23 downto 0);
fracRComp_uid82_fpSinPiTest_b <= fracRComp_uid82_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2(REG,268)@19
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q <= fracRComp_uid82_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1(REG,245)@4
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q <= xRyHalf_uid90_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--xHalfRZI_uid94_fpSinPiTest(LOGICAL,93)@5
xHalfRZI_uid94_fpSinPiTest_a <= reg_xRyHalf_uid90_fpSinPiTest_0_to_xHalfRZI_uid94_fpSinPiTest_1_q;
xHalfRZI_uid94_fpSinPiTest_b <= excRZero_uid92_fpSinPiTest_q;
xHalfRZI_uid94_fpSinPiTest_c <= GND_q;
xHalfRZI_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xHalfRZI_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
xHalfRZI_uid94_fpSinPiTest_q <= xHalfRZI_uid94_fpSinPiTest_a or xHalfRZI_uid94_fpSinPiTest_b or xHalfRZI_uid94_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b(DELAY,363)@6
ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => xHalfRZI_uid94_fpSinPiTest_q, xout => ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc1_uid95_fpSinPiTest(MUX,94)@20
fracRPostExc1_uid95_fpSinPiTest_s <= ld_xHalfRZI_uid94_fpSinPiTest_q_to_fracRPostExc1_uid95_fpSinPiTest_b_q;
fracRPostExc1_uid95_fpSinPiTest: PROCESS (fracRPostExc1_uid95_fpSinPiTest_s, en, reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q, cstAllZWF_uid10_fpSinPiTest_q)
BEGIN
CASE fracRPostExc1_uid95_fpSinPiTest_s IS
WHEN "0" => fracRPostExc1_uid95_fpSinPiTest_q <= reg_fracRComp_uid82_fpSinPiTest_0_to_fracRPostExc1_uid95_fpSinPiTest_2_q;
WHEN "1" => fracRPostExc1_uid95_fpSinPiTest_q <= cstAllZWF_uid10_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc1_uid95_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a(DELAY,547)@0
ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => excRNaN_uid93_fpSinPiTest_q, xout => ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1(REG,269)@19
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q <= ld_excRNaN_uid93_fpSinPiTest_q_to_reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid97_fpSinPiTest(MUX,96)@20
fracRPostExc_uid97_fpSinPiTest_s <= reg_excRNaN_uid93_fpSinPiTest_0_to_fracRPostExc_uid97_fpSinPiTest_1_q;
fracRPostExc_uid97_fpSinPiTest: PROCESS (fracRPostExc_uid97_fpSinPiTest_s, en, fracRPostExc1_uid95_fpSinPiTest_q, oneFracRPostExc2_uid96_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid97_fpSinPiTest_s IS
WHEN "0" => fracRPostExc_uid97_fpSinPiTest_q <= fracRPostExc1_uid95_fpSinPiTest_q;
WHEN "1" => fracRPostExc_uid97_fpSinPiTest_q <= oneFracRPostExc2_uid96_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid97_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid111_fpSinPiTest(BITJOIN,110)@20
R_uid111_fpSinPiTest_q <= ld_signR_uid110_fpSinPiTest_q_to_R_uid111_fpSinPiTest_c_q & expRPostExc_uid104_fpSinPiTest_q & fracRPostExc_uid97_fpSinPiTest_q;
--xOut(GPOUT,4)@20
q <= R_uid111_fpSinPiTest_q;
end normal;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/hcc_castltox.vhd | 10 | 3526 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOX.VHD ***
--*** ***
--*** Function: Cast Long to Internal Single ***
--*** Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltox IS
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castltox;
ARCHITECTURE rtl OF hcc_castltox IS
signal fit : STD_LOGIC;
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(mantissa+10 DOWNTO mantissa+5) <= "00000";
END GENERATE;
gmaa: IF (mantissa = 32) GENERATE
-- 27 significant bits can be fit directly
gmab: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28)) OR
(aa(32) AND aa(31) AND aa(30) AND aa(29) AND aa(28));
END GENERATE;
gmac: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32) OR aa(31) OR aa(30) OR aa(29) OR aa(28));
END GENERATE;
gmad: FOR k IN 1 TO 27 GENERATE
cc(k+10) <= (aa(k) AND fit) OR (aa(k+5) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011010"; -- exponent = 154 due right shift by 27
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmae: FOR k IN 1 TO 10 GENERATE
cc(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
gmba: IF (mantissa = 36) GENERATE
-- 31 significant bits can be fit directly
gmbb: IF (unsigned = 0) GENERATE -- signed
fit <= NOT(aa(32) OR aa(31)) OR
(aa(32) AND aa(31));
END GENERATE;
gmbc: IF (unsigned = 1) GENERATE -- unsigned
fit <= NOT(aa(32));
END GENERATE;
gmbd: FOR k IN 1 TO 31 GENERATE
cc(k+10) <= (aa(k) AND fit) OR (aa(k+1) AND NOT(fit));
END GENERATE;
exponentfit <= "0010011110"; -- exponent = 158 due right shift by 31
exponentnofit <= "0010011111"; -- exponent = 159 due right shift by 32
gmbe: FOR k IN 1 TO 10 GENERATE
cc(k) <= (exponentfit(k) AND fit) OR (exponentnofit(k) AND NOT(fit));
END GENERATE;
END GENERATE;
ccsat <= '0';
cczip <= '0';
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/fp_tanlut1.vhd | 10 | 94202 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_TANLUT1.VHD ***
--*** ***
--*** Function: Tangent Look Up Table ***
--*** (Generated by MATLAB Utility) ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_tanlut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
END fp_tanlut1;
ARCHITECTURE rtl OF fp_tanlut1 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(0,5);
WHEN "000000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131072,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174764,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(0,5);
WHEN "000000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131074,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174780,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(1,5);
WHEN "000000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196617,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(130,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(1,5);
WHEN "000000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131082,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(175036,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5);
WHEN "000000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163860,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219287,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5);
WHEN "000000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196644,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(2074,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5);
WHEN "000000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229433,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(48174,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5);
WHEN "000001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131114,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(179133,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147516,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(204485,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163923,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(100723,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180334,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(261788,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196752,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33207,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213175,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71403,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229604,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(246559,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246041,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(166927,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5);
WHEN "000010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131242,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(244778,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139469,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(18368,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147699,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126224,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155934,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110829,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164174,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39099,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172418,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(240249,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180668,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(257224,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(188924,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(157429,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197186,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(8449,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205453,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(140199,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213727,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(96362,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(222007,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(207256,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(230295,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16983,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(238589,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118443,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246891,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(56191,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(255200,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(161457,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5);
WHEN "000100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131758,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(251787,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135921,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(182851,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140088,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(170994,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144259,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(251287,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148435,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(196795,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152616,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(42877,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(156801,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(87190,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160991,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(103258,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165186,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126910,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(169386,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(194144,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173592,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78984,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(177803,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79918,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182019,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(233473,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(186242,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52073,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(190470,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(96910,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(194704,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142940,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198944,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(227466,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(203191,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125851,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207444,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(137961,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211704,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39590,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215970,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(131044,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220243,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(188568,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(224523,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(250786,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(228811,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94417,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233106,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(20713,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237408,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(69033,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(241718,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16848,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246035,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(166180,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(250361,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(32888,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(254694,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(181681,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259036,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(128971,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5);
WHEN "000111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131693,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(88946,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(133872,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(184862,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136056,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110880,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138244,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(150087,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140437,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(61438,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(142634,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(128336,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144836,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110058,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147043,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(28193,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149254,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(166641,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(151471,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(23046,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(153692,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(143802,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155919,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(26909,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158150,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219127,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160387,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218828,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162630,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(48862,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164877,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(256563,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(167131,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78745,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(169390,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(63145,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171654,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(233418,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173925,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(89145,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(176201,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(178694,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178484,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(2082,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180772,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(108121,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(183066,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(259423,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(185367,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218831,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187675,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(11570,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189988,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(187394,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192308,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(247729,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(194635,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218538,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196969,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126042,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(199309,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(258866,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(201657,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(119470,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(204011,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(259160,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(206373,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180942,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(208742,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174537,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211119,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(5664,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213502,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(226767,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215894,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79866,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218293,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118006,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220700,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(108111,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(223115,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79560,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(225538,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(62056,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(227969,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85630,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(230408,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180644,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(232856,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(115658,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(235312,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(183865,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237777,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(154523,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(240251,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(59395,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(242733,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(192751,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(245225,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(62806,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(247725,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(226729,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(250235,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(193502,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(252754,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(258933,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(255283,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(194946,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(257822,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36018,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(260370,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79189,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5);
WHEN "001110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131464,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(48818,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132748,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(63557,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134037,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(101912,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135331,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(182207,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136631,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(60853,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(137936,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(18783,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139246,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(75024,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140561,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(248849,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "001111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141883,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(35488,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(143209,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(241146,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144542,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(99421,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(145880,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(154894,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147224,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(165983,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148574,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153522,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149930,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(138624,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(151292,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142687,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152660,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(187397,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(154035,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(32592,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155415,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(224845,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(156803,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(313,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158196,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(168333,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159596,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(227841,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(161003,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202385,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162417,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(115847,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163837,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(254593,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165265,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118901,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(166699,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(257978,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168141,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(172818,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(169590,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(151210,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171046,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219176,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172510,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(140977,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173981,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(205552,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(175460,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(177949,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(176947,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85768,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178441,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219166,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(179944,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(82294,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(181454,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(228309,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182973,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(162236,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(184500,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(175979,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(186036,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(37616,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187580,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39982,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189132,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(214250,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(190694,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(67791,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192264,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(157055,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(193843,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(252568,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(195432,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125382,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197030,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71365,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198637,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(124791,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(200254,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(58341,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(201880,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169556,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(203516,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(232268,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205163,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(20904,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(206819,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(96928,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(208485,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(235993,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(210162,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(214385,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211850,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71183,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213548,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(108271,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215257,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(103923,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(216977,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(99249,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218708,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(136066,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220450,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(256917,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(222204,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(242940,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(223970,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(138174,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(225747,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(249580,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(227537,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(98477,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229338,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(255571,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(231152,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(243824,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(232979,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111333,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(234818,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169210,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(236670,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(205169,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(238536,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(7833,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(240414,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153192,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "010111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(242306,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169612,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244212,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110728,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246132,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(31174,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(248065,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(248754,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(250014,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33745,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(251976,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(230368,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(253954,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111078,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(255946,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(260182,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(257954,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(214570,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259978,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36603,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(262017,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52004,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5);
WHEN "011001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132036,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(31728,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(133071,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(199603,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134115,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(170119,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135167,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(239798,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136228,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(181565,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(137298,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(31195,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138376,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(87334,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139463,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125082,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140559,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(182447,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141665,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36078,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(142779,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(249858,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(143904,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(77779,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(145038,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85397,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(146182,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52708,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147336,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(22748,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148500,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39467,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149674,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(147762,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(150859,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(131351,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152055,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(37096,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(153261,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(175023,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(154479,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(69779,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155708,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33524,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(156948,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(117385,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158200,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111488,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159464,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(69279,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160740,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(45413,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162028,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(95789,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163329,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(15442,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164642,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125012,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165968,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(222206,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(167308,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(106129,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168661,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(101608,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(170028,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(10664,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171408,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(161129,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172803,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(95974,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(174212,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(146219,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(175636,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(120264,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(177075,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(90370,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178529,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(130571,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(179999,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(54581,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(181484,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202287,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182986,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(129087,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(184504,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(178815,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(186039,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(173083,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187591,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(197786,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189161,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78873,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(190748,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(168858,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192354,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36174,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(193978,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(38109,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(195621,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(10173,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197283,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52606,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198965,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(6187,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(200666,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(238745,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "011111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(202389,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(72398,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(204132,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142943,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205897,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(40664,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207683,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(145442,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(209492,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(54008,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211323,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(152917,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213178,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(45809,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215056,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126393,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(216959,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(5720,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218886,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85177,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220838,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(245917,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(222817,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111146,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(224822,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94854,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(226854,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(91265,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(228913,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(261427,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(231001,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(246970,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233118,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218857,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(235265,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(91152,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237442,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(45510,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(239650,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(7099,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(241889,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169116,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244161,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(206583,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246467,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(63025,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(248806,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(212871,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(251181,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(88861,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(253591,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(179473,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(256038,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(194218,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(258523,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(112522,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(261046,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(184058,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5);
WHEN "100011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131804,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202396,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(133106,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(127604,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134429,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(5700,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135772,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(241668,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(137138,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(196914,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138527,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(24498,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139938,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(145076,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141373,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(198575,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(142833,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(93021,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144318,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(4818,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(145828,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(116886,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147365,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94683,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148929,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(135102,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(150521,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180373,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152142,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180573,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(153793,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94005,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155474,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(149742,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(157187,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(61623,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158932,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(77284,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160710,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(192200,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162523,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(150199,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164371,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(230433,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(166256,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(199372,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168179,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(97853,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(170140,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(241724,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172142,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(173961,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(174185,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(238269,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(176272,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(6999,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178402,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(116996,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180578,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(173338,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182802,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(61011,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(185074,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(208074,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187398,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(13879,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189773,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(209544,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192203,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(237754,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "100111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(194690,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(89118,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197235,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(41457,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(199840,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(137068,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(202508,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(184378,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205242,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(21881,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(208043,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(44347,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(210914,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(156319,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213859,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36498,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(216879,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(188732,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(219979,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(109619,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(223161,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126346,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(226429,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(89021,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229786,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(160435,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233237,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33224,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(236784,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(244509,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(240434,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(83006,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244189,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(215105,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(248056,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(68494,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(252038,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(196984,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(256142,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(189406,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101010011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(260373,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(249093,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5);
WHEN "101010100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132369,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(76283,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101010101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134621,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153043,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101010110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136947,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(90777,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101010111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139350,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(80594,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141834,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118724,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144404,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(12410,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147063,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(172855,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149818,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(49588,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152672,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(235640,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155633,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(117182,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158705,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(242792,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101011111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(161896,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(237423,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165213,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125600,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168663,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(83253,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172254,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191313,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(175996,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191297,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(179899,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(29637,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(183972,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142533,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(188228,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(171026,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101100111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192680,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(38953,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197340,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(248662,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(202226,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(84469,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207353,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16170,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(212739,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(177173,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218406,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(161382,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(224376,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(140334,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(230674,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(156722,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101101111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237328,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218000,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101110000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244370,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(144312,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101110001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(251834,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(222783,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101110010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259761,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(51093,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5);
WHEN "101110011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134097,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16112,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101110100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138592,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(11144,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101110101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(143394,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(60483,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101110110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148536,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(104003,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101110111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(154056,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(37731,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159996,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218457,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(166408,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191255,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173350,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(113148,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180890,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(176944,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189110,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(163200,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198106,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(211327,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207994,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(247747,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "101111111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218914,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(252397,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "110000000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(231037,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174172,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "110000001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244573,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(197553,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "110000010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259786,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(53842,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5);
WHEN "110000011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138503,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202780,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110000100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148332,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(62994,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110000101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159656,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(230897,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110000110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172847,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(240508,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110000111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(188408,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(183509,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110001000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207041,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(119228,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110001001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229756,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71260,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110001010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(258060,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153597,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5);
WHEN "110001011" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147154,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(32322,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5);
WHEN "110001100" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171195,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78299,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5);
WHEN "110001101" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(204618,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(105365,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5);
WHEN "110001110" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(254248,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(141622,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5);
WHEN "110001111" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(167825,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(19278,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(14,5);
WHEN "110010000" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246850,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(149873,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(14,5);
WHEN "110010001" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233251,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(216105,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(15,5);
WHEN "110010010" =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132278,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191927,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(19,5);
WHEN others =>
mantissa(36 DOWNTO 19) <= conv_std_logic_vector(0,18);
mantissa(18 DOWNTO 1) <= conv_std_logic_vector(0,18);
exponent(5 DOWNTO 1) <= conv_std_logic_vector(0,5);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/dp_lnlut9.vhd | 10 | 142018 | LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNLUT9.VHD ***
--*** ***
--*** Function: Look Up Table - LN() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnlut9 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (12 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END dp_lnlut9;
ARCHITECTURE rtl OF dp_lnlut9 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" =>
inv <= conv_std_logic_vector(2048,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
logexp <= conv_std_logic_vector(0,11);
WHEN "000000001" =>
inv <= conv_std_logic_vector(4089,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12608028,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(166435551,28);
logexp <= conv_std_logic_vector(1013,11);
WHEN "000000010" =>
inv <= conv_std_logic_vector(4081,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14737805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3321276,28);
logexp <= conv_std_logic_vector(1014,11);
WHEN "000000011" =>
inv <= conv_std_logic_vector(4073,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7407998,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148040387,28);
logexp <= conv_std_logic_vector(1015,11);
WHEN "000000100" =>
inv <= conv_std_logic_vector(4065,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15852272,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51070306,28);
logexp <= conv_std_logic_vector(1015,11);
WHEN "000000101" =>
inv <= conv_std_logic_vector(4057,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3767982,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94668708,28);
logexp <= conv_std_logic_vector(1016,11);
WHEN "000000110" =>
inv <= conv_std_logic_vector(4049,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8006786,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237055061,28);
logexp <= conv_std_logic_vector(1016,11);
WHEN "000000111" =>
inv <= conv_std_logic_vector(4041,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12253974,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192188802,28);
logexp <= conv_std_logic_vector(1016,11);
WHEN "000001000" =>
inv <= conv_std_logic_vector(4033,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16509579,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20710393,28);
logexp <= conv_std_logic_vector(1016,11);
WHEN "000001001" =>
inv <= conv_std_logic_vector(4026,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1731473,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180827014,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000001010" =>
inv <= conv_std_logic_vector(4018,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3867211,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(126637664,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000001011" =>
inv <= conv_std_logic_vector(4010,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6007205,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228245542,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000001100" =>
inv <= conv_std_logic_vector(4003,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7883206,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5368567,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000001101" =>
inv <= conv_std_logic_vector(3995,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10031227,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104563152,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000001110" =>
inv <= conv_std_logic_vector(3987,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12183554,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132223343,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000001111" =>
inv <= conv_std_logic_vector(3980,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14070386,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93820959,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000010000" =>
inv <= conv_std_logic_vector(3972,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16230833,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(108537941,28);
logexp <= conv_std_logic_vector(1017,11);
WHEN "000010001" =>
inv <= conv_std_logic_vector(3965,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(673790,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(140554826,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000010010" =>
inv <= conv_std_logic_vector(3957,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1758104,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(208459132,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000010011" =>
inv <= conv_std_logic_vector(3950,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2708679,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147574307,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000010100" =>
inv <= conv_std_logic_vector(3943,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3660940,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102190772,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000010101" =>
inv <= conv_std_logic_vector(3935,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4751310,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(193668840,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000010110" =>
inv <= conv_std_logic_vector(3928,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5707204,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201576161,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000010111" =>
inv <= conv_std_logic_vector(3920,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6801743,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(47496037,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011000" =>
inv <= conv_std_logic_vector(3913,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7761298,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63049717,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011001" =>
inv <= conv_std_logic_vector(3906,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8722571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103870568,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011010" =>
inv <= conv_std_logic_vector(3899,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9685568,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213866899,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011011" =>
inv <= conv_std_logic_vector(3891,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10788256,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(148111271,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011100" =>
inv <= conv_std_logic_vector(3884,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11754969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(190364328,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011101" =>
inv <= conv_std_logic_vector(3877,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12723426,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(191372810,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011110" =>
inv <= conv_std_logic_vector(3870,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13693633,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232417040,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000011111" =>
inv <= conv_std_logic_vector(3863,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14665597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135531172,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000100000" =>
inv <= conv_std_logic_vector(3856,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15639324,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(440444,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000100001" =>
inv <= conv_std_logic_vector(3848,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16754321,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28021513,28);
logexp <= conv_std_logic_vector(1018,11);
WHEN "000100010" =>
inv <= conv_std_logic_vector(3841,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(477315,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(103375890,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000100011" =>
inv <= conv_std_logic_vector(3834,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(966969,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(207463933,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000100100" =>
inv <= conv_std_logic_vector(3827,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1457518,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261454332,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000100101" =>
inv <= conv_std_logic_vector(3820,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1948966,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(71112978,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000100110" =>
inv <= conv_std_logic_vector(3814,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2370924,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27626077,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000100111" =>
inv <= conv_std_logic_vector(3807,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2864048,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(7790664,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101000" =>
inv <= conv_std_logic_vector(3800,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3358079,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(135806794,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101001" =>
inv <= conv_std_logic_vector(3793,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3853021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236303861,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101010" =>
inv <= conv_std_logic_vector(3786,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4348878,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(138889654,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101011" =>
inv <= conv_std_logic_vector(3779,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4845652,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215058204,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101100" =>
inv <= conv_std_logic_vector(3772,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5343348,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36049681,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101101" =>
inv <= conv_std_logic_vector(3766,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5770679,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(216749821,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101110" =>
inv <= conv_std_logic_vector(3759,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6270094,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202231188,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000101111" =>
inv <= conv_std_logic_vector(3752,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6770440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(154557048,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110000" =>
inv <= conv_std_logic_vector(3745,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7271720,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201681452,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110001" =>
inv <= conv_std_logic_vector(3739,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7702135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212518450,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110010" =>
inv <= conv_std_logic_vector(3732,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8205160,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130192328,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110011" =>
inv <= conv_std_logic_vector(3725,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8709129,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153765892,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110100" =>
inv <= conv_std_logic_vector(3719,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9141857,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(115454106,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110101" =>
inv <= conv_std_logic_vector(3712,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9647589,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(223955336,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110110" =>
inv <= conv_std_logic_vector(3706,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10081834,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(106871151,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000110111" =>
inv <= conv_std_logic_vector(3699,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10589342,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(134545541,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111000" =>
inv <= conv_std_logic_vector(3693,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11025114,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118400992,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111001" =>
inv <= conv_std_logic_vector(3686,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11534410,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203065005,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111010" =>
inv <= conv_std_logic_vector(3680,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11971720,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(229464861,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111011" =>
inv <= conv_std_logic_vector(3673,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12482818,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(7696520,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111100" =>
inv <= conv_std_logic_vector(3667,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12921677,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49003431,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111101" =>
inv <= conv_std_logic_vector(3660,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13434587,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267260840,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111110" =>
inv <= conv_std_logic_vector(3654,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13875007,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(58597277,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "000111111" =>
inv <= conv_std_logic_vector(3648,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14316150,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59000478,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "001000000" =>
inv <= conv_std_logic_vector(3641,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14831735,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2814011,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "001000001" =>
inv <= conv_std_logic_vector(3635,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15274454,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104571506,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "001000010" =>
inv <= conv_std_logic_vector(3629,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15717905,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35857837,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "001000011" =>
inv <= conv_std_logic_vector(3623,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16162089,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(177959810,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "001000100" =>
inv <= conv_std_logic_vector(3616,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16681235,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165401956,28);
logexp <= conv_std_logic_vector(1019,11);
WHEN "001000101" =>
inv <= conv_std_logic_vector(3610,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(174901,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50275830,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001000110" =>
inv <= conv_std_logic_vector(3604,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(398163,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(88951577,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001000111" =>
inv <= conv_std_logic_vector(3598,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(621797,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127737931,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001000" =>
inv <= conv_std_logic_vector(3592,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(845804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(231522955,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001001" =>
inv <= conv_std_logic_vector(3585,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1107620,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(57821111,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001010" =>
inv <= conv_std_logic_vector(3579,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1332440,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156464157,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001011" =>
inv <= conv_std_logic_vector(3573,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1557638,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44535294,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001100" =>
inv <= conv_std_logic_vector(3567,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1783214,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62397887,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001101" =>
inv <= conv_std_logic_vector(3561,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2009170,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15263403,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001110" =>
inv <= conv_std_logic_vector(3555,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2235506,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246944822,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001001111" =>
inv <= conv_std_logic_vector(3549,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2462226,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29255593,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010000" =>
inv <= conv_std_logic_vector(3543,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2689328,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246376003,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010001" =>
inv <= conv_std_logic_vector(3537,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2916816,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(173639564,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010010" =>
inv <= conv_std_logic_vector(3531,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3144690,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(161899610,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010011" =>
inv <= conv_std_logic_vector(3525,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3372952,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26928617,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010100" =>
inv <= conv_std_logic_vector(3519,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3601602,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(123172243,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010101" =>
inv <= conv_std_logic_vector(3513,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3830643,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1584354,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010110" =>
inv <= conv_std_logic_vector(3507,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4060075,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(20252153,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001010111" =>
inv <= conv_std_logic_vector(3502,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4251568,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137854980,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011000" =>
inv <= conv_std_logic_vector(3496,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4481721,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(231322588,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011001" =>
inv <= conv_std_logic_vector(3490,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4712270,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147480442,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011010" =>
inv <= conv_std_logic_vector(3484,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4943215,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251536037,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011011" =>
inv <= conv_std_logic_vector(3478,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5174559,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(105278949,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011100" =>
inv <= conv_std_logic_vector(3473,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5367650,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(181375864,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011101" =>
inv <= conv_std_logic_vector(3467,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5599727,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(133308340,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011110" =>
inv <= conv_std_logic_vector(3461,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5832206,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80096944,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001011111" =>
inv <= conv_std_logic_vector(3455,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6065088,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127763081,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100000" =>
inv <= conv_std_logic_vector(3450,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6259466,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27642512,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100001" =>
inv <= conv_std_logic_vector(3444,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6493091,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120806774,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100010" =>
inv <= conv_std_logic_vector(3438,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6727124,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44281139,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100011" =>
inv <= conv_std_logic_vector(3433,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6922463,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171170237,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100100" =>
inv <= conv_std_logic_vector(3427,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7157246,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(240302137,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100101" =>
inv <= conv_std_logic_vector(3422,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7353213,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222094360,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100110" =>
inv <= conv_std_logic_vector(3416,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7588752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(122671437,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001100111" =>
inv <= conv_std_logic_vector(3411,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7785350,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(239607246,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101000" =>
inv <= conv_std_logic_vector(3405,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8021649,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(206841234,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101001" =>
inv <= conv_std_logic_vector(3399,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8258365,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(107795018,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101010" =>
inv <= conv_std_logic_vector(3394,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8455947,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(226201607,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101011" =>
inv <= conv_std_logic_vector(3388,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8693431,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94327085,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101100" =>
inv <= conv_std_logic_vector(3383,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8891655,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(206124156,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101101" =>
inv <= conv_std_logic_vector(3378,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9090173,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(99984141,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101110" =>
inv <= conv_std_logic_vector(3372,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9328782,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195833281,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001101111" =>
inv <= conv_std_logic_vector(3367,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9527948,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110283065,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110000" =>
inv <= conv_std_logic_vector(3361,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9767338,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(282511,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110001" =>
inv <= conv_std_logic_vector(3356,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9967156,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1157748,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110010" =>
inv <= conv_std_logic_vector(3351,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10167271,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250247631,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110011" =>
inv <= conv_std_logic_vector(3345,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10407805,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150148144,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110100" =>
inv <= conv_std_logic_vector(3340,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10608580,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15841264,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110101" =>
inv <= conv_std_logic_vector(3335,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10809655,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(92492368,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110110" =>
inv <= conv_std_logic_vector(3329,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11051343,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267282110,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001110111" =>
inv <= conv_std_logic_vector(3324,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11253084,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(51811246,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111000" =>
inv <= conv_std_logic_vector(3319,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11455128,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(21159361,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111001" =>
inv <= conv_std_logic_vector(3314,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11657476,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152694737,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111010" =>
inv <= conv_std_logic_vector(3308,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11900698,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34843865,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111011" =>
inv <= conv_std_logic_vector(3303,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12103719,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266488285,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111100" =>
inv <= conv_std_logic_vector(3298,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12307049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112230017,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111101" =>
inv <= conv_std_logic_vector(3293,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12510687,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(91030082,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111110" =>
inv <= conv_std_logic_vector(3288,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12714634,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186120630,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "001111111" =>
inv <= conv_std_logic_vector(3282,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12959781,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79635368,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000000" =>
inv <= conv_std_logic_vector(3277,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13164412,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194678646,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000001" =>
inv <= conv_std_logic_vector(3272,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13369356,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165362770,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000010" =>
inv <= conv_std_logic_vector(3267,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13574613,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248228452,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000011" =>
inv <= conv_std_logic_vector(3262,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13780185,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164124274,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000100" =>
inv <= conv_std_logic_vector(3257,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13986072,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171955743,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000101" =>
inv <= conv_std_logic_vector(3252,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14192275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(263386193,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000110" =>
inv <= conv_std_logic_vector(3247,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14398796,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(162844158,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010000111" =>
inv <= conv_std_logic_vector(3242,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14605635,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132837122,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001000" =>
inv <= conv_std_logic_vector(3237,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14812793,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168652610,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001001" =>
inv <= conv_std_logic_vector(3232,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15020271,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266801170,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001010" =>
inv <= conv_std_logic_vector(3227,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15228071,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156588484,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001011" =>
inv <= conv_std_logic_vector(3222,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15436193,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(105429361,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001100" =>
inv <= conv_std_logic_vector(3217,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15644638,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(113549080,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001101" =>
inv <= conv_std_logic_vector(3212,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15853407,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182426590,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001110" =>
inv <= conv_std_logic_vector(3207,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16062502,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(46366848,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010001111" =>
inv <= conv_std_logic_vector(3202,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16271922,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246250548,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010010000" =>
inv <= conv_std_logic_vector(3197,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16481670,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(250493842,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010010001" =>
inv <= conv_std_logic_vector(3193,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16649705,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179677631,28);
logexp <= conv_std_logic_vector(1020,11);
WHEN "010010010" =>
inv <= conv_std_logic_vector(3188,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(41414,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182297714,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010010011" =>
inv <= conv_std_logic_vector(3183,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(146749,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160926493,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010010100" =>
inv <= conv_std_logic_vector(3178,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(252250,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30832263,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010010101" =>
inv <= conv_std_logic_vector(3173,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(357916,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(200433438,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010010110" =>
inv <= conv_std_logic_vector(3168,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(463750,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5068900,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010010111" =>
inv <= conv_std_logic_vector(3164,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(548536,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260761497,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011000" =>
inv <= conv_std_logic_vector(3159,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(654671,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(140824337,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011001" =>
inv <= conv_std_logic_vector(3154,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(760974,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53287185,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011010" =>
inv <= conv_std_logic_vector(3149,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(867445,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(141350373,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011011" =>
inv <= conv_std_logic_vector(3145,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(952744,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102039527,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011100" =>
inv <= conv_std_logic_vector(3140,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1059520,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171297819,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011101" =>
inv <= conv_std_logic_vector(3135,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1166467,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15456691,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011110" =>
inv <= conv_std_logic_vector(3131,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1252147,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19951762,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010011111" =>
inv <= conv_std_logic_vector(3126,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1359401,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(41610452,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100000" =>
inv <= conv_std_logic_vector(3121,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1466826,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248224675,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100001" =>
inv <= conv_std_logic_vector(3117,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1552891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(141314514,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100010" =>
inv <= conv_std_logic_vector(3112,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1660627,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194757369,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100011" =>
inv <= conv_std_logic_vector(3107,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1768537,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43450957,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100100" =>
inv <= conv_std_logic_vector(3103,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1854989,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219219906,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100101" =>
inv <= conv_std_logic_vector(3098,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1963212,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131015724,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100110" =>
inv <= conv_std_logic_vector(3094,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2049916,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(123155162,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010100111" =>
inv <= conv_std_logic_vector(3089,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2158454,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(50751187,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101000" =>
inv <= conv_std_logic_vector(3085,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2245410,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252626322,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101001" =>
inv <= conv_std_logic_vector(3080,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2354265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(153008713,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101010" =>
inv <= conv_std_logic_vector(3076,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2441476,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156128968,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101011" =>
inv <= conv_std_logic_vector(3071,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2550649,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(259057771,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101100" =>
inv <= conv_std_logic_vector(3067,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2638116,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(195294519,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101101" =>
inv <= conv_std_logic_vector(3062,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2747610,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198048260,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101110" =>
inv <= conv_std_logic_vector(3058,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2835334,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202805005,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010101111" =>
inv <= conv_std_logic_vector(3053,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2945151,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75538772,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110000" =>
inv <= conv_std_logic_vector(3049,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3033134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19357354,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110001" =>
inv <= conv_std_logic_vector(3044,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3143275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5155285,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110010" =>
inv <= conv_std_logic_vector(3040,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3231518,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(30629091,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110011" =>
inv <= conv_std_logic_vector(3035,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3341985,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(108686704,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110100" =>
inv <= conv_std_logic_vector(3031,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3430490,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93632684,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110101" =>
inv <= conv_std_logic_vector(3027,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3519112,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45511961,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110110" =>
inv <= conv_std_logic_vector(3022,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3630054,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(73684067,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010110111" =>
inv <= conv_std_logic_vector(3018,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3718940,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53706357,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111000" =>
inv <= conv_std_logic_vector(3014,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3807944,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3094116,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111001" =>
inv <= conv_std_logic_vector(3009,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3919365,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(8048359,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111010" =>
inv <= conv_std_logic_vector(3005,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4008635,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62108895,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111011" =>
inv <= conv_std_logic_vector(3001,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4098024,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(91490091,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111100" =>
inv <= conv_std_logic_vector(2996,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4209928,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114206619,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111101" =>
inv <= conv_std_logic_vector(2992,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4299586,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(64350406,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111110" =>
inv <= conv_std_logic_vector(2988,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4389363,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267789889,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "010111111" =>
inv <= conv_std_logic_vector(2984,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4479262,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5480265,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000000" =>
inv <= conv_std_logic_vector(2979,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4591804,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43802136,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000001" =>
inv <= conv_std_logic_vector(2975,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4681973,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(258711462,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000010" =>
inv <= conv_std_logic_vector(2971,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4772265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(22193356,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000011" =>
inv <= conv_std_logic_vector(2967,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4862677,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227303994,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000100" =>
inv <= conv_std_logic_vector(2963,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4953212,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(156841963,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000101" =>
inv <= conv_std_logic_vector(2958,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5066553,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(8978848,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000110" =>
inv <= conv_std_logic_vector(2954,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5157363,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112226691,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011000111" =>
inv <= conv_std_logic_vector(2950,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5248296,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228718953,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001000" =>
inv <= conv_std_logic_vector(2946,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5339353,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179656048,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001001" =>
inv <= conv_std_logic_vector(2942,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5430534,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(55039221,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001010" =>
inv <= conv_std_logic_vector(2938,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5521838,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213672522,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001011" =>
inv <= conv_std_logic_vector(2934,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5613267,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(209422987,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001100" =>
inv <= conv_std_logic_vector(2929,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5727729,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(122280556,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001101" =>
inv <= conv_std_logic_vector(2925,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5819439,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152340981,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001110" =>
inv <= conv_std_logic_vector(2921,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5911275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(48556746,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011001111" =>
inv <= conv_std_logic_vector(2917,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6003236,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(171693667,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010000" =>
inv <= conv_std_logic_vector(2913,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6095324,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(77591273,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010001" =>
inv <= conv_std_logic_vector(2909,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6187538,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127777649,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010010" =>
inv <= conv_std_logic_vector(2905,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6279879,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147294249,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010011" =>
inv <= conv_std_logic_vector(2901,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6372347,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230004385,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010100" =>
inv <= conv_std_logic_vector(2897,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6464943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201724446,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010101" =>
inv <= conv_std_logic_vector(2893,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6557667,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(157096962,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010110" =>
inv <= conv_std_logic_vector(2889,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6650519,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(191157304,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011010111" =>
inv <= conv_std_logic_vector(2885,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6743500,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130900404,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011000" =>
inv <= conv_std_logic_vector(2881,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6836610,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(72153870,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011001" =>
inv <= conv_std_logic_vector(2877,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6929849,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(111144728,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011010" =>
inv <= conv_std_logic_vector(2873,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7023218,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(76066192,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011011" =>
inv <= conv_std_logic_vector(2869,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7116717,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63950809,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011100" =>
inv <= conv_std_logic_vector(2865,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7210346,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172237270,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011101" =>
inv <= conv_std_logic_vector(2862,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7280654,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(139653305,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011110" =>
inv <= conv_std_logic_vector(2858,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7374513,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(23245886,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011011111" =>
inv <= conv_std_logic_vector(2854,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7468503,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(28873967,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100000" =>
inv <= conv_std_logic_vector(2850,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7562624,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255519588,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100001" =>
inv <= conv_std_logic_vector(2846,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7656878,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265710940,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100010" =>
inv <= conv_std_logic_vector(2842,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7751265,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159266526,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100011" =>
inv <= conv_std_logic_vector(2838,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7845785,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36426622,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100100" =>
inv <= conv_std_logic_vector(2834,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(7940437,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266291107,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100101" =>
inv <= conv_std_logic_vector(2831,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8011515,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93413946,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100110" =>
inv <= conv_std_logic_vector(2827,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8106402,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110277380,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011100111" =>
inv <= conv_std_logic_vector(2823,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8201423,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222008092,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101000" =>
inv <= conv_std_logic_vector(2819,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8296579,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(262447083,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101001" =>
inv <= conv_std_logic_vector(2815,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8391871,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(65871042,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101010" =>
inv <= conv_std_logic_vector(2812,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8463428,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(160477028,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101011" =>
inv <= conv_std_logic_vector(2808,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8558957,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66030540,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101100" =>
inv <= conv_std_logic_vector(2804,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8654622,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19294193,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101101" =>
inv <= conv_std_logic_vector(2800,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8750423,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(124636155,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101110" =>
inv <= conv_std_logic_vector(2797,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8822364,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98044902,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011101111" =>
inv <= conv_std_logic_vector(2793,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(8918405,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(185136678,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110000" =>
inv <= conv_std_logic_vector(2789,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9014584,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(176764031,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110001" =>
inv <= conv_std_logic_vector(2786,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9086809,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(121288912,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110010" =>
inv <= conv_std_logic_vector(2782,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9183230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(67117648,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110011" =>
inv <= conv_std_logic_vector(2778,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9279789,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210248932,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110100" =>
inv <= conv_std_logic_vector(2775,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9352300,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(192854718,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110101" =>
inv <= conv_std_logic_vector(2771,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9449104,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(269037,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110110" =>
inv <= conv_std_logic_vector(2767,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9546047,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32810921,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011110111" =>
inv <= conv_std_logic_vector(2764,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9618846,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(127667797,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111000" =>
inv <= conv_std_logic_vector(2760,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9716035,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(77607514,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111001" =>
inv <= conv_std_logic_vector(2756,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9813365,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(15613650,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111010" =>
inv <= conv_std_logic_vector(2753,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9886455,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(35776871,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111011" =>
inv <= conv_std_logic_vector(2749,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(9984032,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150556503,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111100" =>
inv <= conv_std_logic_vector(2745,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10081752,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19947644,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111101" =>
inv <= conv_std_logic_vector(2742,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10155135,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(54345836,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111110" =>
inv <= conv_std_logic_vector(2738,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10253104,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97812156,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "011111111" =>
inv <= conv_std_logic_vector(2735,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10326675,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(55696655,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000000" =>
inv <= conv_std_logic_vector(2731,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10424895,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(79654305,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000001" =>
inv <= conv_std_logic_vector(2728,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10498654,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(219479460,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000010" =>
inv <= conv_std_logic_vector(2724,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10597127,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(32989146,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000011" =>
inv <= conv_std_logic_vector(2721,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10671076,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(78331980,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000100" =>
inv <= conv_std_logic_vector(2717,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10769802,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29997091,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000101" =>
inv <= conv_std_logic_vector(2714,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10843941,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(243319683,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000110" =>
inv <= conv_std_logic_vector(2710,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(10942922,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(147572067,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100000111" =>
inv <= conv_std_logic_vector(2707,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11017253,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256500550,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001000" =>
inv <= conv_std_logic_vector(2703,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11116490,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(198934815,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001001" =>
inv <= conv_std_logic_vector(2700,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11191014,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(201586837,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001010" =>
inv <= conv_std_logic_vector(2696,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11290509,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2117744,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001011" =>
inv <= conv_std_logic_vector(2693,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11365226,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(167123833,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001100" =>
inv <= conv_std_logic_vector(2689,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11464979,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(185321336,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001101" =>
inv <= conv_std_logic_vector(2686,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11539891,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246540176,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001110" =>
inv <= conv_std_logic_vector(2682,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11639905,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(39481193,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100001111" =>
inv <= conv_std_logic_vector(2679,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11715013,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1327916,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010000" =>
inv <= conv_std_logic_vector(2675,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11815287,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202673946,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010001" =>
inv <= conv_std_logic_vector(2672,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11890592,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(71706890,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010010" =>
inv <= conv_std_logic_vector(2669,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(11965981,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(100723928,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010011" =>
inv <= conv_std_logic_vector(2665,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12066632,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(29193386,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010100" =>
inv <= conv_std_logic_vector(2662,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12142219,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(93571958,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010101" =>
inv <= conv_std_logic_vector(2658,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12243134,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(255701348,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010110" =>
inv <= conv_std_logic_vector(2655,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12318921,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98863551,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100010111" =>
inv <= conv_std_logic_vector(2652,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12394793,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(125312048,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011000" =>
inv <= conv_std_logic_vector(2648,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12496089,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237443793,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011001" =>
inv <= conv_std_logic_vector(2645,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12572162,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(178518688,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011010" =>
inv <= conv_std_logic_vector(2642,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12648321,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(208688605,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011011" =>
inv <= conv_std_logic_vector(2638,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12750001,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(239940349,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011100" =>
inv <= conv_std_logic_vector(2635,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12826363,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(56746753,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011101" =>
inv <= conv_std_logic_vector(2632,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12902811,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(138879938,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011110" =>
inv <= conv_std_logic_vector(2629,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(12979347,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(2730614,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100011111" =>
inv <= conv_std_logic_vector(2625,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13081530,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(81091197,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100000" =>
inv <= conv_std_logic_vector(2622,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13158270,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(1684866,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100001" =>
inv <= conv_std_logic_vector(2619,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13235097,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151292526,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100010" =>
inv <= conv_std_logic_vector(2615,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13337671,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(84646293,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100011" =>
inv <= conv_std_logic_vector(2612,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13414704,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(173861808,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100100" =>
inv <= conv_std_logic_vector(2609,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13491826,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(136139682,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100101" =>
inv <= conv_std_logic_vector(2606,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13569037,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26161775,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100110" =>
inv <= conv_std_logic_vector(2602,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13672122,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(249732568,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100100111" =>
inv <= conv_std_logic_vector(2599,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13749541,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(95394098,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101000" =>
inv <= conv_std_logic_vector(2596,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13827049,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(52442312,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101001" =>
inv <= conv_std_logic_vector(2593,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13904646,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(176384205,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101010" =>
inv <= conv_std_logic_vector(2590,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(13982333,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(254484090,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101011" =>
inv <= conv_std_logic_vector(2586,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14086057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26027470,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101100" =>
inv <= conv_std_logic_vector(2583,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14163954,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214862414,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101101" =>
inv <= conv_std_logic_vector(2580,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14241943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(8054063,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101110" =>
inv <= conv_std_logic_vector(2577,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14320021,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267454282,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100101111" =>
inv <= conv_std_logic_vector(2574,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14398191,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(244499796,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110000" =>
inv <= conv_std_logic_vector(2571,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14476452,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264567670,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110001" =>
inv <= conv_std_logic_vector(2567,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14580943,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(69299566,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110010" =>
inv <= conv_std_logic_vector(2564,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14659417,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233357662,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110011" =>
inv <= conv_std_logic_vector(2561,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14737984,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(94818262,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110100" =>
inv <= conv_std_logic_vector(2558,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14816642,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248364916,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110101" =>
inv <= conv_std_logic_vector(2555,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14895393,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215142880,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110110" =>
inv <= conv_std_logic_vector(2552,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(14974237,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(53372798,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100110111" =>
inv <= conv_std_logic_vector(2549,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15053173,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(89916221,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111000" =>
inv <= conv_std_logic_vector(2546,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15132202,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114970198,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111001" =>
inv <= conv_std_logic_vector(2543,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15211324,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187374614,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111010" =>
inv <= conv_std_logic_vector(2539,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15316966,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(101744986,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111011" =>
inv <= conv_std_logic_vector(2536,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15396306,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246192396,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111100" =>
inv <= conv_std_logic_vector(2533,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15475741,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(98762703,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111101" =>
inv <= conv_std_logic_vector(2530,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15555269,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256076770,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111110" =>
inv <= conv_std_logic_vector(2527,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15634892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241226312,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "100111111" =>
inv <= conv_std_logic_vector(2524,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15714610,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(114387642,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000000" =>
inv <= conv_std_logic_vector(2521,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15794422,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204387226,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000001" =>
inv <= conv_std_logic_vector(2518,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15874330,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34960895,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000010" =>
inv <= conv_std_logic_vector(2515,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(15954332,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(203803056,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000011" =>
inv <= conv_std_logic_vector(2512,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16034430,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235084078,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000100" =>
inv <= conv_std_logic_vector(2509,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16114624,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(190064071,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000101" =>
inv <= conv_std_logic_vector(2506,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16194914,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(130223025,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000110" =>
inv <= conv_std_logic_vector(2503,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16275300,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(117261858,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101000111" =>
inv <= conv_std_logic_vector(2500,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16355782,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213103482,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101001000" =>
inv <= conv_std_logic_vector(2497,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16436361,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211458404,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101001001" =>
inv <= conv_std_logic_vector(2494,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16517037,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(174696720,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101001010" =>
inv <= conv_std_logic_vector(2491,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16597810,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165413733,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101001011" =>
inv <= conv_std_logic_vector(2488,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16678680,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(246431038,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101001100" =>
inv <= conv_std_logic_vector(2485,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(16759648,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212362162,28);
logexp <= conv_std_logic_vector(1021,11);
WHEN "101001101" =>
inv <= conv_std_logic_vector(2482,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(31749,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63242286,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101001110" =>
inv <= conv_std_logic_vector(2479,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(72331,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26152662,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101001111" =>
inv <= conv_std_logic_vector(2476,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(112962,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26781090,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010000" =>
inv <= conv_std_logic_vector(2474,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(140076,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213075491,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010001" =>
inv <= conv_std_logic_vector(2471,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(180789,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(258223654,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010010" =>
inv <= conv_std_logic_vector(2468,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(221552,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(158206290,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010011" =>
inv <= conv_std_logic_vector(2465,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(262364,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(213755501,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010100" =>
inv <= conv_std_logic_vector(2462,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(303226,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188850466,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010101" =>
inv <= conv_std_logic_vector(2459,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(344138,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116024386,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010110" =>
inv <= conv_std_logic_vector(2456,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(385100,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27929606,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101010111" =>
inv <= conv_std_logic_vector(2453,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(426111,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(225773656,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011000" =>
inv <= conv_std_logic_vector(2450,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(467173,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205578013,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011001" =>
inv <= conv_std_logic_vector(2448,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(494576,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(87278952,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011010" =>
inv <= conv_std_logic_vector(2445,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(535722,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45542114,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011011" =>
inv <= conv_std_logic_vector(2442,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(576918,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(142506767,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011100" =>
inv <= conv_std_logic_vector(2439,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(618165,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(143076061,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011101" =>
inv <= conv_std_logic_vector(2436,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(659463,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(80711705,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011110" =>
inv <= conv_std_logic_vector(2433,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(700811,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(257434563,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101011111" =>
inv <= conv_std_logic_vector(2431,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(728406,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17672925,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100000" =>
inv <= conv_std_logic_vector(2428,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(769839,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(220454209,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100001" =>
inv <= conv_std_logic_vector(2425,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(811324,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(215622313,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100010" =>
inv <= conv_std_logic_vector(2422,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(852861,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(37221475,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100011" =>
inv <= conv_std_logic_vector(2419,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(894448,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256293434,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100100" =>
inv <= conv_std_logic_vector(2417,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(922202,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(222525409,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100101" =>
inv <= conv_std_logic_vector(2414,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(963876,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(196069656,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100110" =>
inv <= conv_std_logic_vector(2411,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1005602,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(121961634,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101100111" =>
inv <= conv_std_logic_vector(2408,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1047380,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34841718,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101000" =>
inv <= conv_std_logic_vector(2405,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1089209,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(237915287,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101001" =>
inv <= conv_std_logic_vector(2403,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1117125,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(104353094,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101010" =>
inv <= conv_std_logic_vector(2400,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1159042,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63396520,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101011" =>
inv <= conv_std_logic_vector(2397,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1201011,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137556064,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101100" =>
inv <= conv_std_logic_vector(2395,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1229020,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(59568237,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101101" =>
inv <= conv_std_logic_vector(2392,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1271077,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(46073956,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101110" =>
inv <= conv_std_logic_vector(2389,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1313186,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241992154,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101101111" =>
inv <= conv_std_logic_vector(2386,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1355349,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146057517,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110000" =>
inv <= conv_std_logic_vector(2384,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1383487,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(116561426,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110001" =>
inv <= conv_std_logic_vector(2381,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1425738,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(150565181,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110010" =>
inv <= conv_std_logic_vector(2378,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1468042,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(256758677,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110011" =>
inv <= conv_std_logic_vector(2376,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1496275,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146872826,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110100" =>
inv <= conv_std_logic_vector(2373,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1538669,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(6283669,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110101" =>
inv <= conv_std_logic_vector(2370,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1581116,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(34459956,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110110" =>
inv <= conv_std_logic_vector(2367,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1623616,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267869958,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101110111" =>
inv <= conv_std_logic_vector(2365,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1651980,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(227479388,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111000" =>
inv <= conv_std_logic_vector(2362,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1694571,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168535478,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111001" =>
inv <= conv_std_logic_vector(2360,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1722995,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146252604,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111010" =>
inv <= conv_std_logic_vector(2357,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1765676,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(165723426,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111011" =>
inv <= conv_std_logic_vector(2354,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1808412,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13198653,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111100" =>
inv <= conv_std_logic_vector(2352,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1836932,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(162422791,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111101" =>
inv <= conv_std_logic_vector(2349,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1879758,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253404775,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111110" =>
inv <= conv_std_logic_vector(2346,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1922640,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3516811,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "101111111" =>
inv <= conv_std_logic_vector(2344,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1951257,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232810820,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000000" =>
inv <= conv_std_logic_vector(2341,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(1994230,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(124778707,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000001" =>
inv <= conv_std_logic_vector(2338,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2037258,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(44895651,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000010" =>
inv <= conv_std_logic_vector(2336,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2065973,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(264640088,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000011" =>
inv <= conv_std_logic_vector(2333,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2109093,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(226677719,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000100" =>
inv <= conv_std_logic_vector(2331,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2137871,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(62314345,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000101" =>
inv <= conv_std_logic_vector(2328,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2181083,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(172467092,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000110" =>
inv <= conv_std_logic_vector(2326,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2209922,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(231891008,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110000111" =>
inv <= conv_std_logic_vector(2323,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2253228,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60167664,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001000" =>
inv <= conv_std_logic_vector(2320,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2296589,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(146717848,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001001" =>
inv <= conv_std_logic_vector(2318,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2325528,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(68833327,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001010" =>
inv <= conv_std_logic_vector(2315,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2368983,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(45955088,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001011" =>
inv <= conv_std_logic_vector(2313,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2397984,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(110242438,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001100" =>
inv <= conv_std_logic_vector(2310,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2441533,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(86625006,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001101" =>
inv <= conv_std_logic_vector(2308,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2470597,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(97343330,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001110" =>
inv <= conv_std_logic_vector(2305,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2514240,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182382776,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110001111" =>
inv <= conv_std_logic_vector(2303,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2543367,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(212699904,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010000" =>
inv <= conv_std_logic_vector(2300,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2587105,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(248069835,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010001" =>
inv <= conv_std_logic_vector(2297,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2630901,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(38353874,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010010" =>
inv <= conv_std_logic_vector(2295,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2660129,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(199724201,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010011" =>
inv <= conv_std_logic_vector(2292,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2704020,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(118011763,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010100" =>
inv <= conv_std_logic_vector(2290,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2733312,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(223026379,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010101" =>
inv <= conv_std_logic_vector(2287,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2777299,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112874067,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010110" =>
inv <= conv_std_logic_vector(2285,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2806655,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236438996,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110010111" =>
inv <= conv_std_logic_vector(2282,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2850738,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210574529,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011000" =>
inv <= conv_std_logic_vector(2280,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2880159,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(159652923,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011001" =>
inv <= conv_std_logic_vector(2278,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2909606,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60159477,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011010" =>
inv <= conv_std_logic_vector(2275,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2953824,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182033526,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011011" =>
inv <= conv_std_logic_vector(2273,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(2983336,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(14447396,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011100" =>
inv <= conv_std_logic_vector(2270,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3027651,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(225760651,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011101" =>
inv <= conv_std_logic_vector(2268,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3057228,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66680404,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011110" =>
inv <= conv_std_logic_vector(2265,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3101641,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(214275106,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110011111" =>
inv <= conv_std_logic_vector(2263,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3131283,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(140806814,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100000" =>
inv <= conv_std_logic_vector(2260,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3175795,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(72289811,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100001" =>
inv <= conv_std_logic_vector(2258,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3205502,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(162051533,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100010" =>
inv <= conv_std_logic_vector(2256,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3235236,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(70518411,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100011" =>
inv <= conv_std_logic_vector(2253,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3279886,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(56927398,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100100" =>
inv <= conv_std_logic_vector(2251,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3309685,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(238158383,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100101" =>
inv <= conv_std_logic_vector(2248,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3354435,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(21682069,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100110" =>
inv <= conv_std_logic_vector(2246,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3384301,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17671725,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110100111" =>
inv <= conv_std_logic_vector(2243,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3429149,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253874147,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101000" =>
inv <= conv_std_logic_vector(2241,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3459082,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(144015594,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101001" =>
inv <= conv_std_logic_vector(2239,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3489041,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(228915285,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101010" =>
inv <= conv_std_logic_vector(2236,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3534031,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11297232,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101011" =>
inv <= conv_std_logic_vector(2234,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3564057,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(102394521,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101100" =>
inv <= conv_std_logic_vector(2232,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3594110,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(164843479,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101101" =>
inv <= conv_std_logic_vector(2229,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3639240,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(266678657,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101110" =>
inv <= conv_std_logic_vector(2227,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3669361,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(179992124,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110101111" =>
inv <= conv_std_logic_vector(2224,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3714593,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(119109352,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110000" =>
inv <= conv_std_logic_vector(2222,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3744781,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(233164434,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110001" =>
inv <= conv_std_logic_vector(2220,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3774997,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(128320487,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110010" =>
inv <= conv_std_logic_vector(2217,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3820371,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260492078,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110011" =>
inv <= conv_std_logic_vector(2215,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3850655,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(202899023,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110100" =>
inv <= conv_std_logic_vector(2213,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3880966,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241038144,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110101" =>
inv <= conv_std_logic_vector(2210,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3926485,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3486646,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110110" =>
inv <= conv_std_logic_vector(2208,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3956864,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(204914613,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110110111" =>
inv <= conv_std_logic_vector(2206,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(3987272,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(11839650,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111000" =>
inv <= conv_std_logic_vector(2203,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4032934,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(186275213,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111001" =>
inv <= conv_std_logic_vector(2201,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4063411,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(5198727,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111010" =>
inv <= conv_std_logic_vector(2199,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4093915,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(13571695,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111011" =>
inv <= conv_std_logic_vector(2196,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4139723,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(41866951,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111100" =>
inv <= conv_std_logic_vector(2194,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4170296,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(180504741,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111101" =>
inv <= conv_std_logic_vector(2192,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4200898,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(19253907,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111110" =>
inv <= conv_std_logic_vector(2190,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4231527,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(108649881,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "110111111" =>
inv <= conv_std_logic_vector(2187,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4277523,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(239373474,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000000" =>
inv <= conv_std_logic_vector(2185,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4308223,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(75890782,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000001" =>
inv <= conv_std_logic_vector(2183,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4338950,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(211176572,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000010" =>
inv <= conv_std_logic_vector(2180,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4385094,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(232816832,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000011" =>
inv <= conv_std_logic_vector(2178,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4415892,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(236107455,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000100" =>
inv <= conv_std_logic_vector(2176,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4446719,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(49882053,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000101" =>
inv <= conv_std_logic_vector(2174,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4477573,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(224979561,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000110" =>
inv <= conv_std_logic_vector(2171,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4523909,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(21351166,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111000111" =>
inv <= conv_std_logic_vector(2169,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4554834,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(221595418,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001000" =>
inv <= conv_std_logic_vector(2167,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4585789,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(27048959,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001001" =>
inv <= conv_std_logic_vector(2165,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4616771,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(257160862,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001010" =>
inv <= conv_std_logic_vector(2163,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4647783,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(120806675,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001011" =>
inv <= conv_std_logic_vector(2160,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4694354,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132686548,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001100" =>
inv <= conv_std_logic_vector(2158,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4725437,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(216213494,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001101" =>
inv <= conv_std_logic_vector(2156,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4756549,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(251657420,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001110" =>
inv <= conv_std_logic_vector(2154,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4787690,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(253378504,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111001111" =>
inv <= conv_std_logic_vector(2151,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4834456,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(190686783,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010000" =>
inv <= conv_std_logic_vector(2149,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4865670,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(36971813,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010001" =>
inv <= conv_std_logic_vector(2147,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4896912,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(168546215,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010010" =>
inv <= conv_std_logic_vector(2145,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4928184,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(63080520,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010011" =>
inv <= conv_std_logic_vector(2143,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(4959485,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3592320,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010100" =>
inv <= conv_std_logic_vector(2140,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5006490,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(267447830,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010101" =>
inv <= conv_std_logic_vector(2138,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5037864,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(252750919,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010110" =>
inv <= conv_std_logic_vector(2136,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5069268,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(66956194,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111010111" =>
inv <= conv_std_logic_vector(2134,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5100700,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261701721,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011000" =>
inv <= conv_std_logic_vector(2132,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5132163,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(46489821,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011001" =>
inv <= conv_std_logic_vector(2130,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5163654,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241477251,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011010" =>
inv <= conv_std_logic_vector(2127,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5210947,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(261928568,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011011" =>
inv <= conv_std_logic_vector(2125,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5242513,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(205482523,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011100" =>
inv <= conv_std_logic_vector(2123,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5274109,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(74671864,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011101" =>
inv <= conv_std_logic_vector(2121,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5305734,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(152972013,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011110" =>
inv <= conv_std_logic_vector(2119,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5337389,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(187030043,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111011111" =>
inv <= conv_std_logic_vector(2117,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5369074,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(191971210,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100000" =>
inv <= conv_std_logic_vector(2115,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5400789,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(182963660,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100001" =>
inv <= conv_std_logic_vector(2112,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5448418,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(109475927,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100010" =>
inv <= conv_std_logic_vector(2110,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5480208,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(132240138,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100011" =>
inv <= conv_std_logic_vector(2108,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5512028,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(194484233,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100100" =>
inv <= conv_std_logic_vector(2106,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5543879,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(43135919,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100101" =>
inv <= conv_std_logic_vector(2104,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5575759,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(230473058,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100110" =>
inv <= conv_std_logic_vector(2102,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5607670,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(235075650,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111100111" =>
inv <= conv_std_logic_vector(2100,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5639612,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(72438727,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101000" =>
inv <= conv_std_logic_vector(2098,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5671584,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(26537070,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101001" =>
inv <= conv_std_logic_vector(2096,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5703586,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(112954470,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101010" =>
inv <= conv_std_logic_vector(2093,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5751647,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(55116163,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101011" =>
inv <= conv_std_logic_vector(2091,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5783726,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(3932676,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101100" =>
inv <= conv_std_logic_vector(2089,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5815835,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(139964094,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101101" =>
inv <= conv_std_logic_vector(2087,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5847975,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(210560941,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101110" =>
inv <= conv_std_logic_vector(2085,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5880146,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(231554600,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111101111" =>
inv <= conv_std_logic_vector(2083,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5912348,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(218822034,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110000" =>
inv <= conv_std_logic_vector(2081,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5944581,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(188285963,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110001" =>
inv <= conv_std_logic_vector(2079,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(5976845,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155915034,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110010" =>
inv <= conv_std_logic_vector(2077,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6009140,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(137724004,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110011" =>
inv <= conv_std_logic_vector(2075,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6041466,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(149773915,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110100" =>
inv <= conv_std_logic_vector(2073,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6073823,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(208172277,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110101" =>
inv <= conv_std_logic_vector(2071,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6106212,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(60637778,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110110" =>
inv <= conv_std_logic_vector(2069,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6138631,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(260242308,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111110111" =>
inv <= conv_std_logic_vector(2067,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6171083,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(17927474,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111000" =>
inv <= conv_std_logic_vector(2065,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6203565,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(155294811,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111001" =>
inv <= conv_std_logic_vector(2063,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6236079,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(151815941,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111010" =>
inv <= conv_std_logic_vector(2061,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6268625,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(23880951,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111011" =>
inv <= conv_std_logic_vector(2059,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6301202,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(56363124,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111100" =>
inv <= conv_std_logic_vector(2057,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6333810,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(265748209,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111101" =>
inv <= conv_std_logic_vector(2055,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6366451,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(131699156,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111110" =>
inv <= conv_std_logic_vector(2053,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6399123,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(207669033,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN "111111111" =>
inv <= conv_std_logic_vector(2051,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(6431827,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(241853027,28);
logexp <= conv_std_logic_vector(1022,11);
WHEN others =>
inv <= conv_std_logic_vector(0,12);
logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24);
logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
logexp <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/fpc_library_cmd.vhd | 10 | 105191 | -- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
--***************************************************
--***************************************************
--*** ***
--*** ALTERA ADSPB FLOATING POINT LIBRARY ***
--*** ***
--*** FPC_LIBRARY.VHD ***
--*** ***
--*** Function: Interfaces between ADSBP ***
--*** components and hcc components ***
--*** This solves a number of issues: ***
--*** 1. 0 or 1-based vectors ***
--*** 2. encapsulation of 'target' ***
--*** 3. Allows VHDL library to be ***
--*** isolated from tool ***
--*** 4. Grouping sat/zip with value***
--*** as one signal ***
--*** ***
--*** 25/07/09 SWP ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--***************************************************
--***************************************************
--*** SINGLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_addsub_sInternal_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternal_2_sInternal IS
BEGIN
cmp: hcc_alufp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
shiftspeed => m_fpShiftSpeed,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_addsub_sInternalSM_2_sInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal IS
BEGIN
cmp: hcc_alufp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
shiftspeed => m_fpShiftSpeed,
outputpipe => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_addsub_sInternalSM_2_sInternal_v31 ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_addsub_sInternalSM_2_sInternal_v31 IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (45 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_addsub_sInternalSM_2_sInternal_v31;
ARCHITECTURE rtl OF fp_addsub_sInternalSM_2_sInternal_v31 IS
BEGIN
cmp: hcc_aludot_v2
GENERIC MAP (
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aasign => dataa(42),
aaexponent => dataa(41 DOWNTO 32),
aamantissa => dataa(31 DOWNTO 0),
aasat => dataa(43),
aazip => dataa(44),
aanan => dataa(45),
bbsign => datab(42),
bbexponent => datab(41 DOWNTO 32),
bbmantissa => datab(31 DOWNTO 0),
bbsat => datab(43),
bbzip => datab(44),
bbnan => dataa(45),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_sNorm_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sInternal ;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sInternal IS
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_sNorm_2_sNorm IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sNorm IS
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
multoutput => 1,
xoutput => 0,
device => deviceFamilyA5(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_sNorm_2_sIEEE IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_mult_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_mult_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
outputscale => m_fpOutputScale,
device => deviceFamilyA5(m_family),
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_sIEEE_2_sInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternal;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_mulfp1vec
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_sIEEE_2_sInternalSM IS
GENERIC (
m_family : string;
m_dotopt : positive
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM IS
BEGIN
cmp: hcc_mulfp1_dot
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
device => deviceFamily(m_family),
optimization => m_dotopt,
synthesize => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_sIEEE_2_sInternalSM _v31 ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_sIEEE_2_sInternalSM_v31 IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (45 DOWNTO 0)
);
END fp_mult_sIEEE_2_sInternalSM_v31;
ARCHITECTURE rtl OF fp_mult_sIEEE_2_sInternalSM_v31 IS
BEGIN
cmp: hcc_muldot_v1
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa,
bb => datab,
ccsign => result(42),
ccexponent => result(41 DOWNTO 32),
ccmantissa => result(31 DOWNTO 0),
ccsat => result(43),
cczip => result(44),
ccnan => result(45)
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_div_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_div_sNorm_2_sIEEE;
ARCHITECTURE rtl OF fp_div_sNorm_2_sIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 1,
xoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(31 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_div_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_div_sNorm_2_sInternal;
ARCHITECTURE rtl OF fp_div_sNorm_2_sInternal IS
BEGIN
cmp: hcc_divfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
roundconvert => m_fpRoundConvert,
synthesize => 1,
ieeeoutput => 0,
xoutput => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
bb => datab(41 DOWNTO 0),
bbsat => datab(42),
bbzip => datab(43),
bbnan => datab(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_dNorm_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_mult_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
device => deviceFamily(m_family)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_div_dNorm_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_div_dNorm_2_dIEEE;
ARCHITECTURE rtl OF fp_div_dNorm_2_dIEEE IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 1,
xoutput => 0,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(63 DOWNTO 0),
ccsat => ccsat,
cczip => cczip,
ccnan => ccnan
);
END rtl;
--***************************************************
--*** fp_div_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_div_dNorm_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_div_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_div_dNorm_2_dInternal IS
signal ccsat : std_logic;
signal cczip : std_logic;
signal ccnan : std_logic;
BEGIN
cmp: hcc_divfp2x
GENERIC MAP (
synthesize => 1,
ieeeoutput => 0,
xoutput => 1,
divoutput => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_exp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_exp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_exp_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal oneOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
signal resPreExcHandling: std_logic_vector(31 downto 0);
signal excBits : std_logic_vector(3 downto 0);
BEGIN
cmp: fp_exp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => resPreExcHandling(31),
exponentout => resPreExcHandling(30 downto 23),
mantissaout => resPreExcHandling(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut,
oneOut => oneOut
);
excBits <= nanOut & overflowOut & underflowOut & oneOut;
with excBits select
result <= "01111111100000000000000000000001" when "1000"|"1001"|"1100",
"01111111100000000000000000000000" when "0100",
"00000000000000000000000000000000" when "0010",
"00111111100000000000000000000000" when "0001"|"0011"|"0101",
resPreExcHandling when others;
END rtl;
--***************************************************
--*** fp_log_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_log_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_log_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_log_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: fp_log
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_recip_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recip_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recip_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: fp_inv
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_recipSqRt_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_recipSqRt_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_sIEEE_2_sIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: fp_invsqr
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** fp_sin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_sin_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_sin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_sin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_sin
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_cos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_cos_sIEEE_2_sIEEE IS
GENERIC (m_family : string);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_cos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_cos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_cos
GENERIC MAP(device => deviceFamily(m_Family))
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_tan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_tan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_tan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_tan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_tan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_asin_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_asin_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_asin_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_asin_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_asin
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_acos_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_acos_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_acos_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_acos_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_acos
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_atan_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_atan_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_atan_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_atan_sIEEE_2_sIEEE IS
BEGIN
cmp: fp_atan
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0)
);
END rtl;
--***************************************************
--*** fp_ldexp_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_ldexp_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_ldexp_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_ldexp_sIEEE_2_sIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: fp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
bb => datab,
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** fp_ldexp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_ldexp_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_ldexp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_ldexp_dIEEE_2_dIEEE IS
SIGNAL sat : STD_LOGIC;
SIGNAL zip : STD_LOGIC;
SIGNAL nan : STD_LOGIC;
BEGIN
cmp: dp_ldexp
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
bb => datab,
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
satout => sat,
zeroout => zip,
nanout => nan
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sIEEE_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sNorm;
ARCHITECTURE rtl OF cast_sIEEE_2_sNorm IS
signal res : std_logic_vector (44 downto 0);
signal as : std_logic;
signal ae : std_logic_vector (7 downto 0);
signal am : std_logic_vector (23 downto 0);
signal re : std_logic_vector (9 downto 0);
signal rm : std_logic_vector (31 downto 0);
signal exp : INTEGER;
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
as <= dataa(31);
ae <= dataa(30 downto 23);
am <= '1' & dataa(22 downto 0);
re <= res(9 downto 0);
rm <= res(41 downto 10);
END rtl;
--***************************************************
--*** cast_sIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_sInternal IS
BEGIN
cmp: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_sIEEE_2_dIEEE;
ARCHITECTURE rtl OF cast_sIEEE_2_dIEEE IS
component hcc_castftod IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
cmp: hcc_castftod
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(63 DOWNTO 0));
END rtl;
--***************************************************
--*** cast_dInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_dInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_sIEEE IS
BEGIN
cmp: hcc_castytof
GENERIC MAP (
roundconvert => m_fpRoundConvert
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dIEEE_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dIEEE_2_sInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_sInternal IS
signal mid : std_logic_vector (79 downto 0);
BEGIN
cmp1: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => mid(76 DOWNTO 0),
ccsat => mid(77),
cczip => mid(78),
ccNAN => mid(79)
);
cmp2: hcc_castytox
GENERIC MAP (
roundconvert=>m_fpRoundConvert,
mantissa=>m_SingleMantissaWidth)
PORT MAP (
sysclk=>clock,
reset=>reset,
enable=>clk_en,
aa=>mid(76 DOWNTO 0),
aasat=>mid(77),
aazip=>mid(78),
aanan=>mid(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
-- cmp: hcc_castdtox
-- GENERIC MAP (
-- target => 0,
-- roundconvert => m_fpRoundConvert,
-- mantissa => m_SingleMantissaWidth,
-- doublespeed => m_fpDoubleSpeed
-- )
-- PORT MAP (
-- sysclk => clock,
-- reset => reset,
-- enable => clk_en,
--
-- aa => dataa(63 DOWNTO 0),
-- cc => result(41 DOWNTO 0),
-- ccsat => result(42),
-- cczip => result(43),
-- ccnan => result(44)
-- );
END rtl;
--***************************************************
--*** cast_sIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_sIEEE_2_dInternal IS
BEGIN
cmp: hcc_castftoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(31 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sInternal_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sInternal_2_sNorm;
ARCHITECTURE rtl OF cast_sInternal_2_sNorm IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
inputnormalize => 1,
roundnormalize => 0,
normspeed => 2, --min(2, m_fpNormalisationSpeed), if 3 is used then zip pipeline is broken
target => 0
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sInternal_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sInternal_2_sIEEE;
ARCHITECTURE rtl OF cast_sInternal_2_sIEEE IS
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sNorm_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_sNorm_2_sIEEE;
ARCHITECTURE rtl OF cast_sNorm_2_sIEEE IS
signal x : STD_LOGIC_VECTOR(41 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 --maximum 2 m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
-- truncation; no rounding
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(31 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_sInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sInternal_2_fixed;
ARCHITECTURE rtl OF cast_sInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_sNorm_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sNorm_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_sNorm_2_sInternal;
ARCHITECTURE rtl OF cast_sNorm_2_sInternal IS
BEGIN
-- truncation; no rounding
result <= dataa(44 DOWNTO 42) & dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
END rtl;
--***************************************************
--*** cast_sInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_sInternal_2_dInternal;
ARCHITECTURE rtl OF cast_sInternal_2_dInternal IS
BEGIN
cmp: hcc_castxtoy
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** cast_sNorm_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sNorm_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sNorm_2_fixed;
ARCHITECTURE rtl OF cast_sNorm_2_fixed IS
signal x : STD_LOGIC_VECTOR (41 DOWNTO 0);
signal mid : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- truncation; no rounding
x <= dataa(41) & dataa(41) & dataa(41) & dataa(41) & dataa(41 DOWNTO 14) & dataa(9 downto 0);
cmp: hcc_castxtof
GENERIC MAP (
mantissa => m_SingleMantissaWidth,
normspeed => 2 -- m_fpNormalisationSpeed
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => x,
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => mid(31 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(31),
exponent => mid(30 downto 23),
mantissa => mid(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--***************************************************
--*** DOUBLE PRECISION ***
--***************************************************
--***************************************************
--***************************************************
--*** fp_addsub_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_addsub_dInternal_2_dInternal IS
GENERIC (
addsub_resetval : STD_LOGIC
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
add_sub : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_addsub_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_addsub_dInternal_2_dInternal IS
BEGIN
cmp: hcc_alufp2x
GENERIC MAP (
shiftspeed => m_fpShiftSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1,
addsub_resetval => addsub_resetval
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
addsub => add_sub(0),
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
bb => datab(76 DOWNTO 0),
bbsat => datab(77),
bbzip => datab(78),
bbnan => datab(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79));
END rtl;
--***************************************************
--*** fp_mult_dNorm_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_mult_dNorm_2_dInternal IS
GENERIC ( m_family : string );
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (69 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_mult_dNorm_2_dInternal;
ARCHITECTURE rtl OF fp_mult_dNorm_2_dInternal IS
BEGIN
cmp: hcc_mulfp2x
GENERIC MAP (
ieeeoutput => 0,
xoutput => 1,
multoutput => 0,
device => deviceFamily(m_family),
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
doublespeed => m_fpDoubleSpeed,
outputpipe => m_fpOutputPipe,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(66 DOWNTO 0),
aasat => dataa(67),
aazip => dataa(68),
aanan => dataa(69),
bb => datab(66 DOWNTO 0),
bbsat => datab(67),
bbzip => datab(68),
bbnan => datab(69),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_exp_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_exp_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_exp_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_exp_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal underflowOut : std_logic;
BEGIN
cmp: dp_exp
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
underflowOut => underflowOut
);
END rtl;
--***************************************************
--*** fp_log_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_log_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_log_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_log_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal overflowOut : std_logic;
signal zeroOut : std_logic;
BEGIN
cmp: dp_log
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
overflowOut => overflowOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_recip_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_recip_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recip_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recip_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
signal divideByZeroOut : std_logic;
BEGIN
cmp: dp_inv
GENERIC MAP (
roundconvert => m_fpRoundConvert,
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut,
divideByZeroOut => divideByZeroOut
);
END rtl;
--***************************************************
--*** fp_recipSqRt_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_recipSqRt_dIEEE_2_dIEEE IS
GENERIC (
m_family : string
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_recipSqRt_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_recipSqRt_dIEEE_2_dIEEE IS
signal nanOut : std_logic;
signal invalidOut : std_logic;
BEGIN
cmp: dp_invsqr
GENERIC MAP (
doubleaccuracy => 0, -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed => m_fpDoubleSpeed,
device => deviceFamilyS3(m_family) -- (0 = Stratix II, 1 = Stratix III/IV)
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
invalidOut => invalidOut
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dIEEE_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dIEEE_2_dNorm;
ARCHITECTURE rtl OF cast_dIEEE_2_dNorm IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68)
);
result(69) <= '0'; -- no nan
END rtl;
--***************************************************
--*** cast_dIEEE_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dIEEE_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_dIEEE_2_dInternal;
ARCHITECTURE rtl OF cast_dIEEE_2_dInternal IS
BEGIN
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(63 DOWNTO 0),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dInternal_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (69 DOWNTO 0)
);
END cast_dInternal_2_dNorm;
ARCHITECTURE rtl OF cast_dInternal_2_dNorm IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
roundconvert => m_fpRoundConvert,
roundnormalize => 0,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
target => 0,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(66 DOWNTO 0),
ccsat => result(67),
cczip => result(68),
ccnan => result(69)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dInternal_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_dInternal_2_dIEEE;
ARCHITECTURE rtl OF cast_dInternal_2_dIEEE IS
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(63 DOWNTO 0)
);
END rtl;
--***************************************************
--*** cast_fixed_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_fixed_2_sNorm IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sNorm;
ARCHITECTURE rtl OF cast_fixed_2_sNorm IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sNorm
cmp2: hcc_castftox
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_fixed_2_sInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_fixed_2_sInternal;
ARCHITECTURE rtl OF cast_fixed_2_sInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (44 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
-- Firstly, convert integer to SIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to sInternal
cmp2: hcc_castftox
GENERIC MAP (
target => 0,
roundconvert => m_fpRoundConvert,
mantissa => m_SingleMantissaWidth,
outputpipe => m_fpOutputPipe
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => res(41 DOWNTO 0),
ccsat => res(42),
cczip => res(43),
ccnan => res(44)
);
result <= res;
END rtl;
--***************************************************
--*** cast_fixed_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_fixed_2_sIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END cast_fixed_2_sIEEE;
ARCHITECTURE rtl OF cast_fixed_2_sIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (7 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (22 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_fixed_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_fixed_2_dIEEE IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END cast_fixed_2_dIEEE;
ARCHITECTURE rtl OF cast_fixed_2_dIEEE IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
BEGIN
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
result <= ccsign & ccexponent & ccmantissa;
END rtl;
--***************************************************
--*** cast_sIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_sIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_sIEEE_2_fixed;
ARCHITECTURE rtl OF cast_sIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 0, -- single
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(31),
exponent => dataa(30 downto 23),
mantissa => dataa(22 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dIEEE_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dIEEE_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dIEEE_2_fixed;
ARCHITECTURE rtl OF cast_dIEEE_2_fixed IS
BEGIN
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => dataa(63),
exponent => dataa(62 downto 52),
mantissa => dataa(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_dInternal_2_fixed ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dInternal_2_fixed IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0)
);
END cast_dInternal_2_fixed;
ARCHITECTURE rtl OF cast_dInternal_2_fixed IS
signal mid : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
cmp: hcc_castytod
GENERIC MAP (
roundconvert => m_fpRoundConvert,
normspeed => m_fpNormalisationSpeed,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => mid(63 DOWNTO 0)
);
cmp1: dp_floatfix
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
sign => mid(63),
exponent => mid(62 downto 52),
mantissa => mid(51 downto 0),
fixed_number => result
);
END rtl;
--***************************************************
--*** cast_fixed_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_fixed_2_dInternal IS
GENERIC (
unsigned : integer;
iWidth : integer;
fWidth : integer
);
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (iWidth+fWidth-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END cast_fixed_2_dInternal;
ARCHITECTURE rtl OF cast_fixed_2_dInternal IS
signal ccsign : STD_LOGIC;
signal ccexponent : STD_LOGIC_VECTOR (10 DOWNTO 0);
signal ccmantissa : STD_LOGIC_VECTOR (51 DOWNTO 0);
signal res : STD_LOGIC_VECTOR (79 DOWNTO 0);
signal ccIEEE : STD_LOGIC_VECTOR (63 DOWNTO 0);
BEGIN
-- Firstly, convert integer to dIEEE
cmp1: dp_fixfloat
GENERIC MAP (
unsigned => unsigned,
decimal => iWidth,
fractional => fWidth,
precision => 1, -- double
speed => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
fixed_number => dataa,
sign => ccsign,
exponent => ccexponent,
mantissa => ccmantissa
);
ccIEEE <= ccsign & ccexponent & ccmantissa;
-- then convert that to dInternal
cmp: hcc_castdtoy
GENERIC MAP (
target => 1,
roundconvert => m_fpRoundConvert,
outputpipe => m_fpOutputPipe,
doublespeed => m_fpDoubleSpeed,
synthesize => 1
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => ccIEEE,
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccNAN => result(79)
);
END rtl;
--***************************************************
--*** cast_dInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY cast_dInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END cast_dInternal_2_sInternal;
ARCHITECTURE rtl OF cast_dInternal_2_sInternal IS
BEGIN
cmp: hcc_castytox
GENERIC MAP (
mantissa => m_SingleMantissaWidth
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_abs_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_abs_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_abs_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_abs_sIEEE_2_sIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: fp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(31),
exponentin => dataa(30 downto 23),
mantissain => dataa(22 downto 0),
signout => result(31),
exponentout => result(30 downto 23),
mantissaout => result(22 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_abs_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
USE STD.TEXTIO.ALL;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_abs_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_abs_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_abs_dIEEE_2_dIEEE IS
signal nanOut : STD_LOGIC;
signal satOut : STD_LOGIC;
signal zeroOut : STD_LOGIC;
BEGIN
cmp: dp_fabs
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
signin => dataa(63),
exponentin => dataa(62 downto 52),
mantissain => dataa(51 downto 0),
signout => result(63),
exponentout => result(62 downto 52),
mantissaout => result(51 downto 0),
nanOut => nanOut,
satOut => satOut,
zeroOut => zeroOut
);
END rtl;
--***************************************************
--*** fp_norm_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_norm_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_norm_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_norm_sInternal_2_sInternal IS
BEGIN
cmp: hcc_normfp1x
GENERIC MAP (
mantissa => m_SingleMantissaWidth, -- TODO: add support for 36-bit mantissa too
target => 2 -- adder
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(41 DOWNTO 0),
aasat => dataa(42),
aazip => dataa(43),
aanan => dataa(44),
cc => result(41 DOWNTO 0),
ccsat => result(42),
cczip => result(43),
ccnan => result(44)
);
END rtl;
--***************************************************
--*** fp_norm_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_norm_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_norm_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_norm_dInternal_2_dInternal IS
BEGIN
cmp: hcc_normfp2x
GENERIC MAP (
doublespeed => m_fpDoubleSpeed,
target => 1 -- internal
)
PORT MAP (
sysclk => clock,
reset => reset,
enable => clk_en,
aa => dataa(76 DOWNTO 0),
aasat => dataa(77),
aazip => dataa(78),
aanan => dataa(79),
cc => result(76 DOWNTO 0),
ccsat => result(77),
cczip => result(78),
ccnan => result(79)
);
END rtl;
--***************************************************
--*** fp_negate_sIEEE_2_sIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_negate_sIEEE_2_sIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END fp_negate_sIEEE_2_sIEEE;
ARCHITECTURE rtl OF fp_negate_sIEEE_2_sIEEE IS
BEGIN
result <= (not dataa(31)) & dataa(30 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_sNorm_2_sNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_negate_sNorm_2_sNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sNorm_2_sNorm;
ARCHITECTURE rtl OF fp_negate_sNorm_2_sNorm IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_sInternal_2_sInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_negate_sInternal_2_sInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (44 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (44 DOWNTO 0)
);
END fp_negate_sInternal_2_sInternal;
ARCHITECTURE rtl OF fp_negate_sInternal_2_sInternal IS
signal oMant : STD_LOGIC_VECTOR (31 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR ( 9 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(41 DOWNTO 10));-- 1's complement
oExp <= dataa(9 DOWNTO 0);
oFlags <= dataa(44 downto 42);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dIEEE_2_dIEEE ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_negate_dIEEE_2_dIEEE IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END fp_negate_dIEEE_2_dIEEE;
ARCHITECTURE rtl OF fp_negate_dIEEE_2_dIEEE IS
BEGIN
result <= (not dataa(63)) & dataa(62 downto 0); -- flip sign
END rtl;
--***************************************************
--*** fp_negate_dNorm_2_dNorm ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_negate_dNorm_2_dNorm IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dNorm_2_dNorm;
ARCHITECTURE rtl OF fp_negate_dNorm_2_dNorm IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
--***************************************************
--*** fp_negate_dInternal_2_dInternal ***
--***************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
--USE ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.all;
LIBRARY lpm;
USE lpm.all;
USE work.hcc_package_cmd.all;
USE work.math_package_cmd.all;
USE work.fpc_library_package_cmd.all;
ENTITY fp_negate_dInternal_2_dInternal IS
PORT (
clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk_en : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR (79 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 0)
);
END fp_negate_dInternal_2_dInternal;
ARCHITECTURE rtl OF fp_negate_dInternal_2_dInternal IS
signal oMant : STD_LOGIC_VECTOR (63 DOWNTO 0);
signal oExp : STD_LOGIC_VECTOR (12 DOWNTO 0);
signal oFlags: STD_LOGIC_VECTOR ( 2 DOWNTO 0);
BEGIN
oMant <= not(dataa(76 DOWNTO 13));-- 1's complement
oExp <= dataa(12 DOWNTO 0);
oFlags <= dataa(79 downto 77);
result <= oFlags & oMant & oExp;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/hcc_castxtod.vhd | 10 | 3498 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOD.VHD ***
--*** ***
--*** Function: Cast Internal Single to IEEE754 ***
--*** Double ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtod IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32;
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castxtod;
ARCHITECTURE rtl OF hcc_castxtod IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castxtoy
GENERIC MAP (target=>1,mantissa=>mantissa)
PORT MAP (aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytod
GENERIC MAP (roundconvert=>roundconvert,normspeed=>normspeed,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/math_package.vhd | 20 | 16832 | -- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LIBRARY_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated library functions ***
--*** ***
--*** 06/02/08 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
PACKAGE math_package IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component fp_inv
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
component fp_invsqr
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
end component;
component fp_sqr
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
end component;
component fp_exp
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
end component;
component fp_log
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_ldexp
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component fp_fabs
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component fp_neg
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component fp_sin
GENERIC (
device : integer := 0;
width : positive := 30;
depth : positive := 18;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_cos
GENERIC (
device : integer := 0;
width : positive := 30;
depth : positive := 18;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_tan
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_asin
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_acos
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
component fp_atan
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component dp_inv
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
component dp_invsqr
GENERIC (
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
end component;
component dp_sqr
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
end component;
component dp_exp
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
end component;
component dp_log
GENERIC (
roundconvert : integer := 0; -- 0 = no round, 1 = round
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component dp_ldexp
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component dp_fabs
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component dp_neg
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
end component;
component dp_fixfloat IS
GENERIC (
unsigned : integer := 0; -- unsigned = 0, signed = 1
decimal : integer := 18;
fractional : integer := 14;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fixed_number : IN STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1);
sign : OUT STD_LOGIC;
exponent : OUT STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23+29*precision DOWNTO 1)
);
END component;
component dp_floatfix IS
GENERIC (
unsigned : integer := 1; -- unsigned = 0, signed = 1
decimal : integer := 14;
fractional : integer := 6;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
sign : IN STD_LOGIC;
exponent : IN STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : IN STD_LOGIC_VECTOR (23+29*precision DOWNTO 1);
fixed_number : OUT STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1)
);
END component;
END math_package;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/fp_sincos_s5.vhd | 10 | 671358 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sincos_s5
-- VHDL created on Wed Mar 27 09:55:14 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sincos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
s : out std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sincos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid24_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid25_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid26_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid27_fpSinCosXTest_q : std_logic_vector (13 downto 0);
signal cstNaNwF_uid32_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid52_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal cPi_uid71_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal p_uid73_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal p_uid73_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal expPSin_uid76_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal expPSin_uid76_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal excSelSin_uid119_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expSelectorCos_uid145_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRCond2_uid152_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal zs_uid236_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid239_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (62 downto 0);
signal zs_uid244_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal zs_uid250_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (47 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q : std_logic_vector (37 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q : std_logic_vector (37 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid394_tableGensinPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid396_tableGensinPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid398_tableGensinPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid400_tableGencosPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid402_tableGencosPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid404_tableGencosPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (39 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q : std_logic_vector (67 downto 0);
signal reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q : std_logic_vector (25 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q : std_logic_vector (25 downto 0);
signal reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q : std_logic_vector (67 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (64 downto 0);
signal ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (76 downto 0);
signal ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (75 downto 0);
signal ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (74 downto 0);
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q : std_logic_vector (12 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : signal is true;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 : std_logic;
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal sinXIsXRR_uid41_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal yIsZero_uid51_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid55_fpSinCosXTest_q : std_logic_vector (66 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid43_uid43_fpSinCosXTest_q : std_logic_vector (53 downto 0);
signal half_uid53_fpSinCosXTest_q : std_logic_vector (65 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid9_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid37_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid37_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_q : std_logic_vector (9 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal zSin_uid60_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zSin_uid60_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zCos_uid64_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zCos_uid64_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expSinHC_uid74_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid117_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cosXONe_uid148_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid47_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal normBitSin_uid93_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitSin_uid93_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal normBitCos_uid106_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitCos_uid106_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (23 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid196_rrx_uid34_fpSinCosXTest_q : std_logic_vector (79 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal join_uid99_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal join_uid141_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal excSelBitsSin_uid118_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpSin_uid134_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal join_uid143_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpCos_uid162_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal R_uid167_px_uid33_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal addr_uid81_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid81_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal addr_uid83_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid83_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (75 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (75 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (55 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal cosRndOp_uid112_uid113_fpSinCosXTest_q : std_logic_vector (24 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_b : std_logic_vector (21 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b : std_logic_vector (26 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal intXParity_uid49_fpSinCosXTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid49_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal y_uid50_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal y_uid50_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal sinRndOp_uid100_uid101_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal expSelBitsCos_uid144_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal yT1_uid406_polyEvalsinPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid406_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal yT1_uid419_polyEvalcosPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid419_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_q : std_logic_vector (30 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal signComp_uid129_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_b : std_logic_vector (77 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b : std_logic_vector (26 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal s1_uid408_uid411_polyEvalsinPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid414_uid417_polyEvalsinPiZ_q : std_logic_vector (32 downto 0);
signal s1_uid421_uid424_polyEvalcosPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid427_uid430_polyEvalcosPiZ_q : std_logic_vector (32 downto 0);
signal RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q : std_logic_vector (61 downto 0);
signal signR_uid130_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (61 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (61 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (45 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (29 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (29 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid38_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid38_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid39_fpSinCosXTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid39_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal pHigh_uid72_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid72_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal pCos_uid77_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pCos_uid77_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal r_uid277_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal r_uid356_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (69 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable(LOGICAL,1282)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q <= not ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor(LOGICAL,1422)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q <= not (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a or ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top(CONSTANT,1418)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q <= "01011";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp(LOGICAL,1419)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q <= "1" when ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a = ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b else "0";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg(REG,1420)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena(REG,1423)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd(LOGICAL,1424)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a and ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b;
--expFracX_uid166_px_uid33_fpSinCosXTest(BITSELECT,165)@0
expFracX_uid166_px_uid33_fpSinCosXTest_in <= a(30 downto 0);
expFracX_uid166_px_uid33_fpSinCosXTest_b <= expFracX_uid166_px_uid33_fpSinCosXTest_in(30 downto 0);
--R_uid167_px_uid33_fpSinCosXTest(BITJOIN,166)@0
R_uid167_px_uid33_fpSinCosXTest_q <= GND_q & expFracX_uid166_px_uid33_fpSinCosXTest_b;
--expX_uid186_rrx_uid34_fpSinCosXTest(BITSELECT,185)@0
expX_uid186_rrx_uid34_fpSinCosXTest_in <= R_uid167_px_uid33_fpSinCosXTest_q(30 downto 0);
expX_uid186_rrx_uid34_fpSinCosXTest_b <= expX_uid186_rrx_uid34_fpSinCosXTest_in(30 downto 23);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg(DELAY,1412)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid186_rrx_uid34_fpSinCosXTest_b, xout => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=11, step=1, init=1
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i = 10 THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i - 11;
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg(REG,1415)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux(MUX,1416)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem(DUALMEM,1413)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia
);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--zs_uid244_lzcZSin_uid66_fpSinCosXTest(CONSTANT,243)
zs_uid244_lzcZSin_uid66_fpSinCosXTest_q <= "00000000000000000000000000000000";
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor(LOGICAL,1396)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q <= not (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a or ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg(REG,1318)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena(REG,1397)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q = "1") THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd(LOGICAL,1398)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b <= en;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a and ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg(DELAY,1388)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid167_px_uid33_fpSinCosXTest_q, xout => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt(COUNTER,1314)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i,1));
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg(REG,1315)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux(MUX,1316)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux: PROCESS (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem(DUALMEM,1389)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia
);
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq(31 downto 0);
--fracX_uid187_rrx_uid34_fpSinCosXTest(BITSELECT,186)@4
fracX_uid187_rrx_uid34_fpSinCosXTest_in <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q(22 downto 0);
fracX_uid187_rrx_uid34_fpSinCosXTest_b <= fracX_uid187_rrx_uid34_fpSinCosXTest_in(22 downto 0);
--oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest(BITJOIN,196)@4
oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q <= VCC_q & fracX_uid187_rrx_uid34_fpSinCosXTest_b;
--prod_uid198_rrx_uid34_fpSinCosXTest_b_0(BITSELECT,518)@4
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1(REG,539)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid24_fpSinCosXTest(CONSTANT,23)
cstBiasMwShift_uid24_fpSinCosXTest_q <= "01110011";
--expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest(SUB,191)@0
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expX_uid186_rrx_uid34_fpSinCosXTest_b);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid24_fpSinCosXTest_q);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b));
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expXTableAddr_uid193_rrx_uid34_fpSinCosXTest(BITSELECT,192)@0
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0(REG,534)@0
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,514)@1
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1(REG,537)@3
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,513)@1
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0(REG,536)@3
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid196_rrx_uid34_fpSinCosXTest(BITJOIN,195)@4
os_uid196_rrx_uid34_fpSinCosXTest_q <= reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q & reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q;
--prod_uid198_rrx_uid34_fpSinCosXTest_a_2(BITSELECT,517)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in <= STD_LOGIC_VECTOR("0" & os_uid196_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in(80 downto 54);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0(REG,542)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0(MULT,521)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a(DELAY,1145)@8
ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q, xout => ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid198_rrx_uid34_fpSinCosXTest_align_2(BITSHIFT,524)@9
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int <= ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int(107 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_1(BITSELECT,516)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(53 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in(53 downto 27);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0(REG,540)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0(MULT,520)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_1(BITSHIFT,523)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q & "000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int(80 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_0(BITSELECT,515)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(26 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0(REG,538)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0(MULT,519)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_0(BITSHIFT,522)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int(53 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0(ADD,525)@8
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o(81 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0(ADD,526)@9
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b));
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid199_rrx_uid34_fpSinCosXTest(BITSELECT,198)@9
multFracBits_uid199_rrx_uid34_fpSinCosXTest_in <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q(77 downto 0);
multFracBits_uid199_rrx_uid34_fpSinCosXTest_b <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_in(77 downto 0);
--multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest(BITSELECT,199)@9
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b;
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in(77 downto 46);
--reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,544)@9
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,433)@10
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a(DELAY,1178)@10
ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5(REG,555)@12
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid250_lzcZSin_uid66_fpSinCosXTest(CONSTANT,249)
zs_uid250_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000";
--mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest(CONSTANT,434)
mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "11111111111111111111111111111111";
--vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,436)@10
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,438)@10
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in(31 downto 16);
--reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,546)@10
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,439)@11
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4(REG,554)@11
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e(DELAY,1081)@12
ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid8_fpSinCosXTest(CONSTANT,7)
cstAllZWE_uid8_fpSinCosXTest_q <= "00000000";
--vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,440)@10
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q(15 downto 0);
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 0);
--reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,548)@10
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,442)@11
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,444)@11
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 8);
--vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,445)@11
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d(DELAY,1080)@12
ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest(CONSTANT,212)
leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q <= "0000";
--vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,446)@11
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q(7 downto 0);
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,550)@11
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,549)@11
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,448)@12
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,450)@12
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 4);
--vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,451)@12
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,553)@12
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest(CONSTANT,226)
leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q <= "00";
--vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,452)@12
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 0);
--vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,454)@12
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b, vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,456)@12
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,457)@12
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,458)@12
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,552)@12
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,551)@12
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,460)@13
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,462)@13
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 1);
--vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,463)@13
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= GND_q;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest(BITJOIN,464)@13
r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q & ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q & ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q & reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q & vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q & vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
--cstBiasM1_uid23_fpSinCosXTest(CONSTANT,22)
cstBiasM1_uid23_fpSinCosXTest_q <= "01111110";
--expCompOutExt_uid204_rrx_uid34_fpSinCosXTest(SUB,203)@13
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("000" & r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b));
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expCompOut_uid205_rrx_uid34_fpSinCosXTest(BITSELECT,204)@13
expCompOut_uid205_rrx_uid34_fpSinCosXTest_in <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expCompOut_uid205_rrx_uid34_fpSinCosXTest_b <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2(REG,564)@13
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid191_rrx_uid34_fpSinCosXTest(COMPARE,190)@0
xBranch_uid191_rrx_uid34_fpSinCosXTest_cin <= GND_q;
xBranch_uid191_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
xBranch_uid191_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid186_rrx_uid34_fpSinCosXTest_b) & xBranch_uid191_rrx_uid34_fpSinCosXTest_cin(0);
xBranch_uid191_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_b));
xBranch_uid191_rrx_uid34_fpSinCosXTest_n(0) <= not xBranch_uid191_rrx_uid34_fpSinCosXTest_o(10);
--reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1(REG,563)@0
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= xBranch_uid191_rrx_uid34_fpSinCosXTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b(DELAY,829)@1
ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q, xout => ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid209_rrx_uid34_fpSinCosXTest(MUX,208)@14
finalExp_uid209_rrx_uid34_fpSinCosXTest_s <= ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q;
finalExp_uid209_rrx_uid34_fpSinCosXTest: PROCESS (finalExp_uid209_rrx_uid34_fpSinCosXTest_s, en, reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid209_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b(DELAY,833)@14
ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid209_rrx_uid34_fpSinCosXTest_q, xout => ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1409)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a or ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top(CONSTANT,1279)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q <= "01000";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp(LOGICAL,1280)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q <= "1" when ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a = ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b else "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg(REG,1281)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1410)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1411)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1399)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid187_rrx_uid34_fpSinCosXTest_b, xout => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt(COUNTER,1275)
-- every=1, low=0, high=8, step=1, init=1
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i = 7 THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i - 8;
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg(REG,1276)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux(MUX,1277)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1400)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 9,
width_b => 23,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid206_rrx_uid34_fpSinCosXTest(CONSTANT,205)
ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000";
--fracXRExt_uid207_rrx_uid34_fpSinCosXTest(BITJOIN,206)@15
fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q & ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1499)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1500)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1501)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,474)@9
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(29 downto 0);
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in(29 downto 0);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1491)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1492)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(29 downto 0);
--leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest(CONSTANT,473)
leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,475)@13
leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1488)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1489)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1490)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,471)@9
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(45 downto 0);
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in(45 downto 0);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1480)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1481)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,472)@13
leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1477)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1478)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1479)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,468)@9
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(61 downto 0);
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in(61 downto 0);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1469)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1470)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(61 downto 0);
--leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,469)@13
leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor(LOGICAL,1510)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q <= not (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a or ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b);
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena(REG,1511)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q = "1") THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd(LOGICAL,1512)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b <= en;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a and ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg(DELAY,1502)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 78, depth => 1 )
PORT MAP ( xin => multFracBits_uid199_rrx_uid34_fpSinCosXTest_b, xout => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem(DUALMEM,1503)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 78,
widthad_a => 1,
numwords_a => 2,
width_b => 78,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia
);
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq(77 downto 0);
--leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,476)@13
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in(5 downto 4);
--leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,477)@13
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,485)@13
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in(65 downto 0);
--leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest(CONSTANT,218)
leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q <= "000000000000";
--leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,486)@13
leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5(REG,560)@13
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,482)@13
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(69 downto 0);
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in(69 downto 0);
--leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,483)@13
leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4(REG,559)@13
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,479)@13
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(73 downto 0);
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in(73 downto 0);
--leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,480)@13
leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3(REG,558)@13
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,557)@13
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,487)@13
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,556)@13
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,488)@14
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,496)@14
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(74 downto 0);
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in(74 downto 0);
--ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1112)@14
ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 75, depth => 1 )
PORT MAP ( xin => LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest(CONSTANT,229)
leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q <= "000";
--leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,497)@15
leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,493)@14
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(75 downto 0);
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in(75 downto 0);
--ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1110)@14
ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,494)@15
leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,490)@14
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in(76 downto 0);
--ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1108)@14
ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 77, depth => 1 )
PORT MAP ( xin => LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,491)@15
leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,562)@14
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,498)@13
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a(DELAY,1184)@13
ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,561)@14
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,499)@15
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid203_rrx_uid34_fpSinCosXTest(BITSELECT,202)@15
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in <= leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in(76 downto 24);
--ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b(DELAY,826)@0
ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => xBranch_uid191_rrx_uid34_fpSinCosXTest_n, xout => ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid208_rrx_uid34_fpSinCosXTest(MUX,207)@15
finalFrac_uid208_rrx_uid34_fpSinCosXTest_s <= ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q;
finalFrac_uid208_rrx_uid34_fpSinCosXTest: PROCESS (finalFrac_uid208_rrx_uid34_fpSinCosXTest_s, en, fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b, fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE finalFrac_uid208_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid210_rrx_uid34_fpSinCosXTest(BITJOIN,209)@15
RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q <= GND_q & ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q & finalFrac_uid208_rrx_uid34_fpSinCosXTest_q;
--expXRR_uid38_fpSinCosXTest(BITSELECT,37)@15
expXRR_uid38_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(60 downto 0);
expXRR_uid38_fpSinCosXTest_b <= expXRR_uid38_fpSinCosXTest_in(60 downto 53);
--reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1(REG,565)@15
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= expXRR_uid38_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShiftM2_uid26_fpSinCosXTest(CONSTANT,25)
cstBiasMwShiftM2_uid26_fpSinCosXTest_q <= "01110000";
--cosXIsOneXRR_uid42_fpSinCosXTest(COMPARE,41)@16
cosXIsOneXRR_uid42_fpSinCosXTest_cin <= GND_q;
cosXIsOneXRR_uid42_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q) & '0';
cosXIsOneXRR_uid42_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & cosXIsOneXRR_uid42_fpSinCosXTest_cin(0);
cosXIsOneXRR_uid42_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_a) - SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_b));
cosXIsOneXRR_uid42_fpSinCosXTest_n(0) <= not cosXIsOneXRR_uid42_fpSinCosXTest_o(11);
--exp_uid9_fpSinCosXTest(BITSELECT,8)@0
exp_uid9_fpSinCosXTest_in <= a(30 downto 0);
exp_uid9_fpSinCosXTest_b <= exp_uid9_fpSinCosXTest_in(30 downto 23);
--sinXIsX_uid40_fpSinCosXTest(COMPARE,39)@0
sinXIsX_uid40_fpSinCosXTest_cin <= GND_q;
sinXIsX_uid40_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
sinXIsX_uid40_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpSinCosXTest_b) & sinXIsX_uid40_fpSinCosXTest_cin(0);
sinXIsX_uid40_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid40_fpSinCosXTest_a) - UNSIGNED(sinXIsX_uid40_fpSinCosXTest_b));
sinXIsX_uid40_fpSinCosXTest_n(0) <= not sinXIsX_uid40_fpSinCosXTest_o(10);
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a(DELAY,789)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXONe_uid148_fpSinCosXTest(LOGICAL,147)@16
cosXONe_uid148_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q;
cosXONe_uid148_fpSinCosXTest_b <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
cosXONe_uid148_fpSinCosXTest_q <= cosXONe_uid148_fpSinCosXTest_a or cosXONe_uid148_fpSinCosXTest_b;
--ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a(DELAY,791)@16
ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => cosXONe_uid148_fpSinCosXTest_q, xout => ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXONe_uid149_fpSinCosXTest(LOGICAL,148)@20
InvCosXONe_uid149_fpSinCosXTest_a <= ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q;
InvCosXONe_uid149_fpSinCosXTest_q <= not InvCosXONe_uid149_fpSinCosXTest_a;
--cstZwShiftP1_uid27_fpSinCosXTest(CONSTANT,26)
cstZwShiftP1_uid27_fpSinCosXTest_q <= "00000000000000";
--fracXRR_uid39_fpSinCosXTest(BITSELECT,38)@15
fracXRR_uid39_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(52 downto 0);
fracXRR_uid39_fpSinCosXTest_b <= fracXRR_uid39_fpSinCosXTest_in(52 downto 0);
--ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a(DELAY,668)@15
ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid39_fpSinCosXTest_b, xout => ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid43_uid43_fpSinCosXTest(BITJOIN,42)@16
oFracXRR_uid43_uid43_fpSinCosXTest_q <= VCC_q & ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q;
--extendedFracX_uid47_fpSinCosXTest(BITJOIN,46)@16
extendedFracX_uid47_fpSinCosXTest_q <= cstZwShiftP1_uid27_fpSinCosXTest_q & oFracXRR_uid43_uid43_fpSinCosXTest_q;
--X55dto0_uid220_fxpX_uid48_fpSinCosXTest(BITSELECT,219)@16
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(55 downto 0);
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in(55 downto 0);
--leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest(BITJOIN,220)@16
leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5(REG,571)@16
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X59dto0_uid217_fxpX_uid48_fpSinCosXTest(BITSELECT,216)@16
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(59 downto 0);
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in(59 downto 0);
--leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest(BITJOIN,217)@16
leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4(REG,570)@16
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X63dto0_uid214_fxpX_uid48_fpSinCosXTest(BITSELECT,213)@16
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(63 downto 0);
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in(63 downto 0);
--leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest(BITJOIN,214)@16
leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3(REG,569)@16
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2(REG,568)@16
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= extendedFracX_uid47_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--fxpXShiftValExt_uid45_fpSinCosXTest(SUB,44)@16
fxpXShiftValExt_uid45_fpSinCosXTest_a <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q);
fxpXShiftValExt_uid45_fpSinCosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q);
fxpXShiftValExt_uid45_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_a) - SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_b));
fxpXShiftValExt_uid45_fpSinCosXTest_q <= fxpXShiftValExt_uid45_fpSinCosXTest_o(9 downto 0);
--fxpXShiftVal_uid46_fpSinCosXTest(BITSELECT,45)@16
fxpXShiftVal_uid46_fpSinCosXTest_in <= fxpXShiftValExt_uid45_fpSinCosXTest_q(3 downto 0);
fxpXShiftVal_uid46_fpSinCosXTest_b <= fxpXShiftVal_uid46_fpSinCosXTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest(BITSELECT,221)@16
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b;
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1(REG,567)@16
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest(MUX,222)@17
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s, en, reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q, reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q, reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q, reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest(BITSELECT,230)@17
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(64 downto 0);
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b(DELAY,851)@17
ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest(BITJOIN,231)@18
leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest(BITSELECT,227)@17
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b(DELAY,849)@17
ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest(BITJOIN,228)@18
leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest(BITSELECT,224)@17
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b(DELAY,847)@17
ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest(BITJOIN,225)@18
leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2(REG,573)@17
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest(BITSELECT,232)@16
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a(DELAY,1195)@16
ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1(REG,572)@17
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest(MUX,233)@18
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s, en, reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q, leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q;
WHEN "10" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q;
WHEN "11" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid50_fpSinCosXTest(BITSELECT,49)@18
y_uid50_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
y_uid50_fpSinCosXTest_b <= y_uid50_fpSinCosXTest_in(66 downto 1);
--ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b(DELAY,680)@18
ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid50_fpSinCosXTest_b, xout => ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1(REG,575)@18
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= y_uid50_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid55_fpSinCosXTest(BITJOIN,54)@18
pad_one_uid55_fpSinCosXTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0(REG,574)@18
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= pad_one_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid55_fpSinCosXTest(SUB,55)@19
oneMinusY_uid55_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q);
oneMinusY_uid55_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q);
oneMinusY_uid55_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid55_fpSinCosXTest_a) - UNSIGNED(oneMinusY_uid55_fpSinCosXTest_b));
oneMinusY_uid55_fpSinCosXTest_q <= oneMinusY_uid55_fpSinCosXTest_o(67 downto 0);
--reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0(REG,576)@19
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= oneMinusY_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid57_fpSinCosXTest(COMPARE,56)@20
cmpYToOneMinusY_uid57_fpSinCosXTest_cin <= GND_q;
cmpYToOneMinusY_uid57_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q) & '0';
cmpYToOneMinusY_uid57_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q) & cmpYToOneMinusY_uid57_fpSinCosXTest_cin(0);
cmpYToOneMinusY_uid57_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_a) - UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_b));
cmpYToOneMinusY_uid57_fpSinCosXTest_c(0) <= cmpYToOneMinusY_uid57_fpSinCosXTest_o(70);
--InvCmpYToOneMinusY_uid61_fpSinCosXTest(LOGICAL,60)@20
InvCmpYToOneMinusY_uid61_fpSinCosXTest_a <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
InvCmpYToOneMinusY_uid61_fpSinCosXTest_q <= not InvCmpYToOneMinusY_uid61_fpSinCosXTest_a;
--intXParity_uid49_fpSinCosXTest(BITSELECT,48)@18
intXParity_uid49_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q;
intXParity_uid49_fpSinCosXTest_b <= intXParity_uid49_fpSinCosXTest_in(67 downto 67);
--ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b(DELAY,794)@18
ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid49_fpSinCosXTest_b, xout => ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid51_fpSinCosXTest(LOGICAL,50)@19
yIsZero_uid51_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsZero_uid51_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid51_fpSinCosXTest_q <= "1" when yIsZero_uid51_fpSinCosXTest_a = yIsZero_uid51_fpSinCosXTest_b else "0";
--ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a(DELAY,792)@19
ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid51_fpSinCosXTest_q, xout => ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid151_fpSinCosXTest(LOGICAL,150)@20
InvYIsZero_uid151_fpSinCosXTest_a <= ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q;
InvYIsZero_uid151_fpSinCosXTest_q <= not InvYIsZero_uid151_fpSinCosXTest_a;
--signRCond2_uid152_fpSinCosXTest(LOGICAL,151)@20
signRCond2_uid152_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_b <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
signRCond2_uid152_fpSinCosXTest_c <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_q_i <= signRCond2_uid152_fpSinCosXTest_a and signRCond2_uid152_fpSinCosXTest_b and signRCond2_uid152_fpSinCosXTest_c and signRCond2_uid152_fpSinCosXTest_d;
signRCond2_uid152_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond2_uid152_fpSinCosXTest_q, xin => signRCond2_uid152_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--InvIntXParity_uid155_fpSinCosXTest(LOGICAL,154)@20
InvIntXParity_uid155_fpSinCosXTest_a <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
InvIntXParity_uid155_fpSinCosXTest_q <= not InvIntXParity_uid155_fpSinCosXTest_a;
--signRCond1_uid157_fpSinCosXTest(LOGICAL,156)@20
signRCond1_uid157_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_b <= InvIntXParity_uid155_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_c <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
signRCond1_uid157_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_q_i <= signRCond1_uid157_fpSinCosXTest_a and signRCond1_uid157_fpSinCosXTest_b and signRCond1_uid157_fpSinCosXTest_c and signRCond1_uid157_fpSinCosXTest_d;
signRCond1_uid157_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond1_uid157_fpSinCosXTest_q, xin => signRCond1_uid157_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--signRCos_uid158_fpSinCosXTest(LOGICAL,157)@21
signRCos_uid158_fpSinCosXTest_a <= signRCond1_uid157_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_b <= signRCond2_uid152_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_q <= signRCos_uid158_fpSinCosXTest_a or signRCos_uid158_fpSinCosXTest_b;
--cstAllZWF_uid7_fpSinCosXTest(CONSTANT,6)
cstAllZWF_uid7_fpSinCosXTest_q <= "00000000000000000000000";
--frac_uid13_fpSinCosXTest(BITSELECT,12)@0
frac_uid13_fpSinCosXTest_in <= a(22 downto 0);
frac_uid13_fpSinCosXTest_b <= frac_uid13_fpSinCosXTest_in(22 downto 0);
--fracXIsZero_uid14_fpSinCosXTest(LOGICAL,13)@0
fracXIsZero_uid14_fpSinCosXTest_a <= frac_uid13_fpSinCosXTest_b;
fracXIsZero_uid14_fpSinCosXTest_b <= cstAllZWF_uid7_fpSinCosXTest_q;
fracXIsZero_uid14_fpSinCosXTest_q <= "1" when fracXIsZero_uid14_fpSinCosXTest_a = fracXIsZero_uid14_fpSinCosXTest_b else "0";
--cstAllOWE_uid6_fpSinCosXTest(CONSTANT,5)
cstAllOWE_uid6_fpSinCosXTest_q <= "11111111";
--expXIsMax_uid12_fpSinCosXTest(LOGICAL,11)@0
expXIsMax_uid12_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsMax_uid12_fpSinCosXTest_b <= cstAllOWE_uid6_fpSinCosXTest_q;
expXIsMax_uid12_fpSinCosXTest_q <= "1" when expXIsMax_uid12_fpSinCosXTest_a = expXIsMax_uid12_fpSinCosXTest_b else "0";
--exc_I_uid15_fpSinCosXTest(LOGICAL,14)@0
exc_I_uid15_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_b <= fracXIsZero_uid14_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_q <= exc_I_uid15_fpSinCosXTest_a and exc_I_uid15_fpSinCosXTest_b;
--ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a(DELAY,762)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid131_fpSinCosXTest(LOGICAL,130)@20
InvExc_I_uid131_fpSinCosXTest_a <= ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q;
InvExc_I_uid131_fpSinCosXTest_q <= not InvExc_I_uid131_fpSinCosXTest_a;
--reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2(REG,649)@20
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= InvExc_I_uid131_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpSinCosXTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpSinCosXTest_a <= fracXIsZero_uid14_fpSinCosXTest_q;
InvFracXIsZero_uid16_fpSinCosXTest_q <= not InvFracXIsZero_uid16_fpSinCosXTest_a;
--exc_N_uid17_fpSinCosXTest(LOGICAL,16)@0
exc_N_uid17_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_b <= InvFracXIsZero_uid16_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_q <= exc_N_uid17_fpSinCosXTest_a and exc_N_uid17_fpSinCosXTest_b;
--ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a(DELAY,763)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid132_fpSinCosXTest(LOGICAL,131)@20
InvExc_N_uid132_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q;
InvExc_N_uid132_fpSinCosXTest_q <= not InvExc_N_uid132_fpSinCosXTest_a;
--reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1(REG,648)@20
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= InvExc_N_uid132_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--signRCosFull_uid161_fpSinCosXTest(LOGICAL,160)@21
signRCosFull_uid161_fpSinCosXTest_a <= reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q;
signRCosFull_uid161_fpSinCosXTest_b <= reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q;
signRCosFull_uid161_fpSinCosXTest_c <= signRCos_uid158_fpSinCosXTest_q;
signRCosFull_uid161_fpSinCosXTest_q <= signRCosFull_uid161_fpSinCosXTest_a and signRCosFull_uid161_fpSinCosXTest_b and signRCosFull_uid161_fpSinCosXTest_c;
--ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c(DELAY,809)@21
ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRCosFull_uid161_fpSinCosXTest_q, xout => ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpSinCosXTest(CONSTANT,21)
cstBias_uid22_fpSinCosXTest_q <= "01111111";
--ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a(DELAY,681)@19
ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => oneMinusY_uid55_fpSinCosXTest_q, xout => ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zSinOMyBottom_uid58_fpSinCosXTest(BITSELECT,57)@20
zSinOMyBottom_uid58_fpSinCosXTest_in <= ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q(64 downto 0);
zSinOMyBottom_uid58_fpSinCosXTest_b <= zSinOMyBottom_uid58_fpSinCosXTest_in(64 downto 0);
--reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3(REG,579)@20
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= zSinOMyBottom_uid58_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--zSinYBottom_uid59_fpSinCosXTest(BITSELECT,58)@20
zSinYBottom_uid59_fpSinCosXTest_in <= ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q(64 downto 0);
zSinYBottom_uid59_fpSinCosXTest_b <= zSinYBottom_uid59_fpSinCosXTest_in(64 downto 0);
--reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2(REG,578)@20
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= zSinYBottom_uid59_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1(REG,614)@20
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--zCos_uid64_fpSinCosXTest(MUX,63)@21
zCos_uid64_fpSinCosXTest_s <= reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q;
zCos_uid64_fpSinCosXTest: PROCESS (zCos_uid64_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zCos_uid64_fpSinCosXTest_s IS
WHEN "0" => zCos_uid64_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zCos_uid64_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zCos_uid64_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid83_fpSinCosXTest(BITSELECT,82)@21
addr_uid83_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
addr_uid83_fpSinCosXTest_b <= addr_uid83_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0(REG,630)@21
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= addr_uid83_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid404_tableGencosPiZ_lutmem(DUALMEM,532)@22
memoryC2_uid404_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q;
memoryC2_uid404_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid404_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid404_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid404_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid404_tableGencosPiZ_lutmem_iq,
address_a => memoryC2_uid404_tableGencosPiZ_lutmem_aa,
data_a => memoryC2_uid404_tableGencosPiZ_lutmem_ia
);
memoryC2_uid404_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC2_uid404_tableGencosPiZ_lutmem_q <= memoryC2_uid404_tableGencosPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1(REG,632)@24
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= memoryC2_uid404_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPcosPiZ_uid87_fpSinCosXTest(BITSELECT,86)@21
zPcosPiZ_uid87_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(56 downto 0);
zPcosPiZ_uid87_fpSinCosXTest_b <= zPcosPiZ_uid87_fpSinCosXTest_in(56 downto 42);
--yT1_uid419_polyEvalcosPiZ(BITSELECT,418)@21
yT1_uid419_polyEvalcosPiZ_in <= zPcosPiZ_uid87_fpSinCosXTest_b;
yT1_uid419_polyEvalcosPiZ_b <= yT1_uid419_polyEvalcosPiZ_in(14 downto 2);
--reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0(REG,631)@21
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= yT1_uid419_polyEvalcosPiZ_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg(DELAY,1513)
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a(DELAY,1125)@22
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid508_pT1_uid420_polyEvalcosPiZ(MULT,507)@25
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a),14)) * SIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b);
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ(BITSELECT,508)@28
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q;
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in(25 downto 12);
--highBBits_uid422_polyEvalcosPiZ(BITSELECT,421)@28
highBBits_uid422_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b;
highBBits_uid422_polyEvalcosPiZ_b <= highBBits_uid422_polyEvalcosPiZ_in(13 downto 1);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a(DELAY,1256)@21
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0(REG,633)@24
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid402_tableGencosPiZ_lutmem(DUALMEM,531)@25
memoryC1_uid402_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q;
memoryC1_uid402_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid402_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid402_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid402_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid402_tableGencosPiZ_lutmem_iq,
address_a => memoryC1_uid402_tableGencosPiZ_lutmem_aa,
data_a => memoryC1_uid402_tableGencosPiZ_lutmem_ia
);
memoryC1_uid402_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC1_uid402_tableGencosPiZ_lutmem_q <= memoryC1_uid402_tableGencosPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0(REG,634)@27
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= memoryC1_uid402_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid423_polyEvalcosPiZ(ADD,422)@28
sumAHighB_uid423_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q(20)) & reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q);
sumAHighB_uid423_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid422_polyEvalcosPiZ_b(12)) & highBBits_uid422_polyEvalcosPiZ_b);
sumAHighB_uid423_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid423_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid423_polyEvalcosPiZ_b));
sumAHighB_uid423_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_o(21 downto 0);
--lowRangeB_uid421_polyEvalcosPiZ(BITSELECT,420)@28
lowRangeB_uid421_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b(0 downto 0);
lowRangeB_uid421_polyEvalcosPiZ_b <= lowRangeB_uid421_polyEvalcosPiZ_in(0 downto 0);
--s1_uid421_uid424_polyEvalcosPiZ(BITJOIN,423)@28
s1_uid421_uid424_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_q & lowRangeB_uid421_polyEvalcosPiZ_b;
--reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1(REG,636)@28
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= s1_uid421_uid424_polyEvalcosPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor(LOGICAL,1524)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q <= not (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a or ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b);
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top(CONSTANT,1520)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q <= "0100";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp(LOGICAL,1521)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q <= "1" when ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a = ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b else "0";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg(REG,1522)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena(REG,1525)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd(LOGICAL,1526)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a and ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b;
--reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0(REG,635)@21
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= zPcosPiZ_uid87_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg(DELAY,1514)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q, xout => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt(COUNTER,1516)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i = 3 THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i,3));
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg(REG,1517)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux(MUX,1518)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux: PROCESS (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem(DUALMEM,1515)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq,
address_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa,
data_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia
);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 <= areset;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq(14 downto 0);
--prodXY_uid511_pT2_uid426_polyEvalcosPiZ(MULT,510)@29
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a),16)) * SIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b);
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ(BITSELECT,511)@32
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q;
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in(37 downto 14);
--highBBits_uid428_polyEvalcosPiZ(BITSELECT,427)@32
highBBits_uid428_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b;
highBBits_uid428_polyEvalcosPiZ_b <= highBBits_uid428_polyEvalcosPiZ_in(23 downto 2);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor(LOGICAL,1577)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a or ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena(REG,1578)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd(LOGICAL,1579)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg(DELAY,1567)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem(DUALMEM,1568)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0(REG,637)@28
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid400_tableGencosPiZ_lutmem(DUALMEM,530)@29
memoryC0_uid400_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q;
memoryC0_uid400_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid400_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid400_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid400_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid400_tableGencosPiZ_lutmem_iq,
address_a => memoryC0_uid400_tableGencosPiZ_lutmem_aa,
data_a => memoryC0_uid400_tableGencosPiZ_lutmem_ia
);
memoryC0_uid400_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC0_uid400_tableGencosPiZ_lutmem_q <= memoryC0_uid400_tableGencosPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0(REG,638)@31
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= memoryC0_uid400_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid429_polyEvalcosPiZ(ADD,428)@32
sumAHighB_uid429_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q(29)) & reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q);
sumAHighB_uid429_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid428_polyEvalcosPiZ_b(21)) & highBBits_uid428_polyEvalcosPiZ_b);
sumAHighB_uid429_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid429_polyEvalcosPiZ_b));
sumAHighB_uid429_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_o(30 downto 0);
--lowRangeB_uid427_polyEvalcosPiZ(BITSELECT,426)@32
lowRangeB_uid427_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b(1 downto 0);
lowRangeB_uid427_polyEvalcosPiZ_b <= lowRangeB_uid427_polyEvalcosPiZ_in(1 downto 0);
--s2_uid427_uid430_polyEvalcosPiZ(BITJOIN,429)@32
s2_uid427_uid430_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_q & lowRangeB_uid427_polyEvalcosPiZ_b;
--polyEvalSigcosPiZ_uid89_fpSinCosXTest(BITSELECT,88)@32
polyEvalSigcosPiZ_uid89_fpSinCosXTest_in <= s2_uid427_uid430_polyEvalcosPiZ_q(30 downto 0);
polyEvalSigcosPiZ_uid89_fpSinCosXTest_b <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_in(30 downto 5);
--reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1(REG,640)@32
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor(LOGICAL,1590)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q <= not (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a or ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top(CONSTANT,1586)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q <= "010";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp(LOGICAL,1587)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q <= "1" when ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a = ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b else "0";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg(REG,1588)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena(REG,1591)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd(LOGICAL,1592)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a and ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b;
--LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest(BITSELECT,388)@27
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest(BITJOIN,389)@27
leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b & GND_q;
--cstZmwFRRPwSM1_uid52_fpSinCosXTest(CONSTANT,51)
cstZmwFRRPwSM1_uid52_fpSinCosXTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor(LOGICAL,1455)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a or ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena(REG,1456)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd(LOGICAL,1457)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest(BITSELECT,359)@21
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(32 downto 0);
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b <= X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg(DELAY,1447)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem(DUALMEM,1448)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest(BITJOIN,360)@25
leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor(LOGICAL,1466)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q <= not (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a or ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b);
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena(REG,1467)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q = "1") THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd(LOGICAL,1468)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b <= en;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a and ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg(DELAY,1458)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zCos_uid64_fpSinCosXTest_q, xout => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem(DUALMEM,1459)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia
);
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--zs_uid236_lzcZSin_uid66_fpSinCosXTest(CONSTANT,235)
zs_uid236_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid316_lzcZCos_uid69_fpSinCosXTest(BITSELECT,315)@21
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in(64 downto 1);
--vCount_uid317_lzcZCos_uid69_fpSinCosXTest(LOGICAL,316)@21
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g(DELAY,985)@22
ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid319_lzcZCos_uid69_fpSinCosXTest(BITSELECT,318)@21
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(0 downto 0);
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b(DELAY,943)@21
ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid239_lzcZSin_uid66_fpSinCosXTest(CONSTANT,238)
mO_uid239_lzcZSin_uid66_fpSinCosXTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid320_lzcZCos_uid69_fpSinCosXTest(BITJOIN,319)@22
cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c(DELAY,945)@21
ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid322_lzcZCos_uid69_fpSinCosXTest(MUX,321)@22
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid324_lzcZCos_uid69_fpSinCosXTest(BITSELECT,323)@22
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in(63 downto 32);
--vCount_uid325_lzcZCos_uid69_fpSinCosXTest(LOGICAL,324)@22
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f(DELAY,984)@23
ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid326_lzcZCos_uid69_fpSinCosXTest(BITSELECT,325)@22
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q(31 downto 0);
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d(DELAY,952)@22
ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c(DELAY,951)@22
ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid328_lzcZCos_uid69_fpSinCosXTest(MUX,327)@23
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid330_lzcZCos_uid69_fpSinCosXTest(BITSELECT,329)@23
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in(31 downto 16);
--vCount_uid331_lzcZCos_uid69_fpSinCosXTest(LOGICAL,330)@23
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b else "0";
--reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4(REG,622)@23
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e(DELAY,983)@24
ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid332_lzcZCos_uid69_fpSinCosXTest(BITSELECT,331)@23
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q(15 downto 0);
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in(15 downto 0);
--vStagei_uid334_lzcZCos_uid69_fpSinCosXTest(MUX,333)@23
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid336_lzcZCos_uid69_fpSinCosXTest(BITSELECT,335)@23
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1(REG,617)@23
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid337_lzcZCos_uid69_fpSinCosXTest(LOGICAL,336)@24
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b else "0";
--ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d(DELAY,982)@24
ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid338_lzcZCos_uid69_fpSinCosXTest(BITSELECT,337)@23
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q(7 downto 0);
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3(REG,619)@23
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid340_lzcZCos_uid69_fpSinCosXTest(MUX,339)@24
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q, reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid342_lzcZCos_uid69_fpSinCosXTest(BITSELECT,341)@24
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in(7 downto 4);
--vCount_uid343_lzcZCos_uid69_fpSinCosXTest(LOGICAL,342)@24
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid344_lzcZCos_uid69_fpSinCosXTest(BITSELECT,343)@24
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q(3 downto 0);
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3(REG,621)@24
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2(REG,620)@24
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid346_lzcZCos_uid69_fpSinCosXTest(MUX,345)@25
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q, reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid348_lzcZCos_uid69_fpSinCosXTest(BITSELECT,347)@25
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in(3 downto 2);
--vCount_uid349_lzcZCos_uid69_fpSinCosXTest(LOGICAL,348)@25
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b else "0";
--vStage_uid350_lzcZCos_uid69_fpSinCosXTest(BITSELECT,349)@25
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q(1 downto 0);
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in(1 downto 0);
--vStagei_uid352_lzcZCos_uid69_fpSinCosXTest(MUX,351)@25
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid354_lzcZCos_uid69_fpSinCosXTest(BITSELECT,353)@25
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in(1 downto 1);
--vCount_uid355_lzcZCos_uid69_fpSinCosXTest(LOGICAL,354)@25
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b <= GND_q;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b else "0";
--r_uid356_lzcZCos_uid69_fpSinCosXTest(BITJOIN,355)@25
r_uid356_lzcZCos_uid69_fpSinCosXTest_q <= ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q & ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q & ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q & ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q & vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest(BITSELECT,363)@25
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest(MUX,364)@25
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b;
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s, en, ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest(BITSELECT,372)@25
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest(CONSTANT,292)
leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest(BITJOIN,373)@25
leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5(REG,627)@25
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest(BITSELECT,369)@25
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest(BITJOIN,370)@25
leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4(REG,626)@25
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest(BITSELECT,366)@25
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest(BITJOIN,367)@25
leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3(REG,625)@25
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2(REG,624)@25
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest(BITSELECT,374)@25
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1(REG,623)@25
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest(MUX,375)@26
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q;
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest(BITSELECT,383)@26
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1009)@26
ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest(CONSTANT,303)
leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q <= "000000";
--leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest(BITJOIN,384)@27
leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest(BITSELECT,380)@26
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1007)@26
ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest(BITJOIN,381)@27
leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest(BITSELECT,377)@26
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1005)@26
ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest(BITJOIN,378)@27
leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2(REG,629)@26
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest(BITSELECT,385)@25
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1(REG,628)@25
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1011)@26
ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest(MUX,386)@27
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s <= ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest(BITSELECT,390)@25
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1019)@25
ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest(MUX,391)@27
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s, en, leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pCos_uid77_fpSinCosXTest(BITSELECT,76)@27
pCos_uid77_fpSinCosXTest_in <= leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q;
pCos_uid77_fpSinCosXTest_b <= pCos_uid77_fpSinCosXTest_in(64 downto 39);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg(DELAY,1580)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => pCos_uid77_fpSinCosXTest_b, xout => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt(COUNTER,1582)
-- every=1, low=0, high=2, step=1, init=1
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i = 1 THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i,2));
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg(REG,1583)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux(MUX,1584)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux: PROCESS (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
WHEN "1" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem(DUALMEM,1581)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia
);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq(25 downto 0);
--reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0(REG,639)@32
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mulCos_uid105_fpSinCosXTest(MULT,104)@33
mulCos_uid105_fpSinCosXTest_pr <= UNSIGNED(mulCos_uid105_fpSinCosXTest_a) * UNSIGNED(mulCos_uid105_fpSinCosXTest_b);
mulCos_uid105_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_a <= (others => '0');
mulCos_uid105_fpSinCosXTest_b <= (others => '0');
mulCos_uid105_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_a <= reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q;
mulCos_uid105_fpSinCosXTest_b <= reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q;
mulCos_uid105_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulCos_uid105_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulCos_uid105_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_q <= mulCos_uid105_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitCos_uid106_fpSinCosXTest(BITSELECT,105)@36
normBitCos_uid106_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q;
normBitCos_uid106_fpSinCosXTest_b <= normBitCos_uid106_fpSinCosXTest_in(51 downto 51);
--cosRndOp_uid112_uid113_fpSinCosXTest(BITJOIN,112)@36
cosRndOp_uid112_uid113_fpSinCosXTest_q <= normBitCos_uid106_fpSinCosXTest_b & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor(LOGICAL,1296)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q <= not (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a or ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b);
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top(CONSTANT,1292)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q <= "0110";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp(LOGICAL,1293)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q <= "1" when ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a = ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b else "0";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg(REG,1294)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena(REG,1297)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd(LOGICAL,1298)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a and ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b;
--reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1(REG,641)@25
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg(DELAY,1286)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q, xout => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt(COUNTER,1288)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg(REG,1289)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux(MUX,1290)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux: PROCESS (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem(DUALMEM,1287)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq(6 downto 0);
--expHardCase_uid78_fpSinCosXTest(SUB,77)@35
expHardCase_uid78_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expHardCase_uid78_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q);
expHardCase_uid78_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid78_fpSinCosXTest_a) - UNSIGNED(expHardCase_uid78_fpSinCosXTest_b));
expHardCase_uid78_fpSinCosXTest_q <= expHardCase_uid78_fpSinCosXTest_o(8 downto 0);
--expPCos_uid79_fpSinCosXTest(BITSELECT,78)@35
expPCos_uid79_fpSinCosXTest_in <= expHardCase_uid78_fpSinCosXTest_q(7 downto 0);
expPCos_uid79_fpSinCosXTest_b <= expPCos_uid79_fpSinCosXTest_in(7 downto 0);
--reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1(REG,642)@35
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= expPCos_uid79_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCosPreRndHigh_uid108_fpSinCosXTest(BITSELECT,107)@36
fracRCosPreRndHigh_uid108_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(50 downto 0);
fracRCosPreRndHigh_uid108_fpSinCosXTest_b <= fracRCosPreRndHigh_uid108_fpSinCosXTest_in(50 downto 27);
--fracRCosPreRndLow_uid109_fpSinCosXTest(BITSELECT,108)@36
fracRCosPreRndLow_uid109_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(49 downto 0);
fracRCosPreRndLow_uid109_fpSinCosXTest_b <= fracRCosPreRndLow_uid109_fpSinCosXTest_in(49 downto 26);
--fracRCosPreRnd_uid110_fpSinCosXTest(MUX,109)@36
fracRCosPreRnd_uid110_fpSinCosXTest_s <= normBitCos_uid106_fpSinCosXTest_b;
fracRCosPreRnd_uid110_fpSinCosXTest: PROCESS (fracRCosPreRnd_uid110_fpSinCosXTest_s, en, fracRCosPreRndLow_uid109_fpSinCosXTest_b, fracRCosPreRndHigh_uid108_fpSinCosXTest_b)
BEGIN
CASE fracRCosPreRnd_uid110_fpSinCosXTest_s IS
WHEN "0" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndLow_uid109_fpSinCosXTest_b;
WHEN "1" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndHigh_uid108_fpSinCosXTest_b;
WHEN OTHERS => fracRCosPreRnd_uid110_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRCosPreRnd_uid111_uid111_fpSinCosXTest(BITJOIN,110)@36
expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q <= reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q & fracRCosPreRnd_uid110_fpSinCosXTest_q;
--expFracRCos_uid114_fpSinCosXTest(ADD,113)@36
expFracRCos_uid114_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000" & cosRndOp_uid112_uid113_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRCos_uid114_fpSinCosXTest_a) + UNSIGNED(expFracRCos_uid114_fpSinCosXTest_b));
expFracRCos_uid114_fpSinCosXTest_q <= expFracRCos_uid114_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid116_fpSinCosXTest(BITSELECT,115)@36
expRCompSin_uid116_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid116_fpSinCosXTest_b <= expRCompSin_uid116_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2(REG,646)@36
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= expRCompSin_uid116_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor(LOGICAL,1385)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q <= not (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a or ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top(CONSTANT,1305)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q <= "01101";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp(LOGICAL,1306)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a = ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg(REG,1307)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena(REG,1386)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q = "1") THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd(LOGICAL,1387)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b <= en;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a and ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b;
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a(DELAY,745)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c(DELAY,783)@16
ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOneXRR_uid42_fpSinCosXTest_n, xout => ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOneXRR_uid136_fpSinCosXTest(LOGICAL,135)@16
InvCosXIsOneXRR_uid136_fpSinCosXTest_a <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
InvCosXIsOneXRR_uid136_fpSinCosXTest_q <= not InvCosXIsOneXRR_uid136_fpSinCosXTest_a;
--ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c(DELAY,773)@16
ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => InvCosXIsOneXRR_uid136_fpSinCosXTest_q, xout => ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a(DELAY,755)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid127_fpSinCosXTest(LOGICAL,126)@18
InvSinXIsX_uid127_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q;
InvSinXIsX_uid127_fpSinCosXTest_q <= not InvSinXIsX_uid127_fpSinCosXTest_a;
--ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b(DELAY,772)@18
ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSinXIsX_uid127_fpSinCosXTest_q, xout => ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--half_uid53_fpSinCosXTest(BITJOIN,52)@19
half_uid53_fpSinCosXTest_q <= VCC_q & cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
--yIsHalf_uid54_fpSinCosXTest(LOGICAL,53)@19
yIsHalf_uid54_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsHalf_uid54_fpSinCosXTest_b <= half_uid53_fpSinCosXTest_q;
yIsHalf_uid54_fpSinCosXTest_q <= "1" when yIsHalf_uid54_fpSinCosXTest_a = yIsHalf_uid54_fpSinCosXTest_b else "0";
--yHalfCosXNotOne_uid138_fpSinCosXTest(LOGICAL,137)@19
yHalfCosXNotOne_uid138_fpSinCosXTest_a <= yIsHalf_uid54_fpSinCosXTest_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_b <= ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_c <= ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_a and yHalfCosXNotOne_uid138_fpSinCosXTest_b and yHalfCosXNotOne_uid138_fpSinCosXTest_c;
--ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b(DELAY,744)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a(DELAY,743)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid117_fpSinCosXTest(LOGICAL,116)@19
excRNaN_uid117_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q;
excRNaN_uid117_fpSinCosXTest_b <= ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q;
excRNaN_uid117_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_a or excRNaN_uid117_fpSinCosXTest_b;
--join_uid143_fpSinCosXTest(BITJOIN,142)@19
join_uid143_fpSinCosXTest_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q & yHalfCosXNotOne_uid138_fpSinCosXTest_q & excRNaN_uid117_fpSinCosXTest_q;
--expSelBitsCos_uid144_fpSinCosXTest(BITJOIN,143)@19
expSelBitsCos_uid144_fpSinCosXTest_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q & join_uid143_fpSinCosXTest_q;
--reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0(REG,645)@19
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= expSelBitsCos_uid144_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSelectorCos_uid145_fpSinCosXTest(LOOKUP,144)@20
expSelectorCos_uid145_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelectorCos_uid145_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q) IS
WHEN "0000" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "0101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1000" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
expSelectorCos_uid145_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg(DELAY,1375)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelectorCos_uid145_fpSinCosXTest_q, xout => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt(COUNTER,1301)
-- every=1, low=0, high=13, step=1, init=1
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i = 12 THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i - 13;
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg(REG,1302)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux(MUX,1303)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem(DUALMEM,1376)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia
);
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--expRPostExcCos_uid147_fpSinCosXTest(MUX,146)@37
expRPostExcCos_uid147_fpSinCosXTest_s <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q;
expRPostExcCos_uid147_fpSinCosXTest: PROCESS (expRPostExcCos_uid147_fpSinCosXTest_s, en, reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q, cstBias_uid22_fpSinCosXTest_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcCos_uid147_fpSinCosXTest_s IS
WHEN "00" => expRPostExcCos_uid147_fpSinCosXTest_q <= reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstBias_uid22_fpSinCosXTest_q;
WHEN "10" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcCos_uid147_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid32_fpSinCosXTest(CONSTANT,31)
cstNaNwF_uid32_fpSinCosXTest_q <= "00000000000000000000001";
--fracRCompCos_uid115_fpSinCosXTest(BITSELECT,114)@36
fracRCompCos_uid115_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(23 downto 0);
fracRCompCos_uid115_fpSinCosXTest_b <= fracRCompCos_uid115_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2(REG,644)@36
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= fracRCompCos_uid115_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor(LOGICAL,1372)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q <= not (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a or ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b);
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena(REG,1373)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd(LOGICAL,1374)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a and ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b;
--reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1(REG,613)@19
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= excRNaN_uid117_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3(REG,612)@19
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q;
END IF;
END IF;
END PROCESS;
--reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2(REG,611)@19
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1(REG,610)@19
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--rZOrOne_uid140_fpSinCosXTest(LOGICAL,139)@20
rZOrOne_uid140_fpSinCosXTest_a <= reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q;
rZOrOne_uid140_fpSinCosXTest_b <= reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q;
rZOrOne_uid140_fpSinCosXTest_c <= reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q;
rZOrOne_uid140_fpSinCosXTest_q <= rZOrOne_uid140_fpSinCosXTest_a or rZOrOne_uid140_fpSinCosXTest_b or rZOrOne_uid140_fpSinCosXTest_c;
--join_uid141_fpSinCosXTest(BITJOIN,140)@20
join_uid141_fpSinCosXTest_q <= reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q & rZOrOne_uid140_fpSinCosXTest_q;
--reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1(REG,643)@20
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= join_uid141_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg(DELAY,1362)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q, xout => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem(DUALMEM,1363)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--fracRPostExcCos_uid142_fpSinCosXTest(MUX,141)@37
fracRPostExcCos_uid142_fpSinCosXTest_s <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q;
fracRPostExcCos_uid142_fpSinCosXTest: PROCESS (fracRPostExcCos_uid142_fpSinCosXTest_s, en, reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcCos_uid142_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcCos_uid142_fpSinCosXTest_q <= reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "10" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN "11" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcCos_uid142_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpCos_uid162_fpSinCosXTest(BITJOIN,161)@37
fpCos_uid162_fpSinCosXTest_q <= ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q & expRPostExcCos_uid147_fpSinCosXTest_q & fracRPostExcCos_uid142_fpSinCosXTest_q;
--cstBiasMwShiftM2_uid25_fpSinCosXTest(CONSTANT,24)
cstBiasMwShiftM2_uid25_fpSinCosXTest_q <= "01110001";
--sinXIsXRR_uid41_fpSinCosXTest(COMPARE,40)@16
sinXIsXRR_uid41_fpSinCosXTest_cin <= GND_q;
sinXIsXRR_uid41_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid25_fpSinCosXTest_q) & '0';
sinXIsXRR_uid41_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & sinXIsXRR_uid41_fpSinCosXTest_cin(0);
sinXIsXRR_uid41_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid41_fpSinCosXTest_a) - SIGNED(sinXIsXRR_uid41_fpSinCosXTest_b));
sinXIsXRR_uid41_fpSinCosXTest_n(0) <= not sinXIsXRR_uid41_fpSinCosXTest_o(11);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a(DELAY,756)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsXRR_uid128_fpSinCosXTest(LOGICAL,127)@18
InvSinXIsXRR_uid128_fpSinCosXTest_a <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q;
InvSinXIsXRR_uid128_fpSinCosXTest_q <= not InvSinXIsXRR_uid128_fpSinCosXTest_a;
--signComp_uid129_fpSinCosXTest(LOGICAL,128)@18
signComp_uid129_fpSinCosXTest_a <= InvSinXIsXRR_uid128_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_b <= InvSinXIsX_uid127_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_c <= intXParity_uid49_fpSinCosXTest_b;
signComp_uid129_fpSinCosXTest_q <= signComp_uid129_fpSinCosXTest_a and signComp_uid129_fpSinCosXTest_b and signComp_uid129_fpSinCosXTest_c;
--signX_uid37_fpSinCosXTest(BITSELECT,36)@0
signX_uid37_fpSinCosXTest_in <= a;
signX_uid37_fpSinCosXTest_b <= signX_uid37_fpSinCosXTest_in(31 downto 31);
--ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a(DELAY,760)@0
ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => signX_uid37_fpSinCosXTest_b, xout => ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid130_fpSinCosXTest(LOGICAL,129)@18
signR_uid130_fpSinCosXTest_a <= ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q;
signR_uid130_fpSinCosXTest_b <= signComp_uid129_fpSinCosXTest_q;
signR_uid130_fpSinCosXTest_q <= signR_uid130_fpSinCosXTest_a xor signR_uid130_fpSinCosXTest_b;
--ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c(DELAY,766)@18
ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signR_uid130_fpSinCosXTest_q, xout => ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--signRSinFull_uid133_fpSinCosXTest(LOGICAL,132)@20
signRSinFull_uid133_fpSinCosXTest_a <= InvExc_N_uid132_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_b <= InvExc_I_uid131_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_c <= ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q;
signRSinFull_uid133_fpSinCosXTest_q_i <= signRSinFull_uid133_fpSinCosXTest_a and signRSinFull_uid133_fpSinCosXTest_b and signRSinFull_uid133_fpSinCosXTest_c;
signRSinFull_uid133_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRSinFull_uid133_fpSinCosXTest_q, xin => signRSinFull_uid133_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c(DELAY,769)@21
ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRSinFull_uid133_fpSinCosXTest_q, xout => ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor(LOGICAL,1359)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q <= not (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a or ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top(CONSTANT,1342)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q <= "0100010";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp(LOGICAL,1343)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q <= "1" when ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a = ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b else "0";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg(REG,1344)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena(REG,1360)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q = "1") THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd(LOGICAL,1361)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b <= en;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a and ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg(DELAY,1349)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpSinCosXTest_b, xout => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=34, step=1, init=1
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i = 33 THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i - 34;
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg(REG,1339)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux(MUX,1340)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem(DUALMEM,1350)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 35,
width_b => 8,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia
);
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a(DELAY,1228)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1(REG,605)@35
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor(LOGICAL,1309)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a or ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena(REG,1310)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd(LOGICAL,1311)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid90_fpSinCosXTest(BITSELECT,89)@16
oFracXRRSmallXRR_uid90_fpSinCosXTest_in <= oFracXRR_uid43_uid43_fpSinCosXTest_q;
oFracXRRSmallXRR_uid90_fpSinCosXTest_b <= oFracXRRSmallXRR_uid90_fpSinCosXTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg(DELAY,1299)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid90_fpSinCosXTest_b, xout => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem(DUALMEM,1300)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 14,
width_b => 26,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq(25 downto 0);
--reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1(REG,577)@20
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
END IF;
END IF;
END PROCESS;
--zSin_uid60_fpSinCosXTest(MUX,59)@21
zSin_uid60_fpSinCosXTest_s <= reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q;
zSin_uid60_fpSinCosXTest: PROCESS (zSin_uid60_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zSin_uid60_fpSinCosXTest_s IS
WHEN "0" => zSin_uid60_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zSin_uid60_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zSin_uid60_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid81_fpSinCosXTest(BITSELECT,80)@21
addr_uid81_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
addr_uid81_fpSinCosXTest_b <= addr_uid81_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0(REG,595)@21
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= addr_uid81_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid398_tableGensinPiZ_lutmem(DUALMEM,529)@22
memoryC2_uid398_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q;
memoryC2_uid398_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid398_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid398_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid398_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid398_tableGensinPiZ_lutmem_iq,
address_a => memoryC2_uid398_tableGensinPiZ_lutmem_aa,
data_a => memoryC2_uid398_tableGensinPiZ_lutmem_ia
);
memoryC2_uid398_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC2_uid398_tableGensinPiZ_lutmem_q <= memoryC2_uid398_tableGensinPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1(REG,597)@24
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= memoryC2_uid398_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPsinPiZ_uid84_fpSinCosXTest(BITSELECT,83)@21
zPsinPiZ_uid84_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(56 downto 0);
zPsinPiZ_uid84_fpSinCosXTest_b <= zPsinPiZ_uid84_fpSinCosXTest_in(56 downto 42);
--yT1_uid406_polyEvalsinPiZ(BITSELECT,405)@21
yT1_uid406_polyEvalsinPiZ_in <= zPsinPiZ_uid84_fpSinCosXTest_b;
yT1_uid406_polyEvalsinPiZ_b <= yT1_uid406_polyEvalsinPiZ_in(14 downto 2);
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg(DELAY,1540)
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid406_polyEvalsinPiZ_b, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a(DELAY,1219)@21
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0(REG,596)@24
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid502_pT1_uid407_polyEvalsinPiZ(MULT,501)@25
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a),14)) * SIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b);
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ(BITSELECT,502)@28
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q;
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in(25 downto 12);
--highBBits_uid409_polyEvalsinPiZ(BITSELECT,408)@28
highBBits_uid409_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b;
highBBits_uid409_polyEvalsinPiZ_b <= highBBits_uid409_polyEvalsinPiZ_in(13 downto 1);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a(DELAY,1221)@21
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0(REG,598)@24
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid396_tableGensinPiZ_lutmem(DUALMEM,528)@25
memoryC1_uid396_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q;
memoryC1_uid396_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid396_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid396_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid396_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid396_tableGensinPiZ_lutmem_iq,
address_a => memoryC1_uid396_tableGensinPiZ_lutmem_aa,
data_a => memoryC1_uid396_tableGensinPiZ_lutmem_ia
);
memoryC1_uid396_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC1_uid396_tableGensinPiZ_lutmem_q <= memoryC1_uid396_tableGensinPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0(REG,599)@27
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= memoryC1_uid396_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid410_polyEvalsinPiZ(ADD,409)@28
sumAHighB_uid410_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q(20)) & reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q);
sumAHighB_uid410_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid409_polyEvalsinPiZ_b(12)) & highBBits_uid409_polyEvalsinPiZ_b);
sumAHighB_uid410_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid410_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid410_polyEvalsinPiZ_b));
sumAHighB_uid410_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_o(21 downto 0);
--lowRangeB_uid408_polyEvalsinPiZ(BITSELECT,407)@28
lowRangeB_uid408_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b(0 downto 0);
lowRangeB_uid408_polyEvalsinPiZ_b <= lowRangeB_uid408_polyEvalsinPiZ_in(0 downto 0);
--s1_uid408_uid411_polyEvalsinPiZ(BITJOIN,410)@28
s1_uid408_uid411_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_q & lowRangeB_uid408_polyEvalsinPiZ_b;
--reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1(REG,601)@28
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= s1_uid408_uid411_polyEvalsinPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor(LOGICAL,1551)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q <= not (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a or ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b);
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena(REG,1552)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q = "1") THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd(LOGICAL,1553)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b <= en;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a and ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg(DELAY,1541)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPsinPiZ_uid84_fpSinCosXTest_b, xout => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem(DUALMEM,1542)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq,
address_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa,
data_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia
);
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 <= areset;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq(14 downto 0);
--reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0(REG,600)@28
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid505_pT2_uid413_polyEvalsinPiZ(MULT,504)@29
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a),16)) * SIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b);
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ(BITSELECT,505)@32
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q;
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in(37 downto 14);
--highBBits_uid415_polyEvalsinPiZ(BITSELECT,414)@32
highBBits_uid415_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b;
highBBits_uid415_polyEvalsinPiZ_b <= highBBits_uid415_polyEvalsinPiZ_in(23 downto 2);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor(LOGICAL,1564)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a or ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena(REG,1565)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd(LOGICAL,1566)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg(DELAY,1554)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem(DUALMEM,1555)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0(REG,602)@28
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid394_tableGensinPiZ_lutmem(DUALMEM,527)@29
memoryC0_uid394_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q;
memoryC0_uid394_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid394_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid394_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid394_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid394_tableGensinPiZ_lutmem_iq,
address_a => memoryC0_uid394_tableGensinPiZ_lutmem_aa,
data_a => memoryC0_uid394_tableGensinPiZ_lutmem_ia
);
memoryC0_uid394_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC0_uid394_tableGensinPiZ_lutmem_q <= memoryC0_uid394_tableGensinPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0(REG,603)@31
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= memoryC0_uid394_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid416_polyEvalsinPiZ(ADD,415)@32
sumAHighB_uid416_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q(29)) & reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q);
sumAHighB_uid416_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid415_polyEvalsinPiZ_b(21)) & highBBits_uid415_polyEvalsinPiZ_b);
sumAHighB_uid416_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid416_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid416_polyEvalsinPiZ_b));
sumAHighB_uid416_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_o(30 downto 0);
--lowRangeB_uid414_polyEvalsinPiZ(BITSELECT,413)@32
lowRangeB_uid414_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b(1 downto 0);
lowRangeB_uid414_polyEvalsinPiZ_b <= lowRangeB_uid414_polyEvalsinPiZ_in(1 downto 0);
--s2_uid414_uid417_polyEvalsinPiZ(BITJOIN,416)@32
s2_uid414_uid417_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_q & lowRangeB_uid414_polyEvalsinPiZ_b;
--polyEvalSigsinPiZ_uid86_fpSinCosXTest(BITSELECT,85)@32
polyEvalSigsinPiZ_uid86_fpSinCosXTest_in <= s2_uid414_uid417_polyEvalsinPiZ_q(30 downto 0);
polyEvalSigsinPiZ_uid86_fpSinCosXTest_b <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_in(30 downto 5);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b(DELAY,708)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSinOp2_uid91_fpSinCosXTest(MUX,90)@32
multSinOp2_uid91_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q;
multSinOp2_uid91_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSinOp2_uid91_fpSinCosXTest_s IS
WHEN "0" => multSinOp2_uid91_fpSinCosXTest_q <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_b;
WHEN "1" => multSinOp2_uid91_fpSinCosXTest_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor(LOGICAL,1320)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q <= not (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a or ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena(REG,1321)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd(LOGICAL,1322)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a and ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b;
--cPi_uid71_fpSinCosXTest(CONSTANT,70)
cPi_uid71_fpSinCosXTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest(BITSELECT,309)@27
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest(BITJOIN,310)@27
leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b & GND_q;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor(LOGICAL,1433)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a or ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena(REG,1434)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd(LOGICAL,1435)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest(BITSELECT,280)@21
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(32 downto 0);
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b <= X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg(DELAY,1425)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem(DUALMEM,1426)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest(BITJOIN,281)@25
leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor(LOGICAL,1444)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q <= not (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a or ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b);
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena(REG,1445)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q = "1") THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd(LOGICAL,1446)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b <= en;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a and ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg(DELAY,1436)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zSin_uid60_fpSinCosXTest_q, xout => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem(DUALMEM,1437)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia
);
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--rVStage_uid237_lzcZSin_uid66_fpSinCosXTest(BITSELECT,236)@21
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in(64 downto 1);
--vCount_uid238_lzcZSin_uid66_fpSinCosXTest(LOGICAL,237)@21
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g(DELAY,903)@22
ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid240_lzcZSin_uid66_fpSinCosXTest(BITSELECT,239)@21
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(0 downto 0);
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b(DELAY,861)@21
ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid241_lzcZSin_uid66_fpSinCosXTest(BITJOIN,240)@22
cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c(DELAY,863)@21
ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid243_lzcZSin_uid66_fpSinCosXTest(MUX,242)@22
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid245_lzcZSin_uid66_fpSinCosXTest(BITSELECT,244)@22
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in(63 downto 32);
--vCount_uid246_lzcZSin_uid66_fpSinCosXTest(LOGICAL,245)@22
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f(DELAY,902)@23
ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid247_lzcZSin_uid66_fpSinCosXTest(BITSELECT,246)@22
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q(31 downto 0);
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d(DELAY,870)@22
ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c(DELAY,869)@22
ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid249_lzcZSin_uid66_fpSinCosXTest(MUX,248)@23
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid251_lzcZSin_uid66_fpSinCosXTest(BITSELECT,250)@23
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in(31 downto 16);
--vCount_uid252_lzcZSin_uid66_fpSinCosXTest(LOGICAL,251)@23
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b else "0";
--reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4(REG,585)@23
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e(DELAY,901)@24
ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid253_lzcZSin_uid66_fpSinCosXTest(BITSELECT,252)@23
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q(15 downto 0);
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in(15 downto 0);
--vStagei_uid255_lzcZSin_uid66_fpSinCosXTest(MUX,254)@23
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid257_lzcZSin_uid66_fpSinCosXTest(BITSELECT,256)@23
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1(REG,580)@23
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid258_lzcZSin_uid66_fpSinCosXTest(LOGICAL,257)@24
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b else "0";
--ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d(DELAY,900)@24
ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid259_lzcZSin_uid66_fpSinCosXTest(BITSELECT,258)@23
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q(7 downto 0);
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3(REG,582)@23
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid261_lzcZSin_uid66_fpSinCosXTest(MUX,260)@24
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q, reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid263_lzcZSin_uid66_fpSinCosXTest(BITSELECT,262)@24
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in(7 downto 4);
--vCount_uid264_lzcZSin_uid66_fpSinCosXTest(LOGICAL,263)@24
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid265_lzcZSin_uid66_fpSinCosXTest(BITSELECT,264)@24
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q(3 downto 0);
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3(REG,584)@24
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2(REG,583)@24
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid267_lzcZSin_uid66_fpSinCosXTest(MUX,266)@25
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q, reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid269_lzcZSin_uid66_fpSinCosXTest(BITSELECT,268)@25
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in(3 downto 2);
--vCount_uid270_lzcZSin_uid66_fpSinCosXTest(LOGICAL,269)@25
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b else "0";
--vStage_uid271_lzcZSin_uid66_fpSinCosXTest(BITSELECT,270)@25
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q(1 downto 0);
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in(1 downto 0);
--vStagei_uid273_lzcZSin_uid66_fpSinCosXTest(MUX,272)@25
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid275_lzcZSin_uid66_fpSinCosXTest(BITSELECT,274)@25
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in(1 downto 1);
--vCount_uid276_lzcZSin_uid66_fpSinCosXTest(LOGICAL,275)@25
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b <= GND_q;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b else "0";
--r_uid277_lzcZSin_uid66_fpSinCosXTest(BITJOIN,276)@25
r_uid277_lzcZSin_uid66_fpSinCosXTest_q <= ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q & ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q & ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q & ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q & vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest(BITSELECT,284)@25
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest(MUX,285)@25
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b;
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s, en, ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest(BITSELECT,293)@25
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest(BITJOIN,294)@25
leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5(REG,590)@25
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest(BITSELECT,290)@25
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest(BITJOIN,291)@25
leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4(REG,589)@25
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest(BITSELECT,287)@25
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest(BITJOIN,288)@25
leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3(REG,588)@25
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2(REG,587)@25
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest(BITSELECT,295)@25
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1(REG,586)@25
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest(MUX,296)@26
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest(BITSELECT,304)@26
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b(DELAY,927)@26
ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest(BITJOIN,305)@27
leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest(BITSELECT,301)@26
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b(DELAY,925)@26
ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest(BITJOIN,302)@27
leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest(BITSELECT,298)@26
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b(DELAY,923)@26
ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest(BITJOIN,299)@27
leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2(REG,592)@26
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest(BITSELECT,306)@25
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a(DELAY,1214)@25
ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1(REG,591)@26
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest(MUX,307)@27
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest(BITSELECT,311)@25
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b(DELAY,937)@25
ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest(MUX,312)@27
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q;
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s, en, leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid72_fpSinCosXTest(BITSELECT,71)@27
pHigh_uid72_fpSinCosXTest_in <= leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q;
pHigh_uid72_fpSinCosXTest_b <= pHigh_uid72_fpSinCosXTest_in(64 downto 39);
--reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2(REG,594)@27
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= pHigh_uid72_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a(DELAY,1216)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1(REG,593)@27
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--p_uid73_fpSinCosXTest(MUX,72)@28
p_uid73_fpSinCosXTest_s <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q;
p_uid73_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid73_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid73_fpSinCosXTest_s IS
WHEN "0" => p_uid73_fpSinCosXTest_q <= reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q;
WHEN "1" => p_uid73_fpSinCosXTest_q <= cPi_uid71_fpSinCosXTest_q;
WHEN OTHERS => p_uid73_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg(DELAY,1312)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid73_fpSinCosXTest_q, xout => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem(DUALMEM,1313)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia
);
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq(25 downto 0);
--mulSin_uid92_fpSinCosXTest(MULT,91)@33
mulSin_uid92_fpSinCosXTest_pr <= UNSIGNED(mulSin_uid92_fpSinCosXTest_a) * UNSIGNED(mulSin_uid92_fpSinCosXTest_b);
mulSin_uid92_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_a <= (others => '0');
mulSin_uid92_fpSinCosXTest_b <= (others => '0');
mulSin_uid92_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q;
mulSin_uid92_fpSinCosXTest_b <= multSinOp2_uid91_fpSinCosXTest_q;
mulSin_uid92_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulSin_uid92_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulSin_uid92_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_q <= mulSin_uid92_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitSin_uid93_fpSinCosXTest(BITSELECT,92)@36
normBitSin_uid93_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q;
normBitSin_uid93_fpSinCosXTest_b <= normBitSin_uid93_fpSinCosXTest_in(51 downto 51);
--join_uid99_fpSinCosXTest(BITJOIN,98)@36
join_uid99_fpSinCosXTest_q <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q & normBitSin_uid93_fpSinCosXTest_b;
--sinRndOp_uid100_uid101_fpSinCosXTest(BITJOIN,100)@36
sinRndOp_uid100_uid101_fpSinCosXTest_q <= join_uid99_fpSinCosXTest_q & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor(LOGICAL,1333)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q <= not (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a or ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b);
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena(REG,1334)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q = "1") THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd(LOGICAL,1335)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b <= en;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a and ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor(LOGICAL,1283)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q <= not (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a or ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena(REG,1284)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd(LOGICAL,1285)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a and ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg(DELAY,1273)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid38_fpSinCosXTest_b, xout => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem(DUALMEM,1274)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia
);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1(REG,604)@25
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSinHC_uid74_fpSinCosXTest(SUB,73)@26
expSinHC_uid74_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expSinHC_uid74_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q);
expSinHC_uid74_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSinHC_uid74_fpSinCosXTest_a) - UNSIGNED(expSinHC_uid74_fpSinCosXTest_b));
expSinHC_uid74_fpSinCosXTest_q <= expSinHC_uid74_fpSinCosXTest_o(8 downto 0);
--expSinHCR_uid75_fpSinCosXTest(BITSELECT,74)@26
expSinHCR_uid75_fpSinCosXTest_in <= expSinHC_uid74_fpSinCosXTest_q(7 downto 0);
expSinHCR_uid75_fpSinCosXTest_b <= expSinHCR_uid75_fpSinCosXTest_in(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b(DELAY,695)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expPSin_uid76_fpSinCosXTest(MUX,75)@26
expPSin_uid76_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q;
expPSin_uid76_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expPSin_uid76_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expPSin_uid76_fpSinCosXTest_s IS
WHEN "0" => expPSin_uid76_fpSinCosXTest_q <= expSinHCR_uid75_fpSinCosXTest_b;
WHEN "1" => expPSin_uid76_fpSinCosXTest_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => expPSin_uid76_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg(DELAY,1323)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expPSin_uid76_fpSinCosXTest_q, xout => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem(DUALMEM,1324)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia
);
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq(7 downto 0);
--fracRSinPreRndHigh_uid95_fpSinCosXTest(BITSELECT,94)@36
fracRSinPreRndHigh_uid95_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(50 downto 0);
fracRSinPreRndHigh_uid95_fpSinCosXTest_b <= fracRSinPreRndHigh_uid95_fpSinCosXTest_in(50 downto 27);
--fracRSinPreRndLow_uid96_fpSinCosXTest(BITSELECT,95)@36
fracRSinPreRndLow_uid96_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(49 downto 0);
fracRSinPreRndLow_uid96_fpSinCosXTest_b <= fracRSinPreRndLow_uid96_fpSinCosXTest_in(49 downto 26);
--fracRSinPreRnd_uid97_fpSinCosXTest(MUX,96)@36
fracRSinPreRnd_uid97_fpSinCosXTest_s <= normBitSin_uid93_fpSinCosXTest_b;
fracRSinPreRnd_uid97_fpSinCosXTest: PROCESS (fracRSinPreRnd_uid97_fpSinCosXTest_s, en, fracRSinPreRndLow_uid96_fpSinCosXTest_b, fracRSinPreRndHigh_uid95_fpSinCosXTest_b)
BEGIN
CASE fracRSinPreRnd_uid97_fpSinCosXTest_s IS
WHEN "0" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndLow_uid96_fpSinCosXTest_b;
WHEN "1" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndHigh_uid95_fpSinCosXTest_b;
WHEN OTHERS => fracRSinPreRnd_uid97_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRSinPreRnd_uid98_uid98_fpSinCosXTest(BITJOIN,97)@36
expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q & fracRSinPreRnd_uid97_fpSinCosXTest_q;
--expFracRSin_uid102_fpSinCosXTest(ADD,101)@36
expFracRSin_uid102_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000000" & sinRndOp_uid100_uid101_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRSin_uid102_fpSinCosXTest_a) + UNSIGNED(expFracRSin_uid102_fpSinCosXTest_b));
expFracRSin_uid102_fpSinCosXTest_q <= expFracRSin_uid102_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid104_fpSinCosXTest(BITSELECT,103)@36
expRCompSin_uid104_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid104_fpSinCosXTest_b <= expRCompSin_uid104_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2(REG,607)@36
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= expRCompSin_uid104_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor(LOGICAL,1537)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q <= not (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a or ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b);
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena(REG,1538)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd(LOGICAL,1539)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a and ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b;
--expXIsZero_uid10_fpSinCosXTest(LOGICAL,9)@0
expXIsZero_uid10_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsZero_uid10_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
expXIsZero_uid10_fpSinCosXTest_q <= "1" when expXIsZero_uid10_fpSinCosXTest_a = expXIsZero_uid10_fpSinCosXTest_b else "0";
--ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b(DELAY,746)@0
ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => expXIsZero_uid10_fpSinCosXTest_q, xout => ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excSelBitsSin_uid118_fpSinCosXTest(BITJOIN,117)@19
excSelBitsSin_uid118_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_q & ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q & ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg(DELAY,1527)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => excSelBitsSin_uid118_fpSinCosXTest_q, xout => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem(DUALMEM,1528)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 14,
width_b => 3,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia
);
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq(2 downto 0);
--reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0(REG,533)@35
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excSelSin_uid119_fpSinCosXTest(LOOKUP,118)@36
excSelSin_uid119_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excSelSin_uid119_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q) IS
WHEN "000" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "001" => excSelSin_uid119_fpSinCosXTest_q <= "01";
WHEN "010" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "011" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "100" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "101" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "110" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "111" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
excSelSin_uid119_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExcSin_uid126_fpSinCosXTest(MUX,125)@37
expRPostExcSin_uid126_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
expRPostExcSin_uid126_fpSinCosXTest: PROCESS (expRPostExcSin_uid126_fpSinCosXTest_s, en, reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q, ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcSin_uid126_fpSinCosXTest_s IS
WHEN "00" => expRPostExcSin_uid126_fpSinCosXTest_q <= reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcSin_uid126_fpSinCosXTest_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcSin_uid126_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor(LOGICAL,1346)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q <= not (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a or ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena(REG,1347)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd(LOGICAL,1348)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a and ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg(DELAY,1336)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpSinCosXTest_b, xout => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem(DUALMEM,1337)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 35,
width_b => 23,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia
);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq(22 downto 0);
--fracRCompSin_uid103_fpSinCosXTest(BITSELECT,102)@36
fracRCompSin_uid103_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(23 downto 0);
fracRCompSin_uid103_fpSinCosXTest_b <= fracRCompSin_uid103_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2(REG,606)@36
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= fracRCompSin_uid103_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExcSin_uid122_fpSinCosXTest(MUX,121)@37
fracRPostExcSin_uid122_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
fracRPostExcSin_uid122_fpSinCosXTest: PROCESS (fracRPostExcSin_uid122_fpSinCosXTest_s, en, reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcSin_uid122_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcSin_uid122_fpSinCosXTest_q <= reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcSin_uid122_fpSinCosXTest_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "11" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcSin_uid122_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpSin_uid134_fpSinCosXTest(BITJOIN,133)@37
fpSin_uid134_fpSinCosXTest_q <= ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q & expRPostExcSin_uid126_fpSinCosXTest_q & fracRPostExcSin_uid122_fpSinCosXTest_q;
--xOut(GPOUT,4)@37
s <= fpSin_uid134_fpSinCosXTest_q;
c <= fpCos_uid162_fpSinCosXTest_q;
end normal;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/hcc_delaybit.vhd | 10 | 2330 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAYBIT.VHD ***
--*** ***
--*** Function: Delay a single bit an ***
--*** arbitrary number of stages ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delaybit IS
GENERIC (delay : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
END hcc_delaybit;
ARCHITECTURE rtl OF hcc_delaybit IS
signal delff : STD_LOGIC_VECTOR (delay DOWNTO 1);
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
delff(1) <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1) <= aa;
END IF;
END IF;
END PROCESS;
cc <= delff(1);
END GENERATE;
gdb: IF (delay > 1) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO delay LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff(1) <= aa;
FOR k IN 2 TO delay LOOP
delff(k) <= delff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delff(delay);
END GENERATE;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/CosPiDPStratixVf400.vhd | 10 | 580991 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Debug Version 12.0
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from CosPiDPStratixVf400
-- VHDL created on Wed Sep 05 17:56:14 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
USE work.CosPiDPStratixVf400_safe_path.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
-- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240
entity CosPiDPStratixVf400 is
port (
xIn_v : in std_logic_vector(0 downto 0);
xIn_c : in std_logic_vector(7 downto 0);
xIn_0 : in std_logic_vector(63 downto 0);
xOut_v : out std_logic_vector(0 downto 0);
xOut_c : out std_logic_vector(7 downto 0);
xOut_0 : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic;
bus_clk : in std_logic;
h_areset : in std_logic
);
end;
architecture normal of CosPiDPStratixVf400 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid9_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid10_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal cstBiasM1_uid11_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal cstBiasPwF_uid12_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal biasMwShift_uid13_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal biasMwShiftMO_uid14_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal cst01pWShift_uid15_fpCosPiTest_q : std_logic_vector (27 downto 0);
signal cstZwSwF_uid16_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal cstAllZWE_uid22_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_a : std_logic_vector(81 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_b : std_logic_vector(81 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_o : std_logic_vector (81 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_q : std_logic_vector (81 downto 0);
signal rangeReducedFxPX_uid53_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid53_fpCosPiTest_q : std_logic_vector (79 downto 0);
signal z_halfMRRFxPXE_uid54_fpCosPiTest_a : std_logic_vector(80 downto 0);
signal z_halfMRRFxPXE_uid54_fpCosPiTest_b : std_logic_vector(80 downto 0);
signal z_halfMRRFxPXE_uid54_fpCosPiTest_o : std_logic_vector (80 downto 0);
signal z_halfMRRFxPXE_uid54_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal xIsInt_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_e : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_f : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid88_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid88_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal oneFracRPostExc2_uid89_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal expRPostExc1_uid93_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid93_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid113_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage1Idx3Pad24_uid122_fxpX_uid43_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage2Idx3Pad6_uid133_fxpX_uid43_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal mO_uid147_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (48 downto 0);
signal memoryC3_uid228_sinPiZTableGenerator_q : std_logic_vector(34 downto 0);
signal memoryC4_uid229_sinPiZTableGenerator_q : std_logic_vector(25 downto 0);
signal memoryC5_uid230_sinPiZTableGenerator_q : std_logic_vector(16 downto 0);
signal rndBit_uid245_sinPiZPolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid257_sinPiZPolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid262_pT1_uid232_sinPiZPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid262_pT1_uid232_sinPiZPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid262_pT1_uid232_sinPiZPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid262_pT1_uid232_sinPiZPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid262_pT1_uid232_sinPiZPolyEval_q : std_logic_vector (33 downto 0);
signal prodXY_uid265_pT2_uid238_sinPiZPolyEval_a : std_logic_vector (25 downto 0);
signal prodXY_uid265_pT2_uid238_sinPiZPolyEval_b : std_logic_vector (27 downto 0);
signal prodXY_uid265_pT2_uid238_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid265_pT2_uid238_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal prodXY_uid265_pT2_uid238_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid270_pT3_uid244_sinPiZPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid270_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid270_pT3_uid244_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid270_pT3_uid244_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid270_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid287_pT4_uid250_sinPiZPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid287_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid287_pT4_uid250_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid287_pT4_uid250_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid287_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid302_pT5_uid256_sinPiZPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid302_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid302_pT5_uid256_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid302_pT5_uid256_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid302_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b1_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b1_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b1_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b1_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b1_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_zero_36_q : std_logic_vector (26 downto 0);
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_w : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_w_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_x : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_x_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_y : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_y_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s_type;
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s_type;
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s_type;
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_a : std_logic_vector(90 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_b : std_logic_vector(90 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_o : std_logic_vector (90 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_cin : std_logic_vector (0 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_c : std_logic_vector (0 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q : std_logic_vector (88 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a : std_logic_vector(21 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b : std_logic_vector(21 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_o : std_logic_vector (21 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_cin : std_logic_vector (0 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_q : std_logic_vector (19 downto 0);
signal reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3_q : std_logic_vector (80 downto 0);
signal reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2_q : std_logic_vector (80 downto 0);
signal reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0_q : std_logic_vector (79 downto 0);
signal reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0_q : std_logic_vector (79 downto 0);
signal reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1_q : std_logic_vector (79 downto 0);
signal reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0_q : std_logic_vector (80 downto 0);
signal reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0_q : std_logic_vector (79 downto 0);
signal reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0);
signal reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0);
signal reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1_q : std_logic_vector (36 downto 0);
signal reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0_q : std_logic_vector (51 downto 0);
signal reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1_q : std_logic_vector (53 downto 0);
signal reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0_q : std_logic_vector (60 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0_q : std_logic_vector (26 downto 0);
signal reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (6 downto 0);
signal reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_FxpXFrac79_uid46_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fxpXFrac_uid45_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_c_q : std_logic_vector (79 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_zPPolyEval_uid65_fpCosPiTest_a_q : std_logic_vector (78 downto 0);
signal ld_normBit_uid69_fpCosPiTest_b_to_rndExpUpdate_uid74_uid75_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid38_fpCosPiTest_c_to_InvCosXIsOne_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fxpXFracHalf_uid48_fpCosPiTest_q_to_or_uid87_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_Or2ZeroExcRNaN_uid94_fpCosPiTest_q_to_join_uid96_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q_to_signRComp_uid101_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d_q : std_logic_vector (31 downto 0);
signal ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c_q : std_logic_vector (15 downto 0);
signal ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d_q : std_logic_vector (15 downto 0);
signal ld_vCount_uid160_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid154_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid146_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_g_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC4_uid229_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_lowRangeB_uid239_sinPiZPolyEval_b_to_s2_uid239_uid242_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0);
signal ld_lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b_to_add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0);
signal ld_yT4_uid249_sinPiZPolyEval_b_to_xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b_to_spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b_to_add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b_to_spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0);
signal ld_lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b_to_add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0);
signal ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a_q : std_logic_vector (19 downto 0);
signal ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b_q : std_logic_vector (19 downto 0);
signal ld_mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_a_q : std_logic_vector (88 downto 0);
signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic;
signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic;
signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (6 downto 0);
signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic;
signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_inputreg_q : std_logic_vector (78 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_iq : std_logic_vector (78 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ia : std_logic_vector (78 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ir : std_logic_vector (78 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_q : std_logic_vector (78 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg_q : std_logic_vector (4 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_outputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_outputreg_q : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ir : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_mem_top_q : std_logic_vector (2 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ir : std_logic_vector (14 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg_q : std_logic_vector (78 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_iq : std_logic_vector (78 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ia : std_logic_vector (78 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ir : std_logic_vector (78 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_q : std_logic_vector (78 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_outputreg_q : std_logic_vector (25 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (25 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_outputreg_q : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ir : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_outputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ir : std_logic_vector (1 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal pad_o_uid17_uid49_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal pad_half_uid18_uid54_fpCosPiTest_q : std_logic_vector (79 downto 0);
signal spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (26 downto 0);
signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal rndExpUpdate_uid74_uid75_fpCosPiTest_q : std_logic_vector (53 downto 0);
signal expFracComp_uid76_fpCosPiTest_a : std_logic_vector(64 downto 0);
signal expFracComp_uid76_fpCosPiTest_b : std_logic_vector(64 downto 0);
signal expFracComp_uid76_fpCosPiTest_o : std_logic_vector (64 downto 0);
signal expFracComp_uid76_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal fracRPostExc_uid90_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid90_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid97_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid97_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal memoryC0_uid225_sinPiZTableGenerator_q : std_logic_vector(57 downto 0);
signal memoryC1_uid226_sinPiZTableGenerator_q : std_logic_vector(49 downto 0);
signal memoryC2_uid227_sinPiZTableGenerator_q : std_logic_vector(42 downto 0);
signal sumAHighB_uid241_sinPiZPolyEval_a : std_logic_vector(35 downto 0);
signal sumAHighB_uid241_sinPiZPolyEval_b : std_logic_vector(35 downto 0);
signal sumAHighB_uid241_sinPiZPolyEval_o : std_logic_vector (35 downto 0);
signal sumAHighB_uid241_sinPiZPolyEval_q : std_logic_vector (35 downto 0);
signal ts3_uid247_sinPiZPolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid247_sinPiZPolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid247_sinPiZPolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid247_sinPiZPolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid253_sinPiZPolyEval_a : std_logic_vector(52 downto 0);
signal ts4_uid253_sinPiZPolyEval_b : std_logic_vector(52 downto 0);
signal ts4_uid253_sinPiZPolyEval_o : std_logic_vector (52 downto 0);
signal ts4_uid253_sinPiZPolyEval_q : std_logic_vector (52 downto 0);
signal ts5_uid259_sinPiZPolyEval_a : std_logic_vector(61 downto 0);
signal ts5_uid259_sinPiZPolyEval_b : std_logic_vector(61 downto 0);
signal ts5_uid259_sinPiZPolyEval_o : std_logic_vector (61 downto 0);
signal ts5_uid259_sinPiZPolyEval_q : std_logic_vector (61 downto 0);
signal sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (54 downto 0);
signal cstHalfwSwFP1_uid19_fpCosPiTest_q : std_logic_vector (79 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal expX_uid6_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpCosPiTest_b : std_logic_vector (10 downto 0);
signal fracX_uid7_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal fracX_uid7_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expXIsMax_uid26_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid26_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid26_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid28_fpCosPiTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid28_fpCosPiTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid28_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xEvenInt_uid37_fpCosPiTest_a : std_logic_vector(13 downto 0);
signal xEvenInt_uid37_fpCosPiTest_b : std_logic_vector(13 downto 0);
signal xEvenInt_uid37_fpCosPiTest_o : std_logic_vector (13 downto 0);
signal xEvenInt_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xEvenInt_uid37_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal cosXIsOne_uid38_fpCosPiTest_a : std_logic_vector(13 downto 0);
signal cosXIsOne_uid38_fpCosPiTest_b : std_logic_vector(13 downto 0);
signal cosXIsOne_uid38_fpCosPiTest_o : std_logic_vector (13 downto 0);
signal cosXIsOne_uid38_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid38_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal shiftValFxPX_uid40_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal shiftValFxPX_uid40_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal shiftValFxPX_uid40_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal shiftValFxPX_uid40_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal fxpXFracZero_uid47_fpCosPiTest_a : std_logic_vector(79 downto 0);
signal fxpXFracZero_uid47_fpCosPiTest_b : std_logic_vector(79 downto 0);
signal fxpXFracZero_uid47_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid24_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid24_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid24_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid51_fpCosPiTest_in : std_logic_vector (79 downto 0);
signal oMFxpXFrac_uid51_fpCosPiTest_b : std_logic_vector (79 downto 0);
signal z_uid56_fpCosPiTest_in : std_logic_vector (78 downto 0);
signal z_uid56_fpCosPiTest_b : std_logic_vector (78 downto 0);
signal or_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal or_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal or_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal or_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid154_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid154_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid154_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal vCount_uid166_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid166_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid166_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid160_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid160_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid160_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cIncludingRoundingBit_uid246_sinPiZPolyEval_q : std_logic_vector (44 downto 0);
signal cIncludingRoundingBit_uid252_sinPiZPolyEval_q : std_logic_vector (51 downto 0);
signal cIncludingRoundingBit_uid258_sinPiZPolyEval_q : std_logic_vector (60 downto 0);
signal prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_in : std_logic_vector (53 downto 0);
signal prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1_q : std_logic_vector (107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2_q : std_logic_vector (107 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (29 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_q : std_logic_vector (108 downto 0);
signal fxpXFracHalf_uid48_fpCosPiTest_a : std_logic_vector(79 downto 0);
signal fxpXFracHalf_uid48_fpCosPiTest_b : std_logic_vector(79 downto 0);
signal fxpXFracHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid169_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid169_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (71 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (44 downto 0);
signal InvCosXIsOne_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid85_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid85_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid85_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid85_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid85_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal join_uid96_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal signRComp_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid101_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid157_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid157_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid163_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid163_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal s2_uid239_uid242_sinPiZPolyEval_q : std_logic_vector (36 downto 0);
signal add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (55 downto 0);
signal xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (79 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(6 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(6 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid60_fpCosPiTest_in : std_logic_vector (78 downto 0);
signal alignedZLow_uid60_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal R_uid104_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_a : std_logic_vector(2 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_b : std_logic_vector(2 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid243_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT3_uid243_sinPiZPolyEval_b : std_logic_vector (34 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid249_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT4_uid249_sinPiZPolyEval_b : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal expP_uid62_fpCosPiTest_in : std_logic_vector (10 downto 0);
signal expP_uid62_fpCosPiTest_b : std_logic_vector (10 downto 0);
signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (52 downto 0);
signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (10 downto 0);
signal FxpX80_uid44_fpCosPiTest_in : std_logic_vector (80 downto 0);
signal FxpX80_uid44_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fxpXFrac_uid45_fpCosPiTest_in : std_logic_vector (79 downto 0);
signal fxpXFrac_uid45_fpCosPiTest_b : std_logic_vector (79 downto 0);
signal s3_uid248_sinPiZPolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid248_sinPiZPolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid254_sinPiZPolyEval_in : std_logic_vector (52 downto 0);
signal s4_uid254_sinPiZPolyEval_b : std_logic_vector (51 downto 0);
signal s5_uid260_sinPiZPolyEval_in : std_logic_vector (61 downto 0);
signal s5_uid260_sinPiZPolyEval_b : std_logic_vector (60 downto 0);
signal oFracX_uid39_uid39_fpCosPiTest_q : std_logic_vector (52 downto 0);
signal And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid42_fpCosPiTest_in : std_logic_vector (6 downto 0);
signal fxpShifterBits_uid42_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (78 downto 0);
signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal rVStage_uid145_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (78 downto 0);
signal rVStage_uid145_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (63 downto 0);
signal vStage_uid148_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (14 downto 0);
signal vStage_uid148_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (14 downto 0);
signal X46dto0_uid189_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (46 downto 0);
signal X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (46 downto 0);
signal lowRangeB_uid233_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid233_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid234_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal highBBits_uid234_sinPiZPolyEval_b : std_logic_vector (16 downto 0);
signal lowRangeB_uid239_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid239_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid240_sinPiZPolyEval_in : std_logic_vector (28 downto 0);
signal highBBits_uid240_sinPiZPolyEval_b : std_logic_vector (27 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0_q : std_logic_vector (107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_c : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_q : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_q : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_q : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_q : std_logic_vector(107 downto 0);
signal lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid281_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (29 downto 0);
signal highBBits_uid281_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid296_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid296_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (24 downto 0);
signal lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (24 downto 0);
signal highBBits_uid311_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid311_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal normBit_uid69_fpCosPiTest_in : std_logic_vector (106 downto 0);
signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid70_fpCosPiTest_in : std_logic_vector (105 downto 0);
signal highRes_uid70_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (104 downto 0);
signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal InvFxpXFracHalf_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid171_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid171_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid173_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid173_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (70 downto 0);
signal LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (70 downto 0);
signal LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (54 downto 0);
signal LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (54 downto 0);
signal yT1_uid231_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT1_uid231_sinPiZPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid237_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT2_uid237_sinPiZPolyEval_b : std_logic_vector (25 downto 0);
signal xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal signR_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid103_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid159_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid159_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid161_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid161_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid165_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid165_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid167_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid167_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (36 downto 0);
signal yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (9 downto 0);
signal yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (9 downto 0);
signal yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (36 downto 0);
signal yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal R_uid284_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (54 downto 0);
signal R_uid284_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (36 downto 0);
signal R_uid299_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (71 downto 0);
signal R_uid299_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (45 downto 0);
signal R_uid314_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (78 downto 0);
signal R_uid314_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0);
signal xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (34 downto 0);
signal xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (34 downto 0);
signal xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (7 downto 0);
signal xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (7 downto 0);
signal xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (15 downto 0);
signal FxpXFrac79_uid46_fpCosPiTest_in : std_logic_vector (79 downto 0);
signal FxpXFrac79_uid46_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (51 downto 0);
signal yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (24 downto 0);
signal yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (58 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (53 downto 0);
signal oFracXExt_uid41_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid146_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(63 downto 0);
signal vCount_uid146_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(63 downto 0);
signal vCount_uid146_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cStage_uid149_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal sumAHighB_uid235_sinPiZPolyEval_a : std_logic_vector(26 downto 0);
signal sumAHighB_uid235_sinPiZPolyEval_b : std_logic_vector(26 downto 0);
signal sumAHighB_uid235_sinPiZPolyEval_o : std_logic_vector (26 downto 0);
signal sumAHighB_uid235_sinPiZPolyEval_q : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_a_q : std_logic_vector (108 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_c : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_q : std_logic_vector(107 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (52 downto 0);
signal vCount_uid172_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid172_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid172_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid175_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid175_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx1_uid199_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage1Idx2_uid202_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage1Idx3_uid205_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal spad_yBottomBits_uid272_uid275_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (10 downto 0);
signal pad_xBottomBits_uid273_uid276_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid289_uid291_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b_1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b_1_b : std_logic_vector (26 downto 0);
signal X48dto0_uid108_fxpX_uid43_fpCosPiTest_in : std_logic_vector (48 downto 0);
signal X48dto0_uid108_fxpX_uid43_fpCosPiTest_b : std_logic_vector (48 downto 0);
signal X16dto0_uid111_fxpX_uid43_fpCosPiTest_in : std_logic_vector (16 downto 0);
signal X16dto0_uid111_fxpX_uid43_fpCosPiTest_b : std_logic_vector (16 downto 0);
signal InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid86_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid86_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid86_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid151_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid151_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal s1_uid233_uid236_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_in : std_logic_vector (108 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_b : std_logic_vector (88 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c : std_logic_vector (19 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_in : std_logic_vector (106 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_b : std_logic_vector (106 downto 0);
signal expFracPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal rVStage_uid177_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid177_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid179_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid179_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (17 downto 0);
signal leftShiftStage0Idx1_uid109_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage0Idx2_uid112_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal Or2ZeroExcRNaN_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal Or2ZeroExcRNaN_uid94_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal Or2ZeroExcRNaN_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid153_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid153_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid155_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal vStage_uid155_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_BJ_q : std_logic_vector (107 downto 0);
signal vCount_uid178_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid178_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid178_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid181_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid181_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (72 downto 0);
signal LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (72 downto 0);
signal leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_b_q : std_logic_vector (108 downto 0);
signal rVStage_uid183_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid183_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2Idx1_uid210_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage2Idx2_uid213_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage2Idx3_uid216_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_in : std_logic_vector (72 downto 0);
signal LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_b : std_logic_vector (72 downto 0);
signal LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_b : std_logic_vector (64 downto 0);
signal LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_b : std_logic_vector (56 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_in : std_logic_vector (108 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_b : std_logic_vector (88 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c : std_logic_vector (19 downto 0);
signal vCount_uid184_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid184_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid184_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage1Idx1_uid118_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage1Idx2_uid121_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage1Idx3_uid124_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal r_uid185_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (6 downto 0);
signal LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (77 downto 0);
signal LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage3Idx1_uid221_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_in : std_logic_vector (78 downto 0);
signal LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_b : std_logic_vector (78 downto 0);
signal LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage2Idx1_uid129_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage2Idx2_uid132_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage2Idx3_uid135_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_in : std_logic_vector (79 downto 0);
signal LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_b : std_logic_vector (79 downto 0);
signal leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
begin
--ld_xIn_v_to_xOut_v_notEnable(LOGICAL,852)
ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q;
ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a;
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor(LOGICAL,942)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_b <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_q <= not (ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_a or ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_b);
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_mem_top(CONSTANT,938)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_mem_top_q <= "0100101";
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp(LOGICAL,939)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_a <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_mem_top_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q);
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_q <= "1" when ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_a = ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_b else "0";
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg(REG,940)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_q;
END IF;
END PROCESS;
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena(REG,943)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_q = "1") THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd(LOGICAL,944)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_a <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_b <= VCC_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_a and ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_b;
--LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest(BITSELECT,133)@0
LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_in <= leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx3Pad6_uid133_fxpX_uid43_fpCosPiTest(CONSTANT,132)
leftShiftStage2Idx3Pad6_uid133_fxpX_uid43_fpCosPiTest_q <= "000000";
--leftShiftStage2Idx3_uid135_fxpX_uid43_fpCosPiTest(BITJOIN,134)@0
leftShiftStage2Idx3_uid135_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_b & leftShiftStage2Idx3Pad6_uid133_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest(BITSELECT,130)@0
LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_in <= leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q(76 downto 0);
LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_in(76 downto 0);
--leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest(CONSTANT,129)
leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest_q <= "0000";
--leftShiftStage2Idx2_uid132_fxpX_uid43_fpCosPiTest(BITJOIN,131)@0
leftShiftStage2Idx2_uid132_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_b & leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest(BITSELECT,127)@0
LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_in <= leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q(78 downto 0);
LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_in(78 downto 0);
--leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest(CONSTANT,126)
leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest_q <= "00";
--leftShiftStage2Idx1_uid129_fxpX_uid43_fpCosPiTest(BITJOIN,128)@0
leftShiftStage2Idx1_uid129_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_b & leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest(BITSELECT,122)@0
LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_in <= leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q(56 downto 0);
LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_in(56 downto 0);
--leftShiftStage1Idx3Pad24_uid122_fxpX_uid43_fpCosPiTest(CONSTANT,121)
leftShiftStage1Idx3Pad24_uid122_fxpX_uid43_fpCosPiTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid124_fxpX_uid43_fpCosPiTest(BITJOIN,123)@0
leftShiftStage1Idx3_uid124_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_b & leftShiftStage1Idx3Pad24_uid122_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest(BITSELECT,119)@0
LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_in <= leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q(64 downto 0);
LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_in(64 downto 0);
--leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest(CONSTANT,118)
leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest_q <= "0000000000000000";
--leftShiftStage1Idx2_uid121_fxpX_uid43_fpCosPiTest(BITJOIN,120)@0
leftShiftStage1Idx2_uid121_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_b & leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest(BITSELECT,116)@0
LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_in <= leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q(72 downto 0);
LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_in(72 downto 0);
--leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest(CONSTANT,115)
leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest_q <= "00000000";
--leftShiftStage1Idx1_uid118_fxpX_uid43_fpCosPiTest(BITJOIN,117)@0
leftShiftStage1Idx1_uid118_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_b & leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest_q;
--leftShiftStage0Idx3_uid113_fxpX_uid43_fpCosPiTest(CONSTANT,112)
leftShiftStage0Idx3_uid113_fxpX_uid43_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--X16dto0_uid111_fxpX_uid43_fpCosPiTest(BITSELECT,110)@0
X16dto0_uid111_fxpX_uid43_fpCosPiTest_in <= oFracXExt_uid41_fpCosPiTest_q(16 downto 0);
X16dto0_uid111_fxpX_uid43_fpCosPiTest_b <= X16dto0_uid111_fxpX_uid43_fpCosPiTest_in(16 downto 0);
--leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest(CONSTANT,109)
leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx2_uid112_fxpX_uid43_fpCosPiTest(BITJOIN,111)@0
leftShiftStage0Idx2_uid112_fxpX_uid43_fpCosPiTest_q <= X16dto0_uid111_fxpX_uid43_fpCosPiTest_b & leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest_q;
--X48dto0_uid108_fxpX_uid43_fpCosPiTest(BITSELECT,107)@0
X48dto0_uid108_fxpX_uid43_fpCosPiTest_in <= oFracXExt_uid41_fpCosPiTest_q(48 downto 0);
X48dto0_uid108_fxpX_uid43_fpCosPiTest_b <= X48dto0_uid108_fxpX_uid43_fpCosPiTest_in(48 downto 0);
--leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest(CONSTANT,106)
leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx1_uid109_fxpX_uid43_fpCosPiTest(BITJOIN,108)@0
leftShiftStage0Idx1_uid109_fxpX_uid43_fpCosPiTest_q <= X48dto0_uid108_fxpX_uid43_fpCosPiTest_b & leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest_q;
--cst01pWShift_uid15_fpCosPiTest(CONSTANT,14)
cst01pWShift_uid15_fpCosPiTest_q <= "0000000000000000000000000000";
--xIn(PORTIN,3)@0
--fracX_uid7_fpCosPiTest(BITSELECT,6)@0
fracX_uid7_fpCosPiTest_in <= xIn_0(51 downto 0);
fracX_uid7_fpCosPiTest_b <= fracX_uid7_fpCosPiTest_in(51 downto 0);
--oFracX_uid39_uid39_fpCosPiTest(BITJOIN,38)@0
oFracX_uid39_uid39_fpCosPiTest_q <= VCC_q & fracX_uid7_fpCosPiTest_b;
--oFracXExt_uid41_fpCosPiTest(BITJOIN,40)@0
oFracXExt_uid41_fpCosPiTest_q <= cst01pWShift_uid15_fpCosPiTest_q & oFracX_uid39_uid39_fpCosPiTest_q;
--biasMwShiftMO_uid14_fpCosPiTest(CONSTANT,13)
biasMwShiftMO_uid14_fpCosPiTest_q <= "01111100011";
--expX_uid6_fpCosPiTest(BITSELECT,5)@0
expX_uid6_fpCosPiTest_in <= xIn_0(62 downto 0);
expX_uid6_fpCosPiTest_b <= expX_uid6_fpCosPiTest_in(62 downto 52);
--shiftValFxPX_uid40_fpCosPiTest(SUB,39)@0
shiftValFxPX_uid40_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpCosPiTest_b);
shiftValFxPX_uid40_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & biasMwShiftMO_uid14_fpCosPiTest_q);
shiftValFxPX_uid40_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValFxPX_uid40_fpCosPiTest_a) - UNSIGNED(shiftValFxPX_uid40_fpCosPiTest_b));
shiftValFxPX_uid40_fpCosPiTest_q <= shiftValFxPX_uid40_fpCosPiTest_o(11 downto 0);
--fxpShifterBits_uid42_fpCosPiTest(BITSELECT,41)@0
fxpShifterBits_uid42_fpCosPiTest_in <= shiftValFxPX_uid40_fpCosPiTest_q(6 downto 0);
fxpShifterBits_uid42_fpCosPiTest_b <= fxpShifterBits_uid42_fpCosPiTest_in(6 downto 0);
--leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest(BITSELECT,113)@0
leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_in <= fxpShifterBits_uid42_fpCosPiTest_b;
leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_b <= leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_in(6 downto 5);
--leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest(MUX,114)@0
leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_s <= leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_b;
leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest: PROCESS (leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_s, oFracXExt_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid109_fxpX_uid43_fpCosPiTest_q, leftShiftStage0Idx2_uid112_fxpX_uid43_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q <= oFracXExt_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q <= leftShiftStage0Idx1_uid109_fxpX_uid43_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q <= leftShiftStage0Idx2_uid112_fxpX_uid43_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q <= leftShiftStage0Idx3_uid113_fxpX_uid43_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest(BITSELECT,124)@0
leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_in <= fxpShifterBits_uid42_fpCosPiTest_b(4 downto 0);
leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_in(4 downto 3);
--leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest(MUX,125)@0
leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_b;
leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest: PROCESS (leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_s, leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q, leftShiftStage1Idx1_uid118_fxpX_uid43_fpCosPiTest_q, leftShiftStage1Idx2_uid121_fxpX_uid43_fpCosPiTest_q, leftShiftStage1Idx3_uid124_fxpX_uid43_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q <= leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q;
WHEN "01" => leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q <= leftShiftStage1Idx1_uid118_fxpX_uid43_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q <= leftShiftStage1Idx2_uid121_fxpX_uid43_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q <= leftShiftStage1Idx3_uid124_fxpX_uid43_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest(BITSELECT,135)@0
leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_in <= fxpShifterBits_uid42_fpCosPiTest_b(2 downto 0);
leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_in(2 downto 1);
--leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest(MUX,136)@0
leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_s <= leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_b;
leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest: PROCESS (leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_s, leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q, leftShiftStage2Idx1_uid129_fxpX_uid43_fpCosPiTest_q, leftShiftStage2Idx2_uid132_fxpX_uid43_fpCosPiTest_q, leftShiftStage2Idx3_uid135_fxpX_uid43_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q <= leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q <= leftShiftStage2Idx1_uid129_fxpX_uid43_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q <= leftShiftStage2Idx2_uid132_fxpX_uid43_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q <= leftShiftStage2Idx3_uid135_fxpX_uid43_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest(BITSELECT,138)@0
LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_in <= leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q(79 downto 0);
LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_in(79 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest(BITJOIN,139)@0
leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_b & GND_q;
--reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3(REG,356)@0
reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3_q <= leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_q;
END IF;
END PROCESS;
--reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2(REG,357)@0
reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2_q <= leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q;
END IF;
END PROCESS;
--leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest(BITSELECT,140)@0
leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_in <= fxpShifterBits_uid42_fpCosPiTest_b(0 downto 0);
leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_b(DELAY,547)@0
ld_leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_b_q, clk => clk, aclr => areset );
--leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest(MUX,141)@1
leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_b_q;
leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest: PROCESS (leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_s, reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2_q, reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3_q)
BEGIN
CASE leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_s IS
WHEN "0" => leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q <= reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2_q;
WHEN "1" => leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q <= reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3_q;
WHEN OTHERS => leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpXFrac_uid45_fpCosPiTest(BITSELECT,44)@1
fxpXFrac_uid45_fpCosPiTest_in <= leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q(79 downto 0);
fxpXFrac_uid45_fpCosPiTest_b <= fxpXFrac_uid45_fpCosPiTest_in(79 downto 0);
--FxpXFrac79_uid46_fpCosPiTest(BITSELECT,45)@1
FxpXFrac79_uid46_fpCosPiTest_in <= fxpXFrac_uid45_fpCosPiTest_b;
FxpXFrac79_uid46_fpCosPiTest_b <= FxpXFrac79_uid46_fpCosPiTest_in(79 downto 79);
--FxpX80_uid44_fpCosPiTest(BITSELECT,43)@1
FxpX80_uid44_fpCosPiTest_in <= leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q;
FxpX80_uid44_fpCosPiTest_b <= FxpX80_uid44_fpCosPiTest_in(80 downto 80);
--Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest(LOGICAL,97)@1
Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_a <= FxpX80_uid44_fpCosPiTest_b;
Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_b <= FxpXFrac79_uid46_fpCosPiTest_b;
Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q <= Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_a xor Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_b;
--ld_Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q_to_signRComp_uid101_fpCosPiTest_c(DELAY,504)@1
ld_Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q_to_signRComp_uid101_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q, xout => ld_Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q_to_signRComp_uid101_fpCosPiTest_c_q, clk => clk, aclr => areset );
--cstBiasPwF_uid12_fpCosPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpCosPiTest_q <= "10000110011";
--xEvenInt_uid37_fpCosPiTest(COMPARE,36)@0
xEvenInt_uid37_fpCosPiTest_cin <= GND_q;
xEvenInt_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpCosPiTest_q) & '0';
xEvenInt_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & xEvenInt_uid37_fpCosPiTest_cin(0);
xEvenInt_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xEvenInt_uid37_fpCosPiTest_a) - UNSIGNED(xEvenInt_uid37_fpCosPiTest_b));
xEvenInt_uid37_fpCosPiTest_c(0) <= xEvenInt_uid37_fpCosPiTest_o(13);
--ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a(DELAY,470)@0
ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xEvenInt_uid37_fpCosPiTest_c, xout => ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a_q, clk => clk, aclr => areset );
--InvXEvenInt_uid83_fpCosPiTest(LOGICAL,82)@2
InvXEvenInt_uid83_fpCosPiTest_a <= ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a_q;
InvXEvenInt_uid83_fpCosPiTest_q <= not InvXEvenInt_uid83_fpCosPiTest_a;
--biasMwShift_uid13_fpCosPiTest(CONSTANT,12)
biasMwShift_uid13_fpCosPiTest_q <= "01111100100";
--cosXIsOne_uid38_fpCosPiTest(COMPARE,37)@0
cosXIsOne_uid38_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid38_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & '0';
cosXIsOne_uid38_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid13_fpCosPiTest_q) & cosXIsOne_uid38_fpCosPiTest_cin(0);
cosXIsOne_uid38_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid38_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid38_fpCosPiTest_b));
cosXIsOne_uid38_fpCosPiTest_c(0) <= cosXIsOne_uid38_fpCosPiTest_o(13);
--ld_cosXIsOne_uid38_fpCosPiTest_c_to_InvCosXIsOne_uid79_fpCosPiTest_a(DELAY,467)@0
ld_cosXIsOne_uid38_fpCosPiTest_c_to_InvCosXIsOne_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOne_uid38_fpCosPiTest_c, xout => ld_cosXIsOne_uid38_fpCosPiTest_c_to_InvCosXIsOne_uid79_fpCosPiTest_a_q, clk => clk, aclr => areset );
--InvCosXIsOne_uid79_fpCosPiTest(LOGICAL,78)@2
InvCosXIsOne_uid79_fpCosPiTest_a <= ld_cosXIsOne_uid38_fpCosPiTest_c_to_InvCosXIsOne_uid79_fpCosPiTest_a_q;
InvCosXIsOne_uid79_fpCosPiTest_q <= not InvCosXIsOne_uid79_fpCosPiTest_a;
--signRComp_uid101_fpCosPiTest(LOGICAL,100)@2
signRComp_uid101_fpCosPiTest_a <= InvCosXIsOne_uid79_fpCosPiTest_q;
signRComp_uid101_fpCosPiTest_b <= InvXEvenInt_uid83_fpCosPiTest_q;
signRComp_uid101_fpCosPiTest_c <= ld_Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q_to_signRComp_uid101_fpCosPiTest_c_q;
signRComp_uid101_fpCosPiTest_q <= signRComp_uid101_fpCosPiTest_a and signRComp_uid101_fpCosPiTest_b and signRComp_uid101_fpCosPiTest_c;
--cstZwSwF_uid16_fpCosPiTest(CONSTANT,15)
cstZwSwF_uid16_fpCosPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000";
--cstHalfwSwFP1_uid19_fpCosPiTest(BITJOIN,18)@2
cstHalfwSwFP1_uid19_fpCosPiTest_q <= VCC_q & cstZwSwF_uid16_fpCosPiTest_q;
--reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0(REG,359)@1
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0_q <= fxpXFrac_uid45_fpCosPiTest_b;
END IF;
END PROCESS;
--fxpXFracHalf_uid48_fpCosPiTest(LOGICAL,47)@2
fxpXFracHalf_uid48_fpCosPiTest_a <= reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0_q;
fxpXFracHalf_uid48_fpCosPiTest_b <= cstHalfwSwFP1_uid19_fpCosPiTest_q;
fxpXFracHalf_uid48_fpCosPiTest_q <= "1" when fxpXFracHalf_uid48_fpCosPiTest_a = fxpXFracHalf_uid48_fpCosPiTest_b else "0";
--InvFxpXFracHalf_uid102_fpCosPiTest(LOGICAL,101)@2
InvFxpXFracHalf_uid102_fpCosPiTest_a <= fxpXFracHalf_uid48_fpCosPiTest_q;
InvFxpXFracHalf_uid102_fpCosPiTest_q <= not InvFxpXFracHalf_uid102_fpCosPiTest_a;
--signR_uid103_fpCosPiTest(LOGICAL,102)@2
signR_uid103_fpCosPiTest_a <= InvFxpXFracHalf_uid102_fpCosPiTest_q;
signR_uid103_fpCosPiTest_b <= signRComp_uid101_fpCosPiTest_q;
signR_uid103_fpCosPiTest_q <= signR_uid103_fpCosPiTest_a and signR_uid103_fpCosPiTest_b;
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_inputreg(DELAY,932)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid103_fpCosPiTest_q, xout => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_inputreg_q, clk => clk, aclr => areset );
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt(COUNTER,934)
-- every=1, low=0, high=37, step=1, init=1
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i = 36 THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i - 37;
ELSE
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg(REG,935)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_q;
END IF;
END PROCESS;
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux(MUX,936)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_s <= VCC_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux: PROCESS (ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_s, ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q, ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem(DUALMEM,933)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ia <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_inputreg_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_aa <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ab <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_iq,
address_a => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_aa,
data_a => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ia
);
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid10_fpCosPiTest(CONSTANT,9)
cstBias_uid10_fpCosPiTest_q <= "01111111111";
--cstAllOWE_uid8_fpCosPiTest(CONSTANT,7)
cstAllOWE_uid8_fpCosPiTest_q <= "11111111111";
--cstAllZWE_uid22_fpCosPiTest(CONSTANT,21)
cstAllZWE_uid22_fpCosPiTest_q <= "00000000000";
--reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1(REG,361)@1
reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1_q <= fxpXFrac_uid45_fpCosPiTest_b;
END IF;
END PROCESS;
--pad_o_uid17_uid49_fpCosPiTest(BITJOIN,48)@1
pad_o_uid17_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((79 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0(REG,362)@1
reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0_q <= pad_o_uid17_uid49_fpCosPiTest_q;
END IF;
END PROCESS;
--oMFxpXFrac_uid49_fpCosPiTest(SUB,49)@2
oMFxpXFrac_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0_q);
oMFxpXFrac_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1_q);
oMFxpXFrac_uid49_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oMFxpXFrac_uid49_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
oMFxpXFrac_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid49_fpCosPiTest_a) - UNSIGNED(oMFxpXFrac_uid49_fpCosPiTest_b));
END IF;
END PROCESS;
oMFxpXFrac_uid49_fpCosPiTest_q <= oMFxpXFrac_uid49_fpCosPiTest_o(81 downto 0);
--oMFxpXFrac_uid51_fpCosPiTest(BITSELECT,50)@3
oMFxpXFrac_uid51_fpCosPiTest_in <= oMFxpXFrac_uid49_fpCosPiTest_q(79 downto 0);
oMFxpXFrac_uid51_fpCosPiTest_b <= oMFxpXFrac_uid51_fpCosPiTest_in(79 downto 0);
--ld_fxpXFrac_uid45_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_c(DELAY,443)@1
ld_fxpXFrac_uid45_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 80, depth => 2 )
PORT MAP ( xin => fxpXFrac_uid45_fpCosPiTest_b, xout => ld_fxpXFrac_uid45_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_c_q, clk => clk, aclr => areset );
--ld_FxpXFrac79_uid46_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_b(DELAY,442)@1
ld_FxpXFrac79_uid46_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => FxpXFrac79_uid46_fpCosPiTest_b, xout => ld_FxpXFrac79_uid46_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_b_q, clk => clk, aclr => areset );
--rangeReducedFxPX_uid53_fpCosPiTest(MUX,52)@3
rangeReducedFxPX_uid53_fpCosPiTest_s <= ld_FxpXFrac79_uid46_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_b_q;
rangeReducedFxPX_uid53_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid53_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
CASE rangeReducedFxPX_uid53_fpCosPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid53_fpCosPiTest_q <= ld_fxpXFrac_uid45_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid53_fpCosPiTest_q <= oMFxpXFrac_uid51_fpCosPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid53_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END PROCESS;
--pad_half_uid18_uid54_fpCosPiTest(BITJOIN,53)@3
pad_half_uid18_uid54_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((78 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0(REG,363)@3
reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0_q <= pad_half_uid18_uid54_fpCosPiTest_q;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid54_fpCosPiTest(SUB,54)@4
z_halfMRRFxPXE_uid54_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0_q);
z_halfMRRFxPXE_uid54_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid53_fpCosPiTest_q);
z_halfMRRFxPXE_uid54_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
z_halfMRRFxPXE_uid54_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
z_halfMRRFxPXE_uid54_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid54_fpCosPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid54_fpCosPiTest_b));
END IF;
END PROCESS;
z_halfMRRFxPXE_uid54_fpCosPiTest_q <= z_halfMRRFxPXE_uid54_fpCosPiTest_o(80 downto 0);
--z_uid56_fpCosPiTest(BITSELECT,55)@5
z_uid56_fpCosPiTest_in <= z_halfMRRFxPXE_uid54_fpCosPiTest_q(78 downto 0);
z_uid56_fpCosPiTest_b <= z_uid56_fpCosPiTest_in(78 downto 0);
--zAddr_uid64_fpCosPiTest(BITSELECT,63)@5
zAddr_uid64_fpCosPiTest_in <= z_uid56_fpCosPiTest_b;
zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(78 downto 72);
--memoryC5_uid230_sinPiZTableGenerator(LOOKUP,229)@5
memoryC5_uid230_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC5_uid230_sinPiZTableGenerator_q <= "11111111101000001";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (zAddr_uid64_fpCosPiTest_b) IS
WHEN "0000000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111111101000001";
WHEN "0000001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111110101101000";
WHEN "0000010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111101101011101";
WHEN "0000011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111100110001110";
WHEN "0000100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111100000000010";
WHEN "0000101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111011000000000";
WHEN "0000110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111010001101101";
WHEN "0000111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111001010010111";
WHEN "0001000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111000010110010";
WHEN "0001001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110111100010100";
WHEN "0001010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110110100011111";
WHEN "0001011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110101100101101";
WHEN "0001100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110100101101011";
WHEN "0001101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110011111011101";
WHEN "0001110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110010111001010";
WHEN "0001111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110010001011011";
WHEN "0010000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110001010101011";
WHEN "0010001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110000011011001";
WHEN "0010010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101111011000001";
WHEN "0010011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101110101001010";
WHEN "0010100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101101110100110";
WHEN "0010101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101100111100011";
WHEN "0010110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101011111111111";
WHEN "0010111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101011001001010";
WHEN "0011000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101010010100110";
WHEN "0011001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101001010011011";
WHEN "0011010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101000100011100";
WHEN "0011011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100111101010110";
WHEN "0011100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100110110111000";
WHEN "0011101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100101111110010";
WHEN "0011110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100100111110010";
WHEN "0011111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100100001010101";
WHEN "0100000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100011011011111";
WHEN "0100001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100010011110111";
WHEN "0100010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100001110001010";
WHEN "0100011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100000111000100";
WHEN "0100100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011111111110101";
WHEN "0100101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011111001010110";
WHEN "0100110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011110011000111";
WHEN "0100111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011101101000000";
WHEN "0101000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011100110000011";
WHEN "0101001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011011111111001";
WHEN "0101010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011011000100110";
WHEN "0101011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011010010101100";
WHEN "0101100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011001100010010";
WHEN "0101101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011000101010111";
WHEN "0101110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010111111101010";
WHEN "0101111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010111001010000";
WHEN "0110000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010110011010011";
WHEN "0110001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010101100101011";
WHEN "0110010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010100110111110";
WHEN "0110011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010011111111000";
WHEN "0110100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010011010110010";
WHEN "0110101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010010101001110";
WHEN "0110110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010001110010011";
WHEN "0110111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010001000111011";
WHEN "0111000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010000001111011";
WHEN "0111001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001111011111110";
WHEN "0111010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001110111001010";
WHEN "0111011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001110001110111";
WHEN "0111100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001101011000100";
WHEN "0111101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001100101010010";
WHEN "0111110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001100000011111";
WHEN "0111111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001011010001010";
WHEN "1000000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001010100111110";
WHEN "1000001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001001110110010";
WHEN "1000010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001001010111000";
WHEN "1000011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001000100111111";
WHEN "1000100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000111111001100";
WHEN "1000101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000111010001001";
WHEN "1000110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000110101010110";
WHEN "1000111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000110000011101";
WHEN "1001000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000101001110100";
WHEN "1001001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000100101111001";
WHEN "1001010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000011111111010";
WHEN "1001011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000011011110110";
WHEN "1001100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000010110001100";
WHEN "1001101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000010001001000";
WHEN "1001110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000001101111001";
WHEN "1001111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000001000000111";
WHEN "1010000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000000010111001";
WHEN "1010001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111111110110110";
WHEN "1010010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111111001111111";
WHEN "1010011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111110110010100";
WHEN "1010100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111110001011000";
WHEN "1010101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111101100010111";
WHEN "1010110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111101000010010";
WHEN "1010111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111100100010000";
WHEN "1011000" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111100000111100";
WHEN "1011001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111011011111111";
WHEN "1011010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111010111100000";
WHEN "1011011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111010011110100";
WHEN "1011100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111010000011100";
WHEN "1011101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111001011011110";
WHEN "1011110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111000111111101";
WHEN "1011111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111000100101011";
WHEN "1100000" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111000001100100";
WHEN "1100001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110111101101110";
WHEN "1100010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110111010011000";
WHEN "1100011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110110110110000";
WHEN "1100100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110110010011010";
WHEN "1100101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110110000011110";
WHEN "1100110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110101100101100";
WHEN "1100111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110101000101110";
WHEN "1101000" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110100110100000";
WHEN "1101001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110100100010001";
WHEN "1101010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110100001000000";
WHEN "1101011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110011101101110";
WHEN "1101100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110011011011111";
WHEN "1101101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110010111000100";
WHEN "1101110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110010101110011";
WHEN "1101111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110010001111100";
WHEN "1110000" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110010000001111";
WHEN "1110001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110001110011001";
WHEN "1110010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110001010100010";
WHEN "1110011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110000111111000";
WHEN "1110100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110000101110110";
WHEN "1110101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110000101000100";
WHEN "1110110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110000010100010";
WHEN "1110111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101111111110011";
WHEN "1111000" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101111110010000";
WHEN "1111001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101111100110111";
WHEN "1111010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101111010111000";
WHEN "1111011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101111000101000";
WHEN "1111100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101110110110100";
WHEN "1111101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101110101011010";
WHEN "1111110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101110100000011";
WHEN "1111111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101110010001011";
WHEN OTHERS =>
memoryC5_uid230_sinPiZTableGenerator_q <= "11111111101000001";
END CASE;
END IF;
END PROCESS;
--ld_z_uid56_fpCosPiTest_b_to_zPPolyEval_uid65_fpCosPiTest_a(DELAY,452)@5
ld_z_uid56_fpCosPiTest_b_to_zPPolyEval_uid65_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 79, depth => 1 )
PORT MAP ( xin => z_uid56_fpCosPiTest_b, xout => ld_z_uid56_fpCosPiTest_b_to_zPPolyEval_uid65_fpCosPiTest_a_q, clk => clk, aclr => areset );
--zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@6
zPPolyEval_uid65_fpCosPiTest_in <= ld_z_uid56_fpCosPiTest_b_to_zPPolyEval_uid65_fpCosPiTest_a_q(71 downto 0);
zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(71 downto 27);
--yT1_uid231_sinPiZPolyEval(BITSELECT,230)@6
yT1_uid231_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT1_uid231_sinPiZPolyEval_b <= yT1_uid231_sinPiZPolyEval_in(44 downto 28);
--prodXY_uid262_pT1_uid232_sinPiZPolyEval(MULT,261)@6
prodXY_uid262_pT1_uid232_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid262_pT1_uid232_sinPiZPolyEval_a),18)) * SIGNED(prodXY_uid262_pT1_uid232_sinPiZPolyEval_b);
prodXY_uid262_pT1_uid232_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid262_pT1_uid232_sinPiZPolyEval_a <= (others => '0');
prodXY_uid262_pT1_uid232_sinPiZPolyEval_b <= (others => '0');
prodXY_uid262_pT1_uid232_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid262_pT1_uid232_sinPiZPolyEval_a <= yT1_uid231_sinPiZPolyEval_b;
prodXY_uid262_pT1_uid232_sinPiZPolyEval_b <= memoryC5_uid230_sinPiZTableGenerator_q;
prodXY_uid262_pT1_uid232_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid262_pT1_uid232_sinPiZPolyEval_pr,34));
END IF;
END PROCESS;
prodXY_uid262_pT1_uid232_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid262_pT1_uid232_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid262_pT1_uid232_sinPiZPolyEval_q <= prodXY_uid262_pT1_uid232_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval(BITSELECT,262)@9
prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_in <= prodXY_uid262_pT1_uid232_sinPiZPolyEval_q;
prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_b <= prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_in(33 downto 16);
--highBBits_uid234_sinPiZPolyEval(BITSELECT,233)@9
highBBits_uid234_sinPiZPolyEval_in <= prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_b;
highBBits_uid234_sinPiZPolyEval_b <= highBBits_uid234_sinPiZPolyEval_in(17 downto 1);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC4_uid229_sinPiZTableGenerator_a(DELAY,638)@5
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC4_uid229_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC4_uid229_sinPiZTableGenerator_a_q, clk => clk, aclr => areset );
--memoryC4_uid229_sinPiZTableGenerator(LOOKUP,228)@8
memoryC4_uid229_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100110110001011110";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC4_uid229_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100110110001011110";
WHEN "0000001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100110011111111100";
WHEN "0000010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100101101100110011";
WHEN "0000011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100100010011000101";
WHEN "0000100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100010010010010110";
WHEN "0000101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001011111110011000100";
WHEN "0000110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001011100101011001100";
WHEN "0000111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001011001000001111000";
WHEN "0001000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001010100110101100100";
WHEN "0001001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001010000000010110001";
WHEN "0001010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001001010101111100100";
WHEN "0001011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001000100111000100010";
WHEN "0001100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000111110011011110101";
WHEN "0001101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000110111011001010101";
WHEN "0001110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000101111111000110001";
WHEN "0001111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000100111101101111110";
WHEN "0010000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000011111000010010110";
WHEN "0010001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000010101110100101111";
WHEN "0010010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000001100000110110101";
WHEN "0010011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000000001101111000000";
WHEN "0010100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001111110110110101110011";
WHEN "0010101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001111101011011010111001";
WHEN "0010110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001111011111011110000110";
WHEN "0010111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001111010010111100110100";
WHEN "0011000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001111000101110111111001";
WHEN "0011001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001110111000010100011101";
WHEN "0011010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001110101010001000110011";
WHEN "0011011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001110011011011101100111";
WHEN "0011100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001110001100001110001111";
WHEN "0011101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001101111100011110001010";
WHEN "0011110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001101101100001110100101";
WHEN "0011111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001101011011011000110110";
WHEN "0100000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001101001001111111101110";
WHEN "0100001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001100111000001001001111";
WHEN "0100010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001100100101101100011001";
WHEN "0100011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001100010010110001110000";
WHEN "0100100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001011111111010101110110";
WHEN "0100101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001011101011010111000111";
WHEN "0100110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001011010110110110011110";
WHEN "0100111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001011000001110100011110";
WHEN "0101000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001010101100010100010011";
WHEN "0101001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001010010110010001000111";
WHEN "0101010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001001111111110001000100";
WHEN "0101011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001001101000101100110110";
WHEN "0101100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001001010001001001111011";
WHEN "0101101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001000111001001000001110";
WHEN "0101110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001000100000100011110110";
WHEN "0101111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001000000111100001111001";
WHEN "0110000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000111101101111111011111";
WHEN "0110001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000111010011111111100110";
WHEN "0110010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000110111001011110100100";
WHEN "0110011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000110011110100010000111";
WHEN "0110100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000110000011000010001001";
WHEN "0110101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000101100111000101000011";
WHEN "0110110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000101001010101101011111";
WHEN "0110111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000100101101110011101110";
WHEN "0111000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000100010000100000111110";
WHEN "0111001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000011110010101101110100";
WHEN "0111010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000011010100011010011110";
WHEN "0111011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000010110101101011010111";
WHEN "0111100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000010010110100011011101";
WHEN "0111101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000001110110111100001001";
WHEN "0111110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000001010110110110010000";
WHEN "0111111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000000110110011000001101";
WHEN "1000000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000000010101011011011001";
WHEN "1000001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111111110100000101110010";
WHEN "1000010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111111010010001110101001";
WHEN "1000011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111110110000000001101011";
WHEN "1000100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111110001101011001110011";
WHEN "1000101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111101101010010101011101";
WHEN "1000110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111101000110110101111111";
WHEN "1000111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111100100010111100111100";
WHEN "1001000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111011111110101110100100";
WHEN "1001001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111011011001111111110100";
WHEN "1001010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111010110100111101000111";
WHEN "1001011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111010001111011100101001";
WHEN "1001100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111001101001100111100001";
WHEN "1001101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111001000011011000101011";
WHEN "1001110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111000011100101100110010";
WHEN "1001111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110111110101110000000011";
WHEN "1010000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110111001110011001111101";
WHEN "1010001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110110100110101001110001";
WHEN "1010010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110101111110100101001011";
WHEN "1010011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110101010110000110010110";
WHEN "1010100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110100101101010100111010";
WHEN "1010101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110100000100001101101101";
WHEN "1010110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110011011010101110011000";
WHEN "1010111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110010110000111001010011";
WHEN "1011000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110010000110101101010010";
WHEN "1011001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110001011100010001000010";
WHEN "1011010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110000110001011111001110";
WHEN "1011011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110000000110010110110100";
WHEN "1011100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101111011010111010001000";
WHEN "1011101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101110101111001110001011";
WHEN "1011110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101110000011001011001100";
WHEN "1011111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101101010110110100111111";
WHEN "1100000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101100101010001011011001";
WHEN "1100001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101011111101010010000000";
WHEN "1100010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101011010000000101001000";
WHEN "1100011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101010100010100111110111";
WHEN "1100100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101001110100111011010110";
WHEN "1100101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101001000110110111101100";
WHEN "1100110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101000011000101000001000";
WHEN "1100111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100111101010001001010101";
WHEN "1101000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100110111011010110000011";
WHEN "1101001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100110001100010011011010";
WHEN "1101010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100101011101000100011001";
WHEN "1101011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100100101101100110100111";
WHEN "1101100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100011111101110111111010";
WHEN "1101101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100011001110000000101100";
WHEN "1101110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100010011101110011110101";
WHEN "1101111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100001101101100000010000";
WHEN "1110000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100000111100111010001011";
WHEN "1110001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100000001100000111111010";
WHEN "1110010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011111011011001110101000";
WHEN "1110011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011110101010000110010111";
WHEN "1110100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011101111000110001000001";
WHEN "1110101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011101000111001101001001";
WHEN "1110110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011100010101100011001010";
WHEN "1110111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011011100011101111010110";
WHEN "1111000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011010110001101110011110";
WHEN "1111001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011001111111100011010111";
WHEN "1111010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011001001101010000100101";
WHEN "1111011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011000011010110101101110";
WHEN "1111100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00010111101000010001000000";
WHEN "1111101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00010110110101100011000101";
WHEN "1111110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00010110000010101101010111";
WHEN "1111111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00010101001111110001011010";
WHEN OTHERS =>
memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100110110001011110";
END CASE;
END IF;
END PROCESS;
--sumAHighB_uid235_sinPiZPolyEval(ADD,234)@9
sumAHighB_uid235_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((26 downto 26 => memoryC4_uid229_sinPiZTableGenerator_q(25)) & memoryC4_uid229_sinPiZTableGenerator_q);
sumAHighB_uid235_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((26 downto 17 => highBBits_uid234_sinPiZPolyEval_b(16)) & highBBits_uid234_sinPiZPolyEval_b);
sumAHighB_uid235_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid235_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid235_sinPiZPolyEval_b));
sumAHighB_uid235_sinPiZPolyEval_q <= sumAHighB_uid235_sinPiZPolyEval_o(26 downto 0);
--lowRangeB_uid233_sinPiZPolyEval(BITSELECT,232)@9
lowRangeB_uid233_sinPiZPolyEval_in <= prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid233_sinPiZPolyEval_b <= lowRangeB_uid233_sinPiZPolyEval_in(0 downto 0);
--s1_uid233_uid236_sinPiZPolyEval(BITJOIN,235)@9
s1_uid233_uid236_sinPiZPolyEval_q <= sumAHighB_uid235_sinPiZPolyEval_q & lowRangeB_uid233_sinPiZPolyEval_b;
--reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1(REG,373)@9
reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1_q <= "0000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1_q <= s1_uid233_uid236_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor(LOGICAL,977)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_b <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_q <= not (ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_a or ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_b);
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg(REG,975)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg_q <= VCC_q;
END IF;
END PROCESS;
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena(REG,978)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_q = "1") THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd(LOGICAL,979)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_a <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_b <= VCC_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_a and ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_b;
--yT2_uid237_sinPiZPolyEval(BITSELECT,236)@6
yT2_uid237_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT2_uid237_sinPiZPolyEval_b <= yT2_uid237_sinPiZPolyEval_in(44 downto 19);
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt(COUNTER,971)
-- every=1, low=0, high=1, step=1, init=1
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_i <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_i + 1;
END IF;
END PROCESS;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_i,1));
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg(REG,972)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux(MUX,973)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_s <= VCC_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux: PROCESS (ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_s, ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q, ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q;
WHEN "1" => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem(DUALMEM,1059)
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ia <= yT2_uid237_sinPiZPolyEval_b;
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_aa <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q;
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ab <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q;
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ia
);
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_q <= ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_iq(25 downto 0);
--ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_outputreg(DELAY,1058)
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_outputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_q, xout => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset );
--prodXY_uid265_pT2_uid238_sinPiZPolyEval(MULT,264)@10
prodXY_uid265_pT2_uid238_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid265_pT2_uid238_sinPiZPolyEval_a),27)) * SIGNED(prodXY_uid265_pT2_uid238_sinPiZPolyEval_b);
prodXY_uid265_pT2_uid238_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid265_pT2_uid238_sinPiZPolyEval_a <= (others => '0');
prodXY_uid265_pT2_uid238_sinPiZPolyEval_b <= (others => '0');
prodXY_uid265_pT2_uid238_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid265_pT2_uid238_sinPiZPolyEval_a <= ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_outputreg_q;
prodXY_uid265_pT2_uid238_sinPiZPolyEval_b <= reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1_q;
prodXY_uid265_pT2_uid238_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid265_pT2_uid238_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
prodXY_uid265_pT2_uid238_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid265_pT2_uid238_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid265_pT2_uid238_sinPiZPolyEval_q <= prodXY_uid265_pT2_uid238_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval(BITSELECT,265)@13
prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_in <= prodXY_uid265_pT2_uid238_sinPiZPolyEval_q;
prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_b <= prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_in(53 downto 25);
--highBBits_uid240_sinPiZPolyEval(BITSELECT,239)@13
highBBits_uid240_sinPiZPolyEval_in <= prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_b;
highBBits_uid240_sinPiZPolyEval_b <= highBBits_uid240_sinPiZPolyEval_in(28 downto 1);
--reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1(REG,374)@13
reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1_q <= "0000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1_q <= highBBits_uid240_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor(LOGICAL,1029)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_mem_top(CONSTANT,1025)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_mem_top_q <= "0101";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp(LOGICAL,1026)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_mem_top_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_q <= "1" when ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_a = ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_b else "0";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg(REG,1027)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena(REG,1030)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd(LOGICAL,1031)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_b <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,1021)
-- every=1, low=0, high=5, step=1, init=1
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i = 4 THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i - 5;
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg(REG,1022)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux(MUX,1023)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_s, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem(DUALMEM,1020)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ia <= zAddr_uid64_fpCosPiTest_b;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_aa <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ab <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 6,
width_b => 7,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_outputreg(DELAY,1019)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_q, xout => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC3_uid228_sinPiZTableGenerator(LOOKUP,227)@13
memoryC3_uid228_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC3_uid228_sinPiZTableGenerator_q <= "11111111111111111111111111111001011";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_outputreg_q) IS
WHEN "0000000" => memoryC3_uid228_sinPiZTableGenerator_q <= "11111111111111111111111111111001011";
WHEN "0000001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000001010001100110101000111010101";
WHEN "0000010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000010100011001100101101010110011";
WHEN "0000011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000011110100110001101010100011011";
WHEN "0000100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000101000110010100111100101110011";
WHEN "0000101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000110010111110101111101101101000";
WHEN "0000110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000111101001010100001100001001101";
WHEN "0000111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001000111010101111000010100001000";
WHEN "0001000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001010001100000101111101001011010";
WHEN "0001001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001011011101011000011001000111110";
WHEN "0001010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001100101110100101110001001110101";
WHEN "0001011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001101111111101101100010100000001";
WHEN "0001100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001111010000101111001001101010110";
WHEN "0001101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010000100001101010000011000110101";
WHEN "0001110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010001110010011101101001010101000";
WHEN "0001111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010011000011001001011011101011111";
WHEN "0010000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010100010011101100110100011101011";
WHEN "0010001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010101100100000111010000011110001";
WHEN "0010010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010110110100011000001011111010110";
WHEN "0010011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011000000100011111000101110110101";
WHEN "0010100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011001010100011011011001000001011";
WHEN "0010101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011010100100001100100010010100101";
WHEN "0010110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011011110011110001111110110101010";
WHEN "0010111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011101000011001011001100000011011";
WHEN "0011000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011110010010010111100111000010100";
WHEN "0011001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011111100001010110101011110000110";
WHEN "0011010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100000110000000111111001110100010";
WHEN "0011011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100001111110101010101100100101101";
WHEN "0011100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100011001100111110100010110001111";
WHEN "0011101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100100011011000010111001001011111";
WHEN "0011110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100101101000110111001101001101001";
WHEN "0011111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100110110110011010111110011001100";
WHEN "0100000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101000000011101101101010000100110";
WHEN "0100001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101001010000101110101101000010110";
WHEN "0100010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101010011101011101100111100100100";
WHEN "0100011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101011101001111001110110000110010";
WHEN "0100100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101100110110000010111000000110011";
WHEN "0100101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101110000001111000001100011110100";
WHEN "0100110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101111001101011001010010000000001";
WHEN "0100111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110000011000100101100111100001110";
WHEN "0101000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110001100011011100101011010100101";
WHEN "0101001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110010101101111101111110000010101";
WHEN "0101010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110011111000001000111101011101100";
WHEN "0101011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110101000001111101001011001100010";
WHEN "0101100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110110001011011010000101101010010";
WHEN "0101101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110111010100011111001100111101100";
WHEN "0101110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111000011101001100000010000100010";
WHEN "0101111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111001100101100000000100001010000";
WHEN "0110000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111010101101011010110100011101100";
WHEN "0110001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111011110100111011110011000011110";
WHEN "0110010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111100111100000010100001101010000";
WHEN "0110011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111110000010101110100000001010000";
WHEN "0110100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111111001000111111010001101010001";
WHEN "0110101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000000001110110100010110001111010";
WHEN "0110110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000001010100001101001110111110101";
WHEN "0110111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000010011001001001011111110000001";
WHEN "0111000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000011011101101000101000010101111";
WHEN "0111001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000100100001101010001101000100100";
WHEN "0111010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000101100101001101110000011010101";
WHEN "0111011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000110101000010010110100001011010";
WHEN "0111100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000111101010111000111010101011110";
WHEN "0111101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001000101100111111101000110111000";
WHEN "0111110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001001101110100110100001111001100";
WHEN "0111111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001010101111101101001000001001010";
WHEN "1000000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001011110000010011000001001000011";
WHEN "1000001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001100110000010111101111101010011";
WHEN "1000010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001101101111111010111010011001111";
WHEN "1000011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001110101110111100000011010000110";
WHEN "1000100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001111101101011010110000011010010";
WHEN "1000101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010000101011010110100111100000101";
WHEN "1000110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010001101000101111001101110100011";
WHEN "1000111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010010100101100100001000101010010";
WHEN "1001000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010011100001110100111101001010100";
WHEN "1001001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010100011101100001010100001011100";
WHEN "1001010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010101011000101000110001011100100";
WHEN "1001011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010110010011001010111110000100100";
WHEN "1001100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010111001101000111011111001000111";
WHEN "1001101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011000000110011101111101001011111";
WHEN "1001110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011000111111001110000000110011110";
WHEN "1001111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011001110111010111001110111111110";
WHEN "1010000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011010101110111001010010001110110";
WHEN "1010001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011011100101110011110011000111101";
WHEN "1010010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011100011100000110011001001001001";
WHEN "1010011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011101010001110000101111000101100";
WHEN "1010100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011110000110110010011100011000111";
WHEN "1010101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011110111011001011001011101010011";
WHEN "1010110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011111101110111010100111100011100";
WHEN "1010111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100000100010000000011001111101101";
WHEN "1011000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100001010100011100001101110011100";
WHEN "1011001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100010000110001101101100011100011";
WHEN "1011010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100010110111010100100010100000100";
WHEN "1011011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100011100111110000011100000001010";
WHEN "1011100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100100010111100001000100001101001";
WHEN "1011101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100101000110100110000110001111011";
WHEN "1011110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100101110100111111010000100111001";
WHEN "1011111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100110100010101100001111010001101";
WHEN "1100000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100111001111101100101111101110000";
WHEN "1100001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100111111100000000011110011100101";
WHEN "1100010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101000100111100111001010011110100";
WHEN "1100011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101001010010100000100001001001101";
WHEN "1100100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101001111100101100010000111001000";
WHEN "1100101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101010100110001010001010100001101";
WHEN "1100110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101011001110111001111010101110101";
WHEN "1100111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101011110110111011010001101111010";
WHEN "1101000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101100011110001110000000111001111";
WHEN "1101001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101101000100110001110111010010001";
WHEN "1101010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101101101010100110100100110101101";
WHEN "1101011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101110001111101011111011001010101";
WHEN "1101100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101110110100000001101100000100000";
WHEN "1101101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101111010111100111100111010111000";
WHEN "1101110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101111111010011101100010000110110";
WHEN "1101111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110000011100100011001011010100000";
WHEN "1110000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110000111101111000011000011110011";
WHEN "1110001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110001011110011100111011010000000";
WHEN "1110010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110001111110010000100101111100001";
WHEN "1110011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110010011101010011001110010000111";
WHEN "1110100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110010111011100100100111111111001";
WHEN "1110101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110011011001000100101000000101011";
WHEN "1110110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110011110101110011000001011101010";
WHEN "1110111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110100010001101111101010010100010";
WHEN "1111000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110100101100111010011001000110011";
WHEN "1111001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110101000111010011000011010000011";
WHEN "1111010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110101100000111001011110100010010";
WHEN "1111011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110101111001101101100001110011100";
WHEN "1111100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110110010001101111000100101110110";
WHEN "1111101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110110101000111101111110101001010";
WHEN "1111110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110110111111011010000111000110000";
WHEN "1111111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110111010101000011010110000100000";
WHEN OTHERS =>
memoryC3_uid228_sinPiZTableGenerator_q <= "11111111111111111111111111111001011";
END CASE;
END IF;
END PROCESS;
--sumAHighB_uid241_sinPiZPolyEval(ADD,240)@14
sumAHighB_uid241_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid228_sinPiZTableGenerator_q(34)) & memoryC3_uid228_sinPiZTableGenerator_q);
sumAHighB_uid241_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((35 downto 28 => reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1_q(27)) & reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1_q);
sumAHighB_uid241_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid241_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid241_sinPiZPolyEval_b));
sumAHighB_uid241_sinPiZPolyEval_q <= sumAHighB_uid241_sinPiZPolyEval_o(35 downto 0);
--lowRangeB_uid239_sinPiZPolyEval(BITSELECT,238)@13
lowRangeB_uid239_sinPiZPolyEval_in <= prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid239_sinPiZPolyEval_b <= lowRangeB_uid239_sinPiZPolyEval_in(0 downto 0);
--ld_lowRangeB_uid239_sinPiZPolyEval_b_to_s2_uid239_uid242_sinPiZPolyEval_a(DELAY,652)@13
ld_lowRangeB_uid239_sinPiZPolyEval_b_to_s2_uid239_uid242_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => lowRangeB_uid239_sinPiZPolyEval_b, xout => ld_lowRangeB_uid239_sinPiZPolyEval_b_to_s2_uid239_uid242_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--s2_uid239_uid242_sinPiZPolyEval(BITJOIN,241)@14
s2_uid239_uid242_sinPiZPolyEval_q <= sumAHighB_uid241_sinPiZPolyEval_q & ld_lowRangeB_uid239_sinPiZPolyEval_b_to_s2_uid239_uid242_sinPiZPolyEval_a_q;
--yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval(BITSELECT,273)@14
yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_in <= s2_uid239_uid242_sinPiZPolyEval_q;
yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_b <= yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_in(36 downto 19);
--reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9(REG,375)@14
reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9_q <= "000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9_q <= yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor(LOGICAL,1042)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_b);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_mem_top(CONSTANT,1038)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_mem_top_q <= "0110";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp(LOGICAL,1039)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_mem_top_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg(REG,1040)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena(REG,1043)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd(LOGICAL,1044)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_b <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1034)
-- every=1, low=0, high=6, step=1, init=1
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i = 5 THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg(REG,1035)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux(MUX,1036)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem(DUALMEM,1033)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid65_fpCosPiTest_b;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 3,
numwords_a => 7,
width_b => 45,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_iq(44 downto 0);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_outputreg(DELAY,1032)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset );
--yT3_uid243_sinPiZPolyEval(BITSELECT,242)@15
yT3_uid243_sinPiZPolyEval_in <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_outputreg_q;
yT3_uid243_sinPiZPolyEval_b <= yT3_uid243_sinPiZPolyEval_in(44 downto 10);
--xBottomBits_uid273_pT3_uid244_sinPiZPolyEval(BITSELECT,272)@15
xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_in <= yT3_uid243_sinPiZPolyEval_b(7 downto 0);
xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_b <= xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_in(7 downto 0);
--pad_xBottomBits_uid273_uid276_pT3_uid244_sinPiZPolyEval(BITJOIN,275)@15
pad_xBottomBits_uid273_uid276_pT3_uid244_sinPiZPolyEval_q <= xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q);
--yBottomBits_uid272_pT3_uid244_sinPiZPolyEval(BITSELECT,271)@14
yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_in <= s2_uid239_uid242_sinPiZPolyEval_q(9 downto 0);
yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_b <= yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_in(9 downto 0);
--spad_yBottomBits_uid272_uid275_pT3_uid244_sinPiZPolyEval(BITJOIN,274)@14
spad_yBottomBits_uid272_uid275_pT3_uid244_sinPiZPolyEval_q <= GND_q & yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_b;
--pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval(BITJOIN,276)@14
pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_q <= spad_yBottomBits_uid272_uid275_pT3_uid244_sinPiZPolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6(REG,376)@14
reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6_q <= "000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_q;
END IF;
END PROCESS;
--xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval(BITSELECT,270)@15
xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_in <= yT3_uid243_sinPiZPolyEval_b;
xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_b <= xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_in(34 downto 17);
--multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma(CHAINMULTADD,344)@15
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p(0) <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a(0) * multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c(0);
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p(1) <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a(1) * multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c(1);
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p(1),38);
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_x(0) <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_w(0);
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_y(0) <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_x(0);
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_b),19));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(pad_xBottomBits_uid273_uid276_pT3_uid244_sinPiZPolyEval_q),19));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6_q),18));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9_q),18));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s(0) <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_y(0);
END IF;
END PROCESS;
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s(0),37));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_q <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval(BITSELECT,278)@18
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_in <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_q;
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_b <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_in(36 downto 7);
--highBBits_uid281_pT3_uid244_sinPiZPolyEval(BITSELECT,280)@18
highBBits_uid281_pT3_uid244_sinPiZPolyEval_in <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_b;
highBBits_uid281_pT3_uid244_sinPiZPolyEval_b <= highBBits_uid281_pT3_uid244_sinPiZPolyEval_in(29 downto 1);
--reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1(REG,378)@18
reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1_q <= highBBits_uid281_pT3_uid244_sinPiZPolyEval_b;
END IF;
END PROCESS;
--yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval(BITSELECT,268)@14
yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_in <= s2_uid239_uid242_sinPiZPolyEval_q;
yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_b <= yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_in(36 downto 10);
--reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1(REG,377)@14
reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1_q <= yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_b;
END IF;
END PROCESS;
--xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval(BITSELECT,267)@15
xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_in <= yT3_uid243_sinPiZPolyEval_b;
xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_b <= xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_in(34 downto 8);
--topProd_uid270_pT3_uid244_sinPiZPolyEval(MULT,269)@15
topProd_uid270_pT3_uid244_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid270_pT3_uid244_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid270_pT3_uid244_sinPiZPolyEval_b);
topProd_uid270_pT3_uid244_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid270_pT3_uid244_sinPiZPolyEval_a <= (others => '0');
topProd_uid270_pT3_uid244_sinPiZPolyEval_b <= (others => '0');
topProd_uid270_pT3_uid244_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid270_pT3_uid244_sinPiZPolyEval_a <= xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_b;
topProd_uid270_pT3_uid244_sinPiZPolyEval_b <= reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1_q;
topProd_uid270_pT3_uid244_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid270_pT3_uid244_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
topProd_uid270_pT3_uid244_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid270_pT3_uid244_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid270_pT3_uid244_sinPiZPolyEval_q <= topProd_uid270_pT3_uid244_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0(REG,379)@18
reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0_q <= topProd_uid270_pT3_uid244_sinPiZPolyEval_q;
END IF;
END PROCESS;
--sumAHighB_uid282_pT3_uid244_sinPiZPolyEval(ADD,281)@19
sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0_q(53)) & reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0_q);
sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1_q);
sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_b));
sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_q <= sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_o(54 downto 0);
--lowRangeB_uid280_pT3_uid244_sinPiZPolyEval(BITSELECT,279)@18
lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_in <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b <= lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_in(0 downto 0);
--ld_lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b_to_add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_a(DELAY,690)@18
ld_lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b_to_add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b, xout => ld_lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b_to_add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--add0_uid280_uid283_pT3_uid244_sinPiZPolyEval(BITJOIN,282)@19
add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_q <= sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_q & ld_lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b_to_add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_a_q;
--R_uid284_pT3_uid244_sinPiZPolyEval(BITSELECT,283)@19
R_uid284_pT3_uid244_sinPiZPolyEval_in <= add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_q(54 downto 0);
R_uid284_pT3_uid244_sinPiZPolyEval_b <= R_uid284_pT3_uid244_sinPiZPolyEval_in(54 downto 18);
--reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1(REG,380)@19
reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1_q <= R_uid284_pT3_uid244_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor(LOGICAL,1016)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_mem_top(CONSTANT,1012)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_mem_top_q <= "01011";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp(LOGICAL,1013)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_mem_top_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_q <= "1" when ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_a = ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_b else "0";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg(REG,1014)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena(REG,1017)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd(LOGICAL,1018)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_b <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,1008)
-- every=1, low=0, high=11, step=1, init=1
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i = 10 THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i - 11;
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i,4));
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg(REG,1009)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q <= "0000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux(MUX,1010)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_s, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem(DUALMEM,1007)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ia <= zAddr_uid64_fpCosPiTest_b;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_aa <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ab <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 4,
numwords_a => 12,
width_b => 7,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg(DELAY,1006)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_q, xout => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC2_uid227_sinPiZTableGenerator(LOOKUP,226)@19
memoryC2_uid227_sinPiZTableGenerator: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg_q)
BEGIN
-- Begin reserved scope level
CASE (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg_q) IS
WHEN "0000000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000";
WHEN "0000001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101010010000000010011011110101101000";
WHEN "0000010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101010100110111111010000111001000101";
WHEN "0000011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101011001101001111001000101101101011";
WHEN "0000100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101100000010110001110010011100100110";
WHEN "0000101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101101000111100110110110100100001100";
WHEN "0000110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101110011011101101110110101011000001";
WHEN "0000111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101111111111000110001101110000001000";
WHEN "0001000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110110001110001101111010000000001001001";
WHEN "0001001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110110011110011101000001010111100010011";
WHEN "0001010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110110110000100110000000101010101010010";
WHEN "0001011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110111000100101000101111111001111001110";
WHEN "0001100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110111011010100101000110010000000110000";
WHEN "0001101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110111110010011010111010000010100101101";
WHEN "0001110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111000001100001010000000110001101010110";
WHEN "0001111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111000100111110010001111000111001110001";
WHEN "0010000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111001000101010011011000111000110111111";
WHEN "0010001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111001100100101101010001000110100001110";
WHEN "0010010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111010000101111111101001111011000110110";
WHEN "0010011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111010101001001010010100101011111010000";
WHEN "0010100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111011001110001101000001111010001111100";
WHEN "0010101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111011110101000111100001010010001101000";
WHEN "0010110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111100011101111001100001101011001010011";
WHEN "0010111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111101001000100010110001000111111011001";
WHEN "0011000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111101110101000010111100110110111011101";
WHEN "0011001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111110100011011001110001010010101001001";
WHEN "0011010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111111010011100110111010000000101010000";
WHEN "0011011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000000000101101010000001110011011110111";
WHEN "0011100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000000111001100010110010101001001001010";
WHEN "0011101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000001101111010000110101101100011101100";
WHEN "0011110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000010100110110011110011010100101011100";
WHEN "0011111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000011100000001011010011000101010010101";
WHEN "0100000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000100011011010110111011101111001100010";
WHEN "0100001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000101011000010110010011010000011100100";
WHEN "0100010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000110010111001000111110110011110000010";
WHEN "0100011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000111010111101110100010110010000011111";
WHEN "0100100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001000011010000110100010110001010111111";
WHEN "0100101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001001011110010000100001100101110011011";
WHEN "0100110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001010100100001100000001010001100011000";
WHEN "0100111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001011101011111000100011000101001100001";
WHEN "0101000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001100110101010101100111100000000011011";
WHEN "0101001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001110000000100010101110001111101110010";
WHEN "0101010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001111001101011111010110010001100011010";
WHEN "0101011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010000011100001010111101110001010011110";
WHEN "0101100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010001101100100101000010001011000100111";
WHEN "0101101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010010111110101101000000001010011000010";
WHEN "0101110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010100010010100010010011101010101101010";
WHEN "0101111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010101101000000100010111111000010000011";
WHEN "0110000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010110111111010010100111001111011100110";
WHEN "0110001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011000011000001100011011011101110111001";
WHEN "0110010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011001110010110001001101100001111110101";
WHEN "0110011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011011001111000000010101101100000111100";
WHEN "0110100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011100101100111001001011011101110011000";
WHEN "0110101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011110001100011011000101101011001110101";
WHEN "0110110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011111101101100101011010011010110110001";
WHEN "0110111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011100001010000010111011111000101001101100";
WHEN "0111000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011100010110100110000101000010110110110100";
WHEN "0111001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011100100011010110000001010001110101000110";
WHEN "0111010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011100110000010010101010111111111100101100";
WHEN "0111011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011100111101011011111100100010000110111111";
WHEN "0111100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011101001010110001110000000111101111100101";
WHEN "0111101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011101011000010011111111111010110011011100";
WHEN "0111110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011101100110000010100101111111111011010100";
WHEN "0111111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011101110011111101011100010110011100010110";
WHEN "1000000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011110000010000100011100111000010100111110";
WHEN "1000001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011110010000010111100001011010011001010101";
WHEN "1000010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011110011110110110100011101100001011001000";
WHEN "1000011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011110101101100001011101011000001011011001";
WHEN "1000100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011110111100011000001000000011101110001111";
WHEN "1000101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011111001011011010011101001111000101110001";
WHEN "1000110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011111011010101000010110010101100101000110";
WHEN "1000111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011111101010000001101100101101100010111111";
WHEN "1001000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011111111001100110011001101000011100111011";
WHEN "1001001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100000001001010110010110010010110100011100";
WHEN "1001010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100000011001010001011011110100100000011000";
WHEN "1001011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100000101001010111100011010000011111011101";
WHEN "1001100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100000111001101000100101100101001010011111";
WHEN "1001101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100001001010000100011011101100001100000010";
WHEN "1001110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100001011010101010111110011010101000110000";
WHEN "1001111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100001101011011100000110100001001001100100";
WHEN "1010000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100001111100010111101100101011101111001100";
WHEN "1010001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100010001101011101101001100010000010111010";
WHEN "1010010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100010011110101101110101100111011000000101";
WHEN "1010011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100010110000001000001001011010101000000100";
WHEN "1010100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100011000001101100011101010110100010000110";
WHEN "1010101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100011010011011010101001110001100010110011";
WHEN "1010110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100011100101010010100110111101111101101001";
WHEN "1010111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100011110111010100001101001010000001101110";
WHEN "1011000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100100001001011111010100011111111010110111";
WHEN "1011001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100100011011110011110101000101111001011001";
WHEN "1011010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100100101110010001100110111110001101101110";
WHEN "1011011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100101000000111000100010000111010010100101";
WHEN "1011100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100101010011101000011110011011110001111001";
WHEN "1011101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100101100110100001010011110010100110010101";
WHEN "1011110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100101111001100010111001111110111010001011";
WHEN "1011111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100110001100101101001000110000010101000001";
WHEN "1100000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100110011111111111110111110010111000010010";
WHEN "1100001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100110110011011010111110101111001000100111";
WHEN "1100010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100111000110111110010101001010001010011010";
WHEN "1100011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100111011010101001110010100101101110010111";
WHEN "1100100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100111101110011101001110100000001111101010";
WHEN "1100101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101000000010011000100000010100110110100000";
WHEN "1100110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101000010110011011011111011011100110110011";
WHEN "1100111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101000101010100110000011001001011000000001";
WHEN "1101000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101000111110111000000010101111111100010101";
WHEN "1101001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101001010011010001010101011110001011010100";
WHEN "1101010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101001100111110001110010100000000000010111";
WHEN "1101011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101001111100011001010000111110011101110000";
WHEN "1101100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101010010001000111100111111111110011011101";
WHEN "1101101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101010100101111100101110100111100110010101";
WHEN "1101110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101010111010111000011011110110101001010101";
WHEN "1101111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101011001111111010100110101011010011011011";
WHEN "1110000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101011100101000011000110000001010000000100";
WHEN "1110001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101011111010010001110000110001110011111011";
WHEN "1110010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101100001111100110011101110011111001111111";
WHEN "1110011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101100100101000001000011111100000011011011";
WHEN "1110100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101100111010100001011001111100100100101001";
WHEN "1110101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101101010000000111010110100101100100010111";
WHEN "1110110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101101100101110010110000100101000101101101";
WHEN "1110111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101101111011100011011110100111000011010111";
WHEN "1111000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101110010001011001010111010101011001010001";
WHEN "1111001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101110100111010100010001011000001010110100";
WHEN "1111010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101110111101010100000011010101100101100011";
WHEN "1111011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101111010011011000100011110010000011111011";
WHEN "1111100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101111101001100001101001010000010010001011";
WHEN "1111101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101111111111101111001010010001010101000011";
WHEN "1111110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1110000010110000000111101010100101101001001";
WHEN "1111111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1110000101100010110111000111000011010110101";
WHEN OTHERS =>
memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000";
END CASE;
-- End reserved scope level
END PROCESS;
--rndBit_uid245_sinPiZPolyEval(CONSTANT,244)
rndBit_uid245_sinPiZPolyEval_q <= "01";
--cIncludingRoundingBit_uid246_sinPiZPolyEval(BITJOIN,245)@19
cIncludingRoundingBit_uid246_sinPiZPolyEval_q <= memoryC2_uid227_sinPiZTableGenerator_q & rndBit_uid245_sinPiZPolyEval_q;
--reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0(REG,381)@19
reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid246_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ts3_uid247_sinPiZPolyEval(ADD,246)@20
ts3_uid247_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0_q);
ts3_uid247_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1_q(36)) & reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1_q);
ts3_uid247_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid247_sinPiZPolyEval_a) + SIGNED(ts3_uid247_sinPiZPolyEval_b));
ts3_uid247_sinPiZPolyEval_q <= ts3_uid247_sinPiZPolyEval_o(45 downto 0);
--s3_uid248_sinPiZPolyEval(BITSELECT,247)@20
s3_uid248_sinPiZPolyEval_in <= ts3_uid247_sinPiZPolyEval_q;
s3_uid248_sinPiZPolyEval_b <= s3_uid248_sinPiZPolyEval_in(45 downto 1);
--yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval(BITSELECT,285)@20
yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_in <= s3_uid248_sinPiZPolyEval_b;
yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_b <= yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_in(44 downto 18);
--reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9(REG,382)@20
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor(LOGICAL,1055)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_b);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_mem_top(CONSTANT,1051)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp(LOGICAL,1052)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_mem_top_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg(REG,1053)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena(REG,1056)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd(LOGICAL,1057)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_b <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1047)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg(REG,1048)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q <= "0000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux(MUX,1049)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem(DUALMEM,1046)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid65_fpCosPiTest_b;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 4,
numwords_a => 13,
width_b => 45,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_iq(44 downto 0);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_outputreg(DELAY,1045)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset );
--yT4_uid249_sinPiZPolyEval(BITSELECT,248)@21
yT4_uid249_sinPiZPolyEval_in <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_outputreg_q;
yT4_uid249_sinPiZPolyEval_b <= yT4_uid249_sinPiZPolyEval_in(44 downto 2);
--xBottomBits_uid289_pT4_uid250_sinPiZPolyEval(BITSELECT,288)@21
xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_in <= yT4_uid249_sinPiZPolyEval_b(15 downto 0);
xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_b <= xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_in(15 downto 0);
--pad_xBottomBits_uid289_uid291_pT4_uid250_sinPiZPolyEval(BITJOIN,290)@21
pad_xBottomBits_uid289_uid291_pT4_uid250_sinPiZPolyEval_q <= xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--yBottomBits_uid288_pT4_uid250_sinPiZPolyEval(BITSELECT,287)@20
yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_in <= s3_uid248_sinPiZPolyEval_b(17 downto 0);
yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b <= yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_in(17 downto 0);
--ld_yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b_to_spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_a(DELAY,699)@20
ld_yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b_to_spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b, xout => ld_yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b_to_spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval(BITJOIN,289)@21
spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b_to_spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_a_q;
--pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval(BITJOIN,291)@21
pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_q <= spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6(REG,383)@21
reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ld_yT4_uid249_sinPiZPolyEval_b_to_xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_a(DELAY,693)@21
ld_yT4_uid249_sinPiZPolyEval_b_to_xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid249_sinPiZPolyEval_b, xout => ld_yT4_uid249_sinPiZPolyEval_b_to_xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval(BITSELECT,284)@22
xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_in <= ld_yT4_uid249_sinPiZPolyEval_b_to_xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_a_q;
xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_b <= xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_in(42 downto 16);
--multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma(CHAINMULTADD,345)@22
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c(0);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c(1);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p(0),56);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p(1),56);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w(0);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w(1);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x(0);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x(1);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_b),28));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(pad_xBottomBits_uid289_uid291_pT4_uid250_sinPiZPolyEval_q),28));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6_q),27));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9_q),27));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y(0);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y(1);
END IF;
END PROCESS;
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s(0),55));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval(BITSELECT,293)@25
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_in <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_q;
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_b <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_in(54 downto 8);
--highBBits_uid296_pT4_uid250_sinPiZPolyEval(BITSELECT,295)@25
highBBits_uid296_pT4_uid250_sinPiZPolyEval_in <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_b;
highBBits_uid296_pT4_uid250_sinPiZPolyEval_b <= highBBits_uid296_pT4_uid250_sinPiZPolyEval_in(46 downto 18);
--reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1(REG,385)@25
reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1_q <= highBBits_uid296_pT4_uid250_sinPiZPolyEval_b;
END IF;
END PROCESS;
--reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1(REG,384)@20
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q <= yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_b(DELAY,696)@21
ld_reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_b_q, clk => clk, aclr => areset );
--topProd_uid287_pT4_uid250_sinPiZPolyEval(MULT,286)@22
topProd_uid287_pT4_uid250_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid287_pT4_uid250_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid287_pT4_uid250_sinPiZPolyEval_b);
topProd_uid287_pT4_uid250_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid287_pT4_uid250_sinPiZPolyEval_a <= (others => '0');
topProd_uid287_pT4_uid250_sinPiZPolyEval_b <= (others => '0');
topProd_uid287_pT4_uid250_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid287_pT4_uid250_sinPiZPolyEval_a <= xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_b;
topProd_uid287_pT4_uid250_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_b_q;
topProd_uid287_pT4_uid250_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid287_pT4_uid250_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
topProd_uid287_pT4_uid250_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid287_pT4_uid250_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid287_pT4_uid250_sinPiZPolyEval_q <= topProd_uid287_pT4_uid250_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0(REG,386)@25
reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0_q <= topProd_uid287_pT4_uid250_sinPiZPolyEval_q;
END IF;
END PROCESS;
--sumAHighB_uid297_pT4_uid250_sinPiZPolyEval(ADD,296)@26
sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0_q(53)) & reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0_q);
sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1_q);
sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_b));
sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_q <= sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_o(54 downto 0);
--lowRangeB_uid295_pT4_uid250_sinPiZPolyEval(BITSELECT,294)@25
lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_in <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_b(17 downto 0);
lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b <= lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_in(17 downto 0);
--ld_lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b_to_add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_a(DELAY,707)@25
ld_lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b_to_add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b, xout => ld_lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b_to_add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--add0_uid295_uid298_pT4_uid250_sinPiZPolyEval(BITJOIN,297)@26
add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_q <= sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_q & ld_lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b_to_add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_a_q;
--R_uid299_pT4_uid250_sinPiZPolyEval(BITSELECT,298)@26
R_uid299_pT4_uid250_sinPiZPolyEval_in <= add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_q(71 downto 0);
R_uid299_pT4_uid250_sinPiZPolyEval_b <= R_uid299_pT4_uid250_sinPiZPolyEval_in(71 downto 26);
--reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1(REG,387)@26
reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1_q <= R_uid299_pT4_uid250_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor(LOGICAL,1003)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_mem_top(CONSTANT,999)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_mem_top_q <= "010010";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp(LOGICAL,1000)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_mem_top_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_q <= "1" when ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_a = ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_b else "0";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg(REG,1001)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena(REG,1004)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd(LOGICAL,1005)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_b <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,995)
-- every=1, low=0, high=18, step=1, init=1
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i = 17 THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i - 18;
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i,5));
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg(REG,996)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux(MUX,997)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_s, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem(DUALMEM,994)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ia <= zAddr_uid64_fpCosPiTest_b;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_aa <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ab <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 19,
width_b => 7,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg(DELAY,993)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_q, xout => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC1_uid226_sinPiZTableGenerator(LOOKUP,225)@26
memoryC1_uid226_sinPiZTableGenerator: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg_q)
BEGIN
-- Begin reserved scope level
CASE (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg_q) IS
WHEN "0000000" => memoryC1_uid226_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110";
WHEN "0000001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111110101101010100010101111000000010001111100011";
WHEN "0000010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111101011010101001001010010110100010110001011110";
WHEN "0000011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111100000111111110111100000001110010011010000110";
WHEN "0000100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111010110101010110001001011111100110111111100011";
WHEN "0000101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111001100010101111010001010101001101111010110100";
WHEN "0000110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111000010000001010110010000110111110101011111000";
WHEN "0000111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110110111101101001001010011000001101011000111010";
WHEN "0001000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110101101011001010111000101010111101010010100111";
WHEN "0001001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110100011000110000011011011111110011010111001110";
WHEN "0001010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110011000110011010010001010101101000110101101101";
WHEN "0001011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110001110100001000111000101001011101110011011101";
WHEN "0001100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110000100001111100101111110110001011110001011001";
WHEN "0001101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101111001111110110010101010100011000010010100110";
WHEN "0001110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101101111101110110000111011010000111100011100100";
WHEN "0001111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101100101011111100100100011010101111000101000111";
WHEN "0010000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101011011010001010001010100110101000010011111000";
WHEN "0010001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101010001000011111011000001011000011010110000100";
WHEN "0010010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101000110110111100101011010001111001100111110010";
WHEN "0010011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100111100101100010100010000001100000101010111010";
WHEN "0010100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100110010100010001011010011100011100110101011100";
WHEN "0010101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100101000011001001110010100001010100000101101100";
WHEN "0010110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100011110010001100001000001010100000110110000000";
WHEN "0010111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100010100001011000111001001110000100110010111000";
WHEN "0011000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100001010000110000100011011101011011110011010110";
WHEN "0011001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100000000000010011100100100101001110110011000010";
WHEN "0011010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011110110000000010011010001101000110110000011100";
WHEN "0011011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011101011111111101100001110111011111101010000000";
WHEN "0011100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011100010000000101011001000001011011100001111010";
WHEN "0011101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011011000000011010011101000010010101100000110110";
WHEN "0011110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011001110000111101001011001011110100111101110010";
WHEN "0011111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011000100001101110000000101001100000101000010010";
WHEN "0100000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010111010010101101011010100000110001110011110001";
WHEN "0100001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010110000011111011110101110000100111100111110101";
WHEN "0100010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010100110101011001101111010001011010010011110011";
WHEN "0100011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010011100111000111100011110100101110100010111000";
WHEN "0100100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010010011001000101110000000101001000110111000111";
WHEN "0100101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010001001011010100110000100110000001000100101001";
WHEN "0100110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001111111101110101000001110011010101110010001110";
WHEN "0100111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001110110000100111000000000001011111111100011001";
WHEN "0101000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001101100011101011000111011101000110011100100000";
WHEN "0101001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001100010111000001110100001010110001110100101001";
WHEN "0101010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001011001010101011100010000110111111111100011001";
WHEN "0101011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001001111110101000101101000101110111110101110110";
WHEN "0101100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001000110010111001110000110010111101100001101110";
WHEN "0101101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000111100111011111001000110001000101111011110000";
WHEN "0101110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000110011100011001010000011010001010111001000100";
WHEN "0101111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000101010001101000100010111110111111001010110011";
WHEN "0110000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000100000111001101011011100111000010100110100100";
WHEN "0110001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000010111101001000010101010000010110010001100101";
WHEN "0110010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000001110011011001101010101111010000110001110001";
WHEN "0110011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000000101010000001110110101110010010100010001010";
WHEN "0110100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111111100001000001010011101101111010001101110100";
WHEN "0110101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111110011000011000011100000100011001001100111111";
WHEN "0110110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111101010000000111101001111101101000001001100111";
WHEN "0110111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111100001000001111010111011010111011101000011000";
WHEN "0111000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111011000000101111111110010010111000110100000100";
WHEN "0111001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111001111001101001111000010001001010010011000111";
WHEN "0111010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111000110010111101011110110110010100111101001111";
WHEN "0111011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110111101100101011001011010111101100111001001111";
WHEN "0111100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110110100110110011010110111111001010011111110011";
WHEN "0111101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110101100001010110011010101010111111100100001011";
WHEN "0111110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110100011100010100101111001101101100100000011010";
WHEN "0111111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110011010111101110101101001101110101101001000101";
WHEN "1000000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110010010011100100101101000101111000100111000101";
WHEN "1000001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110001001111110111000111000100000001110100110010";
WHEN "1000010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110000001100100110010011001010000010000100100001";
WHEN "1000011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101111001001110010101001001101000100001000011111";
WHEN "1000100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101110000111011100100000110101100010100101111011";
WHEN "1000101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101101000101100100010001011110111101101010011001";
WHEN "1000110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101100000100001010010010010111110001001000100100";
WHEN "1000111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101011000011001110111010100001001010011011010001";
WHEN "1001000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101010000010110010100000101110111110101110111011";
WHEN "1001001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101001000010110101011011100111100001010010001010";
WHEN "1001010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101000000011011000000001100011011001101001101101";
WHEN "1001011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100111000100011010101000101101011010001111110100";
WHEN "1001100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100110000101111101100111000010010110110101001010";
WHEN "1001101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100101001000000001010010010000111011001100101001";
WHEN "1001110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100100001010100101111111111001100001111011011000";
WHEN "1001111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100011001101101100000101001110001011001110111100";
WHEN "1010000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100010010001010011110111010010010011111110100100";
WHEN "1010001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100001010101011101101010111010101100101110000010";
WHEN "1010010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100000011010001001110100101101010000111010011101";
WHEN "1010011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011111011111011000101001000000111110001110111111";
WHEN "1010100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011110100101001010011011111101101011111101000010";
WHEN "1010101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011101101011011111100001011100000010100000001101";
WHEN "1010110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011100110010011000001101000101010011000110001101";
WHEN "1010111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011011111001110100110010010011001111011110111011";
WHEN "1011000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011011000001110101100100010000000001110100011101";
WHEN "1011001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011010001010011010110101110110000100101001100010";
WHEN "1011010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011001010011100100111001101111111011000001100001";
WHEN "1011011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011000011101010100000010011000001000101101011001";
WHEN "1011100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010111100111101000100001111001001010100001001100";
WHEN "1011101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010110110010100010101010001101001110110001111011";
WHEN "1011110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010101111110000010101100111110001101111011011100";
WHEN "1011111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010101001010001000111011100101100011001011100101";
WHEN "1100000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010100010110110101100111001100000101011000010000";
WHEN "1100001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010011100100001001000000101001111111111010110011";
WHEN "1100010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010010110010000011011000100110101011110110000011";
WHEN "1100011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010010000000100100111111011000101001000001000001";
WHEN "1100100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010001001111101110000101000101010111011100100101";
WHEN "1100101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010000011111011110111001100001010000110000001000";
WHEN "1100110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001111101111110111101100001111100001101100011111";
WHEN "1100111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001111000000111000101100100010000011111010101010";
WHEN "1101000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001110010010100010001001011001010111110000100010";
WHEN "1101001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001101100100110100010001100100011110001100110110";
WHEN "1101010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001100110111101111010011100000110010111101110011";
WHEN "1101011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001100001011010011011101011010000110101111000110";
WHEN "1101100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001011011111100000111101001010011001011111101101";
WHEN "1101101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001010110100011000000000011001110101000000001010";
WHEN "1101110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001010001001111000110100011110100111011011010110";
WHEN "1101111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001001100000000011100110011100111110000011010110";
WHEN "1110000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001000110110111000100011000111000000001100101100";
WHEN "1110001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001000001110010111110110111100101010001100011100";
WHEN "1110010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000111100110100001101110001011101000100010101000";
WHEN "1110011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000110111111010110010100101111010011001100111001";
WHEN "1110100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000110011000110101110110010000101000111111101001";
WHEN "1110101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000101110011000000011110000110001011001010001101";
WHEN "1110110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000101001101110110010111010011111001000001110011";
WHEN "1110111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000100101001010111101100101011001011110111111001";
WHEN "1111000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000100000101100100101000101010110010110110110011";
WHEN "1111001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000011100010011101010101011110101111000111101111";
WHEN "1111010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000011000000000001111101000000010000000010001101";
WHEN "1111011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000010011110010010101000110101101111100100010110";
WHEN "1111100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000001111101001111100010010010101110110011110010";
WHEN "1111101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000001011100111000110010010111110010100110111110";
WHEN "1111110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000000111101001110100001110010100000011000001001";
WHEN "1111111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000000011110010000111000111101011011000001000111";
WHEN OTHERS =>
memoryC1_uid226_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110";
END CASE;
-- End reserved scope level
END PROCESS;
--cIncludingRoundingBit_uid252_sinPiZPolyEval(BITJOIN,251)@26
cIncludingRoundingBit_uid252_sinPiZPolyEval_q <= memoryC1_uid226_sinPiZTableGenerator_q & rndBit_uid245_sinPiZPolyEval_q;
--reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0(REG,388)@26
reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid252_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ts4_uid253_sinPiZPolyEval(ADD,252)@27
ts4_uid253_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((52 downto 52 => reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0_q(51)) & reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0_q);
ts4_uid253_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((52 downto 46 => reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1_q(45)) & reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1_q);
ts4_uid253_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid253_sinPiZPolyEval_a) + SIGNED(ts4_uid253_sinPiZPolyEval_b));
ts4_uid253_sinPiZPolyEval_q <= ts4_uid253_sinPiZPolyEval_o(52 downto 0);
--s4_uid254_sinPiZPolyEval(BITSELECT,253)@27
s4_uid254_sinPiZPolyEval_in <= ts4_uid253_sinPiZPolyEval_q;
s4_uid254_sinPiZPolyEval_b <= s4_uid254_sinPiZPolyEval_in(52 downto 1);
--yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval(BITSELECT,300)@27
yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_in <= s4_uid254_sinPiZPolyEval_b;
yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_b <= yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_in(51 downto 25);
--reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9(REG,389)@27
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor(LOGICAL,1092)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_b <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_q <= not (ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_a or ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_b);
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_mem_top(CONSTANT,1088)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_mem_top_q <= "010011";
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp(LOGICAL,1089)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_a <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_mem_top_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_a = ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg(REG,1090)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_q;
END IF;
END PROCESS;
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena(REG,1093)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd(LOGICAL,1094)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_a <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_b <= VCC_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_a and ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_b;
--xBottomBits_uid304_pT5_uid256_sinPiZPolyEval(BITSELECT,303)@6
xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b(17 downto 0);
xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b <= xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_in(17 downto 0);
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt(COUNTER,1084)
-- every=1, low=0, high=19, step=1, init=1
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i = 18 THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i - 19;
ELSE
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg(REG,1085)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux(MUX,1086)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_s <= VCC_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem(DUALMEM,1083)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ia <= xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 5,
numwords_a => 20,
width_b => 18,
widthad_b => 5,
numwords_b => 20,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_iq(17 downto 0);
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_outputreg(DELAY,1082)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_outputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_q, xout => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_outputreg_q, clk => clk, aclr => areset );
--pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval(BITJOIN,305)@28
pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--yBottomBits_uid303_pT5_uid256_sinPiZPolyEval(BITSELECT,302)@27
yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_in <= s4_uid254_sinPiZPolyEval_b(24 downto 0);
yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b <= yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_in(24 downto 0);
--ld_yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b_to_spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_a(DELAY,716)@27
ld_yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b_to_spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b, xout => ld_yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b_to_spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval(BITJOIN,304)@28
spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b_to_spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_a_q;
--pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval(BITJOIN,306)@28
pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_q <= spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_q & GND_q;
--reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6(REG,390)@28
reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor(LOGICAL,1079)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_b);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_mem_top(CONSTANT,1075)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_mem_top_q <= "010100";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp(LOGICAL,1076)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_mem_top_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg(REG,1077)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena(REG,1080)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd(LOGICAL,1081)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_b <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1071)
-- every=1, low=0, high=20, step=1, init=1
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i = 19 THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i - 20;
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i,5));
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg(REG,1072)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux(MUX,1073)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem(DUALMEM,1070)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid65_fpCosPiTest_b;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 5,
numwords_a => 21,
width_b => 45,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_iq(44 downto 0);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_outputreg(DELAY,1069)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset );
--xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval(BITSELECT,299)@29
xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_in <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_outputreg_q;
xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_b <= xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_in(44 downto 18);
--multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma(CHAINMULTADD,346)@29
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c(0);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c(1);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p(0),56);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p(1),56);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w(0);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w(1);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x(0);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x(1);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_b),28));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_q),28));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6_q),27));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9_q),27));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y(0);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y(1);
END IF;
END PROCESS;
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s(0),55));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval(BITSELECT,308)@32
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_in <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_q;
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_b <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_in(54 downto 1);
--highBBits_uid311_pT5_uid256_sinPiZPolyEval(BITSELECT,310)@32
highBBits_uid311_pT5_uid256_sinPiZPolyEval_in <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_b;
highBBits_uid311_pT5_uid256_sinPiZPolyEval_b <= highBBits_uid311_pT5_uid256_sinPiZPolyEval_in(53 downto 25);
--reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1(REG,392)@32
reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1_q <= highBBits_uid311_pT5_uid256_sinPiZPolyEval_b;
END IF;
END PROCESS;
--reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1(REG,391)@27
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q <= yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_b(DELAY,713)@28
ld_reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_b_q, clk => clk, aclr => areset );
--topProd_uid302_pT5_uid256_sinPiZPolyEval(MULT,301)@29
topProd_uid302_pT5_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid302_pT5_uid256_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid302_pT5_uid256_sinPiZPolyEval_b);
topProd_uid302_pT5_uid256_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid302_pT5_uid256_sinPiZPolyEval_a <= (others => '0');
topProd_uid302_pT5_uid256_sinPiZPolyEval_b <= (others => '0');
topProd_uid302_pT5_uid256_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid302_pT5_uid256_sinPiZPolyEval_a <= xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_b;
topProd_uid302_pT5_uid256_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_b_q;
topProd_uid302_pT5_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid302_pT5_uid256_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
topProd_uid302_pT5_uid256_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid302_pT5_uid256_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid302_pT5_uid256_sinPiZPolyEval_q <= topProd_uid302_pT5_uid256_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0(REG,393)@32
reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0_q <= topProd_uid302_pT5_uid256_sinPiZPolyEval_q;
END IF;
END PROCESS;
--sumAHighB_uid312_pT5_uid256_sinPiZPolyEval(ADD,311)@33
sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0_q(53)) & reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0_q);
sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1_q);
sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_b));
sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_q <= sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_o(54 downto 0);
--lowRangeB_uid310_pT5_uid256_sinPiZPolyEval(BITSELECT,309)@32
lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_in <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_b(24 downto 0);
lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b <= lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_in(24 downto 0);
--ld_lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b_to_add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_a(DELAY,724)@32
ld_lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b_to_add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b, xout => ld_lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b_to_add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--add0_uid310_uid313_pT5_uid256_sinPiZPolyEval(BITJOIN,312)@33
add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_q <= sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_q & ld_lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b_to_add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_a_q;
--R_uid314_pT5_uid256_sinPiZPolyEval(BITSELECT,313)@33
R_uid314_pT5_uid256_sinPiZPolyEval_in <= add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_q(78 downto 0);
R_uid314_pT5_uid256_sinPiZPolyEval_b <= R_uid314_pT5_uid256_sinPiZPolyEval_in(78 downto 25);
--reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1(REG,394)@33
reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1_q <= R_uid314_pT5_uid256_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor(LOGICAL,990)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_mem_top(CONSTANT,986)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_mem_top_q <= "011001";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp(LOGICAL,987)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_mem_top_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_q <= "1" when ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_a = ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_b else "0";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg(REG,988)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena(REG,991)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd(LOGICAL,992)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_b <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,982)
-- every=1, low=0, high=25, step=1, init=1
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i = 24 THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i - 25;
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i,5));
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg(REG,983)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux(MUX,984)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_s, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem(DUALMEM,981)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ia <= zAddr_uid64_fpCosPiTest_b;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_aa <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ab <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 26,
width_b => 7,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg(DELAY,980)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_q, xout => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC0_uid225_sinPiZTableGenerator(LOOKUP,224)@33
memoryC0_uid225_sinPiZTableGenerator: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg_q)
BEGIN
-- Begin reserved scope level
CASE (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg_q) IS
WHEN "0000000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000";
WHEN "0000001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010010000111010001111111001101111011000111100001001010";
WHEN "0000010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010010000101010101111101111010001101100110011111100100";
WHEN "0000011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010010000010000111010001110111000001110010011001110001";
WHEN "0000100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001111101100101111100010000110111011000000101000010";
WHEN "0000101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001110111110001111110110010110011100111000110011101";
WHEN "0000110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001110000101011011011100110100000100010100111010101";
WHEN "0000111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001101000010010010101010100001100000100101011101101";
WHEN "0001000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001011110100110101111000010100110110100001011000010";
WHEN "0001001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001010011101000101100010111000010101101001011110101";
WHEN "0001010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001000111011000010001010101010001011100000010111010";
WHEN "0001011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010000111001110101100010011111100010101010110110110111";
WHEN "0001100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010000101011000000100100110110100010000001101000110010";
WHEN "0001101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010000011010111001011101111001010100111001000011000110";
WHEN "0001110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010000001001100000010011100101010111111111101111100110";
WHEN "0001111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001111110110110101001100010110011100110010010101101111";
WHEN "0010000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001111100010111000001111000110100110100110000010101111";
WHEN "0010001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001111001101101001100011001110000111100101111100011100";
WHEN "0010010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001110110111001001010000100011011101100011000000101111";
WHEN "0010011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001110011111010111011111011011001110010110110010111000";
WHEN "0010100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001110000110010100011000101000000100011000111000100110";
WHEN "0010101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001101101100000000000101011010101010100111001000011100";
WHEN "0010110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001101010000011010101111100001101000100000101011011110";
WHEN "0010111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001100110011100100100001001001011101110011110100001011";
WHEN "0011000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001100010101011101100100111100011101111110101100100111";
WHEN "0011001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001011110110000110000110000010101011100010111110000011";
WHEN "0011010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001011010101011110010000000001110011001100010100001001";
WHEN "0011011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001010110011100110001110111101000110101001111110010101";
WHEN "0011100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001010010000011110001111010101010111011011010001011111";
WHEN "0011101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001001101100000110011110001000110001001111001100110001";
WHEN "0011110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001001000110011111001000110010110100010111000011111111";
WHEN "0011111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001000011111101000011101001100001111101100010010011001";
WHEN "0100000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000111110111100010101001101010111010101001011000110001";
WHEN "0100001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000111001110001101111101000001101110110110001001100100";
WHEN "0100010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000110100011101010100110100000100001100111000110001110";
WHEN "0100011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000101110111111000110101110011111101010000010000111000";
WHEN "0100100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000101001010111000111011000101011010001011010101011100";
WHEN "0100101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000100011100101011000110111010110111110001001101100111";
WHEN "0100110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000011101101001111101010010110110101000111000011000010";
WHEN "0100111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000010111100100110110110111000001001011110110011001101";
WHEN "0101000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000010001010110000111110011001111100101011011000101100";
WHEN "0101001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000001010111101110010011010011011111001000011101001111";
WHEN "0101010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000000100011011111001000011000000001110101111000110101";
WHEN "0101011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111111101110000011110000110110101110000111000001001000";
WHEN "0101100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111110110111011100100000011010011101000101101101101111";
WHEN "0101101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111101111111101001101011001001101111001001010100111010";
WHEN "0101110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111101000110101011100101100110100011000001100101000111";
WHEN "0101111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111100001100100010100100101110001100110101011111100110";
WHEN "0110000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111011010001001110111101111001001100110110011000001101";
WHEN "0110001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111010010100110001000110111011000110000110111110111111";
WHEN "0110010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111001010111001001010110000010010100110110110111111101";
WHEN "0110011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111000011000011000000001111000000100110010000101101101";
WHEN "0110100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110111011000011101100001100000000111000101001011011010";
WHEN "0110101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110110010111011010001100011000101000010101101011001001";
WHEN "0110110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110101010101001110011010011010000110001111000101001011";
WHEN "0110111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110100010001111010100011110111000101000100011101001111";
WHEN "0111000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110011001101011111000001011100000101000110101010111101";
WHEN "0111001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110010000111111100001100001111010111101111011010000110";
WHEN "0111010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110001000001010010011101110000110100100001000000010111";
WHEN "0111011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101111111001100010001111111001101101111011001101100100";
WHEN "0111100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101110110000101011111100111100100110000100111011101101";
WHEN "0111101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101101100110101111111111100101000011001011000100010101";
WHEN "0111110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101100011011101110110010110111100011110100100000110011";
WHEN "0111111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101011001111101000110010010001010011001011011010110110";
WHEN "1000000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101010000010011110011001100111111100111011110011001101";
WHEN "1000001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101000110100010000000101001001100001000111100100001001";
WHEN "1000010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100111100100111110010001011100000111110000000101011101";
WHEN "1000011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100110010100101001011011011101110100010101011000001110";
WHEN "1000100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100101000011010010000000100100011001001010111111110011";
WHEN "1000101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100011110000111000011110011101001010100010101110100101";
WHEN "1000110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100010011101011101010011001100110001101101001100010111";
WHEN "1000111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100001001001000000111101001110111111110000011100100111";
WHEN "1001000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011111110011100011111011010110100000010100101010111001";
WHEN "1001001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011110011101000110101100101100101100000111000011110001";
WHEN "1001010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011101000101101001110000110001011011010011000000110010";
WHEN "1001011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011011101101001101100111011010110111110001101101101010";
WHEN "1001100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011010010011110010110000110101001111010000001101101100";
WHEN "1001101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011000111001011001101101100010100101001100000111100110";
WHEN "1001110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010111011110000010111110011010100100100110111110110011";
WHEN "1001111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010110000001101111000100101010010001110000100000110101";
WHEN "1010000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010100100100011110100001110011111011100111101101011110";
WHEN "1010001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010011000110010001110111101110101101010011000000111111";
WHEN "1010010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010001100111001001101000100110011111001111100111000001";
WHEN "1010011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010000000111000110010110111011101000010111111101010001";
WHEN "1010100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101001110100110001000100101100010101111000001101101010100";
WHEN "1010101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101001101000100010000110111100100011001110011000100010010";
WHEN "1010110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101001011100001011111110000011101000000001111110000000000";
WHEN "1010111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101001001111101110101110011111100011011011101101000101110";
WHEN "1011000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101001000011001010011100110000101110110100001001110110000";
WHEN "1011001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101000110110011111001101011001111011110110010000011100000";
WHEN "1011010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101000101001101101000101000000010010100000111000101001110";
WHEN "1011011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101000011100110100001000001011001111000111011010101001101";
WHEN "1011100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101000001111110100011011100100100000010001010101111111000";
WHEN "1011101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101000000010101110000011111000000100111000111011110010110";
WHEN "1011110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100111110101100001000101110100001010001000111101001001101";
WHEN "1011111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100111101000001101100110001001001001011001011110100011010";
WHEN "1100000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100111011010110011101001101001100110001011110001011110000";
WHEN "1100001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100111001101010011010101001010001100000101010101000000111";
WHEN "1100010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100110111111101100101101100001101100101001111110101000001";
WHEN "1100011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100110110001111111110111101000111101010101001011110111000";
WHEN "1100100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100110100100001100111000011010110101010010011110001011110";
WHEN "1100101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100110010110010011110100110100001011010101000001111000001";
WHEN "1100110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100110001000010100110001110011110011101110100000111111001";
WHEN "1100111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100101111010001111110100011010011110000101000011010111010";
WHEN "1101000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100101101100000101000001101010110011001000011100110100101";
WHEN "1101001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100101011101110100011110101001010010100110101010011100110";
WHEN "1101010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100101001111011110010000011100010000111111100000000100011";
WHEN "1101011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100101000001000010011100001011110101010111100110111011100";
WHEN "1101100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100100110010100001000111000001110111001010101110101010001";
WHEN "1101101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100100100011111010010110001001111011111101010001100000100";
WHEN "1101110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100100010101001110001110110001010101001101001100111101111";
WHEN "1101111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100100000110011100110110000110111110000010001111110011101";
WHEN "1110000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100011110111100110010001011011011000111101011110100101010";
WHEN "1110001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100011101000101010100110000000101101101000001111101101101";
WHEN "1110010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100011011001101001111001001010100110100010100000001010111";
WHEN "1110011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100011001010100100010000001110001110110000100001110111001";
WHEN "1110100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100010111011011001110000100010001111101000000100110100000";
WHEN "1110101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100010101100001010011111011110101110011100111100001100101";
WHEN "1110110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100010011100110110100010011101001010001101000000010101011";
WHEN "1110111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100010001101011101111110111000011001001011101110101101100";
WHEN "1111000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100001111110000000111010001100100110101101001001001010110";
WHEN "1111001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100001101110011111011001110111010000110000010101010100001";
WHEN "1111010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100001011110111001100011010111000101101001011101010010011";
WHEN "1111011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100001001111001111011100001100000001101011010010111101001";
WHEN "1111100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100000111111100001001001110111001100110000010110101011110";
WHEN "1111101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100000101111101110110001111010111000000011100010110001010";
WHEN "1111110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100000011111111000011001111010011011101000011100101001111";
WHEN "1111111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100000001111111110000111011010010100000011001101000010011";
WHEN OTHERS =>
memoryC0_uid225_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000";
END CASE;
-- End reserved scope level
END PROCESS;
--rndBit_uid257_sinPiZPolyEval(CONSTANT,256)
rndBit_uid257_sinPiZPolyEval_q <= "001";
--cIncludingRoundingBit_uid258_sinPiZPolyEval(BITJOIN,257)@33
cIncludingRoundingBit_uid258_sinPiZPolyEval_q <= memoryC0_uid225_sinPiZTableGenerator_q & rndBit_uid257_sinPiZPolyEval_q;
--reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0(REG,395)@33
reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid258_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ts5_uid259_sinPiZPolyEval(ADD,258)@34
ts5_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0_q);
ts5_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((61 downto 54 => reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1_q(53)) & reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1_q);
ts5_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid259_sinPiZPolyEval_a) + SIGNED(ts5_uid259_sinPiZPolyEval_b));
ts5_uid259_sinPiZPolyEval_q <= ts5_uid259_sinPiZPolyEval_o(61 downto 0);
--s5_uid260_sinPiZPolyEval(BITSELECT,259)@34
s5_uid260_sinPiZPolyEval_in <= ts5_uid259_sinPiZPolyEval_q;
s5_uid260_sinPiZPolyEval_b <= s5_uid260_sinPiZPolyEval_in(61 downto 1);
--fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@34
fxpSinRes_uid67_fpCosPiTest_in <= s5_uid260_sinPiZPolyEval_b(58 downto 0);
fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(58 downto 5);
--mul2xSinRes_uid68_fpCosPiTest_b_1(BITSELECT,317)@34
mul2xSinRes_uid68_fpCosPiTest_b_1_in <= fxpSinRes_uid67_fpCosPiTest_b;
mul2xSinRes_uid68_fpCosPiTest_b_1_b <= mul2xSinRes_uid68_fpCosPiTest_b_1_in(53 downto 27);
--reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1(REG,400)@34
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1_q <= mul2xSinRes_uid68_fpCosPiTest_b_1_b;
END IF;
END PROCESS;
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor(LOGICAL,877)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_b <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_q <= not (ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_a or ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_b);
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_mem_top(CONSTANT,873)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_mem_top_q <= "010110";
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp(LOGICAL,874)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_a <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_mem_top_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_q);
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_q <= "1" when ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_a = ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_b else "0";
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg(REG,875)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg_q <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_q;
END IF;
END PROCESS;
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena(REG,878)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_q = "1") THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena_q <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd(LOGICAL,879)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_a <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_b <= VCC_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_q <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_a and ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_b;
--LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest(BITSELECT,219)@9
LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q(77 downto 0);
LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_in(77 downto 0);
--leftShiftStage3Idx1_uid221_alignedZ_uid59_fpCosPiTest(BITJOIN,220)@9
leftShiftStage3Idx1_uid221_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_b & GND_q;
--LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest(BITSELECT,214)@9
LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q(72 downto 0);
LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_in(72 downto 0);
--leftShiftStage2Idx3_uid216_alignedZ_uid59_fpCosPiTest(BITJOIN,215)@9
leftShiftStage2Idx3_uid216_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_b & leftShiftStage2Idx3Pad6_uid133_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest(BITSELECT,211)@9
LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx2_uid213_alignedZ_uid59_fpCosPiTest(BITJOIN,212)@9
leftShiftStage2Idx2_uid213_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_b & leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest(BITSELECT,208)@9
LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q(76 downto 0);
LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_in(76 downto 0);
--leftShiftStage2Idx1_uid210_alignedZ_uid59_fpCosPiTest(BITJOIN,209)@9
leftShiftStage2Idx1_uid210_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_b & leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest(BITSELECT,203)@9
LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q(54 downto 0);
LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_in(54 downto 0);
--leftShiftStage1Idx3_uid205_alignedZ_uid59_fpCosPiTest(BITJOIN,204)@9
leftShiftStage1Idx3_uid205_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_b & leftShiftStage1Idx3Pad24_uid122_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest(BITSELECT,200)@9
LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q(62 downto 0);
LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_in(62 downto 0);
--leftShiftStage1Idx2_uid202_alignedZ_uid59_fpCosPiTest(BITJOIN,201)@9
leftShiftStage1Idx2_uid202_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_b & leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest(BITSELECT,197)@9
LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q(70 downto 0);
LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_in(70 downto 0);
--leftShiftStage1Idx1_uid199_alignedZ_uid59_fpCosPiTest(BITJOIN,198)@9
leftShiftStage1Idx1_uid199_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_b & leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest_q;
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor(LOGICAL,954)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_b <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_q <= not (ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_a or ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_b);
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_mem_top(CONSTANT,950)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_mem_top_q <= "010";
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp(LOGICAL,951)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_a <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_mem_top_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q);
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_q <= "1" when ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_a = ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_b else "0";
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg(REG,952)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena(REG,955)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_q = "1") THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd(LOGICAL,956)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_a <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_b <= VCC_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_a and ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_b;
--vStage_uid148_lzcZ_uid58_fpCosPiTest(BITSELECT,147)@5
vStage_uid148_lzcZ_uid58_fpCosPiTest_in <= z_uid56_fpCosPiTest_b(14 downto 0);
vStage_uid148_lzcZ_uid58_fpCosPiTest_b <= vStage_uid148_lzcZ_uid58_fpCosPiTest_in(14 downto 0);
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt(COUNTER,946)
-- every=1, low=0, high=2, step=1, init=1
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i = 1 THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i - 2;
ELSE
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i,2));
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg(REG,947)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux(MUX,948)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_s <= VCC_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux: PROCESS (ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_s, ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q, ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem(DUALMEM,957)
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia <= vStage_uid148_lzcZ_uid58_fpCosPiTest_b;
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 2,
numwords_a => 3,
width_b => 15,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq(14 downto 0);
--leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest(BITJOIN,192)@9
leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_q <= ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest_q;
--X46dto0_uid189_alignedZ_uid59_fpCosPiTest(BITSELECT,188)@5
X46dto0_uid189_alignedZ_uid59_fpCosPiTest_in <= z_uid56_fpCosPiTest_b(46 downto 0);
X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b <= X46dto0_uid189_alignedZ_uid59_fpCosPiTest_in(46 downto 0);
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem(DUALMEM,945)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia <= X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 47,
widthad_a => 2,
numwords_a => 3,
width_b => 47,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq(46 downto 0);
--leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest(BITJOIN,189)@9
leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest_q;
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem(DUALMEM,970)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ia <= z_uid56_fpCosPiTest_b;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_aa <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ab <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 79,
widthad_a => 1,
numwords_a => 2,
width_b => 79,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_iq,
address_a => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_aa,
data_a => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ia
);
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_iq(78 downto 0);
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg(DELAY,969)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg : dspba_delay
GENERIC MAP ( width => 79, depth => 1 )
PORT MAP ( xin => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_q, xout => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg_q, clk => clk, aclr => areset );
--rVStage_uid145_lzcZ_uid58_fpCosPiTest(BITSELECT,144)@5
rVStage_uid145_lzcZ_uid58_fpCosPiTest_in <= z_uid56_fpCosPiTest_b;
rVStage_uid145_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid145_lzcZ_uid58_fpCosPiTest_in(78 downto 15);
--vCount_uid146_lzcZ_uid58_fpCosPiTest(LOGICAL,145)@5
vCount_uid146_lzcZ_uid58_fpCosPiTest_a <= rVStage_uid145_lzcZ_uid58_fpCosPiTest_b;
vCount_uid146_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest_q;
vCount_uid146_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid146_lzcZ_uid58_fpCosPiTest_a = vCount_uid146_lzcZ_uid58_fpCosPiTest_b else "0";
--ld_vCount_uid146_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_g(DELAY,595)@5
ld_vCount_uid146_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid146_lzcZ_uid58_fpCosPiTest_q, xout => ld_vCount_uid146_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_g_q, clk => clk, aclr => areset );
--mO_uid147_lzcZ_uid58_fpCosPiTest(CONSTANT,146)
mO_uid147_lzcZ_uid58_fpCosPiTest_q <= "1111111111111111111111111111111111111111111111111";
--cStage_uid149_lzcZ_uid58_fpCosPiTest(BITJOIN,148)@5
cStage_uid149_lzcZ_uid58_fpCosPiTest_q <= vStage_uid148_lzcZ_uid58_fpCosPiTest_b & mO_uid147_lzcZ_uid58_fpCosPiTest_q;
--vStagei_uid151_lzcZ_uid58_fpCosPiTest(MUX,150)@5
vStagei_uid151_lzcZ_uid58_fpCosPiTest_s <= vCount_uid146_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid151_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid151_lzcZ_uid58_fpCosPiTest_s, rVStage_uid145_lzcZ_uid58_fpCosPiTest_b, cStage_uid149_lzcZ_uid58_fpCosPiTest_q)
BEGIN
CASE vStagei_uid151_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid151_lzcZ_uid58_fpCosPiTest_q <= rVStage_uid145_lzcZ_uid58_fpCosPiTest_b;
WHEN "1" => vStagei_uid151_lzcZ_uid58_fpCosPiTest_q <= cStage_uid149_lzcZ_uid58_fpCosPiTest_q;
WHEN OTHERS => vStagei_uid151_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid153_lzcZ_uid58_fpCosPiTest(BITSELECT,152)@5
rVStage_uid153_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid151_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid153_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid153_lzcZ_uid58_fpCosPiTest_in(63 downto 32);
--reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0(REG,364)@5
reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0_q <= "00000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0_q <= rVStage_uid153_lzcZ_uid58_fpCosPiTest_b;
END IF;
END PROCESS;
--vCount_uid154_lzcZ_uid58_fpCosPiTest(LOGICAL,153)@6
vCount_uid154_lzcZ_uid58_fpCosPiTest_a <= reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0_q;
vCount_uid154_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest_q;
vCount_uid154_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid154_lzcZ_uid58_fpCosPiTest_a = vCount_uid154_lzcZ_uid58_fpCosPiTest_b else "0";
--ld_vCount_uid154_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_f(DELAY,594)@6
ld_vCount_uid154_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid154_lzcZ_uid58_fpCosPiTest_q, xout => ld_vCount_uid154_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_f_q, clk => clk, aclr => areset );
--vStage_uid155_lzcZ_uid58_fpCosPiTest(BITSELECT,154)@5
vStage_uid155_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid151_lzcZ_uid58_fpCosPiTest_q(31 downto 0);
vStage_uid155_lzcZ_uid58_fpCosPiTest_b <= vStage_uid155_lzcZ_uid58_fpCosPiTest_in(31 downto 0);
--ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d(DELAY,562)@5
ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid155_lzcZ_uid58_fpCosPiTest_b, xout => ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d_q, clk => clk, aclr => areset );
--ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c(DELAY,561)@5
ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid153_lzcZ_uid58_fpCosPiTest_b, xout => ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c_q, clk => clk, aclr => areset );
--vStagei_uid157_lzcZ_uid58_fpCosPiTest(MUX,156)@6
vStagei_uid157_lzcZ_uid58_fpCosPiTest_s <= vCount_uid154_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid157_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid157_lzcZ_uid58_fpCosPiTest_s, ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c_q, ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d_q)
BEGIN
CASE vStagei_uid157_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid157_lzcZ_uid58_fpCosPiTest_q <= ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid157_lzcZ_uid58_fpCosPiTest_q <= ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d_q;
WHEN OTHERS => vStagei_uid157_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid159_lzcZ_uid58_fpCosPiTest(BITSELECT,158)@6
rVStage_uid159_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid157_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid159_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid159_lzcZ_uid58_fpCosPiTest_in(31 downto 16);
--reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0(REG,365)@6
reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0_q <= "0000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0_q <= rVStage_uid159_lzcZ_uid58_fpCosPiTest_b;
END IF;
END PROCESS;
--vCount_uid160_lzcZ_uid58_fpCosPiTest(LOGICAL,159)@7
vCount_uid160_lzcZ_uid58_fpCosPiTest_a <= reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0_q;
vCount_uid160_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest_q;
vCount_uid160_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid160_lzcZ_uid58_fpCosPiTest_a = vCount_uid160_lzcZ_uid58_fpCosPiTest_b else "0";
--ld_vCount_uid160_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_e(DELAY,593)@7
ld_vCount_uid160_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid160_lzcZ_uid58_fpCosPiTest_q, xout => ld_vCount_uid160_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_e_q, clk => clk, aclr => areset );
--vStage_uid161_lzcZ_uid58_fpCosPiTest(BITSELECT,160)@6
vStage_uid161_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid157_lzcZ_uid58_fpCosPiTest_q(15 downto 0);
vStage_uid161_lzcZ_uid58_fpCosPiTest_b <= vStage_uid161_lzcZ_uid58_fpCosPiTest_in(15 downto 0);
--ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d(DELAY,568)@6
ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => vStage_uid161_lzcZ_uid58_fpCosPiTest_b, xout => ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d_q, clk => clk, aclr => areset );
--ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c(DELAY,567)@6
ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => rVStage_uid159_lzcZ_uid58_fpCosPiTest_b, xout => ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c_q, clk => clk, aclr => areset );
--vStagei_uid163_lzcZ_uid58_fpCosPiTest(MUX,162)@7
vStagei_uid163_lzcZ_uid58_fpCosPiTest_s <= vCount_uid160_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid163_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid163_lzcZ_uid58_fpCosPiTest_s, ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c_q, ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d_q)
BEGIN
CASE vStagei_uid163_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid163_lzcZ_uid58_fpCosPiTest_q <= ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid163_lzcZ_uid58_fpCosPiTest_q <= ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d_q;
WHEN OTHERS => vStagei_uid163_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid165_lzcZ_uid58_fpCosPiTest(BITSELECT,164)@7
rVStage_uid165_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid163_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid165_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid165_lzcZ_uid58_fpCosPiTest_in(15 downto 8);
--reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0(REG,366)@7
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0_q <= "00000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0_q <= rVStage_uid165_lzcZ_uid58_fpCosPiTest_b;
END IF;
END PROCESS;
--vCount_uid166_lzcZ_uid58_fpCosPiTest(LOGICAL,165)@8
vCount_uid166_lzcZ_uid58_fpCosPiTest_a <= reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0_q;
vCount_uid166_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest_q;
vCount_uid166_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid166_lzcZ_uid58_fpCosPiTest_a = vCount_uid166_lzcZ_uid58_fpCosPiTest_b else "0";
--vStage_uid167_lzcZ_uid58_fpCosPiTest(BITSELECT,166)@7
vStage_uid167_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid163_lzcZ_uid58_fpCosPiTest_q(7 downto 0);
vStage_uid167_lzcZ_uid58_fpCosPiTest_b <= vStage_uid167_lzcZ_uid58_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3(REG,367)@7
reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3_q <= "00000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3_q <= vStage_uid167_lzcZ_uid58_fpCosPiTest_b;
END IF;
END PROCESS;
--reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2(REG,368)@7
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2_q <= "00000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2_q <= rVStage_uid165_lzcZ_uid58_fpCosPiTest_b;
END IF;
END PROCESS;
--vStagei_uid169_lzcZ_uid58_fpCosPiTest(MUX,168)@8
vStagei_uid169_lzcZ_uid58_fpCosPiTest_s <= vCount_uid166_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid169_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid169_lzcZ_uid58_fpCosPiTest_s, reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2_q, reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid169_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid169_lzcZ_uid58_fpCosPiTest_q <= reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid169_lzcZ_uid58_fpCosPiTest_q <= reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid169_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid171_lzcZ_uid58_fpCosPiTest(BITSELECT,170)@8
rVStage_uid171_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid169_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid171_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid171_lzcZ_uid58_fpCosPiTest_in(7 downto 4);
--vCount_uid172_lzcZ_uid58_fpCosPiTest(LOGICAL,171)@8
vCount_uid172_lzcZ_uid58_fpCosPiTest_a <= rVStage_uid171_lzcZ_uid58_fpCosPiTest_b;
vCount_uid172_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest_q;
vCount_uid172_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid172_lzcZ_uid58_fpCosPiTest_a = vCount_uid172_lzcZ_uid58_fpCosPiTest_b else "0";
--vStage_uid173_lzcZ_uid58_fpCosPiTest(BITSELECT,172)@8
vStage_uid173_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid169_lzcZ_uid58_fpCosPiTest_q(3 downto 0);
vStage_uid173_lzcZ_uid58_fpCosPiTest_b <= vStage_uid173_lzcZ_uid58_fpCosPiTest_in(3 downto 0);
--vStagei_uid175_lzcZ_uid58_fpCosPiTest(MUX,174)@8
vStagei_uid175_lzcZ_uid58_fpCosPiTest_s <= vCount_uid172_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid175_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid175_lzcZ_uid58_fpCosPiTest_s, rVStage_uid171_lzcZ_uid58_fpCosPiTest_b, vStage_uid173_lzcZ_uid58_fpCosPiTest_b)
BEGIN
CASE vStagei_uid175_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid175_lzcZ_uid58_fpCosPiTest_q <= rVStage_uid171_lzcZ_uid58_fpCosPiTest_b;
WHEN "1" => vStagei_uid175_lzcZ_uid58_fpCosPiTest_q <= vStage_uid173_lzcZ_uid58_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid175_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid177_lzcZ_uid58_fpCosPiTest(BITSELECT,176)@8
rVStage_uid177_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid175_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid177_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid177_lzcZ_uid58_fpCosPiTest_in(3 downto 2);
--vCount_uid178_lzcZ_uid58_fpCosPiTest(LOGICAL,177)@8
vCount_uid178_lzcZ_uid58_fpCosPiTest_a <= rVStage_uid177_lzcZ_uid58_fpCosPiTest_b;
vCount_uid178_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest_q;
vCount_uid178_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid178_lzcZ_uid58_fpCosPiTest_a = vCount_uid178_lzcZ_uid58_fpCosPiTest_b else "0";
--vStage_uid179_lzcZ_uid58_fpCosPiTest(BITSELECT,178)@8
vStage_uid179_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid175_lzcZ_uid58_fpCosPiTest_q(1 downto 0);
vStage_uid179_lzcZ_uid58_fpCosPiTest_b <= vStage_uid179_lzcZ_uid58_fpCosPiTest_in(1 downto 0);
--vStagei_uid181_lzcZ_uid58_fpCosPiTest(MUX,180)@8
vStagei_uid181_lzcZ_uid58_fpCosPiTest_s <= vCount_uid178_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid181_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid181_lzcZ_uid58_fpCosPiTest_s, rVStage_uid177_lzcZ_uid58_fpCosPiTest_b, vStage_uid179_lzcZ_uid58_fpCosPiTest_b)
BEGIN
CASE vStagei_uid181_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid181_lzcZ_uid58_fpCosPiTest_q <= rVStage_uid177_lzcZ_uid58_fpCosPiTest_b;
WHEN "1" => vStagei_uid181_lzcZ_uid58_fpCosPiTest_q <= vStage_uid179_lzcZ_uid58_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid181_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid183_lzcZ_uid58_fpCosPiTest(BITSELECT,182)@8
rVStage_uid183_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid181_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid183_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid183_lzcZ_uid58_fpCosPiTest_in(1 downto 1);
--vCount_uid184_lzcZ_uid58_fpCosPiTest(LOGICAL,183)@8
vCount_uid184_lzcZ_uid58_fpCosPiTest_a <= rVStage_uid183_lzcZ_uid58_fpCosPiTest_b;
vCount_uid184_lzcZ_uid58_fpCosPiTest_b <= GND_q;
vCount_uid184_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid184_lzcZ_uid58_fpCosPiTest_a = vCount_uid184_lzcZ_uid58_fpCosPiTest_b else "0";
--r_uid185_lzcZ_uid58_fpCosPiTest(BITJOIN,184)@8
r_uid185_lzcZ_uid58_fpCosPiTest_q <= ld_vCount_uid146_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_g_q & ld_vCount_uid154_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_f_q & ld_vCount_uid160_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_e_q & vCount_uid166_lzcZ_uid58_fpCosPiTest_q & vCount_uid172_lzcZ_uid58_fpCosPiTest_q & vCount_uid178_lzcZ_uid58_fpCosPiTest_q & vCount_uid184_lzcZ_uid58_fpCosPiTest_q;
--leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest(BITSELECT,194)@8
leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_in <= r_uid185_lzcZ_uid58_fpCosPiTest_q;
leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_b <= leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_in(6 downto 5);
--reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1(REG,369)@8
reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1_q <= leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_b;
END IF;
END PROCESS;
--leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest(MUX,195)@9
leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_s <= reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1_q;
leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest: PROCESS (leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_s, ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg_q, leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_q, leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg_q;
WHEN "01" => leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q <= cstZwSwF_uid16_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest(BITSELECT,205)@8
leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_in <= r_uid185_lzcZ_uid58_fpCosPiTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1(REG,370)@8
reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1_q <= leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_b;
END IF;
END PROCESS;
--leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest(MUX,206)@9
leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_s <= reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1_q;
leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest: PROCESS (leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_s, leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q, leftShiftStage1Idx1_uid199_alignedZ_uid59_fpCosPiTest_q, leftShiftStage1Idx2_uid202_alignedZ_uid59_fpCosPiTest_q, leftShiftStage1Idx3_uid205_alignedZ_uid59_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q;
WHEN "01" => leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage1Idx1_uid199_alignedZ_uid59_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage1Idx2_uid202_alignedZ_uid59_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage1Idx3_uid205_alignedZ_uid59_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest(BITSELECT,216)@8
leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_in <= r_uid185_lzcZ_uid58_fpCosPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1(REG,371)@8
reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_b;
END IF;
END PROCESS;
--leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest(MUX,217)@9
leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1_q;
leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest: PROCESS (leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_s, leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q, leftShiftStage2Idx1_uid210_alignedZ_uid59_fpCosPiTest_q, leftShiftStage2Idx2_uid213_alignedZ_uid59_fpCosPiTest_q, leftShiftStage2Idx3_uid216_alignedZ_uid59_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage2Idx1_uid210_alignedZ_uid59_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage2Idx2_uid213_alignedZ_uid59_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage2Idx3_uid216_alignedZ_uid59_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest(BITSELECT,221)@8
leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_in <= r_uid185_lzcZ_uid58_fpCosPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_in(0 downto 0);
--reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1(REG,372)@8
reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1_q <= leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_b;
END IF;
END PROCESS;
--leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest(MUX,222)@9
leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_s <= reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1_q;
leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest: PROCESS (leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_s, leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q, leftShiftStage3Idx1_uid221_alignedZ_uid59_fpCosPiTest_q)
BEGIN
CASE leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_s IS
WHEN "0" => leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q;
WHEN "1" => leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage3Idx1_uid221_alignedZ_uid59_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_inputreg(DELAY,869)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 79, depth => 1 )
PORT MAP ( xin => leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q, xout => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_inputreg_q, clk => clk, aclr => areset );
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg(REG,872)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg_q <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt(COUNTER,871)
-- every=1, low=0, high=22, step=1, init=1
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i = 21 THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_eq = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i - 22;
ELSE
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i,5));
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem(DUALMEM,870)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_reset0 <= areset;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ia <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_inputreg_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_aa <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ab <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 79,
widthad_a => 5,
numwords_a => 23,
width_b => 79,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_q(0),
clocken0 => VCC_q(0),
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_iq,
address_a => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_aa,
data_a => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ia
);
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_q <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_iq(78 downto 0);
--alignedZLow_uid60_fpCosPiTest(BITSELECT,59)@34
alignedZLow_uid60_fpCosPiTest_in <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_q;
alignedZLow_uid60_fpCosPiTest_b <= alignedZLow_uid60_fpCosPiTest_in(78 downto 26);
--mul2xSinRes_uid68_fpCosPiTest_a_1(BITSELECT,315)@34
mul2xSinRes_uid68_fpCosPiTest_a_1_in <= STD_LOGIC_VECTOR("0" & alignedZLow_uid60_fpCosPiTest_b);
mul2xSinRes_uid68_fpCosPiTest_a_1_b <= mul2xSinRes_uid68_fpCosPiTest_a_1_in(53 downto 27);
--reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0(REG,401)@34
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0_q <= mul2xSinRes_uid68_fpCosPiTest_a_1_b;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_a1_b1(MULT,321)@35
mul2xSinRes_uid68_fpCosPiTest_a1_b1_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a1_b1_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a1_b1_b);
mul2xSinRes_uid68_fpCosPiTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b1_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a1_b1_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b1_a <= reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0_q;
mul2xSinRes_uid68_fpCosPiTest_a1_b1_b <= reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1_q;
mul2xSinRes_uid68_fpCosPiTest_a1_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_a1_b1_pr);
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b1_q <= mul2xSinRes_uid68_fpCosPiTest_a1_b1_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1(BITSELECT,328)@38
mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_in <= mul2xSinRes_uid68_fpCosPiTest_a1_b1_q(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_b <= mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_in(26 downto 0);
--reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1(REG,402)@34
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1_q <= mul2xSinRes_uid68_fpCosPiTest_b_1_b;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_a_0(BITSELECT,314)@34
mul2xSinRes_uid68_fpCosPiTest_a_0_in <= alignedZLow_uid60_fpCosPiTest_b(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_a_0_b <= mul2xSinRes_uid68_fpCosPiTest_a_0_in(26 downto 0);
--reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0(REG,403)@34
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0_q <= mul2xSinRes_uid68_fpCosPiTest_a_0_b;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_a0_b1(MULT,320)@35
mul2xSinRes_uid68_fpCosPiTest_a0_b1_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a0_b1_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a0_b1_b);
mul2xSinRes_uid68_fpCosPiTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b1_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a0_b1_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b1_a <= reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0_q;
mul2xSinRes_uid68_fpCosPiTest_a0_b1_b <= reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1_q;
mul2xSinRes_uid68_fpCosPiTest_a0_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_a0_b1_pr);
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b1_q <= mul2xSinRes_uid68_fpCosPiTest_a0_b1_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1(BITSELECT,326)@38
mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_in <= mul2xSinRes_uid68_fpCosPiTest_a0_b1_q(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_b <= mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_in(26 downto 0);
--mul2xSinRes_uid68_fpCosPiTest_zero_36(CONSTANT,331)
mul2xSinRes_uid68_fpCosPiTest_zero_36_q <= "000000000000000000000000000";
--mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2(BITJOIN,335)@38
mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2_q <= mul2xSinRes_uid68_fpCosPiTest_zero_36_q & mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_b & mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_b & mul2xSinRes_uid68_fpCosPiTest_zero_36_q;
--mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1(BITSELECT,327)@38
mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_in <= mul2xSinRes_uid68_fpCosPiTest_a0_b1_q;
mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_b <= mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_in(53 downto 27);
--mul2xSinRes_uid68_fpCosPiTest_b_0(BITSELECT,316)@34
mul2xSinRes_uid68_fpCosPiTest_b_0_in <= fxpSinRes_uid67_fpCosPiTest_b(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_b_0_b <= mul2xSinRes_uid68_fpCosPiTest_b_0_in(26 downto 0);
--reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1(REG,398)@34
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1_q <= mul2xSinRes_uid68_fpCosPiTest_b_0_b;
END IF;
END PROCESS;
--reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0(REG,399)@34
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0_q <= mul2xSinRes_uid68_fpCosPiTest_a_1_b;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_a1_b0(MULT,319)@35
mul2xSinRes_uid68_fpCosPiTest_a1_b0_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a1_b0_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a1_b0_b);
mul2xSinRes_uid68_fpCosPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b0_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a1_b0_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b0_a <= reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0_q;
mul2xSinRes_uid68_fpCosPiTest_a1_b0_b <= reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1_q;
mul2xSinRes_uid68_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_a1_b0_pr);
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b0_q <= mul2xSinRes_uid68_fpCosPiTest_a1_b0_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0(BITSELECT,324)@38
mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_in <= mul2xSinRes_uid68_fpCosPiTest_a1_b0_q(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_b <= mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_in(26 downto 0);
--mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1(BITJOIN,334)@38
mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1_q <= mul2xSinRes_uid68_fpCosPiTest_zero_36_q & mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_b & mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_b & mul2xSinRes_uid68_fpCosPiTest_zero_36_q;
--mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC(LOGICAL,339)@38
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_a <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_b <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_q <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_a and mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_b;
--mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1(BITSELECT,329)@38
mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_in <= mul2xSinRes_uid68_fpCosPiTest_a1_b1_q;
mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_b <= mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_in(53 downto 27);
--mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0(BITSELECT,325)@38
mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_in <= mul2xSinRes_uid68_fpCosPiTest_a1_b0_q;
mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_b <= mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_in(53 downto 27);
--reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1(REG,396)@34
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1_q <= mul2xSinRes_uid68_fpCosPiTest_b_0_b;
END IF;
END PROCESS;
--reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0(REG,397)@34
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0_q <= mul2xSinRes_uid68_fpCosPiTest_a_0_b;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_a0_b0(MULT,318)@35
mul2xSinRes_uid68_fpCosPiTest_a0_b0_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a0_b0_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a0_b0_b);
mul2xSinRes_uid68_fpCosPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b0_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a0_b0_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b0_a <= reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0_q;
mul2xSinRes_uid68_fpCosPiTest_a0_b0_b <= reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1_q;
mul2xSinRes_uid68_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_a0_b0_pr);
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b0_q <= mul2xSinRes_uid68_fpCosPiTest_a0_b0_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0(BITSELECT,323)@38
mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_in <= mul2xSinRes_uid68_fpCosPiTest_a0_b0_q;
mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_b <= mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_in(53 downto 27);
--mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0(BITSELECT,322)@38
mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_in <= mul2xSinRes_uid68_fpCosPiTest_a0_b0_q(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_b <= mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_in(26 downto 0);
--mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0(BITJOIN,333)@38
mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0_q <= mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_b & mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_b & mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_b & mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_b;
--mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC(LOGICAL,338)@38
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_a <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_b <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_q <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_a and mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_b;
--mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB(LOGICAL,337)@38
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_a <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_b <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_q <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_a and mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_b;
--mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne(LOGICAL,340)@38
mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_a <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_b <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_c <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_q <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_a or mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_b or mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_c;
--mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS(BITSELECT,341)@38
mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_in <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_q(106 downto 0);
mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_b <= mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_in(106 downto 0);
--mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_BJ(BITJOIN,342)@38
mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_BJ_q <= mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_b & GND_q;
--mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_b(BITJOIN,349)@38
mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_b_q <= GND_q & mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_BJ_q;
--mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b(BITSELECT,352)@38
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_in <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_b_q;
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_b <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_in(88 downto 0);
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_in(108 downto 89);
--mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne(LOGICAL,336)@38
mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_a <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_b <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_c <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_q <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_a xor mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_b xor mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_c;
--mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_a(BITJOIN,347)@38
mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_a_q <= GND_q & mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_q;
--mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a(BITSELECT,351)@38
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_in <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_a_q;
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_b <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_in(88 downto 0);
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_in(108 downto 89);
--mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2(ADD,353)@38
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_cin <= GND_q;
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_a <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_b) & '1';
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_b <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_b) & mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_cin(0);
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_a) + UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_b));
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_c(0) <= mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_o(90);
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q <= mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_o(89 downto 1);
--ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b(DELAY,788)@38
ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b : dspba_delay
GENERIC MAP ( width => 20, depth => 1 )
PORT MAP ( xin => mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c, xout => ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b_q, clk => clk, aclr => areset );
--ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a(DELAY,787)@38
ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a : dspba_delay
GENERIC MAP ( width => 20, depth => 1 )
PORT MAP ( xin => mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c, xout => ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a_q, clk => clk, aclr => areset );
--mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2(ADD,354)@39
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_cin <= mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_c;
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a_q) & '1';
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b_q) & mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_cin(0);
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a) + UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b));
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_q <= mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_o(20 downto 1);
--ld_mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_a(DELAY,790)@39
ld_mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_a : dspba_delay
GENERIC MAP ( width => 89, depth => 1 )
PORT MAP ( xin => mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q, xout => ld_mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_a_q, clk => clk, aclr => areset );
--mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q(BITJOIN,355)@40
mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_q <= mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_q & ld_mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_a_q;
--normBit_uid69_fpCosPiTest(BITSELECT,68)@40
normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_q(106 downto 0);
normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(106 downto 106);
--ld_normBit_uid69_fpCosPiTest_b_to_rndExpUpdate_uid74_uid75_fpCosPiTest_c(DELAY,462)@40
ld_normBit_uid69_fpCosPiTest_b_to_rndExpUpdate_uid74_uid75_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => normBit_uid69_fpCosPiTest_b, xout => ld_normBit_uid69_fpCosPiTest_b_to_rndExpUpdate_uid74_uid75_fpCosPiTest_c_q, clk => clk, aclr => areset );
--cstAllZWF_uid9_fpCosPiTest(CONSTANT,8)
cstAllZWF_uid9_fpCosPiTest_q <= "0000000000000000000000000000000000000000000000000000";
--rndExpUpdate_uid74_uid75_fpCosPiTest(BITJOIN,74)@41
rndExpUpdate_uid74_uid75_fpCosPiTest_q <= ld_normBit_uid69_fpCosPiTest_b_to_rndExpUpdate_uid74_uid75_fpCosPiTest_c_q & cstAllZWF_uid9_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,890)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b);
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,886)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "011100";
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,887)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,888)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,891)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,892)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= VCC_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b;
--reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,404)@8
reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "0000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid185_lzcZ_uid58_fpCosPiTest_q;
END IF;
END PROCESS;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,882)
-- every=1, low=0, high=28, step=1, init=1
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i = 27 THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i - 28;
ELSE
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,5));
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,883)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,884)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= VCC_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,881)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 29,
width_b => 7,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(6 downto 0);
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_outputreg(DELAY,880)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q, xout => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_outputreg_q, clk => clk, aclr => areset );
--cstBiasM1_uid11_fpCosPiTest(CONSTANT,10)
cstBiasM1_uid11_fpCosPiTest_q <= "01111111110";
--expHardCase_uid61_fpCosPiTest(SUB,60)@40
expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid11_fpCosPiTest_q);
expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000" & ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_outputreg_q);
expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b));
expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(11 downto 0);
--expP_uid62_fpCosPiTest(BITSELECT,61)@40
expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(10 downto 0);
expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(10 downto 0);
--highRes_uid70_fpCosPiTest(BITSELECT,69)@40
highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_q(105 downto 0);
highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(105 downto 53);
--lowRes_uid71_fpCosPiTest(BITSELECT,70)@40
lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_q(104 downto 0);
lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(104 downto 52);
--fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@40
fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b;
fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@40
expFracPreRnd_uid73_uid73_fpCosPiTest_q <= expP_uid62_fpCosPiTest_b & fracRCompPreRnd_uid72_fpCosPiTest_q;
--reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0(REG,405)@40
reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0_q <= expFracPreRnd_uid73_uid73_fpCosPiTest_q;
END IF;
END PROCESS;
--expFracComp_uid76_fpCosPiTest(ADD,75)@41
expFracComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0_q);
expFracComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000" & rndExpUpdate_uid74_uid75_fpCosPiTest_q);
expFracComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid76_fpCosPiTest_a) + UNSIGNED(expFracComp_uid76_fpCosPiTest_b));
expFracComp_uid76_fpCosPiTest_q <= expFracComp_uid76_fpCosPiTest_o(64 downto 0);
--expRComp_uid78_fpCosPiTest(BITSELECT,77)@41
expRComp_uid78_fpCosPiTest_in <= expFracComp_uid76_fpCosPiTest_q(63 downto 0);
expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(63 downto 53);
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor(LOGICAL,929)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_b <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_q <= not (ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_a or ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_b);
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_mem_top(CONSTANT,925)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_mem_top_q <= "0100100";
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp(LOGICAL,926)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_a <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_mem_top_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q);
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_q <= "1" when ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_a = ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_b else "0";
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg(REG,927)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena(REG,930)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_q = "1") THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd(LOGICAL,931)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_a <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_b <= VCC_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_a and ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_b;
--fracXIsZero_uid28_fpCosPiTest(LOGICAL,27)@0
fracXIsZero_uid28_fpCosPiTest_a <= fracX_uid7_fpCosPiTest_b;
fracXIsZero_uid28_fpCosPiTest_b <= cstAllZWF_uid9_fpCosPiTest_q;
fracXIsZero_uid28_fpCosPiTest_q <= "1" when fracXIsZero_uid28_fpCosPiTest_a = fracXIsZero_uid28_fpCosPiTest_b else "0";
--InvFracXIsZero_uid30_fpCosPiTest(LOGICAL,29)@0
InvFracXIsZero_uid30_fpCosPiTest_a <= fracXIsZero_uid28_fpCosPiTest_q;
InvFracXIsZero_uid30_fpCosPiTest_q <= not InvFracXIsZero_uid30_fpCosPiTest_a;
--expXIsMax_uid26_fpCosPiTest(LOGICAL,25)@0
expXIsMax_uid26_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsMax_uid26_fpCosPiTest_b <= cstAllOWE_uid8_fpCosPiTest_q;
expXIsMax_uid26_fpCosPiTest_q <= "1" when expXIsMax_uid26_fpCosPiTest_a = expXIsMax_uid26_fpCosPiTest_b else "0";
--And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest(LOGICAL,30)@0
And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_a <= expXIsMax_uid26_fpCosPiTest_q;
And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_b <= InvFracXIsZero_uid30_fpCosPiTest_q;
And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_q <= And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_a and And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_b;
--InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest(LOGICAL,31)@0
InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_q;
InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_q <= not InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_a;
--And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest(LOGICAL,28)@0
And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_a <= expXIsMax_uid26_fpCosPiTest_q;
And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_b <= fracXIsZero_uid28_fpCosPiTest_q;
And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_q <= And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_a and And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_b;
--InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest(LOGICAL,32)@0
InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_a <= And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_q;
InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_q <= not InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_a;
--expXIsZero_uid24_fpCosPiTest(LOGICAL,23)@0
expXIsZero_uid24_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsZero_uid24_fpCosPiTest_b <= cstAllZWE_uid22_fpCosPiTest_q;
expXIsZero_uid24_fpCosPiTest_q <= "1" when expXIsZero_uid24_fpCosPiTest_a = expXIsZero_uid24_fpCosPiTest_b else "0";
--InvExpXIsZero_uid34_fpCosPiTest(LOGICAL,33)@0
InvExpXIsZero_uid34_fpCosPiTest_a <= expXIsZero_uid24_fpCosPiTest_q;
InvExpXIsZero_uid34_fpCosPiTest_q <= not InvExpXIsZero_uid34_fpCosPiTest_a;
--And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest(LOGICAL,34)@0
And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_a <= InvExpXIsZero_uid34_fpCosPiTest_q;
And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_b <= InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_q;
And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_q <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_a and And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_b;
--And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest(LOGICAL,35)@0
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_a <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_q;
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_b <= InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_q;
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_a and And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_b;
END IF;
END PROCESS;
--ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a(DELAY,472)@1
ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q, xout => ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a_q, clk => clk, aclr => areset );
--xIsHalf_uid85_fpCosPiTest(LOGICAL,84)@2
xIsHalf_uid85_fpCosPiTest_a <= ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a_q;
xIsHalf_uid85_fpCosPiTest_b <= fxpXFracHalf_uid48_fpCosPiTest_q;
xIsHalf_uid85_fpCosPiTest_c <= InvCosXIsOne_uid79_fpCosPiTest_q;
xIsHalf_uid85_fpCosPiTest_d <= InvXEvenInt_uid83_fpCosPiTest_q;
xIsHalf_uid85_fpCosPiTest_q <= xIsHalf_uid85_fpCosPiTest_a and xIsHalf_uid85_fpCosPiTest_b and xIsHalf_uid85_fpCosPiTest_c and xIsHalf_uid85_fpCosPiTest_d;
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_inputreg(DELAY,919)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xIsHalf_uid85_fpCosPiTest_q, xout => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_inputreg_q, clk => clk, aclr => areset );
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt(COUNTER,921)
-- every=1, low=0, high=36, step=1, init=1
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i = 35 THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i - 36;
ELSE
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i,6));
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg(REG,922)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux(MUX,923)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_s <= VCC_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux: PROCESS (ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_s, ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q, ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem(DUALMEM,920)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ia <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_inputreg_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_aa <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ab <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 37,
width_b => 1,
widthad_b => 6,
numwords_b => 37,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_iq,
address_a => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_aa,
data_a => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ia
);
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_iq(0 downto 0);
--expRPostExc1_uid93_fpCosPiTest(MUX,92)@41
expRPostExc1_uid93_fpCosPiTest_s <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_q;
expRPostExc1_uid93_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid93_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
CASE expRPostExc1_uid93_fpCosPiTest_s IS
WHEN "0" => expRPostExc1_uid93_fpCosPiTest_q <= expRComp_uid78_fpCosPiTest_b;
WHEN "1" => expRPostExc1_uid93_fpCosPiTest_q <= cstAllZWE_uid22_fpCosPiTest_q;
WHEN OTHERS => expRPostExc1_uid93_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END PROCESS;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor(LOGICAL,1105)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_b <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_q <= not (ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_a or ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_b);
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_mem_top(CONSTANT,1101)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_mem_top_q <= "0100011";
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp(LOGICAL,1102)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_a <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_mem_top_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q);
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_q <= "1" when ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_a = ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_b else "0";
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg(REG,1103)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_q;
END IF;
END PROCESS;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena(REG,1106)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_q = "1") THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd(LOGICAL,1107)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_b <= VCC_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_a and ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_b;
--ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a(DELAY,481)@0
ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOne_uid38_fpCosPiTest_c, xout => ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a_q, clk => clk, aclr => areset );
--ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d(DELAY,484)@0
ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => expXIsZero_uid24_fpCosPiTest_q, xout => ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d_q, clk => clk, aclr => areset );
--reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0(REG,358)@1
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0_q <= fxpXFrac_uid45_fpCosPiTest_b;
END IF;
END PROCESS;
--fxpXFracZero_uid47_fpCosPiTest(LOGICAL,46)@2
fxpXFracZero_uid47_fpCosPiTest_a <= reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0_q;
fxpXFracZero_uid47_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstZwSwF_uid16_fpCosPiTest_q);
fxpXFracZero_uid47_fpCosPiTest_q <= "1" when fxpXFracZero_uid47_fpCosPiTest_a = fxpXFracZero_uid47_fpCosPiTest_b else "0";
--And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@2
And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_a <= fxpXFracZero_uid47_fpCosPiTest_q;
And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_b <= InvCosXIsOne_uid79_fpCosPiTest_q;
And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_q <= And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_a and And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_b;
--Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest(LOGICAL,80)@2
Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a <= ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a_q;
Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_b <= And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_q;
Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_q <= Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a or Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_b;
--xIsInt_uid82_fpCosPiTest(LOGICAL,81)@2
xIsInt_uid82_fpCosPiTest_a <= ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a_q;
xIsInt_uid82_fpCosPiTest_b <= Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_q;
xIsInt_uid82_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xIsInt_uid82_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
xIsInt_uid82_fpCosPiTest_q <= xIsInt_uid82_fpCosPiTest_a and xIsInt_uid82_fpCosPiTest_b;
END IF;
END PROCESS;
--or_uid95_fpCosPiTest(LOGICAL,94)@3
or_uid95_fpCosPiTest_a <= xIsInt_uid82_fpCosPiTest_q;
or_uid95_fpCosPiTest_b <= ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d_q;
or_uid95_fpCosPiTest_c <= ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a_q;
or_uid95_fpCosPiTest_q <= or_uid95_fpCosPiTest_a or or_uid95_fpCosPiTest_b or or_uid95_fpCosPiTest_c;
--excRNaN_uid86_fpCosPiTest(LOGICAL,85)@0
excRNaN_uid86_fpCosPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_q;
excRNaN_uid86_fpCosPiTest_b <= And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_q;
excRNaN_uid86_fpCosPiTest_q <= excRNaN_uid86_fpCosPiTest_a or excRNaN_uid86_fpCosPiTest_b;
--Or2ZeroExcRNaN_uid94_fpCosPiTest(LOGICAL,93)@0
Or2ZeroExcRNaN_uid94_fpCosPiTest_a <= GND_q;
Or2ZeroExcRNaN_uid94_fpCosPiTest_b <= excRNaN_uid86_fpCosPiTest_q;
Or2ZeroExcRNaN_uid94_fpCosPiTest_q <= Or2ZeroExcRNaN_uid94_fpCosPiTest_a or Or2ZeroExcRNaN_uid94_fpCosPiTest_b;
--ld_Or2ZeroExcRNaN_uid94_fpCosPiTest_q_to_join_uid96_fpCosPiTest_a(DELAY,496)@0
ld_Or2ZeroExcRNaN_uid94_fpCosPiTest_q_to_join_uid96_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => Or2ZeroExcRNaN_uid94_fpCosPiTest_q, xout => ld_Or2ZeroExcRNaN_uid94_fpCosPiTest_q_to_join_uid96_fpCosPiTest_a_q, clk => clk, aclr => areset );
--join_uid96_fpCosPiTest(BITJOIN,95)@3
join_uid96_fpCosPiTest_q <= or_uid95_fpCosPiTest_q & ld_Or2ZeroExcRNaN_uid94_fpCosPiTest_q_to_join_uid96_fpCosPiTest_a_q;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt(COUNTER,1097)
-- every=1, low=0, high=35, step=1, init=1
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i = 34 THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i - 35;
ELSE
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i,6));
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg(REG,1098)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux(MUX,1099)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_s <= VCC_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_s, ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q, ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem(DUALMEM,1096)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ia <= join_uid96_fpCosPiTest_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_aa <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ab <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 6,
numwords_a => 36,
width_b => 2,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ia
);
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_iq(1 downto 0);
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_outputreg(DELAY,1095)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_outputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_q, xout => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_outputreg_q, clk => clk, aclr => areset );
--reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1(REG,406)@41
reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_outputreg_q;
END IF;
END PROCESS;
--expRPostExc_uid97_fpCosPiTest(MUX,96)@42
expRPostExc_uid97_fpCosPiTest_s <= reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_q;
expRPostExc_uid97_fpCosPiTest: PROCESS (expRPostExc_uid97_fpCosPiTest_s, expRPostExc1_uid93_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid97_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid97_fpCosPiTest_q <= expRPostExc1_uid93_fpCosPiTest_q;
WHEN "01" => expRPostExc_uid97_fpCosPiTest_q <= cstAllOWE_uid8_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid97_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid97_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid97_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid89_fpCosPiTest(CONSTANT,88)
oneFracRPostExc2_uid89_fpCosPiTest_q <= "0000000000000000000000000000000000000000000000000001";
--fracRComp_uid77_fpCosPiTest(BITSELECT,76)@41
fracRComp_uid77_fpCosPiTest_in <= expFracComp_uid76_fpCosPiTest_q(52 downto 0);
fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(52 downto 1);
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor(LOGICAL,903)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_b <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_q <= not (ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_a or ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_b);
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_mem_top(CONSTANT,899)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_mem_top_q <= "0100010";
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp(LOGICAL,900)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_a <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_mem_top_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q);
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_q <= "1" when ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_a = ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_b else "0";
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg(REG,901)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena(REG,904)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_q = "1") THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd(LOGICAL,905)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_a <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_b <= VCC_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_a and ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_b;
--reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4(REG,360)@2
reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4_q <= xIsHalf_uid85_fpCosPiTest_q;
END IF;
END PROCESS;
--ld_fxpXFracHalf_uid48_fpCosPiTest_q_to_or_uid87_fpCosPiTest_c(DELAY,483)@2
ld_fxpXFracHalf_uid48_fpCosPiTest_q_to_or_uid87_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fxpXFracHalf_uid48_fpCosPiTest_q, xout => ld_fxpXFracHalf_uid48_fpCosPiTest_q_to_or_uid87_fpCosPiTest_c_q, clk => clk, aclr => areset );
--or_uid87_fpCosPiTest(LOGICAL,86)@3
or_uid87_fpCosPiTest_a <= ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a_q;
or_uid87_fpCosPiTest_b <= xIsInt_uid82_fpCosPiTest_q;
or_uid87_fpCosPiTest_c <= ld_fxpXFracHalf_uid48_fpCosPiTest_q_to_or_uid87_fpCosPiTest_c_q;
or_uid87_fpCosPiTest_d <= ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d_q;
or_uid87_fpCosPiTest_e <= reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4_q;
or_uid87_fpCosPiTest_f <= GND_q;
or_uid87_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
or_uid87_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
or_uid87_fpCosPiTest_q <= or_uid87_fpCosPiTest_a or or_uid87_fpCosPiTest_b or or_uid87_fpCosPiTest_c or or_uid87_fpCosPiTest_d or or_uid87_fpCosPiTest_e or or_uid87_fpCosPiTest_f;
END IF;
END PROCESS;
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt(COUNTER,895)
-- every=1, low=0, high=34, step=1, init=1
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i = 33 THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i - 34;
ELSE
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i,6));
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg(REG,896)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux(MUX,897)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_s <= VCC_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux: PROCESS (ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_s, ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q, ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem(DUALMEM,894)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ia <= or_uid87_fpCosPiTest_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_aa <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ab <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 35,
width_b => 1,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_iq,
address_a => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_aa,
data_a => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ia
);
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_iq(0 downto 0);
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_outputreg(DELAY,893)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_outputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_q, xout => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_outputreg_q, clk => clk, aclr => areset );
--fracRPostExc1_uid88_fpCosPiTest(MUX,87)@41
fracRPostExc1_uid88_fpCosPiTest_s <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_outputreg_q;
fracRPostExc1_uid88_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid88_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
CASE fracRPostExc1_uid88_fpCosPiTest_s IS
WHEN "0" => fracRPostExc1_uid88_fpCosPiTest_q <= fracRComp_uid77_fpCosPiTest_b;
WHEN "1" => fracRPostExc1_uid88_fpCosPiTest_q <= cstAllZWF_uid9_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc1_uid88_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_nor(LOGICAL,853)
ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q;
ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b);
--ld_xIn_v_to_xOut_v_mem_top(CONSTANT,849)
ld_xIn_v_to_xOut_v_mem_top_q <= "0100111";
--ld_xIn_v_to_xOut_v_cmp(LOGICAL,850)
ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q;
ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q);
ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0";
--ld_xIn_v_to_xOut_v_cmpReg(REG,851)
ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_sticky_ena(REG,854)
ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN
ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,855)
ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q;
ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q;
ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b;
--ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,906)
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid86_fpCosPiTest_q, xout => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_inputreg_q, clk => clk, aclr => areset );
--ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,845)
-- every=1, low=0, high=39, step=1, init=1
ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 38 THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 39;
ELSE
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,6));
--ld_xIn_v_to_xOut_v_replace_rdreg(REG,846)
ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_replace_rdmux(MUX,847)
ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q;
ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q)
BEGIN
CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS
WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,907)
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_inputreg_q;
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_iq,
address_a => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_aa,
data_a => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ia
);
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(0 downto 0);
--fracRPostExc_uid90_fpCosPiTest(MUX,89)@42
fracRPostExc_uid90_fpCosPiTest_s <= ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_q;
fracRPostExc_uid90_fpCosPiTest: PROCESS (fracRPostExc_uid90_fpCosPiTest_s, fracRPostExc1_uid88_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid90_fpCosPiTest_s IS
WHEN "0" => fracRPostExc_uid90_fpCosPiTest_q <= fracRPostExc1_uid88_fpCosPiTest_q;
WHEN "1" => fracRPostExc_uid90_fpCosPiTest_q <= oneFracRPostExc2_uid89_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid90_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid104_fpCosPiTest(BITJOIN,103)@42
R_uid104_fpCosPiTest_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_q & expRPostExc_uid97_fpCosPiTest_q & fracRPostExc_uid90_fpCosPiTest_q;
--ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,857)
ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset;
ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c;
ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 40,
width_b => 8,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_c_to_xOut_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_c_to_xOut_c_replace_mem_iq,
address_a => ld_xIn_c_to_xOut_c_replace_mem_aa,
data_a => ld_xIn_c_to_xOut_c_replace_mem_ia
);
ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0);
--ld_xIn_c_to_xOut_c_outputreg(DELAY,856)
ld_xIn_c_to_xOut_c_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset );
--ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,844)
ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset;
ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v;
ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_v_to_xOut_v_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_v_to_xOut_v_replace_mem_iq,
address_a => ld_xIn_v_to_xOut_v_replace_mem_aa,
data_a => ld_xIn_v_to_xOut_v_replace_mem_ia
);
ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0);
--ld_xIn_v_to_xOut_v_outputreg(DELAY,843)
ld_xIn_v_to_xOut_v_outputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset );
--xOut(PORTOUT,4)@42
xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q;
xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q;
xOut_0 <= R_uid104_fpCosPiTest_q;
end normal;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/SqrtDPStratixVf400.vhd | 10 | 437207 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Debug Version 12.0
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from SqrtDPStratixVf400
-- VHDL created on Wed Sep 05 17:57:41 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
USE work.SqrtDPStratixVf400_safe_path.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
-- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240
entity SqrtDPStratixVf400 is
port (
xIn_v : in std_logic_vector(0 downto 0);
xIn_c : in std_logic_vector(7 downto 0);
xIn_0 : in std_logic_vector(63 downto 0);
xOut_v : out std_logic_vector(0 downto 0);
xOut_c : out std_logic_vector(7 downto 0);
xOut_0 : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic;
bus_clk : in std_logic;
h_areset : in std_logic
);
end;
architecture normal of SqrtDPStratixVf400 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cst0_uid10_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal bias_q : std_logic_vector (10 downto 0);
signal biasP1_q : std_logic_vector (10 downto 0);
signal expAllZeros_uid39_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal fracNaN_uid44_fpSqrtTest_q : std_logic_vector (51 downto 0);
signal fracInf_uid45_fpSqrtTest_q : std_logic_vector (51 downto 0);
signal memoryC2_uid52_sqrtTableGenerator_q : std_logic_vector(39 downto 0);
signal memoryC3_uid53_sqrtTableGenerator_q : std_logic_vector(32 downto 0);
signal memoryC4_uid54_sqrtTableGenerator_q : std_logic_vector(23 downto 0);
signal memoryC5_uid55_sqrtTableGenerator_q : std_logic_vector(16 downto 0);
signal rndBit_uid76_sqrtPolynomialEvaluator_q : std_logic_vector (1 downto 0);
signal rndBit_uid82_sqrtPolynomialEvaluator_q : std_logic_vector (2 downto 0);
signal prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_a : std_logic_vector (16 downto 0);
signal prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0);
signal prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_pr : SIGNED (34 downto 0);
signal prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0);
signal prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a : std_logic_vector (23 downto 0);
signal prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0);
signal prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_s1 : std_logic_vector (49 downto 0);
signal prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_pr : SIGNED (50 downto 0);
signal prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_q : std_logic_vector (49 downto 0);
signal prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a : std_logic_vector (32 downto 0);
signal prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0);
signal prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_s1 : std_logic_vector (67 downto 0);
signal prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_pr : SIGNED (68 downto 0);
signal prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_q : std_logic_vector (67 downto 0);
signal topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0);
signal topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0);
signal topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0);
signal topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0);
signal topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_a : std_logic_vector (26 downto 0);
signal topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_s1 : std_logic_vector (53 downto 0);
signal topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_pr : SIGNED (54 downto 0);
signal topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_q : std_logic_vector (53 downto 0);
type multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a : multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a_type;
type multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c : multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c_type;
type multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_p : multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_p_type;
type multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_w : multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_w_type;
type multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_x : multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_x_type;
type multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_y : multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_y_type;
type multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s : multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s_type;
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a : multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a_type;
type multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c : multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c_type;
type multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_p : multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_p_type;
type multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_w : multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_w_type;
type multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_x : multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_x_type;
type multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_y : multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_y_type;
type multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s : multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s_type;
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_q : std_logic_vector (54 downto 0);
signal reg_fracSelIn_uid42_fpSqrtTest_0_to_fracSel_uid43_fpSqrtTest_0_q : std_logic_vector (3 downto 0);
signal reg_s1_uid58_uid61_sqrtPolynomialEvaluator_0_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0);
signal reg_highBBits_uid65_sqrtPolynomialEvaluator_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_1_q : std_logic_vector (25 downto 0);
signal reg_s2_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_1_q : std_logic_vector (34 downto 0);
signal reg_highBBits_uid71_sqrtPolynomialEvaluator_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_1_q : std_logic_vector (32 downto 0);
signal reg_yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (17 downto 0);
signal reg_yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_0_to_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid112_pT4_uid75_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_1_q : std_logic_vector (42 downto 0);
signal reg_cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_0_q : std_logic_vector (50 downto 0);
signal reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_9_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_6_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid127_pT5_uid81_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_1_q : std_logic_vector (52 downto 0);
signal reg_cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_0_q : std_logic_vector (59 downto 0);
signal reg_fracR_uid35_fpSqrtTest_0_to_fracRPostExc_uid47_fpSqrtTest_3_q : std_logic_vector (51 downto 0);
signal ld_xIn_0_to_X44dto0_uid33_fpSqrtTest_a_q : std_logic_vector (63 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC4_uid54_sqrtTableGenerator_a_q : std_logic_vector (7 downto 0);
signal ld_lowRangeB_uid64_sqrtPolynomialEvaluator_b_to_s2_uid64_uid67_sqrtPolynomialEvaluator_a_q : std_logic_vector (0 downto 0);
signal ld_lowRangeB_uid70_sqrtPolynomialEvaluator_b_to_s3_uid70_uid73_sqrtPolynomialEvaluator_a_q : std_logic_vector (0 downto 0);
signal ld_lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b_to_add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_a_q : std_logic_vector (5 downto 0);
signal ld_reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b_to_spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_a_q : std_logic_vector (23 downto 0);
signal ld_lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b_to_add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_a_q : std_logic_vector (23 downto 0);
signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic;
signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic;
signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic;
signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_outputreg_q : std_logic_vector (1 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_ir : std_logic_vector (1 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_eq : std_logic;
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_ir : std_logic_vector (10 downto 0);
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_outputreg_q : std_logic_vector (0 downto 0);
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_reset0 : std_logic;
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_ir : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_ir : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_ir : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_ir : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_outputreg_q : std_logic_vector (23 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_ir : std_logic_vector (23 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_outputreg_q : std_logic_vector (32 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_ir : std_logic_vector (32 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_reset0 : std_logic;
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_eq : std_logic;
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_outputreg_q : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_ir : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0);
signal pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_q : std_logic_vector (26 downto 0);
signal fracSel_uid43_fpSqrtTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid47_fpSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid47_fpSqrtTest_q : std_logic_vector (51 downto 0);
signal memoryC0_uid50_sqrtTableGenerator_q : std_logic_vector(56 downto 0);
signal memoryC1_uid51_sqrtTableGenerator_q : std_logic_vector(48 downto 0);
signal sumAHighB_uid66_sqrtPolynomialEvaluator_a : std_logic_vector(33 downto 0);
signal sumAHighB_uid66_sqrtPolynomialEvaluator_b : std_logic_vector(33 downto 0);
signal sumAHighB_uid66_sqrtPolynomialEvaluator_o : std_logic_vector (33 downto 0);
signal sumAHighB_uid66_sqrtPolynomialEvaluator_q : std_logic_vector (33 downto 0);
signal sumAHighB_uid72_sqrtPolynomialEvaluator_a : std_logic_vector(40 downto 0);
signal sumAHighB_uid72_sqrtPolynomialEvaluator_b : std_logic_vector(40 downto 0);
signal sumAHighB_uid72_sqrtPolynomialEvaluator_o : std_logic_vector (40 downto 0);
signal sumAHighB_uid72_sqrtPolynomialEvaluator_q : std_logic_vector (40 downto 0);
signal ts4_uid78_sqrtPolynomialEvaluator_a : std_logic_vector(51 downto 0);
signal ts4_uid78_sqrtPolynomialEvaluator_b : std_logic_vector(51 downto 0);
signal ts4_uid78_sqrtPolynomialEvaluator_o : std_logic_vector (51 downto 0);
signal ts4_uid78_sqrtPolynomialEvaluator_q : std_logic_vector (51 downto 0);
signal ts5_uid84_sqrtPolynomialEvaluator_a : std_logic_vector(60 downto 0);
signal ts5_uid84_sqrtPolynomialEvaluator_b : std_logic_vector(60 downto 0);
signal ts5_uid84_sqrtPolynomialEvaluator_o : std_logic_vector (60 downto 0);
signal ts5_uid84_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0);
signal sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_q : std_logic_vector (54 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_q : std_logic_vector(0 downto 0);
signal expX_uid6_fpSqrtTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpSqrtTest_b : std_logic_vector (10 downto 0);
signal fracX_uid7_fpSqrtTest_in : std_logic_vector (51 downto 0);
signal fracX_uid7_fpSqrtTest_b : std_logic_vector (51 downto 0);
signal signX_uid8_fpSqrtTest_in : std_logic_vector (63 downto 0);
signal signX_uid8_fpSqrtTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid31_fpSqrtTest_in : std_logic_vector (51 downto 0);
signal fracXAddr_uid31_fpSqrtTest_b : std_logic_vector (6 downto 0);
signal cmpEQ_w11_uid11_fpSqrtTest_a : std_logic_vector(10 downto 0);
signal cmpEQ_w11_uid11_fpSqrtTest_b : std_logic_vector(10 downto 0);
signal cmpEQ_w11_uid11_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid22_fpSqrtTest_a : std_logic_vector(11 downto 0);
signal expEvenSig_uid22_fpSqrtTest_b : std_logic_vector(11 downto 0);
signal expEvenSig_uid22_fpSqrtTest_o : std_logic_vector (11 downto 0);
signal expEvenSig_uid22_fpSqrtTest_q : std_logic_vector (11 downto 0);
signal expOddSig_uid25_fpSqrtTest_a : std_logic_vector(11 downto 0);
signal expOddSig_uid25_fpSqrtTest_b : std_logic_vector(11 downto 0);
signal expOddSig_uid25_fpSqrtTest_o : std_logic_vector (11 downto 0);
signal expOddSig_uid25_fpSqrtTest_q : std_logic_vector (11 downto 0);
signal cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_q : std_logic_vector (50 downto 0);
signal cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_q : std_logic_vector (59 downto 0);
signal prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator_in : std_logic_vector (49 downto 0);
signal prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator_in : std_logic_vector (67 downto 0);
signal prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator_b : std_logic_vector (33 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (34 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (52 downto 0);
signal X44dto0_uid33_fpSqrtTest_in : std_logic_vector (44 downto 0);
signal X44dto0_uid33_fpSqrtTest_b : std_logic_vector (44 downto 0);
signal s2_uid64_uid67_sqrtPolynomialEvaluator_q : std_logic_vector (34 downto 0);
signal s3_uid70_uid73_sqrtPolynomialEvaluator_q : std_logic_vector (41 downto 0);
signal add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_q : std_logic_vector (60 downto 0);
signal add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_q : std_logic_vector (78 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(5 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(5 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal RSqrt_uid48_fpSqrtTest_q : std_logic_vector (63 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid74_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT4_uid74_sqrtPolynomialEvaluator_b : std_logic_vector (39 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_q : std_logic_vector(0 downto 0);
signal s4_uid79_sqrtPolynomialEvaluator_in : std_logic_vector (51 downto 0);
signal s4_uid79_sqrtPolynomialEvaluator_b : std_logic_vector (50 downto 0);
signal s5_uid85_sqrtPolynomialEvaluator_in : std_logic_vector (60 downto 0);
signal s5_uid85_sqrtPolynomialEvaluator_b : std_logic_vector (59 downto 0);
signal expZ_uid9_fpSqrtTest_a : std_logic_vector(10 downto 0);
signal expZ_uid9_fpSqrtTest_b : std_logic_vector(10 downto 0);
signal expZ_uid9_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expX0_uid27_fpSqrtTest_in : std_logic_vector (0 downto 0);
signal expX0_uid27_fpSqrtTest_b : std_logic_vector (0 downto 0);
signal fracIsZero_uid12_fpSqrtTest_a : std_logic_vector(51 downto 0);
signal fracIsZero_uid12_fpSqrtTest_b : std_logic_vector(51 downto 0);
signal fracIsZero_uid12_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal excMZero_uid13_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal excMZero_uid13_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal excMZero_uid13_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal excInf_uid14_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal excInf_uid14_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal excInf_uid14_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expREven_uid23_fpSqrtTest_in : std_logic_vector (11 downto 0);
signal expREven_uid23_fpSqrtTest_b : std_logic_vector (10 downto 0);
signal expROdd_uid26_fpSqrtTest_in : std_logic_vector (11 downto 0);
signal expROdd_uid26_fpSqrtTest_b : std_logic_vector (10 downto 0);
signal lowRangeB_uid58_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid58_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid59_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0);
signal highBBits_uid59_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0);
signal lowRangeB_uid64_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid64_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid65_sqrtPolynomialEvaluator_in : std_logic_vector (26 downto 0);
signal highBBits_uid65_sqrtPolynomialEvaluator_b : std_logic_vector (25 downto 0);
signal lowRangeB_uid70_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid70_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid71_sqrtPolynomialEvaluator_in : std_logic_vector (33 downto 0);
signal highBBits_uid71_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0);
signal lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (5 downto 0);
signal lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (5 downto 0);
signal highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (34 downto 0);
signal highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (52 downto 0);
signal highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (28 downto 0);
signal yT1_uid56_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT1_uid56_sqrtPolynomialEvaluator_b : std_logic_vector (16 downto 0);
signal yT2_uid62_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT2_uid62_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal yT3_uid68_sqrtPolynomialEvaluator_in : std_logic_vector (44 downto 0);
signal yT3_uid68_sqrtPolynomialEvaluator_b : std_logic_vector (32 downto 0);
signal xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (17 downto 0);
signal xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0);
signal yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid100_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (14 downto 0);
signal yBottomBits_uid100_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (14 downto 0);
signal yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (41 downto 0);
signal yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal R_uid112_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (59 downto 0);
signal R_uid112_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (42 downto 0);
signal R_uid127_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (77 downto 0);
signal R_uid127_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (52 downto 0);
signal xTop27Bits_uid96_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0);
signal xTop27Bits_uid96_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid99_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (39 downto 0);
signal xTop18Bits_uid99_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid101_pT4_uid75_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal xBottomBits_uid101_pT4_uid75_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (50 downto 0);
signal yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal fracR_uid35_fpSqrtTest_in : std_logic_vector (56 downto 0);
signal fracR_uid35_fpSqrtTest_b : std_logic_vector (51 downto 0);
signal expOddSelect_uid28_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid28_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracIsZero_uid16_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracIsZero_uid16_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExcMZero_uid18_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExcMZero_uid18_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal expRMux_uid29_fpSqrtTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid29_fpSqrtTest_q : std_logic_vector (10 downto 0);
signal sumAHighB_uid60_sqrtPolynomialEvaluator_a : std_logic_vector(24 downto 0);
signal sumAHighB_uid60_sqrtPolynomialEvaluator_b : std_logic_vector(24 downto 0);
signal sumAHighB_uid60_sqrtPolynomialEvaluator_o : std_logic_vector (24 downto 0);
signal sumAHighB_uid60_sqrtPolynomialEvaluator_q : std_logic_vector (24 downto 0);
signal spad_yBottomBits_uid100_uid103_pT4_uid75_sqrtPolynomialEvaluator_q : std_logic_vector (15 downto 0);
signal pad_xBottomBits_uid101_uid104_pT4_uid75_sqrtPolynomialEvaluator_q : std_logic_vector (16 downto 0);
signal addrTable_uid32_fpSqrtTest_q : std_logic_vector (7 downto 0);
signal excNaN_uid17_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal excNaN_uid17_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal excNaN_uid17_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal operandIsNegative_uid19_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal operandIsNegative_uid19_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal operandIsNegative_uid19_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid58_uid61_sqrtPolynomialEvaluator_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_q : std_logic_vector (17 downto 0);
signal join_uid41_fpSqrtTest_q : std_logic_vector (2 downto 0);
signal expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_a : std_logic_vector(0 downto 0);
signal expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_b : std_logic_vector(0 downto 0);
signal expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_q : std_logic_vector(0 downto 0);
signal fracSelIn_uid42_fpSqrtTest_q : std_logic_vector (3 downto 0);
signal join_uid36_fpSqrtTest_q : std_logic_vector (1 downto 0);
signal expRPostExc_uid40_fpSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid40_fpSqrtTest_q : std_logic_vector (10 downto 0);
begin
--ld_xIn_v_to_xOut_v_notEnable(LOGICAL,317)
ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q;
ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a;
--ld_xIn_v_to_xOut_v_nor(LOGICAL,318)
ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q;
ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b);
--ld_xIn_v_to_xOut_v_mem_top(CONSTANT,314)
ld_xIn_v_to_xOut_v_mem_top_q <= "011001";
--ld_xIn_v_to_xOut_v_cmp(LOGICAL,315)
ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q;
ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q);
ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0";
--ld_xIn_v_to_xOut_v_cmpReg(REG,316)
ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_sticky_ena(REG,319)
ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN
ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,320)
ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q;
ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q;
ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b;
--GND(CONSTANT,0)
GND_q <= "0";
--xIn(PORTIN,3)@0
--expX_uid6_fpSqrtTest(BITSELECT,5)@0
expX_uid6_fpSqrtTest_in <= xIn_0(62 downto 0);
expX_uid6_fpSqrtTest_b <= expX_uid6_fpSqrtTest_in(62 downto 52);
--expZ_uid9_fpSqrtTest(LOGICAL,8)@0
expZ_uid9_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b;
expZ_uid9_fpSqrtTest_b <= STD_LOGIC_VECTOR("0000000000" & GND_q);
expZ_uid9_fpSqrtTest_q <= "1" when expZ_uid9_fpSqrtTest_a = expZ_uid9_fpSqrtTest_b else "0";
--signX_uid8_fpSqrtTest(BITSELECT,7)@0
signX_uid8_fpSqrtTest_in <= xIn_0;
signX_uid8_fpSqrtTest_b <= signX_uid8_fpSqrtTest_in(63 downto 63);
--excMZero_uid13_fpSqrtTest(LOGICAL,12)@0
excMZero_uid13_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b;
excMZero_uid13_fpSqrtTest_b <= expZ_uid9_fpSqrtTest_q;
excMZero_uid13_fpSqrtTest_q <= excMZero_uid13_fpSqrtTest_a and excMZero_uid13_fpSqrtTest_b;
--ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,310)
-- every=1, low=0, high=25, step=1, init=1
ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 24 THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 25;
ELSE
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,5));
--ld_xIn_v_to_xOut_v_replace_rdreg(REG,311)
ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q;
END IF;
END PROCESS;
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_xIn_v_to_xOut_v_replace_rdmux(MUX,312)
ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q;
ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q)
BEGIN
CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS
WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem(DUALMEM,361)
ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_reset0 <= areset;
ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_ia <= excMZero_uid13_fpSqrtTest_q;
ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 26,
width_b => 1,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_iq,
address_a => ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_aa,
data_a => ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_ia
);
ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_q <= ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_iq(0 downto 0);
--ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_outputreg(DELAY,360)
ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_outputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_replace_mem_q, xout => ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_outputreg_q, clk => clk, aclr => areset );
--cst0_uid10_fpSqrtTest(CONSTANT,9)
cst0_uid10_fpSqrtTest_q <= "11111111111";
--expAllZeros_uid39_fpSqrtTest(CONSTANT,38)
expAllZeros_uid39_fpSqrtTest_q <= "00000000000";
--biasP1(CONSTANT,23)
biasP1_q <= "01111111110";
--expOddSig_uid25_fpSqrtTest(ADD,24)@0
expOddSig_uid25_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b);
expOddSig_uid25_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & biasP1_q);
expOddSig_uid25_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid25_fpSqrtTest_a) + UNSIGNED(expOddSig_uid25_fpSqrtTest_b));
expOddSig_uid25_fpSqrtTest_q <= expOddSig_uid25_fpSqrtTest_o(11 downto 0);
--expROdd_uid26_fpSqrtTest(BITSELECT,25)@0
expROdd_uid26_fpSqrtTest_in <= expOddSig_uid25_fpSqrtTest_q;
expROdd_uid26_fpSqrtTest_b <= expROdd_uid26_fpSqrtTest_in(11 downto 1);
--bias(CONSTANT,20)
bias_q <= "01111111111";
--expEvenSig_uid22_fpSqrtTest(ADD,21)@0
expEvenSig_uid22_fpSqrtTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpSqrtTest_b);
expEvenSig_uid22_fpSqrtTest_b <= STD_LOGIC_VECTOR("0" & bias_q);
expEvenSig_uid22_fpSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid22_fpSqrtTest_a) + UNSIGNED(expEvenSig_uid22_fpSqrtTest_b));
expEvenSig_uid22_fpSqrtTest_q <= expEvenSig_uid22_fpSqrtTest_o(11 downto 0);
--expREven_uid23_fpSqrtTest(BITSELECT,22)@0
expREven_uid23_fpSqrtTest_in <= expEvenSig_uid22_fpSqrtTest_q;
expREven_uid23_fpSqrtTest_b <= expREven_uid23_fpSqrtTest_in(11 downto 1);
--expX0_uid27_fpSqrtTest(BITSELECT,26)@0
expX0_uid27_fpSqrtTest_in <= expX_uid6_fpSqrtTest_b(0 downto 0);
expX0_uid27_fpSqrtTest_b <= expX0_uid27_fpSqrtTest_in(0 downto 0);
--expOddSelect_uid28_fpSqrtTest(LOGICAL,27)@0
expOddSelect_uid28_fpSqrtTest_a <= expX0_uid27_fpSqrtTest_b;
expOddSelect_uid28_fpSqrtTest_q <= not expOddSelect_uid28_fpSqrtTest_a;
--expRMux_uid29_fpSqrtTest(MUX,28)@0
expRMux_uid29_fpSqrtTest_s <= expOddSelect_uid28_fpSqrtTest_q;
expRMux_uid29_fpSqrtTest: PROCESS (expRMux_uid29_fpSqrtTest_s, expREven_uid23_fpSqrtTest_b, expROdd_uid26_fpSqrtTest_b)
BEGIN
CASE expRMux_uid29_fpSqrtTest_s IS
WHEN "0" => expRMux_uid29_fpSqrtTest_q <= expREven_uid23_fpSqrtTest_b;
WHEN "1" => expRMux_uid29_fpSqrtTest_q <= expROdd_uid26_fpSqrtTest_b;
WHEN OTHERS => expRMux_uid29_fpSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--InvExcMZero_uid18_fpSqrtTest(LOGICAL,17)@0
InvExcMZero_uid18_fpSqrtTest_a <= excMZero_uid13_fpSqrtTest_q;
InvExcMZero_uid18_fpSqrtTest_q <= not InvExcMZero_uid18_fpSqrtTest_a;
--operandIsNegative_uid19_fpSqrtTest(LOGICAL,18)@0
operandIsNegative_uid19_fpSqrtTest_a <= signX_uid8_fpSqrtTest_b;
operandIsNegative_uid19_fpSqrtTest_b <= InvExcMZero_uid18_fpSqrtTest_q;
operandIsNegative_uid19_fpSqrtTest_q <= operandIsNegative_uid19_fpSqrtTest_a and operandIsNegative_uid19_fpSqrtTest_b;
--cmpEQ_w11_uid11_fpSqrtTest(LOGICAL,10)@0
cmpEQ_w11_uid11_fpSqrtTest_a <= expX_uid6_fpSqrtTest_b;
cmpEQ_w11_uid11_fpSqrtTest_b <= cst0_uid10_fpSqrtTest_q;
cmpEQ_w11_uid11_fpSqrtTest_q <= "1" when cmpEQ_w11_uid11_fpSqrtTest_a = cmpEQ_w11_uid11_fpSqrtTest_b else "0";
--expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest(LOGICAL,19)@0
expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_a <= cmpEQ_w11_uid11_fpSqrtTest_q;
expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_b <= operandIsNegative_uid19_fpSqrtTest_q;
expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_q <= expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_a or expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_b;
--join_uid36_fpSqrtTest(BITJOIN,35)@0
join_uid36_fpSqrtTest_q <= expISMaxOrOpIsLessThanZero_uid20_fpSqrtTest_q & expZ_uid9_fpSqrtTest_q;
--expRPostExc_uid40_fpSqrtTest(MUX,39)@0
expRPostExc_uid40_fpSqrtTest_s <= join_uid36_fpSqrtTest_q;
expRPostExc_uid40_fpSqrtTest: PROCESS (expRPostExc_uid40_fpSqrtTest_s, expRMux_uid29_fpSqrtTest_q)
BEGIN
CASE expRPostExc_uid40_fpSqrtTest_s IS
WHEN "00" => expRPostExc_uid40_fpSqrtTest_q <= expRMux_uid29_fpSqrtTest_q;
WHEN "01" => expRPostExc_uid40_fpSqrtTest_q <= expAllZeros_uid39_fpSqrtTest_q;
WHEN "10" => expRPostExc_uid40_fpSqrtTest_q <= cst0_uid10_fpSqrtTest_q;
WHEN "11" => expRPostExc_uid40_fpSqrtTest_q <= cst0_uid10_fpSqrtTest_q;
WHEN OTHERS => expRPostExc_uid40_fpSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_inputreg(DELAY,347)
ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expRPostExc_uid40_fpSqrtTest_q, xout => ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_inputreg_q, clk => clk, aclr => areset );
--ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem(DUALMEM,348)
ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_inputreg_q;
ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 26,
width_b => 11,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_iq(10 downto 0);
--fracNaN_uid44_fpSqrtTest(CONSTANT,43)
fracNaN_uid44_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000001";
--fracXAddr_uid31_fpSqrtTest(BITSELECT,30)@0
fracXAddr_uid31_fpSqrtTest_in <= xIn_0(51 downto 0);
fracXAddr_uid31_fpSqrtTest_b <= fracXAddr_uid31_fpSqrtTest_in(51 downto 45);
--addrTable_uid32_fpSqrtTest(BITJOIN,31)@0
addrTable_uid32_fpSqrtTest_q <= expOddSelect_uid28_fpSqrtTest_q & fracXAddr_uid31_fpSqrtTest_b;
--memoryC5_uid55_sqrtTableGenerator(LOOKUP,54)@0
memoryC5_uid55_sqrtTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC5_uid55_sqrtTableGenerator_q <= "00110111000001001";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (addrTable_uid32_fpSqrtTest_q) IS
WHEN "00000000" => memoryC5_uid55_sqrtTableGenerator_q <= "00110111000001001";
WHEN "00000001" => memoryC5_uid55_sqrtTableGenerator_q <= "00110101001010110";
WHEN "00000010" => memoryC5_uid55_sqrtTableGenerator_q <= "00110011011100000";
WHEN "00000011" => memoryC5_uid55_sqrtTableGenerator_q <= "00110001101001100";
WHEN "00000100" => memoryC5_uid55_sqrtTableGenerator_q <= "00101111111011110";
WHEN "00000101" => memoryC5_uid55_sqrtTableGenerator_q <= "00101110010111110";
WHEN "00000110" => memoryC5_uid55_sqrtTableGenerator_q <= "00101100110101001";
WHEN "00000111" => memoryC5_uid55_sqrtTableGenerator_q <= "00101011010000110";
WHEN "00001000" => memoryC5_uid55_sqrtTableGenerator_q <= "00101001111000000";
WHEN "00001001" => memoryC5_uid55_sqrtTableGenerator_q <= "00101000100001000";
WHEN "00001010" => memoryC5_uid55_sqrtTableGenerator_q <= "00100111001111011";
WHEN "00001011" => memoryC5_uid55_sqrtTableGenerator_q <= "00100110000101101";
WHEN "00001100" => memoryC5_uid55_sqrtTableGenerator_q <= "00100100111010100";
WHEN "00001101" => memoryC5_uid55_sqrtTableGenerator_q <= "00100011100110101";
WHEN "00001110" => memoryC5_uid55_sqrtTableGenerator_q <= "00100010100100011";
WHEN "00001111" => memoryC5_uid55_sqrtTableGenerator_q <= "00100001011010100";
WHEN "00010000" => memoryC5_uid55_sqrtTableGenerator_q <= "00100000011111001";
WHEN "00010001" => memoryC5_uid55_sqrtTableGenerator_q <= "00011111011001000";
WHEN "00010010" => memoryC5_uid55_sqrtTableGenerator_q <= "00011110011100100";
WHEN "00010011" => memoryC5_uid55_sqrtTableGenerator_q <= "00011101101010111";
WHEN "00010100" => memoryC5_uid55_sqrtTableGenerator_q <= "00011100110101000";
WHEN "00010101" => memoryC5_uid55_sqrtTableGenerator_q <= "00011011111011001";
WHEN "00010110" => memoryC5_uid55_sqrtTableGenerator_q <= "00011011000101001";
WHEN "00010111" => memoryC5_uid55_sqrtTableGenerator_q <= "00011010010110101";
WHEN "00011000" => memoryC5_uid55_sqrtTableGenerator_q <= "00011001011110000";
WHEN "00011001" => memoryC5_uid55_sqrtTableGenerator_q <= "00011000101111100";
WHEN "00011010" => memoryC5_uid55_sqrtTableGenerator_q <= "00010111111010101";
WHEN "00011011" => memoryC5_uid55_sqrtTableGenerator_q <= "00010111010001011";
WHEN "00011100" => memoryC5_uid55_sqrtTableGenerator_q <= "00010110101101000";
WHEN "00011101" => memoryC5_uid55_sqrtTableGenerator_q <= "00010110000110110";
WHEN "00011110" => memoryC5_uid55_sqrtTableGenerator_q <= "00010101010110001";
WHEN "00011111" => memoryC5_uid55_sqrtTableGenerator_q <= "00010100110100010";
WHEN "00100000" => memoryC5_uid55_sqrtTableGenerator_q <= "00010100001100111";
WHEN "00100001" => memoryC5_uid55_sqrtTableGenerator_q <= "00010011100111000";
WHEN "00100010" => memoryC5_uid55_sqrtTableGenerator_q <= "00010011001010000";
WHEN "00100011" => memoryC5_uid55_sqrtTableGenerator_q <= "00010010100101111";
WHEN "00100100" => memoryC5_uid55_sqrtTableGenerator_q <= "00010010000100110";
WHEN "00100101" => memoryC5_uid55_sqrtTableGenerator_q <= "00010001101001000";
WHEN "00100110" => memoryC5_uid55_sqrtTableGenerator_q <= "00010001000100000";
WHEN "00100111" => memoryC5_uid55_sqrtTableGenerator_q <= "00010000101000001";
WHEN "00101000" => memoryC5_uid55_sqrtTableGenerator_q <= "00010000001001100";
WHEN "00101001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001111110000101";
WHEN "00101010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001111011100000";
WHEN "00101011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001110111110110";
WHEN "00101100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001110101011010";
WHEN "00101101" => memoryC5_uid55_sqrtTableGenerator_q <= "00001110010101101";
WHEN "00101110" => memoryC5_uid55_sqrtTableGenerator_q <= "00001101111010001";
WHEN "00101111" => memoryC5_uid55_sqrtTableGenerator_q <= "00001101011110111";
WHEN "00110000" => memoryC5_uid55_sqrtTableGenerator_q <= "00001101001111111";
WHEN "00110001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001100110010111";
WHEN "00110010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001100100001101";
WHEN "00110011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001100010000010";
WHEN "00110100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001100000000110";
WHEN "00110101" => memoryC5_uid55_sqrtTableGenerator_q <= "00001011100111001";
WHEN "00110110" => memoryC5_uid55_sqrtTableGenerator_q <= "00001011001111001";
WHEN "00110111" => memoryC5_uid55_sqrtTableGenerator_q <= "00001011001000110";
WHEN "00111000" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010110010000";
WHEN "00111001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010100101100";
WHEN "00111010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010010110001";
WHEN "00111011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010000111011";
WHEN "00111100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001110100010";
WHEN "00111101" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001100100101";
WHEN "00111110" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001010010011";
WHEN "00111111" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001001110110";
WHEN "01000000" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000111011100";
WHEN "01000001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000101011101";
WHEN "01000010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000011011000";
WHEN "01000011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000010110101";
WHEN "01000100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000000111101";
WHEN "01000101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111111000001";
WHEN "01000110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111101101011";
WHEN "01000111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111100110101";
WHEN "01001000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111011110100";
WHEN "01001001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111010100100";
WHEN "01001010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111001110111";
WHEN "01001011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111000000010";
WHEN "01001100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110110110001";
WHEN "01001101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110101100000";
WHEN "01001110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110011010111";
WHEN "01001111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110010111010";
WHEN "01010000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110001111110";
WHEN "01010001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110001101110";
WHEN "01010010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101111100111";
WHEN "01010011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101110111000";
WHEN "01010100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101101010111";
WHEN "01010101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101100111011";
WHEN "01010110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101100010111";
WHEN "01010111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101010010100";
WHEN "01011000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101001110101";
WHEN "01011001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101001010100";
WHEN "01011010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100111110101";
WHEN "01011011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100111100111";
WHEN "01011100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100110111101";
WHEN "01011101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100110001010";
WHEN "01011110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100110000011";
WHEN "01011111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100011111110";
WHEN "01100000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100011000000";
WHEN "01100001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100011100011";
WHEN "01100010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100010111110";
WHEN "01100011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100001000111";
WHEN "01100100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100001010011";
WHEN "01100101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100000111001";
WHEN "01100110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100000001100";
WHEN "01100111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011110011011";
WHEN "01101000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011101110001";
WHEN "01101001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011110100010";
WHEN "01101010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011101110100";
WHEN "01101011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011101011101";
WHEN "01101100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011100001000";
WHEN "01101101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011100001011";
WHEN "01101110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011011000111";
WHEN "01101111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011010101011";
WHEN "01110000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011001010011";
WHEN "01110001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011001010011";
WHEN "01110010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011001010101";
WHEN "01110011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011001100100";
WHEN "01110100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011000110010";
WHEN "01110101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010111101100";
WHEN "01110110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010110111100";
WHEN "01110111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010110111110";
WHEN "01111000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010110000110";
WHEN "01111001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010101101001";
WHEN "01111010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010100111110";
WHEN "01111011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010100110010";
WHEN "01111100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010100111111";
WHEN "01111101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010101011000";
WHEN "01111110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010100001000";
WHEN "01111111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000010100100111";
WHEN "10000000" => memoryC5_uid55_sqrtTableGenerator_q <= "01001101101101100";
WHEN "10000001" => memoryC5_uid55_sqrtTableGenerator_q <= "01001011001110100";
WHEN "10000010" => memoryC5_uid55_sqrtTableGenerator_q <= "01001000100110100";
WHEN "10000011" => memoryC5_uid55_sqrtTableGenerator_q <= "01000110000111011";
WHEN "10000100" => memoryC5_uid55_sqrtTableGenerator_q <= "01000011111000010";
WHEN "10000101" => memoryC5_uid55_sqrtTableGenerator_q <= "01000001100001110";
WHEN "10000110" => memoryC5_uid55_sqrtTableGenerator_q <= "00111111011010101";
WHEN "10000111" => memoryC5_uid55_sqrtTableGenerator_q <= "00111101010100001";
WHEN "10001000" => memoryC5_uid55_sqrtTableGenerator_q <= "00111011001110101";
WHEN "10001001" => memoryC5_uid55_sqrtTableGenerator_q <= "00111001010100100";
WHEN "10001010" => memoryC5_uid55_sqrtTableGenerator_q <= "00110111101001000";
WHEN "10001011" => memoryC5_uid55_sqrtTableGenerator_q <= "00110101110111110";
WHEN "10001100" => memoryC5_uid55_sqrtTableGenerator_q <= "00110100001000110";
WHEN "10001101" => memoryC5_uid55_sqrtTableGenerator_q <= "00110010011001110";
WHEN "10001110" => memoryC5_uid55_sqrtTableGenerator_q <= "00110000111010001";
WHEN "10001111" => memoryC5_uid55_sqrtTableGenerator_q <= "00101111010011101";
WHEN "10010000" => memoryC5_uid55_sqrtTableGenerator_q <= "00101101110111100";
WHEN "10010001" => memoryC5_uid55_sqrtTableGenerator_q <= "00101100011101010";
WHEN "10010010" => memoryC5_uid55_sqrtTableGenerator_q <= "00101011000100101";
WHEN "10010011" => memoryC5_uid55_sqrtTableGenerator_q <= "00101001110101110";
WHEN "10010100" => memoryC5_uid55_sqrtTableGenerator_q <= "00101000100111100";
WHEN "10010101" => memoryC5_uid55_sqrtTableGenerator_q <= "00100111011000100";
WHEN "10010110" => memoryC5_uid55_sqrtTableGenerator_q <= "00100110001011010";
WHEN "10010111" => memoryC5_uid55_sqrtTableGenerator_q <= "00100101000111110";
WHEN "10011000" => memoryC5_uid55_sqrtTableGenerator_q <= "00100100000000001";
WHEN "10011001" => memoryC5_uid55_sqrtTableGenerator_q <= "00100010111100001";
WHEN "10011010" => memoryC5_uid55_sqrtTableGenerator_q <= "00100001111111000";
WHEN "10011011" => memoryC5_uid55_sqrtTableGenerator_q <= "00100000111111101";
WHEN "10011100" => memoryC5_uid55_sqrtTableGenerator_q <= "00100000000011111";
WHEN "10011101" => memoryC5_uid55_sqrtTableGenerator_q <= "00011111000001100";
WHEN "10011110" => memoryC5_uid55_sqrtTableGenerator_q <= "00011110010000001";
WHEN "10011111" => memoryC5_uid55_sqrtTableGenerator_q <= "00011101011000101";
WHEN "10100000" => memoryC5_uid55_sqrtTableGenerator_q <= "00011100100001110";
WHEN "10100001" => memoryC5_uid55_sqrtTableGenerator_q <= "00011011110000010";
WHEN "10100010" => memoryC5_uid55_sqrtTableGenerator_q <= "00011011000111101";
WHEN "10100011" => memoryC5_uid55_sqrtTableGenerator_q <= "00011010010011000";
WHEN "10100100" => memoryC5_uid55_sqrtTableGenerator_q <= "00011001101011110";
WHEN "10100101" => memoryC5_uid55_sqrtTableGenerator_q <= "00011000110100010";
WHEN "10100110" => memoryC5_uid55_sqrtTableGenerator_q <= "00011000010001000";
WHEN "10100111" => memoryC5_uid55_sqrtTableGenerator_q <= "00010111100001000";
WHEN "10101000" => memoryC5_uid55_sqrtTableGenerator_q <= "00010110111011101";
WHEN "10101001" => memoryC5_uid55_sqrtTableGenerator_q <= "00010110010111111";
WHEN "10101010" => memoryC5_uid55_sqrtTableGenerator_q <= "00010101110101111";
WHEN "10101011" => memoryC5_uid55_sqrtTableGenerator_q <= "00010101010000000";
WHEN "10101100" => memoryC5_uid55_sqrtTableGenerator_q <= "00010100101000111";
WHEN "10101101" => memoryC5_uid55_sqrtTableGenerator_q <= "00010100010000111";
WHEN "10101110" => memoryC5_uid55_sqrtTableGenerator_q <= "00010011101001011";
WHEN "10101111" => memoryC5_uid55_sqrtTableGenerator_q <= "00010011001001010";
WHEN "10110000" => memoryC5_uid55_sqrtTableGenerator_q <= "00010010100100010";
WHEN "10110001" => memoryC5_uid55_sqrtTableGenerator_q <= "00010010001011101";
WHEN "10110010" => memoryC5_uid55_sqrtTableGenerator_q <= "00010001101011001";
WHEN "10110011" => memoryC5_uid55_sqrtTableGenerator_q <= "00010001001110100";
WHEN "10110100" => memoryC5_uid55_sqrtTableGenerator_q <= "00010000110110010";
WHEN "10110101" => memoryC5_uid55_sqrtTableGenerator_q <= "00010000011100011";
WHEN "10110110" => memoryC5_uid55_sqrtTableGenerator_q <= "00010000000110010";
WHEN "10110111" => memoryC5_uid55_sqrtTableGenerator_q <= "00001111101001000";
WHEN "10111000" => memoryC5_uid55_sqrtTableGenerator_q <= "00001111010100001";
WHEN "10111001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001110111110111";
WHEN "10111010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001110101010110";
WHEN "10111011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001110001010111";
WHEN "10111100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001101111000100";
WHEN "10111101" => memoryC5_uid55_sqrtTableGenerator_q <= "00001101100101100";
WHEN "10111110" => memoryC5_uid55_sqrtTableGenerator_q <= "00001101010001010";
WHEN "10111111" => memoryC5_uid55_sqrtTableGenerator_q <= "00001100111001110";
WHEN "11000000" => memoryC5_uid55_sqrtTableGenerator_q <= "00001100100101000";
WHEN "11000001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001100011000011";
WHEN "11000010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001011111100011";
WHEN "11000011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001011110011100";
WHEN "11000100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001011100001111";
WHEN "11000101" => memoryC5_uid55_sqrtTableGenerator_q <= "00001011001101110";
WHEN "11000110" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010111100000";
WHEN "11000111" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010101101011";
WHEN "11001000" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010011011010";
WHEN "11001001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001010010010100";
WHEN "11001010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001111100111";
WHEN "11001011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001110101011";
WHEN "11001100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001101001110";
WHEN "11001101" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001011000111";
WHEN "11001110" => memoryC5_uid55_sqrtTableGenerator_q <= "00001001001111110";
WHEN "11001111" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000111110000";
WHEN "11010000" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000110101011";
WHEN "11010001" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000101101110";
WHEN "11010010" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000011111110";
WHEN "11010011" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000001100010";
WHEN "11010100" => memoryC5_uid55_sqrtTableGenerator_q <= "00001000000101110";
WHEN "11010101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111111101011";
WHEN "11010110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111101111100";
WHEN "11010111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111100011101";
WHEN "11011000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111011000110";
WHEN "11011001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111001100010";
WHEN "11011010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000111001100100";
WHEN "11011011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110111100110";
WHEN "11011100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110110001100";
WHEN "11011101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110101100011";
WHEN "11011110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110100010111";
WHEN "11011111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110011101011";
WHEN "11100000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110010100100";
WHEN "11100001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110001001011";
WHEN "11100010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110000010111";
WHEN "11100011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000110000011010";
WHEN "11100100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101110011000";
WHEN "11100101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101101011001";
WHEN "11100110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101100100100";
WHEN "11100111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101100000001";
WHEN "11101000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101010100011";
WHEN "11101001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101001110111";
WHEN "11101010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101001000010";
WHEN "11101011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101001000111";
WHEN "11101100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000101000010010";
WHEN "11101101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100111000101";
WHEN "11101110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100110011111";
WHEN "11101111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100101001100";
WHEN "11110000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100100101010";
WHEN "11110001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100011110110";
WHEN "11110010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100011111000";
WHEN "11110011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100011011101";
WHEN "11110100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100010000011";
WHEN "11110101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100001010101";
WHEN "11110110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000100001000101";
WHEN "11110111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011111111000";
WHEN "11111000" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011111111011";
WHEN "11111001" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011111010101";
WHEN "11111010" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011110010101";
WHEN "11111011" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011101101010";
WHEN "11111100" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011101000001";
WHEN "11111101" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011101100010";
WHEN "11111110" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011100010101";
WHEN "11111111" => memoryC5_uid55_sqrtTableGenerator_q <= "00000011011110110";
WHEN OTHERS =>
memoryC5_uid55_sqrtTableGenerator_q <= "00110111000001001";
END CASE;
END IF;
END PROCESS;
--ld_xIn_0_to_X44dto0_uid33_fpSqrtTest_a(DELAY,182)@0
ld_xIn_0_to_X44dto0_uid33_fpSqrtTest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => xIn_0, xout => ld_xIn_0_to_X44dto0_uid33_fpSqrtTest_a_q, clk => clk, aclr => areset );
--X44dto0_uid33_fpSqrtTest(BITSELECT,32)@1
X44dto0_uid33_fpSqrtTest_in <= ld_xIn_0_to_X44dto0_uid33_fpSqrtTest_a_q(44 downto 0);
X44dto0_uid33_fpSqrtTest_b <= X44dto0_uid33_fpSqrtTest_in(44 downto 0);
--yT1_uid56_sqrtPolynomialEvaluator(BITSELECT,55)@1
yT1_uid56_sqrtPolynomialEvaluator_in <= X44dto0_uid33_fpSqrtTest_b;
yT1_uid56_sqrtPolynomialEvaluator_b <= yT1_uid56_sqrtPolynomialEvaluator_in(44 downto 28);
--prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator(MULT,86)@1
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_a),18)) * SIGNED(prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_b);
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_a <= yT1_uid56_sqrtPolynomialEvaluator_b;
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_b <= memoryC5_uid55_sqrtTableGenerator_q;
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_pr,34));
END IF;
END PROCESS;
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_q <= prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_s1;
END IF;
END PROCESS;
--prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator(BITSELECT,87)@4
prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator_in <= prodXY_uid87_pT1_uid57_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator_in(33 downto 16);
--highBBits_uid59_sqrtPolynomialEvaluator(BITSELECT,58)@4
highBBits_uid59_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator_b;
highBBits_uid59_sqrtPolynomialEvaluator_b <= highBBits_uid59_sqrtPolynomialEvaluator_in(17 downto 1);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC4_uid54_sqrtTableGenerator_a(DELAY,203)@0
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC4_uid54_sqrtTableGenerator_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addrTable_uid32_fpSqrtTest_q, xout => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC4_uid54_sqrtTableGenerator_a_q, clk => clk, aclr => areset );
--memoryC4_uid54_sqrtTableGenerator(LOOKUP,53)@3
memoryC4_uid54_sqrtTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC4_uid54_sqrtTableGenerator_q <= "101100000000001000110110";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC4_uid54_sqrtTableGenerator_a_q) IS
WHEN "00000000" => memoryC4_uid54_sqrtTableGenerator_q <= "101100000000001000110110";
WHEN "00000001" => memoryC4_uid54_sqrtTableGenerator_q <= "101100100010100000111110";
WHEN "00000010" => memoryC4_uid54_sqrtTableGenerator_q <= "101101000011101100101111";
WHEN "00000011" => memoryC4_uid54_sqrtTableGenerator_q <= "101101100011110010111000";
WHEN "00000100" => memoryC4_uid54_sqrtTableGenerator_q <= "101110000010110011110010";
WHEN "00000101" => memoryC4_uid54_sqrtTableGenerator_q <= "101110100000110000011101";
WHEN "00000110" => memoryC4_uid54_sqrtTableGenerator_q <= "101110111101101101110111";
WHEN "00000111" => memoryC4_uid54_sqrtTableGenerator_q <= "101111011001110000010110";
WHEN "00001000" => memoryC4_uid54_sqrtTableGenerator_q <= "101111110100110101011001";
WHEN "00001001" => memoryC4_uid54_sqrtTableGenerator_q <= "110000001111000010101011";
WHEN "00001010" => memoryC4_uid54_sqrtTableGenerator_q <= "110000101000011000110010";
WHEN "00001011" => memoryC4_uid54_sqrtTableGenerator_q <= "110001000000111001101101";
WHEN "00001100" => memoryC4_uid54_sqrtTableGenerator_q <= "110001011000101001111000";
WHEN "00001101" => memoryC4_uid54_sqrtTableGenerator_q <= "110001101111101101110000";
WHEN "00001110" => memoryC4_uid54_sqrtTableGenerator_q <= "110010000101111110100011";
WHEN "00001111" => memoryC4_uid54_sqrtTableGenerator_q <= "110010011011100110011110";
WHEN "00010000" => memoryC4_uid54_sqrtTableGenerator_q <= "110010110000011111000101";
WHEN "00010001" => memoryC4_uid54_sqrtTableGenerator_q <= "110011000100110011011001";
WHEN "00010010" => memoryC4_uid54_sqrtTableGenerator_q <= "110011011000011101100101";
WHEN "00010011" => memoryC4_uid54_sqrtTableGenerator_q <= "110011101011011110011101";
WHEN "00010100" => memoryC4_uid54_sqrtTableGenerator_q <= "110011111101111100111101";
WHEN "00010101" => memoryC4_uid54_sqrtTableGenerator_q <= "110100001111111001111010";
WHEN "00010110" => memoryC4_uid54_sqrtTableGenerator_q <= "110100100001010011111101";
WHEN "00010111" => memoryC4_uid54_sqrtTableGenerator_q <= "110100110010001011011100";
WHEN "00011000" => memoryC4_uid54_sqrtTableGenerator_q <= "110101000010100110110011";
WHEN "00011001" => memoryC4_uid54_sqrtTableGenerator_q <= "110101010010100001000100";
WHEN "00011010" => memoryC4_uid54_sqrtTableGenerator_q <= "110101100010000000011111";
WHEN "00011011" => memoryC4_uid54_sqrtTableGenerator_q <= "110101110001000000000111";
WHEN "00011100" => memoryC4_uid54_sqrtTableGenerator_q <= "110101111111100011001100";
WHEN "00011101" => memoryC4_uid54_sqrtTableGenerator_q <= "110110001101101100101011";
WHEN "00011110" => memoryC4_uid54_sqrtTableGenerator_q <= "110110011011100000011011";
WHEN "00011111" => memoryC4_uid54_sqrtTableGenerator_q <= "110110101000110111000100";
WHEN "00100000" => memoryC4_uid54_sqrtTableGenerator_q <= "110110110101111000000011";
WHEN "00100001" => memoryC4_uid54_sqrtTableGenerator_q <= "110111000010100010000101";
WHEN "00100010" => memoryC4_uid54_sqrtTableGenerator_q <= "110111001110110011001000";
WHEN "00100011" => memoryC4_uid54_sqrtTableGenerator_q <= "110111011010110001010101";
WHEN "00100100" => memoryC4_uid54_sqrtTableGenerator_q <= "110111100110011001111011";
WHEN "00100101" => memoryC4_uid54_sqrtTableGenerator_q <= "110111110001101101000100";
WHEN "00100110" => memoryC4_uid54_sqrtTableGenerator_q <= "110111111100110000001111";
WHEN "00100111" => memoryC4_uid54_sqrtTableGenerator_q <= "111000000111011101110001";
WHEN "00101000" => memoryC4_uid54_sqrtTableGenerator_q <= "111000010001111010010001";
WHEN "00101001" => memoryC4_uid54_sqrtTableGenerator_q <= "111000011100000011100111";
WHEN "00101010" => memoryC4_uid54_sqrtTableGenerator_q <= "111000100101111010101011";
WHEN "00101011" => memoryC4_uid54_sqrtTableGenerator_q <= "111000101111100100001111";
WHEN "00101100" => memoryC4_uid54_sqrtTableGenerator_q <= "111000111000111011000011";
WHEN "00101101" => memoryC4_uid54_sqrtTableGenerator_q <= "111001000010000011001101";
WHEN "00101110" => memoryC4_uid54_sqrtTableGenerator_q <= "111001001010111110010111";
WHEN "00101111" => memoryC4_uid54_sqrtTableGenerator_q <= "111001010011101011100011";
WHEN "00110000" => memoryC4_uid54_sqrtTableGenerator_q <= "111001011100000110010100";
WHEN "00110001" => memoryC4_uid54_sqrtTableGenerator_q <= "111001100100011000101111";
WHEN "00110010" => memoryC4_uid54_sqrtTableGenerator_q <= "111001101100011001111001";
WHEN "00110011" => memoryC4_uid54_sqrtTableGenerator_q <= "111001110100001110101001";
WHEN "00110100" => memoryC4_uid54_sqrtTableGenerator_q <= "111001111011110110010110";
WHEN "00110101" => memoryC4_uid54_sqrtTableGenerator_q <= "111010000011010101101010";
WHEN "00110110" => memoryC4_uid54_sqrtTableGenerator_q <= "111010001010101000110111";
WHEN "00110111" => memoryC4_uid54_sqrtTableGenerator_q <= "111010010001101011001011";
WHEN "00111000" => memoryC4_uid54_sqrtTableGenerator_q <= "111010011000100111111001";
WHEN "00111001" => memoryC4_uid54_sqrtTableGenerator_q <= "111010011111010110110101";
WHEN "00111010" => memoryC4_uid54_sqrtTableGenerator_q <= "111010100101111100001111";
WHEN "00111011" => memoryC4_uid54_sqrtTableGenerator_q <= "111010101100010111100101";
WHEN "00111100" => memoryC4_uid54_sqrtTableGenerator_q <= "111010110010101010111100";
WHEN "00111101" => memoryC4_uid54_sqrtTableGenerator_q <= "111010111000110011100111";
WHEN "00111110" => memoryC4_uid54_sqrtTableGenerator_q <= "111010111110110100010010";
WHEN "00111111" => memoryC4_uid54_sqrtTableGenerator_q <= "111011000100100110111100";
WHEN "01000000" => memoryC4_uid54_sqrtTableGenerator_q <= "111011001010010110011111";
WHEN "01000001" => memoryC4_uid54_sqrtTableGenerator_q <= "111011001111111100010110";
WHEN "01000010" => memoryC4_uid54_sqrtTableGenerator_q <= "111011010101011010011100";
WHEN "01000011" => memoryC4_uid54_sqrtTableGenerator_q <= "111011011010101100100101";
WHEN "01000100" => memoryC4_uid54_sqrtTableGenerator_q <= "111011011111111010100100";
WHEN "01000101" => memoryC4_uid54_sqrtTableGenerator_q <= "111011100101000001011010";
WHEN "01000110" => memoryC4_uid54_sqrtTableGenerator_q <= "111011101001111111010111";
WHEN "01000111" => memoryC4_uid54_sqrtTableGenerator_q <= "111011101110110100110100";
WHEN "01001000" => memoryC4_uid54_sqrtTableGenerator_q <= "111011110011100100000110";
WHEN "01001001" => memoryC4_uid54_sqrtTableGenerator_q <= "111011111000001101000001";
WHEN "01001010" => memoryC4_uid54_sqrtTableGenerator_q <= "111011111100101110010010";
WHEN "01001011" => memoryC4_uid54_sqrtTableGenerator_q <= "111100000001001100000001";
WHEN "01001100" => memoryC4_uid54_sqrtTableGenerator_q <= "111100000101100010000010";
WHEN "01001101" => memoryC4_uid54_sqrtTableGenerator_q <= "111100001001110010011010";
WHEN "01001110" => memoryC4_uid54_sqrtTableGenerator_q <= "111100001101111111001110";
WHEN "01001111" => memoryC4_uid54_sqrtTableGenerator_q <= "111100010010000001101101";
WHEN "01010000" => memoryC4_uid54_sqrtTableGenerator_q <= "111100010110000000000101";
WHEN "01010001" => memoryC4_uid54_sqrtTableGenerator_q <= "111100011001110111001110";
WHEN "01010010" => memoryC4_uid54_sqrtTableGenerator_q <= "111100011101101110000110";
WHEN "01010011" => memoryC4_uid54_sqrtTableGenerator_q <= "111100100001011100010000";
WHEN "01010100" => memoryC4_uid54_sqrtTableGenerator_q <= "111100100101000111001110";
WHEN "01010101" => memoryC4_uid54_sqrtTableGenerator_q <= "111100101000101010101011";
WHEN "01010110" => memoryC4_uid54_sqrtTableGenerator_q <= "111100101100001010000000";
WHEN "01010111" => memoryC4_uid54_sqrtTableGenerator_q <= "111100101111101000001100";
WHEN "01011000" => memoryC4_uid54_sqrtTableGenerator_q <= "111100110010111110001101";
WHEN "01011001" => memoryC4_uid54_sqrtTableGenerator_q <= "111100110110001111101111";
WHEN "01011010" => memoryC4_uid54_sqrtTableGenerator_q <= "111100111001011111010100";
WHEN "01011011" => memoryC4_uid54_sqrtTableGenerator_q <= "111100111100100111100011";
WHEN "01011100" => memoryC4_uid54_sqrtTableGenerator_q <= "111100111111101101000001";
WHEN "01011101" => memoryC4_uid54_sqrtTableGenerator_q <= "111101000010101110111101";
WHEN "01011110" => memoryC4_uid54_sqrtTableGenerator_q <= "111101000101101011001001";
WHEN "01011111" => memoryC4_uid54_sqrtTableGenerator_q <= "111101001000101000100111";
WHEN "01100000" => memoryC4_uid54_sqrtTableGenerator_q <= "111101001011011111101000";
WHEN "01100001" => memoryC4_uid54_sqrtTableGenerator_q <= "111101001110001111001010";
WHEN "01100010" => memoryC4_uid54_sqrtTableGenerator_q <= "111101010000111101111101";
WHEN "01100011" => memoryC4_uid54_sqrtTableGenerator_q <= "111101010011101101000100";
WHEN "01100100" => memoryC4_uid54_sqrtTableGenerator_q <= "111101010110010011001101";
WHEN "01100101" => memoryC4_uid54_sqrtTableGenerator_q <= "111101011000110111100010";
WHEN "01100110" => memoryC4_uid54_sqrtTableGenerator_q <= "111101011011011001011101";
WHEN "01100111" => memoryC4_uid54_sqrtTableGenerator_q <= "111101011101111011011000";
WHEN "01101000" => memoryC4_uid54_sqrtTableGenerator_q <= "111101100000010111001000";
WHEN "01101001" => memoryC4_uid54_sqrtTableGenerator_q <= "111101100010101100011001";
WHEN "01101010" => memoryC4_uid54_sqrtTableGenerator_q <= "111101100101000010011010";
WHEN "01101011" => memoryC4_uid54_sqrtTableGenerator_q <= "111101100111010100101100";
WHEN "01101100" => memoryC4_uid54_sqrtTableGenerator_q <= "111101101001100110111000";
WHEN "01101101" => memoryC4_uid54_sqrtTableGenerator_q <= "111101101011110010111010";
WHEN "01101110" => memoryC4_uid54_sqrtTableGenerator_q <= "111101101101111111000110";
WHEN "01101111" => memoryC4_uid54_sqrtTableGenerator_q <= "111101110000000111000001";
WHEN "01110000" => memoryC4_uid54_sqrtTableGenerator_q <= "111101110010001110111001";
WHEN "01110001" => memoryC4_uid54_sqrtTableGenerator_q <= "111101110100010000110100";
WHEN "01110010" => memoryC4_uid54_sqrtTableGenerator_q <= "111101110110010000001010";
WHEN "01110011" => memoryC4_uid54_sqrtTableGenerator_q <= "111101111000001100100111";
WHEN "01110100" => memoryC4_uid54_sqrtTableGenerator_q <= "111101111010001001011001";
WHEN "01110101" => memoryC4_uid54_sqrtTableGenerator_q <= "111101111100000100110100";
WHEN "01110110" => memoryC4_uid54_sqrtTableGenerator_q <= "111101111101111101010110";
WHEN "01110111" => memoryC4_uid54_sqrtTableGenerator_q <= "111101111111110001010110";
WHEN "01111000" => memoryC4_uid54_sqrtTableGenerator_q <= "111110000001100101111100";
WHEN "01111001" => memoryC4_uid54_sqrtTableGenerator_q <= "111110000011010111010000";
WHEN "01111010" => memoryC4_uid54_sqrtTableGenerator_q <= "111110000101000111000000";
WHEN "01111011" => memoryC4_uid54_sqrtTableGenerator_q <= "111110000110110011100101";
WHEN "01111100" => memoryC4_uid54_sqrtTableGenerator_q <= "111110001000011101100000";
WHEN "01111101" => memoryC4_uid54_sqrtTableGenerator_q <= "111110001010000100101101";
WHEN "01111110" => memoryC4_uid54_sqrtTableGenerator_q <= "111110001011101110100001";
WHEN "01111111" => memoryC4_uid54_sqrtTableGenerator_q <= "111110001101010001110000";
WHEN "10000000" => memoryC4_uid54_sqrtTableGenerator_q <= "100011101110000010001011";
WHEN "10000001" => memoryC4_uid54_sqrtTableGenerator_q <= "100100011110100110110110";
WHEN "10000010" => memoryC4_uid54_sqrtTableGenerator_q <= "100101001101100110001001";
WHEN "10000011" => memoryC4_uid54_sqrtTableGenerator_q <= "100101111010111110010000";
WHEN "10000100" => memoryC4_uid54_sqrtTableGenerator_q <= "100110100110110001001000";
WHEN "10000101" => memoryC4_uid54_sqrtTableGenerator_q <= "100111010001001010100111";
WHEN "10000110" => memoryC4_uid54_sqrtTableGenerator_q <= "100111111010000110110101";
WHEN "10000111" => memoryC4_uid54_sqrtTableGenerator_q <= "101000100001101101101101";
WHEN "10001000" => memoryC4_uid54_sqrtTableGenerator_q <= "101001001000000011011001";
WHEN "10001001" => memoryC4_uid54_sqrtTableGenerator_q <= "101001101101000111000101";
WHEN "10001010" => memoryC4_uid54_sqrtTableGenerator_q <= "101010010000111010101000";
WHEN "10001011" => memoryC4_uid54_sqrtTableGenerator_q <= "101010110011101000001011";
WHEN "10001100" => memoryC4_uid54_sqrtTableGenerator_q <= "101011010101001111100100";
WHEN "10001101" => memoryC4_uid54_sqrtTableGenerator_q <= "101011110101110100010100";
WHEN "10001110" => memoryC4_uid54_sqrtTableGenerator_q <= "101100010101010100000011";
WHEN "10001111" => memoryC4_uid54_sqrtTableGenerator_q <= "101100110011111000001011";
WHEN "10010000" => memoryC4_uid54_sqrtTableGenerator_q <= "101101010001011101011110";
WHEN "10010001" => memoryC4_uid54_sqrtTableGenerator_q <= "101101101110001001011111";
WHEN "10010010" => memoryC4_uid54_sqrtTableGenerator_q <= "101110001001111101011011";
WHEN "10010011" => memoryC4_uid54_sqrtTableGenerator_q <= "101110100100111001011001";
WHEN "10010100" => memoryC4_uid54_sqrtTableGenerator_q <= "101110111111000010010010";
WHEN "10010101" => memoryC4_uid54_sqrtTableGenerator_q <= "101111011000011010010001";
WHEN "10010110" => memoryC4_uid54_sqrtTableGenerator_q <= "101111110001000010000111";
WHEN "10010111" => memoryC4_uid54_sqrtTableGenerator_q <= "110000001000111001001111";
WHEN "10011000" => memoryC4_uid54_sqrtTableGenerator_q <= "110000100000000101100111";
WHEN "10011001" => memoryC4_uid54_sqrtTableGenerator_q <= "110000110110100110100110";
WHEN "10011010" => memoryC4_uid54_sqrtTableGenerator_q <= "110001001100011011101101";
WHEN "10011011" => memoryC4_uid54_sqrtTableGenerator_q <= "110001100001101010011101";
WHEN "10011100" => memoryC4_uid54_sqrtTableGenerator_q <= "110001110110010001110111";
WHEN "10011101" => memoryC4_uid54_sqrtTableGenerator_q <= "110010001010010110100101";
WHEN "10011110" => memoryC4_uid54_sqrtTableGenerator_q <= "110010011101110010010001";
WHEN "10011111" => memoryC4_uid54_sqrtTableGenerator_q <= "110010110000101101010100";
WHEN "10100000" => memoryC4_uid54_sqrtTableGenerator_q <= "110011000011000111001010";
WHEN "10100001" => memoryC4_uid54_sqrtTableGenerator_q <= "110011010100111111001010";
WHEN "10100010" => memoryC4_uid54_sqrtTableGenerator_q <= "110011100110010101010100";
WHEN "10100011" => memoryC4_uid54_sqrtTableGenerator_q <= "110011110111010001011001";
WHEN "10100100" => memoryC4_uid54_sqrtTableGenerator_q <= "110100000111101011111011";
WHEN "10100101" => memoryC4_uid54_sqrtTableGenerator_q <= "110100010111110000000111";
WHEN "10100110" => memoryC4_uid54_sqrtTableGenerator_q <= "110100100111010010010010";
WHEN "10100111" => memoryC4_uid54_sqrtTableGenerator_q <= "110100110110011110101011";
WHEN "10101000" => memoryC4_uid54_sqrtTableGenerator_q <= "110101000101001110010000";
WHEN "10101001" => memoryC4_uid54_sqrtTableGenerator_q <= "110101010011100100100010";
WHEN "10101010" => memoryC4_uid54_sqrtTableGenerator_q <= "110101100001100010110001";
WHEN "10101011" => memoryC4_uid54_sqrtTableGenerator_q <= "110101101111001010110110";
WHEN "10101100" => memoryC4_uid54_sqrtTableGenerator_q <= "110101111100011101100111";
WHEN "10101101" => memoryC4_uid54_sqrtTableGenerator_q <= "110110001001010101100000";
WHEN "10101110" => memoryC4_uid54_sqrtTableGenerator_q <= "110110010101111101011110";
WHEN "10101111" => memoryC4_uid54_sqrtTableGenerator_q <= "110110100010001110111110";
WHEN "10110000" => memoryC4_uid54_sqrtTableGenerator_q <= "110110101110001110100011";
WHEN "10110001" => memoryC4_uid54_sqrtTableGenerator_q <= "110110111001110111001101";
WHEN "10110010" => memoryC4_uid54_sqrtTableGenerator_q <= "110111000101001111100001";
WHEN "10110011" => memoryC4_uid54_sqrtTableGenerator_q <= "110111010000010101000000";
WHEN "10110100" => memoryC4_uid54_sqrtTableGenerator_q <= "110111011011000111100010";
WHEN "10110101" => memoryC4_uid54_sqrtTableGenerator_q <= "110111100101101001111010";
WHEN "10110110" => memoryC4_uid54_sqrtTableGenerator_q <= "110111101111111010111001";
WHEN "10110111" => memoryC4_uid54_sqrtTableGenerator_q <= "110111111001111110001110";
WHEN "10111000" => memoryC4_uid54_sqrtTableGenerator_q <= "111000000011101111100110";
WHEN "10111001" => memoryC4_uid54_sqrtTableGenerator_q <= "111000001101010001111110";
WHEN "10111010" => memoryC4_uid54_sqrtTableGenerator_q <= "111000010110100101101100";
WHEN "10111011" => memoryC4_uid54_sqrtTableGenerator_q <= "111000011111101111001011";
WHEN "10111100" => memoryC4_uid54_sqrtTableGenerator_q <= "111000101000100110100101";
WHEN "10111101" => memoryC4_uid54_sqrtTableGenerator_q <= "111000110001010000101101";
WHEN "10111110" => memoryC4_uid54_sqrtTableGenerator_q <= "111000111001101110110011";
WHEN "10111111" => memoryC4_uid54_sqrtTableGenerator_q <= "111001000010000001001111";
WHEN "11000000" => memoryC4_uid54_sqrtTableGenerator_q <= "111001001010000110110111";
WHEN "11000001" => memoryC4_uid54_sqrtTableGenerator_q <= "111001010001111101100010";
WHEN "11000010" => memoryC4_uid54_sqrtTableGenerator_q <= "111001011001101110010000";
WHEN "11000011" => memoryC4_uid54_sqrtTableGenerator_q <= "111001100001001101011000";
WHEN "11000100" => memoryC4_uid54_sqrtTableGenerator_q <= "111001101000100100101100";
WHEN "11000101" => memoryC4_uid54_sqrtTableGenerator_q <= "111001101111110010000010";
WHEN "11000110" => memoryC4_uid54_sqrtTableGenerator_q <= "111001110110110100101000";
WHEN "11000111" => memoryC4_uid54_sqrtTableGenerator_q <= "111001111101101011110111";
WHEN "11001000" => memoryC4_uid54_sqrtTableGenerator_q <= "111010000100011010110110";
WHEN "11001001" => memoryC4_uid54_sqrtTableGenerator_q <= "111010001010111101001010";
WHEN "11001010" => memoryC4_uid54_sqrtTableGenerator_q <= "111010010001011010101101";
WHEN "11001011" => memoryC4_uid54_sqrtTableGenerator_q <= "111010010111101010011100";
WHEN "11001100" => memoryC4_uid54_sqrtTableGenerator_q <= "111010011101110011001001";
WHEN "11001101" => memoryC4_uid54_sqrtTableGenerator_q <= "111010100011110100111101";
WHEN "11001110" => memoryC4_uid54_sqrtTableGenerator_q <= "111010101001101100000101";
WHEN "11001111" => memoryC4_uid54_sqrtTableGenerator_q <= "111010101111011101110101";
WHEN "11010000" => memoryC4_uid54_sqrtTableGenerator_q <= "111010110101000100111000";
WHEN "11010001" => memoryC4_uid54_sqrtTableGenerator_q <= "111010111010100011111001";
WHEN "11010010" => memoryC4_uid54_sqrtTableGenerator_q <= "111010111111111101101000";
WHEN "11010011" => memoryC4_uid54_sqrtTableGenerator_q <= "111011000101010010001111";
WHEN "11010100" => memoryC4_uid54_sqrtTableGenerator_q <= "111011001010011011001101";
WHEN "11010101" => memoryC4_uid54_sqrtTableGenerator_q <= "111011001111011101110100";
WHEN "11010110" => memoryC4_uid54_sqrtTableGenerator_q <= "111011010100011011110101";
WHEN "11010111" => memoryC4_uid54_sqrtTableGenerator_q <= "111011011001010010111100";
WHEN "11011000" => memoryC4_uid54_sqrtTableGenerator_q <= "111011011110000010110111";
WHEN "11011001" => memoryC4_uid54_sqrtTableGenerator_q <= "111011100010101101010110";
WHEN "11011010" => memoryC4_uid54_sqrtTableGenerator_q <= "111011100111001101101101";
WHEN "11011011" => memoryC4_uid54_sqrtTableGenerator_q <= "111011101011101101010100";
WHEN "11011100" => memoryC4_uid54_sqrtTableGenerator_q <= "111011110000000101110010";
WHEN "11011101" => memoryC4_uid54_sqrtTableGenerator_q <= "111011110100010110110100";
WHEN "11011110" => memoryC4_uid54_sqrtTableGenerator_q <= "111011111000100011011111";
WHEN "11011111" => memoryC4_uid54_sqrtTableGenerator_q <= "111011111100101001101100";
WHEN "11100000" => memoryC4_uid54_sqrtTableGenerator_q <= "111100000000101011110100";
WHEN "11100001" => memoryC4_uid54_sqrtTableGenerator_q <= "111100000100101001011101";
WHEN "11100010" => memoryC4_uid54_sqrtTableGenerator_q <= "111100001000100001000011";
WHEN "11100011" => memoryC4_uid54_sqrtTableGenerator_q <= "111100001100010001001010";
WHEN "11100100" => memoryC4_uid54_sqrtTableGenerator_q <= "111100010000000010001010";
WHEN "11100101" => memoryC4_uid54_sqrtTableGenerator_q <= "111100010011101011111111";
WHEN "11100110" => memoryC4_uid54_sqrtTableGenerator_q <= "111100010111010000100001";
WHEN "11100111" => memoryC4_uid54_sqrtTableGenerator_q <= "111100011010110000000111";
WHEN "11101000" => memoryC4_uid54_sqrtTableGenerator_q <= "111100011110001101111110";
WHEN "11101001" => memoryC4_uid54_sqrtTableGenerator_q <= "111100100001100101100111";
WHEN "11101010" => memoryC4_uid54_sqrtTableGenerator_q <= "111100100100111001100011";
WHEN "11101011" => memoryC4_uid54_sqrtTableGenerator_q <= "111100101000000110101010";
WHEN "11101100" => memoryC4_uid54_sqrtTableGenerator_q <= "111100101011010010110101";
WHEN "11101101" => memoryC4_uid54_sqrtTableGenerator_q <= "111100101110011011111110";
WHEN "11101110" => memoryC4_uid54_sqrtTableGenerator_q <= "111100110001011111110001";
WHEN "11101111" => memoryC4_uid54_sqrtTableGenerator_q <= "111100110100100001111101";
WHEN "11110000" => memoryC4_uid54_sqrtTableGenerator_q <= "111100110111011110100110";
WHEN "11110001" => memoryC4_uid54_sqrtTableGenerator_q <= "111100111010011000000100";
WHEN "11110010" => memoryC4_uid54_sqrtTableGenerator_q <= "111100111101001100001110";
WHEN "11110011" => memoryC4_uid54_sqrtTableGenerator_q <= "111100111111111110011110";
WHEN "11110100" => memoryC4_uid54_sqrtTableGenerator_q <= "111101000010101111101110";
WHEN "11110101" => memoryC4_uid54_sqrtTableGenerator_q <= "111101000101011100010001";
WHEN "11110110" => memoryC4_uid54_sqrtTableGenerator_q <= "111101001000000100001101";
WHEN "11110111" => memoryC4_uid54_sqrtTableGenerator_q <= "111101001010101011110100";
WHEN "11111000" => memoryC4_uid54_sqrtTableGenerator_q <= "111101001101001101000000";
WHEN "11111001" => memoryC4_uid54_sqrtTableGenerator_q <= "111101001111101101000010";
WHEN "11111010" => memoryC4_uid54_sqrtTableGenerator_q <= "111101010010001011011111";
WHEN "11111011" => memoryC4_uid54_sqrtTableGenerator_q <= "111101010100100110001101";
WHEN "11111100" => memoryC4_uid54_sqrtTableGenerator_q <= "111101010110111110000100";
WHEN "11111101" => memoryC4_uid54_sqrtTableGenerator_q <= "111101011001010000010000";
WHEN "11111110" => memoryC4_uid54_sqrtTableGenerator_q <= "111101011011100100010001";
WHEN "11111111" => memoryC4_uid54_sqrtTableGenerator_q <= "111101011101110100001010";
WHEN OTHERS =>
memoryC4_uid54_sqrtTableGenerator_q <= "101100000000001000110110";
END CASE;
END IF;
END PROCESS;
--sumAHighB_uid60_sqrtPolynomialEvaluator(ADD,59)@4
sumAHighB_uid60_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((24 downto 24 => memoryC4_uid54_sqrtTableGenerator_q(23)) & memoryC4_uid54_sqrtTableGenerator_q);
sumAHighB_uid60_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((24 downto 17 => highBBits_uid59_sqrtPolynomialEvaluator_b(16)) & highBBits_uid59_sqrtPolynomialEvaluator_b);
sumAHighB_uid60_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid60_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid60_sqrtPolynomialEvaluator_b));
sumAHighB_uid60_sqrtPolynomialEvaluator_q <= sumAHighB_uid60_sqrtPolynomialEvaluator_o(24 downto 0);
--lowRangeB_uid58_sqrtPolynomialEvaluator(BITSELECT,57)@4
lowRangeB_uid58_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid88_pT1_uid57_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid58_sqrtPolynomialEvaluator_b <= lowRangeB_uid58_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid58_uid61_sqrtPolynomialEvaluator(BITJOIN,60)@4
s1_uid58_uid61_sqrtPolynomialEvaluator_q <= sumAHighB_uid60_sqrtPolynomialEvaluator_q & lowRangeB_uid58_sqrtPolynomialEvaluator_b;
--reg_s1_uid58_uid61_sqrtPolynomialEvaluator_0_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_1(REG,130)@4
reg_s1_uid58_uid61_sqrtPolynomialEvaluator_0_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid58_uid61_sqrtPolynomialEvaluator_0_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_s1_uid58_uid61_sqrtPolynomialEvaluator_0_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_1_q <= s1_uid58_uid61_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor(LOGICAL,446)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_b <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_q <= not (ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_a or ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_b);
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_cmpReg(REG,444)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_cmpReg_q <= VCC_q;
END IF;
END PROCESS;
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_sticky_ena(REG,447)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,448)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_b <= VCC_q;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_a and ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_b;
--yT2_uid62_sqrtPolynomialEvaluator(BITSELECT,61)@1
yT2_uid62_sqrtPolynomialEvaluator_in <= X44dto0_uid33_fpSqrtTest_b;
yT2_uid62_sqrtPolynomialEvaluator_b <= yT2_uid62_sqrtPolynomialEvaluator_in(44 downto 21);
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,440)
-- every=1, low=0, high=1, step=1, init=1
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END PROCESS;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_i,1));
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg(REG,441)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,442)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_s <= VCC_q;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,439)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_ia <= yT2_uid62_sqrtPolynomialEvaluator_b;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_iq(23 downto 0);
--ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_outputreg(DELAY,438)
ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_outputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_replace_mem_q, xout => ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_outputreg_q, clk => clk, aclr => areset );
--prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator(MULT,89)@5
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a),25)) * SIGNED(prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_b);
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a <= ld_yT2_uid62_sqrtPolynomialEvaluator_b_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_a_outputreg_q;
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_b <= reg_s1_uid58_uid61_sqrtPolynomialEvaluator_0_to_prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_1_q;
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_pr,50));
END IF;
END PROCESS;
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_q <= prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_s1;
END IF;
END PROCESS;
--prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator(BITSELECT,90)@8
prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator_in <= prodXY_uid90_pT2_uid63_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator_in(49 downto 23);
--highBBits_uid65_sqrtPolynomialEvaluator(BITSELECT,64)@8
highBBits_uid65_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator_b;
highBBits_uid65_sqrtPolynomialEvaluator_b <= highBBits_uid65_sqrtPolynomialEvaluator_in(26 downto 1);
--reg_highBBits_uid65_sqrtPolynomialEvaluator_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_1(REG,131)@8
reg_highBBits_uid65_sqrtPolynomialEvaluator_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid65_sqrtPolynomialEvaluator_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid65_sqrtPolynomialEvaluator_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_1_q <= highBBits_uid65_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor(LOGICAL,422)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_b <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_q <= not (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_a or ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_b);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_mem_top(CONSTANT,418)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_mem_top_q <= "0101";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp(LOGICAL,419)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_mem_top_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_q);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_q <= "1" when ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_a = ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_b else "0";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmpReg(REG,420)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmpReg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_sticky_ena(REG,423)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_nor_q = "1") THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_sticky_ena_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd(LOGICAL,424)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_b <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_a and ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_b;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt(COUNTER,414)
-- every=1, low=0, high=5, step=1, init=1
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i = 4 THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i - 5;
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_i,3));
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg(REG,415)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg_q <= "000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux(MUX,416)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux: PROCESS (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_s, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg_q, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem(DUALMEM,413)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_reset0 <= areset;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_ia <= addrTable_uid32_fpSqrtTest_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_aa <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdreg_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_ab <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_rdmux_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_iq,
address_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_aa,
data_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_ia
);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_iq(7 downto 0);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_outputreg(DELAY,412)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_replace_mem_q, xout => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC3_uid53_sqrtTableGenerator(LOOKUP,52)@8
memoryC3_uid53_sqrtTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC3_uid53_sqrtTableGenerator_q <= "001111111111111111111110110111010";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC3_uid53_sqrtTableGenerator_a_outputreg_q) IS
WHEN "00000000" => memoryC3_uid53_sqrtTableGenerator_q <= "001111111111111111111110110111010";
WHEN "00000001" => memoryC3_uid53_sqrtTableGenerator_q <= "001111101100010001010010000100011";
WHEN "00000010" => memoryC3_uid53_sqrtTableGenerator_q <= "001111011001000100011000101011111";
WHEN "00000011" => memoryC3_uid53_sqrtTableGenerator_q <= "001111000110011000000111111111100";
WHEN "00000100" => memoryC3_uid53_sqrtTableGenerator_q <= "001110110100001011011001101101100";
WHEN "00000101" => memoryC3_uid53_sqrtTableGenerator_q <= "001110100010011101001010011010001";
WHEN "00000110" => memoryC3_uid53_sqrtTableGenerator_q <= "001110010001001100011000100000111";
WHEN "00000111" => memoryC3_uid53_sqrtTableGenerator_q <= "001110000000011000000100111001011";
WHEN "00001000" => memoryC3_uid53_sqrtTableGenerator_q <= "001101101111111111010100111001001";
WHEN "00001001" => memoryC3_uid53_sqrtTableGenerator_q <= "001101100000000001001110000101000";
WHEN "00001010" => memoryC3_uid53_sqrtTableGenerator_q <= "001101010000011100111001101000110";
WHEN "00001011" => memoryC3_uid53_sqrtTableGenerator_q <= "001101000001010001100010010001111";
WHEN "00001100" => memoryC3_uid53_sqrtTableGenerator_q <= "001100110010011110010100100010000";
WHEN "00001101" => memoryC3_uid53_sqrtTableGenerator_q <= "001100100100000010011110101011100";
WHEN "00001110" => memoryC3_uid53_sqrtTableGenerator_q <= "001100010101111101010011100100111";
WHEN "00001111" => memoryC3_uid53_sqrtTableGenerator_q <= "001100001000001110000011110010001";
WHEN "00010000" => memoryC3_uid53_sqrtTableGenerator_q <= "001011111010110100000101110011001";
WHEN "00010001" => memoryC3_uid53_sqrtTableGenerator_q <= "001011101101101110101101000100101";
WHEN "00010010" => memoryC3_uid53_sqrtTableGenerator_q <= "001011100000111101010011000110001";
WHEN "00010011" => memoryC3_uid53_sqrtTableGenerator_q <= "001011010100011111010001001001111";
WHEN "00010100" => memoryC3_uid53_sqrtTableGenerator_q <= "001011001000010100000000010010011";
WHEN "00010101" => memoryC3_uid53_sqrtTableGenerator_q <= "001010111100011010111100100111001";
WHEN "00010110" => memoryC3_uid53_sqrtTableGenerator_q <= "001010110000110011100011111110101";
WHEN "00010111" => memoryC3_uid53_sqrtTableGenerator_q <= "001010100101011101010100111110011";
WHEN "00011000" => memoryC3_uid53_sqrtTableGenerator_q <= "001010011010010111101110001010010";
WHEN "00011001" => memoryC3_uid53_sqrtTableGenerator_q <= "001010001111100010010001101010101";
WHEN "00011010" => memoryC3_uid53_sqrtTableGenerator_q <= "001010000100111100100000010000111";
WHEN "00011011" => memoryC3_uid53_sqrtTableGenerator_q <= "001001111010100101111110011001010";
WHEN "00011100" => memoryC3_uid53_sqrtTableGenerator_q <= "001001110000011110001111100001011";
WHEN "00011101" => memoryC3_uid53_sqrtTableGenerator_q <= "001001100110100100111000001110000";
WHEN "00011110" => memoryC3_uid53_sqrtTableGenerator_q <= "001001011100111001011101101010100";
WHEN "00011111" => memoryC3_uid53_sqrtTableGenerator_q <= "001001010011011011101000101001110";
WHEN "00100000" => memoryC3_uid53_sqrtTableGenerator_q <= "001001001010001010111111010011001";
WHEN "00100001" => memoryC3_uid53_sqrtTableGenerator_q <= "001001000001000111001010100100010";
WHEN "00100010" => memoryC3_uid53_sqrtTableGenerator_q <= "001000111000001111110100100001110";
WHEN "00100011" => memoryC3_uid53_sqrtTableGenerator_q <= "001000101111100100100101111011100";
WHEN "00100100" => memoryC3_uid53_sqrtTableGenerator_q <= "001000100111000101001010011100010";
WHEN "00100101" => memoryC3_uid53_sqrtTableGenerator_q <= "001000011110110001001101101000001";
WHEN "00100110" => memoryC3_uid53_sqrtTableGenerator_q <= "001000010110101000011010100000111";
WHEN "00100111" => memoryC3_uid53_sqrtTableGenerator_q <= "001000001110101010011111100000001";
WHEN "00101000" => memoryC3_uid53_sqrtTableGenerator_q <= "001000000110110111001001000100011";
WHEN "00101001" => memoryC3_uid53_sqrtTableGenerator_q <= "000111111111001110000101111001000";
WHEN "00101010" => memoryC3_uid53_sqrtTableGenerator_q <= "000111110111101111000100100101000";
WHEN "00101011" => memoryC3_uid53_sqrtTableGenerator_q <= "000111110000011001110011010011110";
WHEN "00101100" => memoryC3_uid53_sqrtTableGenerator_q <= "000111101001001110000011000111001";
WHEN "00101101" => memoryC3_uid53_sqrtTableGenerator_q <= "000111100010001011100011011101001";
WHEN "00101110" => memoryC3_uid53_sqrtTableGenerator_q <= "000111011011010010000100110011101";
WHEN "00101111" => memoryC3_uid53_sqrtTableGenerator_q <= "000111010100100001011000100100111";
WHEN "00110000" => memoryC3_uid53_sqrtTableGenerator_q <= "000111001101111001010001110110101";
WHEN "00110001" => memoryC3_uid53_sqrtTableGenerator_q <= "000111000111011001100000001100010";
WHEN "00110010" => memoryC3_uid53_sqrtTableGenerator_q <= "000111000001000001111000100101110";
WHEN "00110011" => memoryC3_uid53_sqrtTableGenerator_q <= "000110111010110010001100110011001";
WHEN "00110100" => memoryC3_uid53_sqrtTableGenerator_q <= "000110110100101010010000100000110";
WHEN "00110101" => memoryC3_uid53_sqrtTableGenerator_q <= "000110101110101001110110010110101";
WHEN "00110110" => memoryC3_uid53_sqrtTableGenerator_q <= "000110101000110000110011011101100";
WHEN "00110111" => memoryC3_uid53_sqrtTableGenerator_q <= "000110100010111110111101011110110";
WHEN "00111000" => memoryC3_uid53_sqrtTableGenerator_q <= "000110011101010100000110101010100";
WHEN "00111001" => memoryC3_uid53_sqrtTableGenerator_q <= "000110010111110000000110000111001";
WHEN "00111010" => memoryC3_uid53_sqrtTableGenerator_q <= "000110010010010010110000011100001";
WHEN "00111011" => memoryC3_uid53_sqrtTableGenerator_q <= "000110001100111011111011100001100";
WHEN "00111100" => memoryC3_uid53_sqrtTableGenerator_q <= "000110000111101011011100111110000";
WHEN "00111101" => memoryC3_uid53_sqrtTableGenerator_q <= "000110000010100001001011111100001";
WHEN "00111110" => memoryC3_uid53_sqrtTableGenerator_q <= "000101111101011100111110011000101";
WHEN "00111111" => memoryC3_uid53_sqrtTableGenerator_q <= "000101111000011110101100110111000";
WHEN "01000000" => memoryC3_uid53_sqrtTableGenerator_q <= "000101110011100110001011110010110";
WHEN "01000001" => memoryC3_uid53_sqrtTableGenerator_q <= "000101101110110011010100010111111";
WHEN "01000010" => memoryC3_uid53_sqrtTableGenerator_q <= "000101101010000101111101110001000";
WHEN "01000011" => memoryC3_uid53_sqrtTableGenerator_q <= "000101100101011110000000111100100";
WHEN "01000100" => memoryC3_uid53_sqrtTableGenerator_q <= "000101100000111011010100001101001";
WHEN "01000101" => memoryC3_uid53_sqrtTableGenerator_q <= "000101011100011101110000100110111";
WHEN "01000110" => memoryC3_uid53_sqrtTableGenerator_q <= "000101011000000101001111001110000";
WHEN "01000111" => memoryC3_uid53_sqrtTableGenerator_q <= "000101010011110001101000110001000";
WHEN "01001000" => memoryC3_uid53_sqrtTableGenerator_q <= "000101001111100010110101100101101";
WHEN "01001001" => memoryC3_uid53_sqrtTableGenerator_q <= "000101001011011000101111000011101";
WHEN "01001010" => memoryC3_uid53_sqrtTableGenerator_q <= "000101000111010011001110101100111";
WHEN "01001011" => memoryC3_uid53_sqrtTableGenerator_q <= "000101000011010010001101001101001";
WHEN "01001100" => memoryC3_uid53_sqrtTableGenerator_q <= "000100111111010101100101010001000";
WHEN "01001101" => memoryC3_uid53_sqrtTableGenerator_q <= "000100111011011101010000001010011";
WHEN "01001110" => memoryC3_uid53_sqrtTableGenerator_q <= "000100110111101001000111100011110";
WHEN "01001111" => memoryC3_uid53_sqrtTableGenerator_q <= "000100110011111001000111010100010";
WHEN "01010000" => memoryC3_uid53_sqrtTableGenerator_q <= "000100110000001101001000001110011";
WHEN "01010001" => memoryC3_uid53_sqrtTableGenerator_q <= "000100101100100101000101100101100";
WHEN "01010010" => memoryC3_uid53_sqrtTableGenerator_q <= "000100101001000000111000010111010";
WHEN "01010011" => memoryC3_uid53_sqrtTableGenerator_q <= "000100100101100000011101011000000";
WHEN "01010100" => memoryC3_uid53_sqrtTableGenerator_q <= "000100100010000011101110010011100";
WHEN "01010101" => memoryC3_uid53_sqrtTableGenerator_q <= "000100011110101010100111001000010";
WHEN "01010110" => memoryC3_uid53_sqrtTableGenerator_q <= "000100011011010101000010001100010";
WHEN "01010111" => memoryC3_uid53_sqrtTableGenerator_q <= "000100011000000010111010010001101";
WHEN "01011000" => memoryC3_uid53_sqrtTableGenerator_q <= "000100010100110100001100010000010";
WHEN "01011001" => memoryC3_uid53_sqrtTableGenerator_q <= "000100010001101000110010111100100";
WHEN "01011010" => memoryC3_uid53_sqrtTableGenerator_q <= "000100001110100000101001011010100";
WHEN "01011011" => memoryC3_uid53_sqrtTableGenerator_q <= "000100001011011011101100100110110";
WHEN "01011100" => memoryC3_uid53_sqrtTableGenerator_q <= "000100001000011001110111010011000";
WHEN "01011101" => memoryC3_uid53_sqrtTableGenerator_q <= "000100000101011011000101101010011";
WHEN "01011110" => memoryC3_uid53_sqrtTableGenerator_q <= "000100000010011111010100010101000";
WHEN "01011111" => memoryC3_uid53_sqrtTableGenerator_q <= "000011111111100110011101110011011";
WHEN "01100000" => memoryC3_uid53_sqrtTableGenerator_q <= "000011111100110000100000000111100";
WHEN "01100001" => memoryC3_uid53_sqrtTableGenerator_q <= "000011111001111101010111110111111";
WHEN "01100010" => memoryC3_uid53_sqrtTableGenerator_q <= "000011110111001100111111111110111";
WHEN "01100011" => memoryC3_uid53_sqrtTableGenerator_q <= "000011110100011111010100100100100";
WHEN "01100100" => memoryC3_uid53_sqrtTableGenerator_q <= "000011110001110100010100100111011";
WHEN "01100101" => memoryC3_uid53_sqrtTableGenerator_q <= "000011101111001011111011000100011";
WHEN "01100110" => memoryC3_uid53_sqrtTableGenerator_q <= "000011101100100110000100110011101";
WHEN "01100111" => memoryC3_uid53_sqrtTableGenerator_q <= "000011101010000010101110000001001";
WHEN "01101000" => memoryC3_uid53_sqrtTableGenerator_q <= "000011100111100001110101001111000";
WHEN "01101001" => memoryC3_uid53_sqrtTableGenerator_q <= "000011100101000011010111011001101";
WHEN "01101010" => memoryC3_uid53_sqrtTableGenerator_q <= "000011100010100111001111111110111";
WHEN "01101011" => memoryC3_uid53_sqrtTableGenerator_q <= "000011100000001101011101000110100";
WHEN "01101100" => memoryC3_uid53_sqrtTableGenerator_q <= "000011011101110101111011000100000";
WHEN "01101101" => memoryC3_uid53_sqrtTableGenerator_q <= "000011011011100000101000100100000";
WHEN "01101110" => memoryC3_uid53_sqrtTableGenerator_q <= "000011011001001101100001011111110";
WHEN "01101111" => memoryC3_uid53_sqrtTableGenerator_q <= "000011010110111100100100010001111";
WHEN "01110000" => memoryC3_uid53_sqrtTableGenerator_q <= "000011010100101101101101010101111";
WHEN "01110001" => memoryC3_uid53_sqrtTableGenerator_q <= "000011010010100000111011100100000";
WHEN "01110010" => memoryC3_uid53_sqrtTableGenerator_q <= "000011010000010110001011110000001";
WHEN "01110011" => memoryC3_uid53_sqrtTableGenerator_q <= "000011001110001101011011100100111";
WHEN "01110100" => memoryC3_uid53_sqrtTableGenerator_q <= "000011001100000110100111111100100";
WHEN "01110101" => memoryC3_uid53_sqrtTableGenerator_q <= "000011001010000001101110111101011";
WHEN "01110110" => memoryC3_uid53_sqrtTableGenerator_q <= "000011000111111110101110101101100";
WHEN "01110111" => memoryC3_uid53_sqrtTableGenerator_q <= "000011000101111101100101100011011";
WHEN "01111000" => memoryC3_uid53_sqrtTableGenerator_q <= "000011000011111110001111111101111";
WHEN "01111001" => memoryC3_uid53_sqrtTableGenerator_q <= "000011000010000000101100111001111";
WHEN "01111010" => memoryC3_uid53_sqrtTableGenerator_q <= "000011000000000100111001111010111";
WHEN "01111011" => memoryC3_uid53_sqrtTableGenerator_q <= "000010111110001010110101010110011";
WHEN "01111100" => memoryC3_uid53_sqrtTableGenerator_q <= "000010111100010010011101000100001";
WHEN "01111101" => memoryC3_uid53_sqrtTableGenerator_q <= "000010111010011011101111010101010";
WHEN "01111110" => memoryC3_uid53_sqrtTableGenerator_q <= "000010111000100110101000111001001";
WHEN "01111111" => memoryC3_uid53_sqrtTableGenerator_q <= "000010110110110011001010001100111";
WHEN "10000000" => memoryC3_uid53_sqrtTableGenerator_q <= "010110101000001001110111100000000";
WHEN "10000001" => memoryC3_uid53_sqrtTableGenerator_q <= "010110001100010000001001100111010";
WHEN "10000010" => memoryC3_uid53_sqrtTableGenerator_q <= "010101110001000110001101101001100";
WHEN "10000011" => memoryC3_uid53_sqrtTableGenerator_q <= "010101010110101010011100101011011";
WHEN "10000100" => memoryC3_uid53_sqrtTableGenerator_q <= "010100111100111011010011000010100";
WHEN "10000101" => memoryC3_uid53_sqrtTableGenerator_q <= "010100100011110111001110110000110";
WHEN "10000110" => memoryC3_uid53_sqrtTableGenerator_q <= "010100001011011100110101100110101";
WHEN "10000111" => memoryC3_uid53_sqrtTableGenerator_q <= "010011110011101010101110010001011";
WHEN "10001000" => memoryC3_uid53_sqrtTableGenerator_q <= "010011011100011111100011100010111";
WHEN "10001001" => memoryC3_uid53_sqrtTableGenerator_q <= "010011000101111010000101000111101";
WHEN "10001010" => memoryC3_uid53_sqrtTableGenerator_q <= "010010101111111001000101001000011";
WHEN "10001011" => memoryC3_uid53_sqrtTableGenerator_q <= "010010011010011011010110100110101";
WHEN "10001100" => memoryC3_uid53_sqrtTableGenerator_q <= "010010000101011111110010001001000";
WHEN "10001101" => memoryC3_uid53_sqrtTableGenerator_q <= "010001110001000101010010001000010";
WHEN "10001110" => memoryC3_uid53_sqrtTableGenerator_q <= "010001011101001010110101000000000";
WHEN "10001111" => memoryC3_uid53_sqrtTableGenerator_q <= "010001001001101111011001000001000";
WHEN "10010000" => memoryC3_uid53_sqrtTableGenerator_q <= "010000110110110010000001101111111";
WHEN "10010001" => memoryC3_uid53_sqrtTableGenerator_q <= "010000100100010001110010111000000";
WHEN "10010010" => memoryC3_uid53_sqrtTableGenerator_q <= "010000010010001101110011101101010";
WHEN "10010011" => memoryC3_uid53_sqrtTableGenerator_q <= "010000000000100101001101011110000";
WHEN "10010100" => memoryC3_uid53_sqrtTableGenerator_q <= "001111101111010111001010011110000";
WHEN "10010101" => memoryC3_uid53_sqrtTableGenerator_q <= "001111011110100010110111100111010";
WHEN "10010110" => memoryC3_uid53_sqrtTableGenerator_q <= "001111001110000111100011111111100";
WHEN "10010111" => memoryC3_uid53_sqrtTableGenerator_q <= "001110111110000100100000101010000";
WHEN "10011000" => memoryC3_uid53_sqrtTableGenerator_q <= "001110101110011000111110111010101";
WHEN "10011001" => memoryC3_uid53_sqrtTableGenerator_q <= "001110011111000100010011001001001";
WHEN "10011010" => memoryC3_uid53_sqrtTableGenerator_q <= "001110010000000101110011100011000";
WHEN "10011011" => memoryC3_uid53_sqrtTableGenerator_q <= "001110000001011100110101110111000";
WHEN "10011100" => memoryC3_uid53_sqrtTableGenerator_q <= "001101110011001000110011001100111";
WHEN "10011101" => memoryC3_uid53_sqrtTableGenerator_q <= "001101100101001001000100100110001";
WHEN "10011110" => memoryC3_uid53_sqrtTableGenerator_q <= "001101010111011101000110111101000";
WHEN "10011111" => memoryC3_uid53_sqrtTableGenerator_q <= "001101001010000100010101000101011";
WHEN "10100000" => memoryC3_uid53_sqrtTableGenerator_q <= "001100111100111110001100111001001";
WHEN "10100001" => memoryC3_uid53_sqrtTableGenerator_q <= "001100110000001010001101101001100";
WHEN "10100010" => memoryC3_uid53_sqrtTableGenerator_q <= "001100100011100111110111100000010";
WHEN "10100011" => memoryC3_uid53_sqrtTableGenerator_q <= "001100010111010110101001110111111";
WHEN "10100100" => memoryC3_uid53_sqrtTableGenerator_q <= "001100001011010110001000110101101";
WHEN "10100101" => memoryC3_uid53_sqrtTableGenerator_q <= "001011111111100101110100110110000";
WHEN "10100110" => memoryC3_uid53_sqrtTableGenerator_q <= "001011110100000101010101000001011";
WHEN "10100111" => memoryC3_uid53_sqrtTableGenerator_q <= "001011101000110100001011011011101";
WHEN "10101000" => memoryC3_uid53_sqrtTableGenerator_q <= "001011011101110001111111110010000";
WHEN "10101001" => memoryC3_uid53_sqrtTableGenerator_q <= "001011010010111110011000001000000";
WHEN "10101010" => memoryC3_uid53_sqrtTableGenerator_q <= "001011001000011000111011101010101";
WHEN "10101011" => memoryC3_uid53_sqrtTableGenerator_q <= "001010111110000001010010100011011";
WHEN "10101100" => memoryC3_uid53_sqrtTableGenerator_q <= "001010110011110111000101011111001";
WHEN "10101101" => memoryC3_uid53_sqrtTableGenerator_q <= "001010101001111001111111111010101";
WHEN "10101110" => memoryC3_uid53_sqrtTableGenerator_q <= "001010100000001001101001101111110";
WHEN "10101111" => memoryC3_uid53_sqrtTableGenerator_q <= "001010010110100101101111101101001";
WHEN "10110000" => memoryC3_uid53_sqrtTableGenerator_q <= "001010001101001101111100101000101";
WHEN "10110001" => memoryC3_uid53_sqrtTableGenerator_q <= "001010000100000001111110001110000";
WHEN "10110010" => memoryC3_uid53_sqrtTableGenerator_q <= "001001111011000001100000001011001";
WHEN "10110011" => memoryC3_uid53_sqrtTableGenerator_q <= "001001110010001100010000100101000";
WHEN "10110100" => memoryC3_uid53_sqrtTableGenerator_q <= "001001101001100001111101110101010";
WHEN "10110101" => memoryC3_uid53_sqrtTableGenerator_q <= "001001100001000010010101111110010";
WHEN "10110110" => memoryC3_uid53_sqrtTableGenerator_q <= "001001011000101101001000100101110";
WHEN "10110111" => memoryC3_uid53_sqrtTableGenerator_q <= "001001010000100010000100101011100";
WHEN "10111000" => memoryC3_uid53_sqrtTableGenerator_q <= "001001001000100000111011011101101";
WHEN "10111001" => memoryC3_uid53_sqrtTableGenerator_q <= "001001000000101001011101000100111";
WHEN "10111010" => memoryC3_uid53_sqrtTableGenerator_q <= "001000111000111011011010100010000";
WHEN "10111011" => memoryC3_uid53_sqrtTableGenerator_q <= "001000110001010110100100011101100";
WHEN "10111100" => memoryC3_uid53_sqrtTableGenerator_q <= "001000101001111010101110110001011";
WHEN "10111101" => memoryC3_uid53_sqrtTableGenerator_q <= "001000100010100111101010110101010";
WHEN "10111110" => memoryC3_uid53_sqrtTableGenerator_q <= "001000011011011101001011000000100";
WHEN "10111111" => memoryC3_uid53_sqrtTableGenerator_q <= "001000010100011011000010100110011";
WHEN "11000000" => memoryC3_uid53_sqrtTableGenerator_q <= "001000001101100001000101010110001";
WHEN "11000001" => memoryC3_uid53_sqrtTableGenerator_q <= "001000000110101111000111111000011";
WHEN "11000010" => memoryC3_uid53_sqrtTableGenerator_q <= "001000000000000100111100000101000";
WHEN "11000011" => memoryC3_uid53_sqrtTableGenerator_q <= "000111111001100010011001011111000";
WHEN "11000100" => memoryC3_uid53_sqrtTableGenerator_q <= "000111110011000111010010100110110";
WHEN "11000101" => memoryC3_uid53_sqrtTableGenerator_q <= "000111101100110011011101010010101";
WHEN "11000110" => memoryC3_uid53_sqrtTableGenerator_q <= "000111100110100110101111000111110";
WHEN "11000111" => memoryC3_uid53_sqrtTableGenerator_q <= "000111100000100000111110001101111";
WHEN "11001000" => memoryC3_uid53_sqrtTableGenerator_q <= "000111011010100001111111110000100";
WHEN "11001001" => memoryC3_uid53_sqrtTableGenerator_q <= "000111010100101001101011010010011";
WHEN "11001010" => memoryC3_uid53_sqrtTableGenerator_q <= "000111001110110111110101011100110";
WHEN "11001011" => memoryC3_uid53_sqrtTableGenerator_q <= "000111001001001100010111011001000";
WHEN "11001100" => memoryC3_uid53_sqrtTableGenerator_q <= "000111000011100111000110011110100";
WHEN "11001101" => memoryC3_uid53_sqrtTableGenerator_q <= "000110111110000111111010001001100";
WHEN "11001110" => memoryC3_uid53_sqrtTableGenerator_q <= "000110111000101110101010110101100";
WHEN "11001111" => memoryC3_uid53_sqrtTableGenerator_q <= "000110110011011011001111001010010";
WHEN "11010000" => memoryC3_uid53_sqrtTableGenerator_q <= "000110101110001101100000010101111";
WHEN "11010001" => memoryC3_uid53_sqrtTableGenerator_q <= "000110101001000101010110000001111";
WHEN "11010010" => memoryC3_uid53_sqrtTableGenerator_q <= "000110100100000010100111111110001";
WHEN "11010011" => memoryC3_uid53_sqrtTableGenerator_q <= "000110011111000101001110101100110";
WHEN "11010100" => memoryC3_uid53_sqrtTableGenerator_q <= "000110011010001101000100110000011";
WHEN "11010101" => memoryC3_uid53_sqrtTableGenerator_q <= "000110010101011010000001110101010";
WHEN "11010110" => memoryC3_uid53_sqrtTableGenerator_q <= "000110010000101011111110100101111";
WHEN "11010111" => memoryC3_uid53_sqrtTableGenerator_q <= "000110001100000010110100111100110";
WHEN "11011000" => memoryC3_uid53_sqrtTableGenerator_q <= "000110000111011110011110101101001";
WHEN "11011001" => memoryC3_uid53_sqrtTableGenerator_q <= "000110000010111110110100111100100";
WHEN "11011010" => memoryC3_uid53_sqrtTableGenerator_q <= "000101111110100011110010101010110";
WHEN "11011011" => memoryC3_uid53_sqrtTableGenerator_q <= "000101111010001101001111101100111";
WHEN "11011100" => memoryC3_uid53_sqrtTableGenerator_q <= "000101110101111011000111101010111";
WHEN "11011101" => memoryC3_uid53_sqrtTableGenerator_q <= "000101110001101101010100111011000";
WHEN "11011110" => memoryC3_uid53_sqrtTableGenerator_q <= "000101101101100011110001010010100";
WHEN "11011111" => memoryC3_uid53_sqrtTableGenerator_q <= "000101101001011110010111101110100";
WHEN "11100000" => memoryC3_uid53_sqrtTableGenerator_q <= "000101100101011101000010011010000";
WHEN "11100001" => memoryC3_uid53_sqrtTableGenerator_q <= "000101100001011111101100010011111";
WHEN "11100010" => memoryC3_uid53_sqrtTableGenerator_q <= "000101011101100110010000100111101";
WHEN "11100011" => memoryC3_uid53_sqrtTableGenerator_q <= "000101011001110000101010111110100";
WHEN "11100100" => memoryC3_uid53_sqrtTableGenerator_q <= "000101010101111110110100011100101";
WHEN "11100101" => memoryC3_uid53_sqrtTableGenerator_q <= "000101010010010000101010010000100";
WHEN "11100110" => memoryC3_uid53_sqrtTableGenerator_q <= "000101001110100110000111100010110";
WHEN "11100111" => memoryC3_uid53_sqrtTableGenerator_q <= "000101001010111111000111100110001";
WHEN "11101000" => memoryC3_uid53_sqrtTableGenerator_q <= "000101000111011011100101010100001";
WHEN "11101001" => memoryC3_uid53_sqrtTableGenerator_q <= "000101000011111011011101100010111";
WHEN "11101010" => memoryC3_uid53_sqrtTableGenerator_q <= "000101000000011110101011100001101";
WHEN "11101011" => memoryC3_uid53_sqrtTableGenerator_q <= "000100111101000101001100000100010";
WHEN "11101100" => memoryC3_uid53_sqrtTableGenerator_q <= "000100111001101110111001100010000";
WHEN "11101101" => memoryC3_uid53_sqrtTableGenerator_q <= "000100110110011011110000101111110";
WHEN "11101110" => memoryC3_uid53_sqrtTableGenerator_q <= "000100110011001011101110011011111";
WHEN "11101111" => memoryC3_uid53_sqrtTableGenerator_q <= "000100101111111110101101111101001";
WHEN "11110000" => memoryC3_uid53_sqrtTableGenerator_q <= "000100101100110100101100101011010";
WHEN "11110001" => memoryC3_uid53_sqrtTableGenerator_q <= "000100101001101101100110100111010";
WHEN "11110010" => memoryC3_uid53_sqrtTableGenerator_q <= "000100100110101001011000101001000";
WHEN "11110011" => memoryC3_uid53_sqrtTableGenerator_q <= "000100100011100111111110100101110";
WHEN "11110100" => memoryC3_uid53_sqrtTableGenerator_q <= "000100100000101001010101000110001";
WHEN "11110101" => memoryC3_uid53_sqrtTableGenerator_q <= "000100011101101101011001101010000";
WHEN "11110110" => memoryC3_uid53_sqrtTableGenerator_q <= "000100011010110100001001001111011";
WHEN "11110111" => memoryC3_uid53_sqrtTableGenerator_q <= "000100010111111101011111100111110";
WHEN "11111000" => memoryC3_uid53_sqrtTableGenerator_q <= "000100010101001001011011010101100";
WHEN "11111001" => memoryC3_uid53_sqrtTableGenerator_q <= "000100010010010111111000000111011";
WHEN "11111010" => memoryC3_uid53_sqrtTableGenerator_q <= "000100001111101000110011001001101";
WHEN "11111011" => memoryC3_uid53_sqrtTableGenerator_q <= "000100001100111100001010001101001";
WHEN "11111100" => memoryC3_uid53_sqrtTableGenerator_q <= "000100001010010001111010010011100";
WHEN "11111101" => memoryC3_uid53_sqrtTableGenerator_q <= "000100000111101010000001011001100";
WHEN "11111110" => memoryC3_uid53_sqrtTableGenerator_q <= "000100000101000100011011000101011";
WHEN "11111111" => memoryC3_uid53_sqrtTableGenerator_q <= "000100000010100001000110000110010";
WHEN OTHERS =>
memoryC3_uid53_sqrtTableGenerator_q <= "001111111111111111111110110111010";
END CASE;
END IF;
END PROCESS;
--sumAHighB_uid66_sqrtPolynomialEvaluator(ADD,65)@9
sumAHighB_uid66_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((33 downto 33 => memoryC3_uid53_sqrtTableGenerator_q(32)) & memoryC3_uid53_sqrtTableGenerator_q);
sumAHighB_uid66_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((33 downto 26 => reg_highBBits_uid65_sqrtPolynomialEvaluator_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_1_q(25)) & reg_highBBits_uid65_sqrtPolynomialEvaluator_0_to_sumAHighB_uid66_sqrtPolynomialEvaluator_1_q);
sumAHighB_uid66_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid66_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid66_sqrtPolynomialEvaluator_b));
sumAHighB_uid66_sqrtPolynomialEvaluator_q <= sumAHighB_uid66_sqrtPolynomialEvaluator_o(33 downto 0);
--lowRangeB_uid64_sqrtPolynomialEvaluator(BITSELECT,63)@8
lowRangeB_uid64_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid91_pT2_uid63_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid64_sqrtPolynomialEvaluator_b <= lowRangeB_uid64_sqrtPolynomialEvaluator_in(0 downto 0);
--ld_lowRangeB_uid64_sqrtPolynomialEvaluator_b_to_s2_uid64_uid67_sqrtPolynomialEvaluator_a(DELAY,217)@8
ld_lowRangeB_uid64_sqrtPolynomialEvaluator_b_to_s2_uid64_uid67_sqrtPolynomialEvaluator_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => lowRangeB_uid64_sqrtPolynomialEvaluator_b, xout => ld_lowRangeB_uid64_sqrtPolynomialEvaluator_b_to_s2_uid64_uid67_sqrtPolynomialEvaluator_a_q, clk => clk, aclr => areset );
--s2_uid64_uid67_sqrtPolynomialEvaluator(BITJOIN,66)@9
s2_uid64_uid67_sqrtPolynomialEvaluator_q <= sumAHighB_uid66_sqrtPolynomialEvaluator_q & ld_lowRangeB_uid64_sqrtPolynomialEvaluator_b_to_s2_uid64_uid67_sqrtPolynomialEvaluator_a_q;
--reg_s2_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_1(REG,132)@9
reg_s2_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s2_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_s2_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_1_q <= s2_uid64_uid67_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor(LOGICAL,459)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_b <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_q <= not (ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_a or ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_b);
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,455)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_mem_top_q <= "0110";
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp(LOGICAL,456)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_a <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_mem_top_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_a = ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmpReg(REG,457)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END PROCESS;
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_sticky_ena(REG,460)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,461)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_b <= VCC_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_a and ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_b;
--yT3_uid68_sqrtPolynomialEvaluator(BITSELECT,67)@1
yT3_uid68_sqrtPolynomialEvaluator_in <= X44dto0_uid33_fpSqrtTest_b;
yT3_uid68_sqrtPolynomialEvaluator_b <= yT3_uid68_sqrtPolynomialEvaluator_in(44 downto 12);
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,451)
-- every=1, low=0, high=6, step=1, init=1
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 5 THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 6;
ELSE
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_i,3));
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg(REG,452)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,453)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_s <= VCC_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,450)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_ia <= yT3_uid68_sqrtPolynomialEvaluator_b;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 3,
numwords_a => 7,
width_b => 33,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_iq(32 downto 0);
--ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_outputreg(DELAY,449)
ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_outputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_replace_mem_q, xout => ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_outputreg_q, clk => clk, aclr => areset );
--prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator(MULT,92)@10
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a),34)) * SIGNED(prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_b);
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a <= ld_yT3_uid68_sqrtPolynomialEvaluator_b_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_a_outputreg_q;
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_b <= reg_s2_uid64_uid67_sqrtPolynomialEvaluator_0_to_prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_1_q;
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_pr,68));
END IF;
END PROCESS;
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_q <= prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_s1;
END IF;
END PROCESS;
--prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator(BITSELECT,93)@13
prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator_in <= prodXY_uid93_pT3_uid69_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator_in(67 downto 34);
--highBBits_uid71_sqrtPolynomialEvaluator(BITSELECT,70)@13
highBBits_uid71_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator_b;
highBBits_uid71_sqrtPolynomialEvaluator_b <= highBBits_uid71_sqrtPolynomialEvaluator_in(33 downto 1);
--reg_highBBits_uid71_sqrtPolynomialEvaluator_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_1(REG,133)@13
reg_highBBits_uid71_sqrtPolynomialEvaluator_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid71_sqrtPolynomialEvaluator_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid71_sqrtPolynomialEvaluator_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_1_q <= highBBits_uid71_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor(LOGICAL,409)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_b <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_q <= not (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_a or ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_b);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_mem_top(CONSTANT,405)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_mem_top_q <= "01010";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp(LOGICAL,406)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_mem_top_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_q);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_q <= "1" when ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_a = ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_b else "0";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmpReg(REG,407)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmpReg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_sticky_ena(REG,410)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_nor_q = "1") THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_sticky_ena_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd(LOGICAL,411)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_b <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_a and ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_b;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt(COUNTER,401)
-- every=1, low=0, high=10, step=1, init=1
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i = 9 THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i - 10;
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_i,4));
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg(REG,402)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg_q <= "0000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux(MUX,403)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux: PROCESS (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_s, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg_q, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem(DUALMEM,400)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_reset0 <= areset;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_ia <= addrTable_uid32_fpSqrtTest_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_aa <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdreg_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_ab <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_rdmux_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_iq,
address_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_aa,
data_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_ia
);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_iq(7 downto 0);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_outputreg(DELAY,399)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_replace_mem_q, xout => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC2_uid52_sqrtTableGenerator(LOOKUP,51)@13
memoryC2_uid52_sqrtTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid52_sqrtTableGenerator_q <= "1100000000000000000000000000000001000010";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC2_uid52_sqrtTableGenerator_a_outputreg_q) IS
WHEN "00000000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100000000000000000000000000000001000010";
WHEN "00000001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100000010111110001001000101011001110000";
WHEN "00000010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100000101111000101000100110010100110010";
WHEN "00000011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100001000101111100100110001011011010000";
WHEN "00000100" => memoryC2_uid52_sqrtTableGenerator_q <= "1100001011100011000011100111110000000101";
WHEN "00000101" => memoryC2_uid52_sqrtTableGenerator_q <= "1100001110010011001010111101010101110111";
WHEN "00000110" => memoryC2_uid52_sqrtTableGenerator_q <= "1100010001000000000000011001110010011100";
WHEN "00000111" => memoryC2_uid52_sqrtTableGenerator_q <= "1100010011101001101001011000101110111001";
WHEN "00001000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100010110010000001011001010010001101000";
WHEN "00001001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100011000110011101010110011100011101000";
WHEN "00001010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100011011010100001101001111000110001010";
WHEN "00001011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100011101110001110111001101010001100100";
WHEN "00001100" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100000001100101101010100101100111111";
WHEN "00001101" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100010100100110100000010100111100111";
WHEN "00001110" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100100111010001111101011001010101101";
WHEN "00001111" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100111001101000100011001111011000110";
WHEN "00010000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101001011101010110010010000000000001";
WHEN "00010001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101011101011001001001110100111100110";
WHEN "00010010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101101110110100001000011001001000101";
WHEN "00010011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101111111111100001011011100010101101";
WHEN "00010100" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110010000110001101111100101011011110";
WHEN "00010101" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110100001010101010000100011101100010";
WHEN "00010110" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110110001100111001001010001001001001";
WHEN "00010111" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111000001100111110011110100101110000";
WHEN "00011000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111010001010111101001100100001010100";
WHEN "00011001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111100000110111000011000101001011010";
WHEN "00011010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111110000000110011000001111111111110";
WHEN "00011011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111111111000110000000010000000011001";
WHEN "00011100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000001101110110010001100110011100101";
WHEN "00011101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000011100010111100010001011000001100";
WHEN "00011110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000101010101010000111001101111001101";
WHEN "00011111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000111000101110010101011000001100011";
WHEN "00100000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001000110100100100000101110101001011";
WHEN "00100001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001010100001100111100110001110000001";
WHEN "00100010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001100001100111111100011111010001100";
WHEN "00100011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001101110110101110010010011111110011";
WHEN "00100100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001111011110110110000001011110011110";
WHEN "00100101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010001000101011000111100011101001111";
WHEN "00100110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010010101010011001001011010011001010";
WHEN "00100111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010100001101111000110010001000110010";
WHEN "00101000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010101101111111001110001101000110010";
WHEN "00101001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010111010000011110000111000000010011";
WHEN "00101010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011000101111100111101100001001100100";
WHEN "00101011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011010001101011000010111110011100010";
WHEN "00101100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011011101001110001111101100010111110";
WHEN "00101101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011101000100110110001101111111100111";
WHEN "00101110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011110011110100110110110110110011010";
WHEN "00101111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011111110111000101100010111111100010";
WHEN "00110000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100001001110010011111010100001110010";
WHEN "00110001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100010100100010011100011000010010010";
WHEN "00110010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100011111001000101111111011000111001";
WHEN "00110011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100101001100101100110000000101010010";
WHEN "00110100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100110011111001001010011001010000000";
WHEN "00110101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100111110000011101000100010110111001";
WHEN "00110110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101001000000101001011101000111000010";
WHEN "00110111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101010001111101111110100101000110110";
WHEN "00111000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101011011101110001100000001000011001";
WHEN "00111001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101100101010101111110010100110001000";
WHEN "00111010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101101110110101011111101000110011011";
WHEN "00111011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101111000001100111001110101111110010";
WHEN "00111100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110000001011100010110100110000100000";
WHEN "00111101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110001010100011111111010011111000011";
WHEN "00111110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110010011100011111101001100010101000";
WHEN "00111111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110011100011100011001001101111010001";
WHEN "01000000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110100101001101011100001010101010010";
WHEN "01000001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110101101110111001110100110100010001";
WHEN "01000010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110110110011001111000111001010011001";
WHEN "01000011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110111110110101100011001110000001111";
WHEN "01000100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111000111001010010101100100011010011";
WHEN "01000101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111001111011000010111101111111100100";
WHEN "01000110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111010111011111110001011000110011111";
WHEN "01000111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111011111100000101001111100010001110";
WHEN "01001000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111100111011011001000101101000010111";
WHEN "01001001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111101111001111010100110011001001100";
WHEN "01001010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111110110111101010101001100100011000";
WHEN "01001011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111111110100101010000101101011110101";
WHEN "01001100" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000000110000111001110000000001110010";
WHEN "01001101" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000001101100011010011100110000011111";
WHEN "01001110" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000010100111001100111110111000100101";
WHEN "01001111" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000011100001010010001000010000100110";
WHEN "01010000" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000100011010101010101001101111101001";
WHEN "01010001" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000101010011010111010011000101011101";
WHEN "01010010" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000110001011011000110011000100100110";
WHEN "01010011" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000111000010101111110111011001101011";
WHEN "01010100" => memoryC2_uid52_sqrtTableGenerator_q <= "1110000111111001011101001100111000100001";
WHEN "01010101" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001000101111100001011111010101001110";
WHEN "01010110" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001001100100111101011001101011110000";
WHEN "01010111" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001010011001110001100101111101101110";
WHEN "01011000" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001011001101111110101101010010010001";
WHEN "01011001" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001100000001100101010111111100111010";
WHEN "01011010" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001100110100100110001101011100000000";
WHEN "01011011" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001101100111000001110100010111010111";
WHEN "01011100" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001110011000111000110010100111110110";
WHEN "01011101" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001111001010001011101101010010110110";
WHEN "01011110" => memoryC2_uid52_sqrtTableGenerator_q <= "1110001111111010111011001000101101000110";
WHEN "01011111" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010000101011000111101000100000001001";
WHEN "01100000" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010001011010110001101111100010010001";
WHEN "01100001" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010010001001111001111111111111100011";
WHEN "01100010" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010010111000100000111011011011010100";
WHEN "01100011" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010011100110100111000010101101000000";
WHEN "01100100" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010100010100001100110101111101011011";
WHEN "01100101" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010101000001010010110100110100000110";
WHEN "01100110" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010101101101111001011110001110000000";
WHEN "01100111" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010110011010000001010000100010111011";
WHEN "01101000" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010111000101101010101001100000110100";
WHEN "01101001" => memoryC2_uid52_sqrtTableGenerator_q <= "1110010111110000110110000110010100001001";
WHEN "01101010" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011000011011100100000011100111100101";
WHEN "01101011" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011001000101110100111101011110110110";
WHEN "01101100" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011001101111101001001111011110011101";
WHEN "01101101" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011010011001000001010100100101100101";
WHEN "01101110" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011011000001111101100111010111010110";
WHEN "01101111" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011011101010011110100001110011000011";
WHEN "01110000" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011100010010100100011101011100001011";
WHEN "01110001" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011100111010001111110011010011110011";
WHEN "01110010" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011101100001100000111100000000100110";
WHEN "01110011" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011110001000011000001111101010111100";
WHEN "01110100" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011110101110110110000110000000000010";
WHEN "01110101" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011111010100111010110110001111011011";
WHEN "01110110" => memoryC2_uid52_sqrtTableGenerator_q <= "1110011111111010100110110111001101100111";
WHEN "01110111" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100000011111111010011111010011110101";
WHEN "01111000" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100001000100110110000100100101000010";
WHEN "01111001" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100001101001011001111100100110001111";
WHEN "01111010" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100010001101100110011100100110001011";
WHEN "01111011" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100010110001011011111001011010001001";
WHEN "01111100" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100011010100111010100111100000011111";
WHEN "01111101" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100011111000000010111010111111010011";
WHEN "01111110" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100100011010110101000111101001000001";
WHEN "01111111" => memoryC2_uid52_sqrtTableGenerator_q <= "1110100100111101010001100000110011010011";
WHEN "10000000" => memoryC2_uid52_sqrtTableGenerator_q <= "1010010101111101100001100110011010010110";
WHEN "10000001" => memoryC2_uid52_sqrtTableGenerator_q <= "1010011010001010011011010010001010010101";
WHEN "10000010" => memoryC2_uid52_sqrtTableGenerator_q <= "1010011110010010001010101001101000100010";
WHEN "10000011" => memoryC2_uid52_sqrtTableGenerator_q <= "1010100010010100111000100000100001010100";
WHEN "10000100" => memoryC2_uid52_sqrtTableGenerator_q <= "1010100110010010101101010111010111011000";
WHEN "10000101" => memoryC2_uid52_sqrtTableGenerator_q <= "1010101010001011110001011100011000100011";
WHEN "10000110" => memoryC2_uid52_sqrtTableGenerator_q <= "1010101110000000001100101100000011010111";
WHEN "10000111" => memoryC2_uid52_sqrtTableGenerator_q <= "1010110001110000000110110010000000000011";
WHEN "10001000" => memoryC2_uid52_sqrtTableGenerator_q <= "1010110101011011100111001001100111011011";
WHEN "10001001" => memoryC2_uid52_sqrtTableGenerator_q <= "1010111001000010110100111110101001100111";
WHEN "10001010" => memoryC2_uid52_sqrtTableGenerator_q <= "1010111100100101110111001101111010011010";
WHEN "10001011" => memoryC2_uid52_sqrtTableGenerator_q <= "1011000000000100110100100101111001101001";
WHEN "10001100" => memoryC2_uid52_sqrtTableGenerator_q <= "1011000011011111110011100111001110011011";
WHEN "10001101" => memoryC2_uid52_sqrtTableGenerator_q <= "1011000110110110111010100101010000010010";
WHEN "10001110" => memoryC2_uid52_sqrtTableGenerator_q <= "1011001010001010001111100110100011110101";
WHEN "10001111" => memoryC2_uid52_sqrtTableGenerator_q <= "1011001101011001111000100101100000101111";
WHEN "10010000" => memoryC2_uid52_sqrtTableGenerator_q <= "1011010000100101111011010000100110101110";
WHEN "10010001" => memoryC2_uid52_sqrtTableGenerator_q <= "1011010011101110011101001011000010101011";
WHEN "10010010" => memoryC2_uid52_sqrtTableGenerator_q <= "1011010110110011100011101101000011000010";
WHEN "10010011" => memoryC2_uid52_sqrtTableGenerator_q <= "1011011001110101010100000100010110000111";
WHEN "10010100" => memoryC2_uid52_sqrtTableGenerator_q <= "1011011100110011110011010100100011000111";
WHEN "10010101" => memoryC2_uid52_sqrtTableGenerator_q <= "1011011111101111000110010111011111101100";
WHEN "10010110" => memoryC2_uid52_sqrtTableGenerator_q <= "1011100010100111010001111101100111011011";
WHEN "10010111" => memoryC2_uid52_sqrtTableGenerator_q <= "1011100101011100011010101110010010000110";
WHEN "10011000" => memoryC2_uid52_sqrtTableGenerator_q <= "1011101000001110100101001000001010111101";
WHEN "10011001" => memoryC2_uid52_sqrtTableGenerator_q <= "1011101010111101110101100001100000011001";
WHEN "10011010" => memoryC2_uid52_sqrtTableGenerator_q <= "1011101101101010010000001000011000010001";
WHEN "10011011" => memoryC2_uid52_sqrtTableGenerator_q <= "1011110000010011111001000011000111101011";
WHEN "10011100" => memoryC2_uid52_sqrtTableGenerator_q <= "1011110010111010110100010000011100001100";
WHEN "10011101" => memoryC2_uid52_sqrtTableGenerator_q <= "1011110101011111000101100111110011100101";
WHEN "10011110" => memoryC2_uid52_sqrtTableGenerator_q <= "1011111000000000110000111001100101000110";
WHEN "10011111" => memoryC2_uid52_sqrtTableGenerator_q <= "1011111010011111111001101111011010100001";
WHEN "10100000" => memoryC2_uid52_sqrtTableGenerator_q <= "1011111100111100100011101100010111001001";
WHEN "10100001" => memoryC2_uid52_sqrtTableGenerator_q <= "1011111111010110110010001101001000000010";
WHEN "10100010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100000001101110101000101000010011000010";
WHEN "10100011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100000100000100001010001110100110010110";
WHEN "10100100" => memoryC2_uid52_sqrtTableGenerator_q <= "1100000110010111011010001010111100001100";
WHEN "10100101" => memoryC2_uid52_sqrtTableGenerator_q <= "1100001000101000011011100010110101000101";
WHEN "10100110" => memoryC2_uid52_sqrtTableGenerator_q <= "1100001010110111010001010110010001011110";
WHEN "10100111" => memoryC2_uid52_sqrtTableGenerator_q <= "1100001101000011111110100000010001011111";
WHEN "10101000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100001111001110100101110110101101000100";
WHEN "10101001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100010001010111001010001010101010101100";
WHEN "10101010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100010011011101101110001000100101000110";
WHEN "10101011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100010101100010010100011000010100001111";
WHEN "10101100" => memoryC2_uid52_sqrtTableGenerator_q <= "1100010111100100111111011101011000100010";
WHEN "10101101" => memoryC2_uid52_sqrtTableGenerator_q <= "1100011001100101110001110110111110010101";
WHEN "10101110" => memoryC2_uid52_sqrtTableGenerator_q <= "1100011011100100101110000000010010011100";
WHEN "10101111" => memoryC2_uid52_sqrtTableGenerator_q <= "1100011101100001110110010000011011110101";
WHEN "10110000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100011111011101001100111010101110100000";
WHEN "10110001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100001010110110100001110101011100101";
WHEN "10110010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100011001110101110011000010000001010";
WHEN "10110011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100101000100111101011111110110001110";
WHEN "10110100" => memoryC2_uid52_sqrtTableGenerator_q <= "1100100110111001100011101010011101101000";
WHEN "10110101" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101000101100100010111001110100110000";
WHEN "10110110" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101010011101111101001100011011001010";
WHEN "10110111" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101100001101110100011101101011001111";
WHEN "10111000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101101111100001010100101111011111011";
WHEN "10111001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100101111101001000001011010101011010010";
WHEN "10111010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110001010100011010101110100001011000";
WHEN "10111011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110010111110011000010001010111000011";
WHEN "10111100" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110100100110111011110000010101011000";
WHEN "10111101" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110110001110000110110110000100000011";
WHEN "10111110" => memoryC2_uid52_sqrtTableGenerator_q <= "1100110111110011111011001010101000110101";
WHEN "10111111" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111001011000011010010011101011001011";
WHEN "11000000" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111010111011100101110100011010101110";
WHEN "11000001" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111100011101011111001101110001101111";
WHEN "11000010" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111101111110000111111110100000110001";
WHEN "11000011" => memoryC2_uid52_sqrtTableGenerator_q <= "1100111111011101100001100011000011000000";
WHEN "11000100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000000111011101101010101110101010001";
WHEN "11000101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000010011000101100101111001011000001";
WHEN "11000110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000011110100100001000101011000110001";
WHEN "11000111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000101001111001011101100110101010110";
WHEN "11001000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101000110101000101101111000000000110111";
WHEN "11001001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001000000001001000110111100001010111";
WHEN "11001010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001001011000011101111010001111110001";
WHEN "11001011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001010101110101110001101001101110101";
WHEN "11001100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001100000011111010111011110111110000";
WHEN "11001101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001101011000000101001111111100011101";
WHEN "11001110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001110101011001110010001100010111100";
WHEN "11001111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101001111111101010111000111010001000110";
WHEN "11010000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010001001110100000110110000111100011";
WHEN "11010001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010010011110101100100001101010101001";
WHEN "11010010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010011101101111011001100000010100000";
WHEN "11010011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010100111100001101110101111100001101";
WHEN "11010100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010110001001100101011110101001100110";
WHEN "11010101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101010111010110000011000100001100011101";
WHEN "11010110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011000100001100111100011010001111111";
WHEN "11010111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011001101100010011110111010100001110";
WHEN "11011000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011010110110001000111010011110001001";
WHEN "11011001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011011111111000111100101101111110010";
WHEN "11011010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011101000111010000110000111010101011";
WHEN "11011011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011110001110100101010010101100100001";
WHEN "11011100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101011111010101000110000000100101101100";
WHEN "11011101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100000011010110011101111000011001010";
WHEN "11011110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100001011111101111010001011110110001";
WHEN "11011111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100010100011111001011010001110110110";
WHEN "11100000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100011100111010010111010101010010110";
WHEN "11100001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100100101001111100100011000111111010";
WHEN "11100010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100101101011110111000011000000111010";
WHEN "11100011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100110101101000011001000110001011000";
WHEN "11100100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101100111101101100001100001111111111000";
WHEN "11100101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101000101101010010111011010010110011";
WHEN "11100110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101001101100011000000000011100000010";
WHEN "11100111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101010101010110001011100010111011101";
WHEN "11101000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101011101000011111111001001100001101";
WHEN "11101001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101100100101100100000000001010010110";
WHEN "11101010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101101100001111110011001110010001001";
WHEN "11101011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101110011101101111101101101111100100";
WHEN "11101100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101101111011000111000100011000011000111";
WHEN "11101101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110000010011011001011111111001001110";
WHEN "11101110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110001001101010011001001110000110111";
WHEN "11101111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110010000110100110000101011110010110";
WHEN "11110000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110010111111010010110111000110011101";
WHEN "11110001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110011110111011010000010000101001011";
WHEN "11110010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110100101110111100001001001011100101";
WHEN "11110011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110101100101111001101110100011000111";
WHEN "11110100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110110011100010011010011101011100000";
WHEN "11110101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101110111010010001001011001011100011001";
WHEN "11110110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111000000111011100100000000111011011";
WHEN "11110111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111000111100001101000111011011001110";
WHEN "11111000" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111001110000011011101110011100101111";
WHEN "11111001" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111010100100001000110011110010000101";
WHEN "11111010" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111011010111010100110101011011110000";
WHEN "11111011" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111100001010000000010000110110110111";
WHEN "11111100" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111100111100001011100011000000010101";
WHEN "11111101" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111101101101110111001000010010110000";
WHEN "11111110" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111110011111000011011100101100011100";
WHEN "11111111" => memoryC2_uid52_sqrtTableGenerator_q <= "1101111111001111110000111011100111010010";
WHEN OTHERS =>
memoryC2_uid52_sqrtTableGenerator_q <= "1100000000000000000000000000000001000010";
END CASE;
END IF;
END PROCESS;
--sumAHighB_uid72_sqrtPolynomialEvaluator(ADD,71)@14
sumAHighB_uid72_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((40 downto 40 => memoryC2_uid52_sqrtTableGenerator_q(39)) & memoryC2_uid52_sqrtTableGenerator_q);
sumAHighB_uid72_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((40 downto 33 => reg_highBBits_uid71_sqrtPolynomialEvaluator_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_1_q(32)) & reg_highBBits_uid71_sqrtPolynomialEvaluator_0_to_sumAHighB_uid72_sqrtPolynomialEvaluator_1_q);
sumAHighB_uid72_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid72_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid72_sqrtPolynomialEvaluator_b));
sumAHighB_uid72_sqrtPolynomialEvaluator_q <= sumAHighB_uid72_sqrtPolynomialEvaluator_o(40 downto 0);
--lowRangeB_uid70_sqrtPolynomialEvaluator(BITSELECT,69)@13
lowRangeB_uid70_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid94_pT3_uid69_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid70_sqrtPolynomialEvaluator_b <= lowRangeB_uid70_sqrtPolynomialEvaluator_in(0 downto 0);
--ld_lowRangeB_uid70_sqrtPolynomialEvaluator_b_to_s3_uid70_uid73_sqrtPolynomialEvaluator_a(DELAY,224)@13
ld_lowRangeB_uid70_sqrtPolynomialEvaluator_b_to_s3_uid70_uid73_sqrtPolynomialEvaluator_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => lowRangeB_uid70_sqrtPolynomialEvaluator_b, xout => ld_lowRangeB_uid70_sqrtPolynomialEvaluator_b_to_s3_uid70_uid73_sqrtPolynomialEvaluator_a_q, clk => clk, aclr => areset );
--s3_uid70_uid73_sqrtPolynomialEvaluator(BITJOIN,72)@14
s3_uid70_uid73_sqrtPolynomialEvaluator_q <= sumAHighB_uid72_sqrtPolynomialEvaluator_q & ld_lowRangeB_uid70_sqrtPolynomialEvaluator_b_to_s3_uid70_uid73_sqrtPolynomialEvaluator_a_q;
--yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,101)@14
yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_in <= s3_uid70_uid73_sqrtPolynomialEvaluator_q;
yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_b <= yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_in(41 downto 24);
--reg_yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_9(REG,134)@14
reg_yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_9_q <= yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor(LOGICAL,435)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_b <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_q <= not (ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_a or ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_b);
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,431)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_mem_top_q <= "01011";
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp(LOGICAL,432)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_a <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_mem_top_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_a = ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmpReg(REG,433)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_sticky_ena(REG,436)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,437)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_b <= VCC_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_a and ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_b;
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,427)
-- every=1, low=0, high=11, step=1, init=1
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 10 THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 11;
ELSE
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_i,4));
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg(REG,428)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "0000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,429)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_s <= VCC_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,426)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_ia <= X44dto0_uid33_fpSqrtTest_b;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 4,
numwords_a => 12,
width_b => 45,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0);
--ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_outputreg(DELAY,425)
ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_replace_mem_q, xout => ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_outputreg_q, clk => clk, aclr => areset );
--yT4_uid74_sqrtPolynomialEvaluator(BITSELECT,73)@15
yT4_uid74_sqrtPolynomialEvaluator_in <= ld_X44dto0_uid33_fpSqrtTest_b_to_yT4_uid74_sqrtPolynomialEvaluator_a_outputreg_q;
yT4_uid74_sqrtPolynomialEvaluator_b <= yT4_uid74_sqrtPolynomialEvaluator_in(44 downto 5);
--xBottomBits_uid101_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,100)@15
xBottomBits_uid101_pT4_uid75_sqrtPolynomialEvaluator_in <= yT4_uid74_sqrtPolynomialEvaluator_b(12 downto 0);
xBottomBits_uid101_pT4_uid75_sqrtPolynomialEvaluator_b <= xBottomBits_uid101_pT4_uid75_sqrtPolynomialEvaluator_in(12 downto 0);
--pad_xBottomBits_uid101_uid104_pT4_uid75_sqrtPolynomialEvaluator(BITJOIN,103)@15
pad_xBottomBits_uid101_uid104_pT4_uid75_sqrtPolynomialEvaluator_q <= xBottomBits_uid101_pT4_uid75_sqrtPolynomialEvaluator_b & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--yBottomBits_uid100_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,99)@14
yBottomBits_uid100_pT4_uid75_sqrtPolynomialEvaluator_in <= s3_uid70_uid73_sqrtPolynomialEvaluator_q(14 downto 0);
yBottomBits_uid100_pT4_uid75_sqrtPolynomialEvaluator_b <= yBottomBits_uid100_pT4_uid75_sqrtPolynomialEvaluator_in(14 downto 0);
--spad_yBottomBits_uid100_uid103_pT4_uid75_sqrtPolynomialEvaluator(BITJOIN,102)@14
spad_yBottomBits_uid100_uid103_pT4_uid75_sqrtPolynomialEvaluator_q <= GND_q & yBottomBits_uid100_pT4_uid75_sqrtPolynomialEvaluator_b;
--pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator(BITJOIN,104)@14
pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid100_uid103_pT4_uid75_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_6(REG,135)@14
reg_pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--xTop18Bits_uid99_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,98)@15
xTop18Bits_uid99_pT4_uid75_sqrtPolynomialEvaluator_in <= yT4_uid74_sqrtPolynomialEvaluator_b;
xTop18Bits_uid99_pT4_uid75_sqrtPolynomialEvaluator_b <= xTop18Bits_uid99_pT4_uid75_sqrtPolynomialEvaluator_in(39 downto 22);
--multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma(CHAINMULTADD,127)@15
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a(0) * multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c(0);
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a(1) * multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c(1);
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_p(0),38) + RESIZE(multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_p(1),38);
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_w(0);
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_x(0);
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(xTop18Bits_uid99_pT4_uid75_sqrtPolynomialEvaluator_b),19));
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(pad_xBottomBits_uid101_uid104_pT4_uid75_sqrtPolynomialEvaluator_q),19));
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid100_uid105_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_6_q),18));
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid102_pT4_uid75_sqrtPolynomialEvaluator_0_to_multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_9_q),18));
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_y(0);
END IF;
END PROCESS;
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s(0),37));
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_q <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,106)@18
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_cma_q;
multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_b <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_in(36 downto 2);
--highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,108)@18
highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_b;
highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_b <= highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_in(34 downto 6);
--reg_highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_1(REG,137)@18
reg_highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_1_q <= highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,96)@14
yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_in <= s3_uid70_uid73_sqrtPolynomialEvaluator_q;
yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_b <= yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_in(41 downto 15);
--reg_yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_0_to_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_1(REG,136)@14
reg_yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_0_to_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_0_to_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_0_to_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--xTop27Bits_uid96_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,95)@15
xTop27Bits_uid96_pT4_uid75_sqrtPolynomialEvaluator_in <= yT4_uid74_sqrtPolynomialEvaluator_b;
xTop27Bits_uid96_pT4_uid75_sqrtPolynomialEvaluator_b <= xTop27Bits_uid96_pT4_uid75_sqrtPolynomialEvaluator_in(39 downto 13);
--topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator(MULT,97)@15
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_b);
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_a <= (others => '0');
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_b <= (others => '0');
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_a <= xTop27Bits_uid96_pT4_uid75_sqrtPolynomialEvaluator_b;
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_b <= reg_yTop27Bits_uid97_pT4_uid75_sqrtPolynomialEvaluator_0_to_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_1_q;
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_pr,54));
END IF;
END PROCESS;
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_q <= topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_s1;
END IF;
END PROCESS;
--reg_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_0(REG,138)@18
reg_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_0_q <= topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator(ADD,109)@19
sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_0_q(53)) & reg_topProd_uid98_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_1_q(28)) & reg_highBBits_uid109_pT4_uid75_sqrtPolynomialEvaluator_0_to_sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_1_q);
sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_b));
sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_q <= sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_o(54 downto 0);
--lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,107)@18
lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_in <= multSumOfTwo18_uid103_pT4_uid75_sqrtPolynomialEvaluator_b(5 downto 0);
lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b <= lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_in(5 downto 0);
--ld_lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b_to_add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_a(DELAY,260)@18
ld_lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b_to_add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b, xout => ld_lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b_to_add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_a_q, clk => clk, aclr => areset );
--add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator(BITJOIN,110)@19
add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_q <= sumAHighB_uid110_pT4_uid75_sqrtPolynomialEvaluator_q & ld_lowRangeB_uid108_pT4_uid75_sqrtPolynomialEvaluator_b_to_add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_a_q;
--R_uid112_pT4_uid75_sqrtPolynomialEvaluator(BITSELECT,111)@19
R_uid112_pT4_uid75_sqrtPolynomialEvaluator_in <= add0_uid108_uid111_pT4_uid75_sqrtPolynomialEvaluator_q(59 downto 0);
R_uid112_pT4_uid75_sqrtPolynomialEvaluator_b <= R_uid112_pT4_uid75_sqrtPolynomialEvaluator_in(59 downto 17);
--reg_R_uid112_pT4_uid75_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_1(REG,139)@19
reg_R_uid112_pT4_uid75_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid112_pT4_uid75_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_1_q <= "0000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid112_pT4_uid75_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_1_q <= R_uid112_pT4_uid75_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor(LOGICAL,396)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_b <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_q <= not (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_a or ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_b);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_mem_top(CONSTANT,392)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_mem_top_q <= "010000";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp(LOGICAL,393)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_mem_top_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_q);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_q <= "1" when ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_a = ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_b else "0";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmpReg(REG,394)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmpReg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_sticky_ena(REG,397)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_nor_q = "1") THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_sticky_ena_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd(LOGICAL,398)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_b <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_a and ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_b;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt(COUNTER,388)
-- every=1, low=0, high=16, step=1, init=1
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i = 15 THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i - 16;
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_i,5));
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg(REG,389)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux(MUX,390)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux: PROCESS (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_s, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg_q, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem(DUALMEM,387)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_reset0 <= areset;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_ia <= addrTable_uid32_fpSqrtTest_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_aa <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdreg_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_ab <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_rdmux_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 17,
width_b => 8,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_iq,
address_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_aa,
data_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_ia
);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_iq(7 downto 0);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_outputreg(DELAY,386)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_replace_mem_q, xout => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC1_uid51_sqrtTableGenerator(LOOKUP,50)@19
memoryC1_uid51_sqrtTableGenerator: PROCESS (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_outputreg_q)
BEGIN
-- Begin reserved scope level
CASE (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC1_uid51_sqrtTableGenerator_a_outputreg_q) IS
WHEN "00000000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111111111111111111111111111111111111111111011";
WHEN "00000001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111111000000010111110110000100010110000010100";
WHEN "00000010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111110000001011110110001000101000001111001011";
WHEN "00000011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111101000011010011110111011011000011101001111";
WHEN "00000100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111100000101110110010001000001011000000111001";
WHEN "00000101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111011001001000101000111010001100100001111010";
WHEN "00000110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111010001100111111100101000000101001011000100";
WHEN "00000111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111001010001100100110110011100000001110100011";
WHEN "00001000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011111000010110110100001001000110100101010110011";
WHEN "00001001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110111011100101100101011110101110101001001000";
WHEN "00001010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110110100011001101101110101111001111000100001";
WHEN "00001011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110101101010010110100011000101100111101001111";
WHEN "00001100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110100110010000110011011010110101010110000000";
WHEN "00001101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110011111010011100101011001000100010010001010";
WHEN "00001110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110011000011011000100111000111100011000101011";
WHEN "00001111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110010001100111001100101000011111111001101011";
WHEN "00010000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110001010110111110111011101111111101111101110";
WHEN "00010001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011110000100001101000000010111101011000100111101";
WHEN "00010010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101111101100110100010011011011111100110000011";
WHEN "00010011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101110111000100011000110110111010010101100011";
WHEN "00010100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101110000100110011110111110101001000101011101";
WHEN "00010101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101101010001100110000001110011100010100101010";
WHEN "00010110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101100011110111001000001000111001101011100100";
WHEN "00010111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101011101100101100010010111001110111000101001";
WHEN "00011000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101010111010111111010101001000101001011100110";
WHEN "00011001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101010001001110001100110100010101001110000111";
WHEN "00011010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101001011001000010100110100111011010110101100";
WHEN "00011011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011101000101000110001110101100101100011000010100";
WHEN "00011100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100111111000111110110100011001010101001001000";
WHEN "00011101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100111001001101001000100101011011100011011010";
WHEN "00011110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100110011010110000001000101111101011101000111";
WHEN "00011111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100101101100010011100011100011101110111000011";
WHEN "00100000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100100111110010010111000101101111111110110110";
WHEN "00100001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100100010000101101101100011100011101000111011";
WHEN "00100010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100011100011100011100011100011100011100011100";
WHEN "00100011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100010110110110100000011011101001010001110001";
WHEN "00100100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100010001010011110110010000111100000101011100";
WHEN "00100101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100001011110100011010110000100001111010011010";
WHEN "00100110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100000110011000001010110010111011001110001001";
WHEN "00100111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011100000000111111000011010100110100011110000000";
WHEN "00101000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011111011101001000001010110111110111001100111";
WHEN "00101001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011110110010110000001111110001001100110111100";
WHEN "00101010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011110001000110000010010010111010110011000101";
WHEN "00101011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011101011111000111111100001101001010001010000";
WHEN "00101100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011100110101110110110111010010110001000010000";
WHEN "00101101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011100001100111100101110000100110101010110010";
WHEN "00101110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011011100100011001001011011011110011101110000";
WHEN "00101111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011010111100001011111010101011001101001111001";
WHEN "00110000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011010010100010100100111100000111011001011100";
WHEN "00110001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011001101100110010111110000100100011110010000";
WHEN "00110010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011001000101100110101010110110110000111110100";
WHEN "00110011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011011000011110101111011010110000100111101010001";
WHEN "00110100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010111111000001100111011000011000000110001110";
WHEN "00110101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010111010001111110111001010110000011010000111";
WHEN "00110110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010110101100000101000011101000011111011000100";
WHEN "00110111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010110000110011111001000001111001010111101100";
WHEN "00111000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010101100001001100110101110100011110101001011";
WHEN "00111001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010100111100001101111011010111110100100110000";
WHEN "00111010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010100010111100010001000001101000111101000110";
WHEN "00111011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010011110011001001001011111100010011110000100";
WHEN "00111100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010011001111000010110110100000110111010110100";
WHEN "00111101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010010101011001110111000001001010101011110101";
WHEN "00111110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010010000111101101000001010110111000110011001";
WHEN "00111111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010001100100011101000010111100110111101000001";
WHEN "01000000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010001000001011110101110000000011000010101111";
WHEN "01000001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011010000011110110001110011110111110111001110101";
WHEN "01000010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001111111100010110000110001010101100011010110";
WHEN "01000011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001111011010001011010110110000110011000000010";
WHEN "01000100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001110111000010001010111110010010000100010000";
WHEN "01000101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001110010110100111111011100110111101100001101";
WHEN "01000110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001101110101001110110100110110001110011001101";
WHEN "01000111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001101010100000101110110010110011101000100110";
WHEN "01001000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001100110011001100110011001100110011001100111";
WHEN "01001001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001100010010100011011110101100110101000110100";
WHEN "01001010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001011110010001001101100011000001101000110111";
WHEN "01001011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001011010001111111001111111110010111100011010";
WHEN "01001100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001010110010000011111101011100001111010110101";
WHEN "01001101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001010010010010111101000111011111010111100111";
WHEN "01001110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001001110010111010000110110100011001111011111";
WHEN "01001111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001001010011101011001011101001010011001000011";
WHEN "01010000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001000110100101010101100001010100010111011001";
WHEN "01010001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011001000010101111000011101010100001010011101010";
WHEN "01010010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000111110111010100010100001101111110110111011";
WHEN "01010011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000111011000111110000110001011011001010110110";
WHEN "01010100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000110111010110101101000101011000111001111100";
WHEN "01010101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000110011100111010110001010110111010110011001";
WHEN "01010110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000101111111001101010110000011011100001101110";
WHEN "01010111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000101100001101101001100101111111011001001000";
WHEN "01011000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000101000100011010001011100110000000100001011";
WHEN "01011001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000100100111010100001000111001100000101101001";
WHEN "01011010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000100001010011010111011001000001110000001010";
WHEN "01011011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000011101101101110011000111001101011101101001";
WHEN "01011100" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000011010001001110011000111111000000111111110";
WHEN "01011101" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000010110100111010110010010010101100110000110";
WHEN "01011110" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000010011000110011011011111000011001010011100";
WHEN "01011111" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000001111100111000001100111100110000011001110";
WHEN "01100000" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000001100001001000111100110101001111111011001";
WHEN "01100001" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000001000101100101100010111111111110011000000";
WHEN "01100010" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000000101010001101110111000011011111111000001";
WHEN "01100011" => memoryC1_uid51_sqrtTableGenerator_q <= "0011000000001111000001110000101110101011011111010";
WHEN "01100100" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111111110100000001000111111000100000110100011";
WHEN "01100101" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111111011001001011110100011111111101100000101";
WHEN "01100110" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111110111110100001101110101011110011011101110";
WHEN "01100111" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111110100100000010101110101010011111000000000";
WHEN "01101000" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111110001001101110101100110001111101011100110";
WHEN "01101001" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111101101111100101100001011111100011101100000";
WHEN "01101010" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111101010101100111000101010111110101000110011";
WHEN "01101011" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111100111011110011010001000110011010110100011";
WHEN "01101100" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111100100010001001111101011101111010111011101";
WHEN "01101101" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111100001000101011000011010111110000001010110";
WHEN "01101110" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111011101111010110011011110100000001011101001";
WHEN "01101111" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111011010110001011111111111001011010000001011";
WHEN "01110000" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111010111101001011101000110101000001010111000";
WHEN "01110001" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111010100100010101001111111010010011101010111";
WHEN "01110010" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111010001011101000101110100010111010001011101";
WHEN "01110011" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111001110011000101111110001110100011111000010";
WHEN "01110100" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111001011010101100111000100010111110010000101";
WHEN "01110101" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111001000010011101010111001011101110010111011";
WHEN "01110110" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111000101010010111010011111010001001110111001";
WHEN "01110111" => memoryC1_uid51_sqrtTableGenerator_q <= "0010111000010010011010101000100101010000010101111";
WHEN "01111000" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110111111010100111001111001001100100101001010";
WHEN "01111001" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110111100010111101000001101001000110100111100";
WHEN "01111010" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110111001011011011111010001011001100101010110";
WHEN "01111011" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110110110100000011110010111100011101101100100";
WHEN "01111100" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110110011100110100100110001110101011000010010";
WHEN "01111101" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110110000101101110001110011000101010101000000";
WHEN "01111110" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110101101110110000100101110110010001001001000";
WHEN "01111111" => memoryC1_uid51_sqrtTableGenerator_q <= "0010110101010111111011100111001000001100100101101";
WHEN "10000000" => memoryC1_uid51_sqrtTableGenerator_q <= "0101101010000010011110011001100111111100111001110";
WHEN "10000001" => memoryC1_uid51_sqrtTableGenerator_q <= "0101101000101000011111100000001101011100010111111";
WHEN "10000010" => memoryC1_uid51_sqrtTableGenerator_q <= "0101100111001111100011001011101111011000111000110";
WHEN "10000011" => memoryC1_uid51_sqrtTableGenerator_q <= "0101100101110111101000001010101111100101100001110";
WHEN "10000100" => memoryC1_uid51_sqrtTableGenerator_q <= "0101100100100000101101001101111010010110100100001";
WHEN "10000101" => memoryC1_uid51_sqrtTableGenerator_q <= "0101100011001010110001001000000001110100111001000";
WHEN "10000110" => memoryC1_uid51_sqrtTableGenerator_q <= "0101100001110101110010101101111001011110000101111";
WHEN "10000111" => memoryC1_uid51_sqrtTableGenerator_q <= "0101100000100001110000110110010001101111110011101";
WHEN "10001000" => memoryC1_uid51_sqrtTableGenerator_q <= "0101011111001110101010011001110011111110100111011";
WHEN "10001001" => memoryC1_uid51_sqrtTableGenerator_q <= "0101011101111100011110010010111110010111100101110";
WHEN "10001010" => memoryC1_uid51_sqrtTableGenerator_q <= "0101011100101011001011011110000000001011110011110";
WHEN "10001011" => memoryC1_uid51_sqrtTableGenerator_q <= "0101011011011010110000111000110110000101100111000";
WHEN "10001100" => memoryC1_uid51_sqrtTableGenerator_q <= "0101011010001011001101100011000110100111010110010";
WHEN "10001101" => memoryC1_uid51_sqrtTableGenerator_q <= "0101011000111100100000011101111110110010100110011";
WHEN "10001110" => memoryC1_uid51_sqrtTableGenerator_q <= "0101010111101110101000101100001110111000000001100";
WHEN "10001111" => memoryC1_uid51_sqrtTableGenerator_q <= "0101010110100001100101010010000111001111000000110";
WHEN "10010000" => memoryC1_uid51_sqrtTableGenerator_q <= "0101010101010101010101010101010101010101010100111";
WHEN "10010001" => memoryC1_uid51_sqrtTableGenerator_q <= "0101010100001001110111111101000000110101101011100";
WHEN "10010010" => memoryC1_uid51_sqrtTableGenerator_q <= "0101010010111111001100010001101000110101101010011";
WHEN "10010011" => memoryC1_uid51_sqrtTableGenerator_q <= "0101010001110101010001011101000001001010000011100";
WHEN "10010100" => memoryC1_uid51_sqrtTableGenerator_q <= "0101010000101100000110101010001111110001101011100";
WHEN "10010101" => memoryC1_uid51_sqrtTableGenerator_q <= "0101001111100011101011000101101010010110010111111";
WHEN "10010110" => memoryC1_uid51_sqrtTableGenerator_q <= "0101001110011011111101111100110011110011101111100";
WHEN "10010111" => memoryC1_uid51_sqrtTableGenerator_q <= "0101001101010100111110011110011010000011100001010";
WHEN "10011000" => memoryC1_uid51_sqrtTableGenerator_q <= "0101001100001110101011111010010011101111001111000";
WHEN "10011001" => memoryC1_uid51_sqrtTableGenerator_q <= "0101001011001001000101100001011110000111001000110";
WHEN "10011010" => memoryC1_uid51_sqrtTableGenerator_q <= "0101001010000100001010100101111010111101111011111";
WHEN "10011011" => memoryC1_uid51_sqrtTableGenerator_q <= "0101001000111111111010011010101110101001000101111";
WHEN "10011100" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000111111100010100010011111110000101111111100";
WHEN "10011101" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000110111001010111100110101101000011000010110";
WHEN "10011110" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000101110111000011101000111100001101001110110";
WHEN "10011111" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000100110101010111110001100111100001010011101";
WHEN "10100000" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000011110100010011011000100100100001000111110";
WHEN "10100001" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000010110011110101110110100000101100011100100";
WHEN "10100010" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000001110011111110100100111111111101010001110";
WHEN "10100011" => memoryC1_uid51_sqrtTableGenerator_q <= "0101000000110100101100111110011011000111100001000";
WHEN "10100100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111111110110000000011101111110011100000110010";
WHEN "10100101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111110110111111000011111101000001110110000000";
WHEN "10100110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111101111010010100100000000111011111011011100";
WHEN "10100111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111100111101010011111100111010100101110001111";
WHEN "10101000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111100000000110110010100001110000000001101000";
WHEN "10101001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111011000100111011000100111011000100111010111";
WHEN "10101010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111010001001100001101110100110110101111010010";
WHEN "10101011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111001001110101001110001100000110111010001010";
WHEN "10101100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100111000010100010010101110100010000111110100001";
WHEN "10101101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110111011010011100000111001011111100001100000";
WHEN "10101110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110110100001000101011101100110111011101100111";
WHEN "10101111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110101101000001110010100100001111111111001110";
WHEN "10110000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110100101111110110001111010001010101100111001";
WHEN "10110001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110011110111111100110001101101100000010010101";
WHEN "10110010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110011000000100001100000010010011111000000001";
WHEN "10110011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110010001001100011111111111110110011011010111";
WHEN "10110100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110001010011000011110110010010101010011110100";
WHEN "10110101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100110000011101000000101001001111000110101000111";
WHEN "10110110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101111100111011001111111010101001011111101101";
WHEN "10110111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101110110010001111011111100101001101100011101";
WHEN "10111000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101101111101100000110001011101111100101100101";
WHEN "10111001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101101001001001101011100111011111001001111100";
WHEN "10111010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101100010101010101001010011000100011100101001";
WHEN "10111011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101011100001110111100010101001101111111000001";
WHEN "10111100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101010101110110100001111000000111010110000110";
WHEN "10111101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101001111100001010111001001010011110111110010";
WHEN "10111110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101001001001111011001011001101001100100001010";
WHEN "10111111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100101000011000000100101111101001100000111110011";
WHEN "11000000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100111100110100111010001011001000000110010001";
WHEN "11000001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100110110101100010011011101101110001110100001";
WHEN "11000010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100110000100110101111010010001110110101110001";
WHEN "11000011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100101010100100001011001000110101011111000110";
WHEN "11000100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100100100100100100100100100100100100100100100";
WHEN "11000101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100011110100111111001001011010001001110001011";
WHEN "11000110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100011000101110000110100101011111001100010100";
WHEN "11000111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100010010110111001010011110011100111011010000";
WHEN "11001000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100001101000011000010100011111111101100010000";
WHEN "11001001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100000111010001101100100110011111110111100100";
WHEN "11001010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100100000001100011000110011000110101010001110001";
WHEN "11001011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011111011110111001101110000010011101011101001";
WHEN "11001100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011110110001110000000100100100111010011001010";
WHEN "11001101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011110000100111011100101111110001011110111100";
WHEN "11001110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011101011000011100000001110000101011100111111";
WHEN "11001111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011100101100010001000111110000101000110111001";
WHEN "11010000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011100000000011010101000000011101111101000101";
WHEN "11010001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011011010100111000010011000000110000101001110";
WHEN "11010010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011010101001101001111001001111001001111000010";
WHEN "11010011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011001111110101111001011100110101111101110110";
WHEN "11010100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011001010100000111111011001111010110111001110";
WHEN "11010101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100011000101001110011111001100000011110011111110";
WHEN "11010110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010111111111110010111000000000111011000100001";
WHEN "11010111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010111010110000100101000100110100010000100010";
WHEN "11011000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010110101100101000111101010101110101110010011";
WHEN "11011001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010110000011011111101000100001110001101111001";
WHEN "11011010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010101011010101000011100101011010111110000000";
WHEN "11011011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010100110010000011001100100001011101001111001";
WHEN "11011100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010100001001101111101011000000011001010100000";
WHEN "11011101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010011100001101101101011010001110010111111110";
WHEN "11011110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010010111001111101000000101100010000000001111";
WHEN "11011111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010010010010011101011110110011000100001000001";
WHEN "11100000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010001101011001110111001010110000000100100001";
WHEN "11100001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010001000100010001000100010001000100010000111";
WHEN "11100010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100010000011101100011110011101100001100001010100";
WHEN "11100011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001111110111000110111011111011000100000101010";
WHEN "11100100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001111010000111010010001011100110111101101010";
WHEN "11100101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001110101010111101101000111100000100011001100";
WHEN "11100110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001110000101010000110111001110001010110101110";
WHEN "11100111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001101011111110011110001010011100001010010000";
WHEN "11101000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001100111010100110001100010111000110000110000";
WHEN "11101001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001100010101100111111101101110010010101100001";
WHEN "11101010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001011110000111000111010111000101110100011000";
WHEN "11101011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001011001100011000111001100000000010110011100";
WHEN "11101100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001010101000000111101111010111101101110101000";
WHEN "11101101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001010000100000101010010011100110111011111001";
WHEN "11101110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001001100000010001011000110110000101010100110";
WHEN "11101111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001000111100101011111000110011001111000111011";
WHEN "11110000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100001000011001010100101000101101010011110101110";
WHEN "11110001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000111110110001011011111000110001110101010010";
WHEN "11110010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000111010011010000010010101000101100010100101";
WHEN "11110011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000110110000100010111010001000000000101101101";
WHEN "11110100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000110001110000011001100011111111100101111111";
WHEN "11110101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000101101011110001000000110100100100011001001";
WHEN "11110110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000101001001101100001110010010000100111011110";
WHEN "11110111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000100100111110100101100001100101011011010000";
WHEN "11111000" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000100000110001010010010000000011011011110100";
WHEN "11111001" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000011100100101100110111010001000110000111101";
WHEN "11111010" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000011000011011100010011101010000000111001101";
WHEN "11111011" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000010100010011000011110111101111101010000000";
WHEN "11111100" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000010000001100001010001000110111111111001100";
WHEN "11111101" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000001100000110110100010000110011000100111101";
WHEN "11111110" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000001000000011000001010000100011001111110101";
WHEN "11111111" => memoryC1_uid51_sqrtTableGenerator_q <= "0100000000100000000110000001010000010001100011010";
WHEN OTHERS =>
memoryC1_uid51_sqrtTableGenerator_q <= "0011111111111111111111111111111111111111111111011";
END CASE;
-- End reserved scope level
END PROCESS;
--rndBit_uid76_sqrtPolynomialEvaluator(CONSTANT,75)
rndBit_uid76_sqrtPolynomialEvaluator_q <= "01";
--cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator(BITJOIN,76)@19
cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_q <= memoryC1_uid51_sqrtTableGenerator_q & rndBit_uid76_sqrtPolynomialEvaluator_q;
--reg_cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_0(REG,140)@19
reg_cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--ts4_uid78_sqrtPolynomialEvaluator(ADD,77)@20
ts4_uid78_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((51 downto 51 => reg_cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_0_q(50)) & reg_cIncludingRoundingBit_uid77_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_0_q);
ts4_uid78_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((51 downto 43 => reg_R_uid112_pT4_uid75_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_1_q(42)) & reg_R_uid112_pT4_uid75_sqrtPolynomialEvaluator_0_to_ts4_uid78_sqrtPolynomialEvaluator_1_q);
ts4_uid78_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid78_sqrtPolynomialEvaluator_a) + SIGNED(ts4_uid78_sqrtPolynomialEvaluator_b));
ts4_uid78_sqrtPolynomialEvaluator_q <= ts4_uid78_sqrtPolynomialEvaluator_o(51 downto 0);
--s4_uid79_sqrtPolynomialEvaluator(BITSELECT,78)@20
s4_uid79_sqrtPolynomialEvaluator_in <= ts4_uid78_sqrtPolynomialEvaluator_q;
s4_uid79_sqrtPolynomialEvaluator_b <= s4_uid79_sqrtPolynomialEvaluator_in(51 downto 1);
--yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,113)@20
yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_in <= s4_uid79_sqrtPolynomialEvaluator_b;
yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_b <= yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_in(50 downto 24);
--reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_9(REG,141)@20
reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_9_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_9_q <= yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor(LOGICAL,485)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_b <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_sticky_ena_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_q <= not (ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_a or ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_b);
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_mem_top(CONSTANT,481)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_mem_top_q <= "010001";
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp(LOGICAL,482)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_a <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_mem_top_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_q);
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_q <= "1" when ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_a = ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_b else "0";
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmpReg(REG,483)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmpReg_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmp_q;
END IF;
END PROCESS;
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_sticky_ena(REG,486)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_nor_q = "1") THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_sticky_ena_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd(LOGICAL,487)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_a <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_sticky_ena_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_b <= VCC_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_a and ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_b;
--xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,116)@1
xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_in <= X44dto0_uid33_fpSqrtTest_b(17 downto 0);
xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b <= xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_in(17 downto 0);
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt(COUNTER,477)
-- every=1, low=0, high=17, step=1, init=1
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i = 16 THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i - 17;
ELSE
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg(REG,478)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux(MUX,479)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_s <= VCC_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux: PROCESS (ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_s, ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg_q, ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem(DUALMEM,476)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_ia <= xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_aa <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdreg_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_ab <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_rdmux_q;
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 5,
numwords_a => 18,
width_b => 18,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_iq,
address_a => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_aa,
data_a => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_ia
);
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_iq(17 downto 0);
--ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_outputreg(DELAY,475)
ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_outputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_replace_mem_q, xout => ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_outputreg_q, clk => clk, aclr => areset );
--pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator(BITJOIN,118)@21
pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_q <= ld_xBottomBits_uid117_pT5_uid81_sqrtPolynomialEvaluator_b_to_pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,115)@20
yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_in <= s4_uid79_sqrtPolynomialEvaluator_b(23 downto 0);
yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b <= yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_in(23 downto 0);
--ld_yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b_to_spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_a(DELAY,269)@20
ld_yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b_to_spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_a : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b, xout => ld_yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b_to_spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_a_q, clk => clk, aclr => areset );
--spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator(BITJOIN,117)@21
spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_q <= GND_q & ld_yBottomBits_uid116_pT5_uid81_sqrtPolynomialEvaluator_b_to_spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_a_q;
--pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator(BITJOIN,119)@21
pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_q <= spad_yBottomBits_uid116_uid118_pT5_uid81_sqrtPolynomialEvaluator_q & STD_LOGIC_VECTOR((1 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_6(REG,142)@21
reg_pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_6_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_6_q <= pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor(LOGICAL,472)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_b <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_q <= not (ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_a or ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_b);
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_mem_top(CONSTANT,468)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_mem_top_q <= "010010";
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp(LOGICAL,469)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_a <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_mem_top_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_q);
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_q <= "1" when ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_a = ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_b else "0";
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmpReg(REG,470)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmpReg_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmp_q;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_sticky_ena(REG,473)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_nor_q = "1") THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_sticky_ena_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd(LOGICAL,474)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_a <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_sticky_ena_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_b <= VCC_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_a and ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_b;
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt(COUNTER,464)
-- every=1, low=0, high=18, step=1, init=1
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i = 17 THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '1';
ELSE
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_eq = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i - 18;
ELSE
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_i,5));
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg(REG,465)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux(MUX,466)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_s <= VCC_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux: PROCESS (ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_s, ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg_q, ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_q)
BEGIN
CASE ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_s IS
WHEN "0" => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg_q;
WHEN "1" => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdcnt_q;
WHEN OTHERS => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem(DUALMEM,463)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_reset0 <= areset;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_ia <= X44dto0_uid33_fpSqrtTest_b;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_aa <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdreg_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_ab <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_rdmux_q;
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 5,
numwords_a => 19,
width_b => 45,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_iq,
address_a => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_aa,
data_a => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_ia
);
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_q <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_iq(44 downto 0);
--ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_outputreg(DELAY,462)
ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_replace_mem_q, xout => ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_outputreg_q, clk => clk, aclr => areset );
--xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,112)@22
xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_in <= ld_X44dto0_uid33_fpSqrtTest_b_to_xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_a_outputreg_q;
xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_b <= xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_in(44 downto 18);
--multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma(CHAINMULTADD,128)@22
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_p(0) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a(0) * multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c(0);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_p(1) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a(1) * multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c(1);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_w(0) <= RESIZE(multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_p(0),56);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_w(1) <= RESIZE(multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_p(1),56);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_x(0) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_w(0);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_x(1) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_w(1);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_y(0) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s(1) + multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_x(0);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_y(1) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_x(1);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_b),28));
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(pad_xBottomBits_uid117_uid119_pT5_uid81_sqrtPolynomialEvaluator_q),28));
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid116_uid120_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_6_q),27));
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_9_q),27));
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s(0) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_y(0);
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s(1) <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_y(1);
END IF;
END PROCESS;
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s(0),55));
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_q <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,121)@25
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_in <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_cma_q;
multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_b <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_in(54 downto 2);
--highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,123)@25
highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_in <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_b;
highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_b <= highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_in(52 downto 24);
--reg_highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_1(REG,144)@25
reg_highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_1_q <= highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1(REG,143)@20
reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q <= yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--ld_reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b(DELAY,266)@21
ld_reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q, xout => ld_reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b_q, clk => clk, aclr => areset );
--topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator(MULT,114)@22
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_a),28)) * SIGNED(topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b);
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_a <= (others => '0');
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b <= (others => '0');
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_a <= xTop27Bits_uid113_pT5_uid81_sqrtPolynomialEvaluator_b;
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b <= ld_reg_yTop27Bits_uid114_pT5_uid81_sqrtPolynomialEvaluator_0_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_1_q_to_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_b_q;
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_pr,54));
END IF;
END PROCESS;
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_q <= topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_s1;
END IF;
END PROCESS;
--reg_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_0(REG,145)@25
reg_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_0_q <= topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator(ADD,124)@26
sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_0_q(53)) & reg_topProd_uid115_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_0_q);
sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_1_q(28)) & reg_highBBits_uid124_pT5_uid81_sqrtPolynomialEvaluator_0_to_sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_1_q);
sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_b));
sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_q <= sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_o(54 downto 0);
--lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,122)@25
lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_in <= multSumOfTwo27_uid118_pT5_uid81_sqrtPolynomialEvaluator_b(23 downto 0);
lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b <= lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_in(23 downto 0);
--ld_lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b_to_add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_a(DELAY,277)@25
ld_lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b_to_add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_a : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b, xout => ld_lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b_to_add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_a_q, clk => clk, aclr => areset );
--add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator(BITJOIN,125)@26
add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_q <= sumAHighB_uid125_pT5_uid81_sqrtPolynomialEvaluator_q & ld_lowRangeB_uid123_pT5_uid81_sqrtPolynomialEvaluator_b_to_add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_a_q;
--R_uid127_pT5_uid81_sqrtPolynomialEvaluator(BITSELECT,126)@26
R_uid127_pT5_uid81_sqrtPolynomialEvaluator_in <= add0_uid123_uid126_pT5_uid81_sqrtPolynomialEvaluator_q(77 downto 0);
R_uid127_pT5_uid81_sqrtPolynomialEvaluator_b <= R_uid127_pT5_uid81_sqrtPolynomialEvaluator_in(77 downto 25);
--reg_R_uid127_pT5_uid81_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_1(REG,146)@26
reg_R_uid127_pT5_uid81_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid127_pT5_uid81_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid127_pT5_uid81_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_1_q <= R_uid127_pT5_uid81_sqrtPolynomialEvaluator_b;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor(LOGICAL,383)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_b <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_q <= not (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_a or ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_b);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_mem_top(CONSTANT,379)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_mem_top_q <= "010111";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp(LOGICAL,380)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_mem_top_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_q);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_q <= "1" when ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_a = ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_b else "0";
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmpReg(REG,381)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmpReg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_sticky_ena(REG,384)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_nor_q = "1") THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_sticky_ena_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd(LOGICAL,385)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_a <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_sticky_ena_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_b <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_a and ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_b;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt(COUNTER,375)
-- every=1, low=0, high=23, step=1, init=1
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i = 22 THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i - 23;
ELSE
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_i,5));
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg(REG,376)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux(MUX,377)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux: PROCESS (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_s, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg_q, ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem(DUALMEM,374)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_reset0 <= areset;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_ia <= addrTable_uid32_fpSqrtTest_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_aa <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdreg_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_ab <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_rdmux_q;
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 24,
width_b => 8,
widthad_b => 5,
numwords_b => 24,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_iq,
address_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_aa,
data_a => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_ia
);
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_q <= ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_iq(7 downto 0);
--ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_outputreg(DELAY,373)
ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_replace_mem_q, xout => ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC0_uid50_sqrtTableGenerator(LOOKUP,49)@26
memoryC0_uid50_sqrtTableGenerator: PROCESS (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_outputreg_q)
BEGIN
-- Begin reserved scope level
CASE (ld_addrTable_uid32_fpSqrtTest_q_to_memoryC0_uid50_sqrtTableGenerator_a_outputreg_q) IS
WHEN "00000000" => memoryC0_uid50_sqrtTableGenerator_q <= "010000000000000000000000000000000000000000000000000000100";
WHEN "00000001" => memoryC0_uid50_sqrtTableGenerator_q <= "010000000011111111100000000111111101100000110111101011101";
WHEN "00000010" => memoryC0_uid50_sqrtTableGenerator_q <= "010000000111111110000000111111011000011011101011010000110";
WHEN "00000011" => memoryC0_uid50_sqrtTableGenerator_q <= "010000001011111011100011010100111000110000111101001000001";
WHEN "00000100" => memoryC0_uid50_sqrtTableGenerator_q <= "010000001111111000000111110110001101101011100000001100010";
WHEN "00000101" => memoryC0_uid50_sqrtTableGenerator_q <= "010000010011110011101111010000001111000000101001100100110";
WHEN "00000110" => memoryC0_uid50_sqrtTableGenerator_q <= "010000010111101110011010001110111110101101010010001011010";
WHEN "00000111" => memoryC0_uid50_sqrtTableGenerator_q <= "010000011011101000001001011101101010001111110000101011110";
WHEN "00001000" => memoryC0_uid50_sqrtTableGenerator_q <= "010000011111100000111101100110101011111110110100000111100";
WHEN "00001001" => memoryC0_uid50_sqrtTableGenerator_q <= "010000100011011000110111010011101100011101100110101010101";
WHEN "00001010" => memoryC0_uid50_sqrtTableGenerator_q <= "010000100111001111110111001101100011101101000000001001100";
WHEN "00001011" => memoryC0_uid50_sqrtTableGenerator_q <= "010000101011000101111101111100011010011010001111001000111";
WHEN "00001100" => memoryC0_uid50_sqrtTableGenerator_q <= "010000101110111011001100000111101011001010111111011011011";
WHEN "00001101" => memoryC0_uid50_sqrtTableGenerator_q <= "010000110010101111100010010110000011100111000100001101110";
WHEN "00001110" => memoryC0_uid50_sqrtTableGenerator_q <= "010000110110100011000001001101100101011111101100000110010";
WHEN "00001111" => memoryC0_uid50_sqrtTableGenerator_q <= "010000111010010101101001010011100111110100100100101100100";
WHEN "00010000" => memoryC0_uid50_sqrtTableGenerator_q <= "010000111110000111011011001100110111110110110011011001111";
WHEN "00010001" => memoryC0_uid50_sqrtTableGenerator_q <= "010001000001111000010111011101011010001001101000101001001";
WHEN "00010010" => memoryC0_uid50_sqrtTableGenerator_q <= "010001000101101000011110101000101011100001010010100100000";
WHEN "00010011" => memoryC0_uid50_sqrtTableGenerator_q <= "010001001001010111110001010001100001111111110100001001001";
WHEN "00010100" => memoryC0_uid50_sqrtTableGenerator_q <= "010001001101000110001111111010001101110000000101001110100";
WHEN "00010101" => memoryC0_uid50_sqrtTableGenerator_q <= "010001010000110011111011000100011001111110111111111011101";
WHEN "00010110" => memoryC0_uid50_sqrtTableGenerator_q <= "010001010100100000110011010001001101110010111111101011000";
WHEN "00010111" => memoryC0_uid50_sqrtTableGenerator_q <= "010001011000001100111001000001001101000001110101110100101";
WHEN "00011000" => memoryC0_uid50_sqrtTableGenerator_q <= "010001011011111000001100110100011001000100110111111001000";
WHEN "00011001" => memoryC0_uid50_sqrtTableGenerator_q <= "010001011111100010101111001010010001101011101010111001110";
WHEN "00011010" => memoryC0_uid50_sqrtTableGenerator_q <= "010001100011001100100000100001110101101101001111100011010";
WHEN "00011011" => memoryC0_uid50_sqrtTableGenerator_q <= "010001100110110101100001011001100011110111110010011111100";
WHEN "00011100" => memoryC0_uid50_sqrtTableGenerator_q <= "010001101010011101110010001111011011011111000100000100000";
WHEN "00011101" => memoryC0_uid50_sqrtTableGenerator_q <= "010001101110000101010011100000111101001001011010100000110";
WHEN "00011110" => memoryC0_uid50_sqrtTableGenerator_q <= "010001110001101100000101101011001011011011100001110000101";
WHEN "00011111" => memoryC0_uid50_sqrtTableGenerator_q <= "010001110101010010001001001010101011100010111011100001111";
WHEN "00100000" => memoryC0_uid50_sqrtTableGenerator_q <= "010001111000110111011110011011100101111111010010101000010";
WHEN "00100001" => memoryC0_uid50_sqrtTableGenerator_q <= "010001111100011100000101111001100111001010100011111111010";
WHEN "00100010" => memoryC0_uid50_sqrtTableGenerator_q <= "010010000000000000000000000000000000000000000000000000100";
WHEN "00100011" => memoryC0_uid50_sqrtTableGenerator_q <= "010010000011100011001101001001100110100010000110101001011";
WHEN "00100100" => memoryC0_uid50_sqrtTableGenerator_q <= "010010000111000101101101110000110110011111100000100100001";
WHEN "00100101" => memoryC0_uid50_sqrtTableGenerator_q <= "010010001010100111100010001111110001110110110111100101101";
WHEN "00100110" => memoryC0_uid50_sqrtTableGenerator_q <= "010010001110001000101011000000000001011001110000101000011";
WHEN "00100111" => memoryC0_uid50_sqrtTableGenerator_q <= "010010010001101001001000011010110101001110101001001001001";
WHEN "00101000" => memoryC0_uid50_sqrtTableGenerator_q <= "010010010101001000111010111001000101010001111010000101110";
WHEN "00101001" => memoryC0_uid50_sqrtTableGenerator_q <= "010010011000101000000010110011010001110110000010010110110";
WHEN "00101010" => memoryC0_uid50_sqrtTableGenerator_q <= "010010011100000110100000100001100100000010111010011010101";
WHEN "00101011" => memoryC0_uid50_sqrtTableGenerator_q <= "010010011111100100010100011011101110010100010011000011101";
WHEN "00101100" => memoryC0_uid50_sqrtTableGenerator_q <= "010010100011000001011110111001001100110111100000110100011";
WHEN "00101101" => memoryC0_uid50_sqrtTableGenerator_q <= "010010100110011110000000010001000110001000010101110101010";
WHEN "00101110" => memoryC0_uid50_sqrtTableGenerator_q <= "010010101001111001111000111010001011001101001011100110001";
WHEN "00101111" => memoryC0_uid50_sqrtTableGenerator_q <= "010010101101010101001001001010111000010010011110001110010";
WHEN "00110000" => memoryC0_uid50_sqrtTableGenerator_q <= "010010110000101111110001011001010101000101011010100111010";
WHEN "00110001" => memoryC0_uid50_sqrtTableGenerator_q <= "010010110100001001110001111011010101001110000000111110110";
WHEN "00110010" => memoryC0_uid50_sqrtTableGenerator_q <= "010010110111100011001011000110011000101000011101000001111";
WHEN "00110011" => memoryC0_uid50_sqrtTableGenerator_q <= "010010111010111011111101001111101011111101110101001011001";
WHEN "00110100" => memoryC0_uid50_sqrtTableGenerator_q <= "010010111110010100001000101100001000111100010001111110011";
WHEN "00110101" => memoryC0_uid50_sqrtTableGenerator_q <= "010011000001101011101101110000010110101110011111000100000";
WHEN "00110110" => memoryC0_uid50_sqrtTableGenerator_q <= "010011000101000010101100110000101010010010100110101011110";
WHEN "00110111" => memoryC0_uid50_sqrtTableGenerator_q <= "010011001000011001000110000001000110110000101001000001010";
WHEN "00111000" => memoryC0_uid50_sqrtTableGenerator_q <= "010011001011101110111001110101011101110000010000010111000";
WHEN "00111001" => memoryC0_uid50_sqrtTableGenerator_q <= "010011001111000100001000100001001111101110000011001001111";
WHEN "00111010" => memoryC0_uid50_sqrtTableGenerator_q <= "010011010010011000110010010111101100010000010101000000100";
WHEN "00111011" => memoryC0_uid50_sqrtTableGenerator_q <= "010011010101101100110111101011110010011011010111100010101";
WHEN "00111100" => memoryC0_uid50_sqrtTableGenerator_q <= "010011011001000000011000110000010001000101001100000110001";
WHEN "00111101" => memoryC0_uid50_sqrtTableGenerator_q <= "010011011100010011010101110111100111001000110111001011011";
WHEN "00111110" => memoryC0_uid50_sqrtTableGenerator_q <= "010011011111100101101111010100000011111001010110100010000";
WHEN "00111111" => memoryC0_uid50_sqrtTableGenerator_q <= "010011100010110111100101010111100111010011111010101011000";
WHEN "01000000" => memoryC0_uid50_sqrtTableGenerator_q <= "010011100110001000111000010100000010010010000100101111000";
WHEN "01000001" => memoryC0_uid50_sqrtTableGenerator_q <= "010011101001011001101000011010110110111011001001010111111";
WHEN "01000010" => memoryC0_uid50_sqrtTableGenerator_q <= "010011101100101001110101111101011000110101011001100011000";
WHEN "01000011" => memoryC0_uid50_sqrtTableGenerator_q <= "010011101111111001100001001100101101010110110001110111111";
WHEN "01000100" => memoryC0_uid50_sqrtTableGenerator_q <= "010011110011001000101010011001101011110101010001010011100";
WHEN "01000101" => memoryC0_uid50_sqrtTableGenerator_q <= "010011110110010111010001110100111101110110110111110010101";
WHEN "01000110" => memoryC0_uid50_sqrtTableGenerator_q <= "010011111001100101010111101110111111100001001101100111101";
WHEN "01000111" => memoryC0_uid50_sqrtTableGenerator_q <= "010011111100110010111100010111111111101000110100000100011";
WHEN "01001000" => memoryC0_uid50_sqrtTableGenerator_q <= "010100000000000000000000000000000000000000000000000000100";
WHEN "01001001" => memoryC0_uid50_sqrtTableGenerator_q <= "010100000011001100100010110110110101100101011111000010010";
WHEN "01001010" => memoryC0_uid50_sqrtTableGenerator_q <= "010100000110011000100101001100001000110010100111110000101";
WHEN "01001011" => memoryC0_uid50_sqrtTableGenerator_q <= "010100001001100100000111001111010101101001010101110010000";
WHEN "01001100" => memoryC0_uid50_sqrtTableGenerator_q <= "010100001100101111001001001111101100000001110001111010110";
WHEN "01001101" => memoryC0_uid50_sqrtTableGenerator_q <= "010100001111111001101011011100001111110111100111001110100";
WHEN "01001110" => memoryC0_uid50_sqrtTableGenerator_q <= "010100010011000011101110000011111001010111000101010011110";
WHEN "01001111" => memoryC0_uid50_sqrtTableGenerator_q <= "010100010110001101010001010101010101001001110000011010110";
WHEN "01010000" => memoryC0_uid50_sqrtTableGenerator_q <= "010100011001010110010101011111000100100010111111110110111";
WHEN "01010001" => memoryC0_uid50_sqrtTableGenerator_q <= "010100011100011110111010101111011101101100001011000110101";
WHEN "01010010" => memoryC0_uid50_sqrtTableGenerator_q <= "010100011111100111000001010100101011110000100110001001110";
WHEN "01010011" => memoryC0_uid50_sqrtTableGenerator_q <= "010100100010101110101001011100101111001001001101011111001";
WHEN "01010100" => memoryC0_uid50_sqrtTableGenerator_q <= "010100100101110101110011010101011101101000000010001000010";
WHEN "01010101" => memoryC0_uid50_sqrtTableGenerator_q <= "010100101000111100011111001100100010100011010110001010010";
WHEN "01010110" => memoryC0_uid50_sqrtTableGenerator_q <= "010100101100000010101101001111011111000000101010001000000";
WHEN "01010111" => memoryC0_uid50_sqrtTableGenerator_q <= "010100101111001000011101101011101001111111011011101100110";
WHEN "01011000" => memoryC0_uid50_sqrtTableGenerator_q <= "010100110010001101110000101110010000100011100110000000011";
WHEN "01011001" => memoryC0_uid50_sqrtTableGenerator_q <= "010100110101010010100110100100010101111111110011111100010";
WHEN "01011010" => memoryC0_uid50_sqrtTableGenerator_q <= "010100111000010110111111011010110011111111100100110111010";
WHEN "01011011" => memoryC0_uid50_sqrtTableGenerator_q <= "010100111011011010111011011110011010110001000011111110111";
WHEN "01011100" => memoryC0_uid50_sqrtTableGenerator_q <= "010100111110011110011010111011110001001110110010110011100";
WHEN "01011101" => memoryC0_uid50_sqrtTableGenerator_q <= "010101000001100001011101111111010101001001000110111011010";
WHEN "01011110" => memoryC0_uid50_sqrtTableGenerator_q <= "010101000100100100000100110101011011001111011011100000110";
WHEN "01011111" => memoryC0_uid50_sqrtTableGenerator_q <= "010101000111100110001111101010001111011001010110110001000";
WHEN "01100000" => memoryC0_uid50_sqrtTableGenerator_q <= "010101001010100111111110101001110100101111100011101010010";
WHEN "01100001" => memoryC0_uid50_sqrtTableGenerator_q <= "010101001101101001010010000000000101110100100000010000010";
WHEN "01100010" => memoryC0_uid50_sqrtTableGenerator_q <= "010101010000101010001001111000110100101101000000110110001";
WHEN "01100011" => memoryC0_uid50_sqrtTableGenerator_q <= "010101010011101010100110011111101011001000101000001111101";
WHEN "01100100" => memoryC0_uid50_sqrtTableGenerator_q <= "010101010110101010101000000000001010101001110101011010100";
WHEN "01100101" => memoryC0_uid50_sqrtTableGenerator_q <= "010101011001101010001110100101101100101110000110110001111";
WHEN "01100110" => memoryC0_uid50_sqrtTableGenerator_q <= "010101011100101001011010011011100010110101110011011000110";
WHEN "01100111" => memoryC0_uid50_sqrtTableGenerator_q <= "010101011111101000001011101100110110101011111010001101100";
WHEN "01101000" => memoryC0_uid50_sqrtTableGenerator_q <= "010101100010100110100010100100101010001101100111110011111";
WHEN "01101001" => memoryC0_uid50_sqrtTableGenerator_q <= "010101100101100100011111001101110111110001110010100101110";
WHEN "01101010" => memoryC0_uid50_sqrtTableGenerator_q <= "010101101000100010000001110011010010010000001101110111000";
WHEN "01101011" => memoryC0_uid50_sqrtTableGenerator_q <= "010101101011011111001010011111100101001000110011111011001";
WHEN "01101100" => memoryC0_uid50_sqrtTableGenerator_q <= "010101101110011011111001011101010100101010100111011010101";
WHEN "01101101" => memoryC0_uid50_sqrtTableGenerator_q <= "010101110001011000001110110110111101111010101100000011111";
WHEN "01101110" => memoryC0_uid50_sqrtTableGenerator_q <= "010101110100010100001010110110110110111010110111000101111";
WHEN "01101111" => memoryC0_uid50_sqrtTableGenerator_q <= "010101110111001111101101100111001110110000010111011111010";
WHEN "01110000" => memoryC0_uid50_sqrtTableGenerator_q <= "010101111010001010110111010010001101101010010110001111100";
WHEN "01110001" => memoryC0_uid50_sqrtTableGenerator_q <= "010101111101000101101000000001110101001000001110110100011";
WHEN "01110010" => memoryC0_uid50_sqrtTableGenerator_q <= "010110000000000000000000000000000000000000000000000000100";
WHEN "01110011" => memoryC0_uid50_sqrtTableGenerator_q <= "010110000010111001111111010110100010100100010101010100110";
WHEN "01110100" => memoryC0_uid50_sqrtTableGenerator_q <= "010110000101110011100110001111001010101010101001001000010";
WHEN "01110101" => memoryC0_uid50_sqrtTableGenerator_q <= "010110001000101100110100110011011111110000111111101000110";
WHEN "01110110" => memoryC0_uid50_sqrtTableGenerator_q <= "010110001011100101101011001101000011000011111010111110010";
WHEN "01110111" => memoryC0_uid50_sqrtTableGenerator_q <= "010110001110011110001001100101001111100100001000011011010";
WHEN "01111000" => memoryC0_uid50_sqrtTableGenerator_q <= "010110010001010110010000000101011010001100000111000100000";
WHEN "01111001" => memoryC0_uid50_sqrtTableGenerator_q <= "010110010100001101111110110110110001110101100111110100110";
WHEN "01111010" => memoryC0_uid50_sqrtTableGenerator_q <= "010110010111000101010110000010011111011111000111010010010";
WHEN "01111011" => memoryC0_uid50_sqrtTableGenerator_q <= "010110011001111100010101110001100110010001000001001011101";
WHEN "01111100" => memoryC0_uid50_sqrtTableGenerator_q <= "010110011100110010111110001101000011100010111101110111011";
WHEN "01111101" => memoryC0_uid50_sqrtTableGenerator_q <= "010110011111101001001111011101101111000000111001110011011";
WHEN "01111110" => memoryC0_uid50_sqrtTableGenerator_q <= "010110100010011111001001101100011010110000000111010001000";
WHEN "01111111" => memoryC0_uid50_sqrtTableGenerator_q <= "010110100101010100101101000001110011010100001010010011110";
WHEN "10000000" => memoryC0_uid50_sqrtTableGenerator_q <= "010110101000001001111001100110011111110011101111001101001";
WHEN "10000001" => memoryC0_uid50_sqrtTableGenerator_q <= "010110101101110011001110111111110110001100011001001000100";
WHEN "10000010" => memoryC0_uid50_sqrtTableGenerator_q <= "010110110011011011001010111011101100100001001011101011111";
WHEN "10000011" => memoryC0_uid50_sqrtTableGenerator_q <= "010110111001000001101110011011111110110011101101110101010";
WHEN "10000100" => memoryC0_uid50_sqrtTableGenerator_q <= "010110111110100110111010100001011000101101000011110000100";
WHEN "10000101" => memoryC0_uid50_sqrtTableGenerator_q <= "010111000100001010110000001011010111100101111000110010001";
WHEN "10000110" => memoryC0_uid50_sqrtTableGenerator_q <= "010111001001101101010000011000001100101010000010111110100";
WHEN "10000111" => memoryC0_uid50_sqrtTableGenerator_q <= "010111001111001110011100000100111110110111101100100011110";
WHEN "10001000" => memoryC0_uid50_sqrtTableGenerator_q <= "010111010100101110010100001101101100111010001110100010010";
WHEN "10001001" => memoryC0_uid50_sqrtTableGenerator_q <= "010111011010001100111001101101001111000001000111100000010";
WHEN "10001010" => memoryC0_uid50_sqrtTableGenerator_q <= "010111011111101010001101011101011000110010111001000011110";
WHEN "10001011" => memoryC0_uid50_sqrtTableGenerator_q <= "010111100101000110010000010110111010111100010101101100111";
WHEN "10001100" => memoryC0_uid50_sqrtTableGenerator_q <= "010111101010100001000011010001100100111100001000101101011";
WHEN "10001101" => memoryC0_uid50_sqrtTableGenerator_q <= "010111101111111010100111000100000110101011000001000000110";
WHEN "10001110" => memoryC0_uid50_sqrtTableGenerator_q <= "010111110101010010111100100100010010000000100111101001110";
WHEN "10001111" => memoryC0_uid50_sqrtTableGenerator_q <= "010111111010101010000100100110111100010101001010000100011";
WHEN "10010000" => memoryC0_uid50_sqrtTableGenerator_q <= "011000000000000000000000000000000000000000000000000000100";
WHEN "10010001" => memoryC0_uid50_sqrtTableGenerator_q <= "011000000101010100101111100010011101110011010100100110011";
WHEN "10010010" => memoryC0_uid50_sqrtTableGenerator_q <= "011000001010101000010100000000011110010100111001101100011";
WHEN "10010011" => memoryC0_uid50_sqrtTableGenerator_q <= "011000001111111010101110001011010011010100001100010101101";
WHEN "10010100" => memoryC0_uid50_sqrtTableGenerator_q <= "011000010101001011111110110011011000111101110000111001111";
WHEN "10010101" => memoryC0_uid50_sqrtTableGenerator_q <= "011000011010011100000110101000010111001100001101000111000";
WHEN "10010110" => memoryC0_uid50_sqrtTableGenerator_q <= "011000011111101011000110011001000010110110100101111010101";
WHEN "10010111" => memoryC0_uid50_sqrtTableGenerator_q <= "011000100100111000111110110011011110111100100111000001011";
WHEN "10011000" => memoryC0_uid50_sqrtTableGenerator_q <= "011000101010000101110000100100111101110000011001011010000";
WHEN "10011001" => memoryC0_uid50_sqrtTableGenerator_q <= "011000101111010001011100011010000001111110001110001011000";
WHEN "10011010" => memoryC0_uid50_sqrtTableGenerator_q <= "011000110100011100000010111110011111110010000010101100010";
WHEN "10011011" => memoryC0_uid50_sqrtTableGenerator_q <= "011000111001100101100100111101011101111011000010111000011";
WHEN "10011100" => memoryC0_uid50_sqrtTableGenerator_q <= "011000111110101110000011000001010110101101001110001010011";
WHEN "10011101" => memoryC0_uid50_sqrtTableGenerator_q <= "011001000011110101011101110011111001000001000011100100101";
WHEN "10011110" => memoryC0_uid50_sqrtTableGenerator_q <= "011001001000111011110101111110001001010001011001001101010";
WHEN "10011111" => memoryC0_uid50_sqrtTableGenerator_q <= "011001001110000001001100001000100010010111100011000101100";
WHEN "10100000" => memoryC0_uid50_sqrtTableGenerator_q <= "011001010011000101100000111010110110100101101101010011001";
WHEN "10100001" => memoryC0_uid50_sqrtTableGenerator_q <= "011001011000001000110100111100010000011111101101001011101";
WHEN "10100010" => memoryC0_uid50_sqrtTableGenerator_q <= "011001011101001011001000110011010011110010001101000110101";
WHEN "10100011" => memoryC0_uid50_sqrtTableGenerator_q <= "011001100010001100011101000101111110001000010110010010111";
WHEN "10100100" => memoryC0_uid50_sqrtTableGenerator_q <= "011001100111001100110010011001100111111111111100000000101";
WHEN "10100101" => memoryC0_uid50_sqrtTableGenerator_q <= "011001101100001100001001010011000101011100001011001110011";
WHEN "10100110" => memoryC0_uid50_sqrtTableGenerator_q <= "011001110001001010100010010110100110110111000001110111001";
WHEN "10100111" => memoryC0_uid50_sqrtTableGenerator_q <= "011001110110000111111110000111111001110001010000100010011";
WHEN "10101000" => memoryC0_uid50_sqrtTableGenerator_q <= "011001111011000100011101001010001001100001001001100100011";
WHEN "10101001" => memoryC0_uid50_sqrtTableGenerator_q <= "011010000000000000000000000000000000000000000000000000100";
WHEN "10101010" => memoryC0_uid50_sqrtTableGenerator_q <= "011010000100111010100111001011100110010110011001010001000";
WHEN "10101011" => memoryC0_uid50_sqrtTableGenerator_q <= "011010001001110100010011001110100101100111010011110101010";
WHEN "10101100" => memoryC0_uid50_sqrtTableGenerator_q <= "011010001110101101000100101010000111011010000101100000111";
WHEN "10101101" => memoryC0_uid50_sqrtTableGenerator_q <= "011010010011100100111011111110110110100011010011011110100";
WHEN "10101110" => memoryC0_uid50_sqrtTableGenerator_q <= "011010011000011011111001101100111111101100100110010111010";
WHEN "10101111" => memoryC0_uid50_sqrtTableGenerator_q <= "011010011101010001111110010100010001111011011100100100101";
WHEN "10110000" => memoryC0_uid50_sqrtTableGenerator_q <= "011010100010000111001010010011111111010110111100110100101";
WHEN "10110001" => memoryC0_uid50_sqrtTableGenerator_q <= "011010100110111011011110001010111101101100101010111100110";
WHEN "10110010" => memoryC0_uid50_sqrtTableGenerator_q <= "011010101011101110111010010111100110110100100000111000010";
WHEN "10110011" => memoryC0_uid50_sqrtTableGenerator_q <= "011010110000100001011111010111111001010011101101100110100";
WHEN "10110100" => memoryC0_uid50_sqrtTableGenerator_q <= "011010110101010011001101101001011000111110111011111100001";
WHEN "10110101" => memoryC0_uid50_sqrtTableGenerator_q <= "011010111010000100000101101001001111011011100010110100110";
WHEN "10110110" => memoryC0_uid50_sqrtTableGenerator_q <= "011010111110110100000111110100001100100000000000101110011";
WHEN "10110111" => memoryC0_uid50_sqrtTableGenerator_q <= "011011000011100011010100100110100110110011100011110101100";
WHEN "10111000" => memoryC0_uid50_sqrtTableGenerator_q <= "011011001000010001101100011100011100001101000000100011100";
WHEN "10111001" => memoryC0_uid50_sqrtTableGenerator_q <= "011011001100111111001111110001010010010000110111101111001";
WHEN "10111010" => memoryC0_uid50_sqrtTableGenerator_q <= "011011010001101011111111000000010110101110101110001001111";
WHEN "10111011" => memoryC0_uid50_sqrtTableGenerator_q <= "011011010110010111111010100100011111111101110110100011010";
WHEN "10111100" => memoryC0_uid50_sqrtTableGenerator_q <= "011011011011000011000010111000001101011001001111100110110";
WHEN "10111101" => memoryC0_uid50_sqrtTableGenerator_q <= "011011011111101101011000010101100111111010110111001000010";
WHEN "10111110" => memoryC0_uid50_sqrtTableGenerator_q <= "011011100100010110111011010110100010010110010011101100101";
WHEN "10111111" => memoryC0_uid50_sqrtTableGenerator_q <= "011011101000111111101100010100011001110010110101111100011";
WHEN "11000000" => memoryC0_uid50_sqrtTableGenerator_q <= "011011101101100111101011101000010110000100110010101011000";
WHEN "11000001" => memoryC0_uid50_sqrtTableGenerator_q <= "011011110010001110111001101011001010000110010110111001110";
WHEN "11000010" => memoryC0_uid50_sqrtTableGenerator_q <= "011011110110110101010110110101010100001111110110111100101";
WHEN "11000011" => memoryC0_uid50_sqrtTableGenerator_q <= "011011111011011011000011011110111110101111011001100001110";
WHEN "11000100" => memoryC0_uid50_sqrtTableGenerator_q <= "011100000000000000000000000000000000000000000000000000100";
WHEN "11000101" => memoryC0_uid50_sqrtTableGenerator_q <= "011100000100100100001100101111111011000000001100101001111";
WHEN "11000110" => memoryC0_uid50_sqrtTableGenerator_q <= "011100001001000111101010000101111111101000000111111010110";
WHEN "11000111" => memoryC0_uid50_sqrtTableGenerator_q <= "011100001101101010011000011001001010111111000101101000010";
WHEN "11001000" => memoryC0_uid50_sqrtTableGenerator_q <= "011100010010001100011000000000000111110000101011000000010";
WHEN "11001001" => memoryC0_uid50_sqrtTableGenerator_q <= "011100010110101101101001010001001110100001010110010011011";
WHEN "11001010" => memoryC0_uid50_sqrtTableGenerator_q <= "011100011011001110001100100010100110000010101000111111110";
WHEN "11001011" => memoryC0_uid50_sqrtTableGenerator_q <= "011100011111101110000010001010000011100110110101001100111";
WHEN "11001100" => memoryC0_uid50_sqrtTableGenerator_q <= "011100100100001101001010011101001011010100001111001110000";
WHEN "11001101" => memoryC0_uid50_sqrtTableGenerator_q <= "011100101000101011100101110001010000011000000011110111011";
WHEN "11001110" => memoryC0_uid50_sqrtTableGenerator_q <= "011100101101001001010100011011010101011000110100010111110";
WHEN "11001111" => memoryC0_uid50_sqrtTableGenerator_q <= "011100110001100110010110110000001100101000011000100010010";
WHEN "11010000" => memoryC0_uid50_sqrtTableGenerator_q <= "011100110110000010101101000100011000010101100111110011111";
WHEN "11010001" => memoryC0_uid50_sqrtTableGenerator_q <= "011100111010011110010111101100001010111101101010000000001";
WHEN "11010010" => memoryC0_uid50_sqrtTableGenerator_q <= "011100111110111001010110111011100111011100110000001100110";
WHEN "11010011" => memoryC0_uid50_sqrtTableGenerator_q <= "011101000011010011101011000110100001011110110110100100111";
WHEN "11010100" => memoryC0_uid50_sqrtTableGenerator_q <= "011101000111101101010100100000011101101111101111101001110";
WHEN "11010101" => memoryC0_uid50_sqrtTableGenerator_q <= "011101001100000110010011011100110010001010111001100111110";
WHEN "11010110" => memoryC0_uid50_sqrtTableGenerator_q <= "011101010000011110101000001110100110001010111110010001101";
WHEN "11010111" => memoryC0_uid50_sqrtTableGenerator_q <= "011101010100110110010011001000110010111000111110000110110";
WHEN "11011000" => memoryC0_uid50_sqrtTableGenerator_q <= "011101011001001101010100011110000011011011000111000110010";
WHEN "11011001" => memoryC0_uid50_sqrtTableGenerator_q <= "011101011101100011101100100000110101000011010111110000000";
WHEN "11011010" => memoryC0_uid50_sqrtTableGenerator_q <= "011101100001111001011011100011010111011101101110110010101";
WHEN "11011011" => memoryC0_uid50_sqrtTableGenerator_q <= "011101100110001110100001110111101100111110001000000111100";
WHEN "11011100" => memoryC0_uid50_sqrtTableGenerator_q <= "011101101010100010111111101111101010101110000111011000100";
WHEN "11011101" => memoryC0_uid50_sqrtTableGenerator_q <= "011101101110110110110101011100111000111010010000101111010";
WHEN "11011110" => memoryC0_uid50_sqrtTableGenerator_q <= "011101110011001010000011010000110010111111010000001000101";
WHEN "11011111" => memoryC0_uid50_sqrtTableGenerator_q <= "011101110111011100101001011100100111110110101111101000101";
WHEN "11100000" => memoryC0_uid50_sqrtTableGenerator_q <= "011101111011101110101000010001011010000011111101001001101";
WHEN "11100001" => memoryC0_uid50_sqrtTableGenerator_q <= "011110000000000000000000000000000000000000000000000000100";
WHEN "11100010" => memoryC0_uid50_sqrtTableGenerator_q <= "011110000100010000110000111001000100000101111110101111101";
WHEN "11100011" => memoryC0_uid50_sqrtTableGenerator_q <= "011110001000100000111011001101000100111110110101100000011";
WHEN "11100100" => memoryC0_uid50_sqrtTableGenerator_q <= "011110001100110000011111001100010101101100111101011100011";
WHEN "11100101" => memoryC0_uid50_sqrtTableGenerator_q <= "011110010000111111011101000110111101110111100101011011010";
WHEN "11100110" => memoryC0_uid50_sqrtTableGenerator_q <= "011110010101001101110101001100111001110101111100011110011";
WHEN "11100111" => memoryC0_uid50_sqrtTableGenerator_q <= "011110011001011011100111101101111010111010001110001110011";
WHEN "11101000" => memoryC0_uid50_sqrtTableGenerator_q <= "011110011101101000110100111001100111011100010001110000001";
WHEN "11101001" => memoryC0_uid50_sqrtTableGenerator_q <= "011110100001110101011100111111011011000100001011000110000";
WHEN "11101010" => memoryC0_uid50_sqrtTableGenerator_q <= "011110100110000001100000001110100110110100011111110010001";
WHEN "11101011" => memoryC0_uid50_sqrtTableGenerator_q <= "011110101010001100111110110110010001010100011110101011101";
WHEN "11101100" => memoryC0_uid50_sqrtTableGenerator_q <= "011110101110010111111001000101010110111001111011011011111";
WHEN "11101101" => memoryC0_uid50_sqrtTableGenerator_q <= "011110110010100010001111001010101001110010111101110011101";
WHEN "11101110" => memoryC0_uid50_sqrtTableGenerator_q <= "011110110110101100000001010100110010001111100101001100110";
WHEN "11101111" => memoryC0_uid50_sqrtTableGenerator_q <= "011110111010110101001111110010001110101011000000101000011";
WHEN "11110000" => memoryC0_uid50_sqrtTableGenerator_q <= "011110111110111101111010110001010011110100111011011010010";
WHEN "11110001" => memoryC0_uid50_sqrtTableGenerator_q <= "011111000011000110000010100000001100111010011110110011010";
WHEN "11110010" => memoryC0_uid50_sqrtTableGenerator_q <= "011111000111001101100111001100111011101111001000111001110";
WHEN "11110011" => memoryC0_uid50_sqrtTableGenerator_q <= "011111001011010100101001000101011000110101011001000000010";
WHEN "11110100" => memoryC0_uid50_sqrtTableGenerator_q <= "011111001111011011001000010111010011100111010001101001000";
WHEN "11110101" => memoryC0_uid50_sqrtTableGenerator_q <= "011111010011100001000101010000010010011110110000100110001";
WHEN "11110110" => memoryC0_uid50_sqrtTableGenerator_q <= "011111010111100110011111111101110010111101111101000100001";
WHEN "11110111" => memoryC0_uid50_sqrtTableGenerator_q <= "011111011011101011011000101101001001110111001100001101010";
WHEN "11111000" => memoryC0_uid50_sqrtTableGenerator_q <= "011111011111101111101111101011100011010100111100010010011";
WHEN "11111001" => memoryC0_uid50_sqrtTableGenerator_q <= "011111100011110011100101000110000011000001100110101000111";
WHEN "11111010" => memoryC0_uid50_sqrtTableGenerator_q <= "011111100111110110111001001001100100001111001000100111110";
WHEN "11111011" => memoryC0_uid50_sqrtTableGenerator_q <= "011111101011111001101100000010111001111110100011110010110";
WHEN "11111100" => memoryC0_uid50_sqrtTableGenerator_q <= "011111101111111011111101111110101111000111010101011111001";
WHEN "11111101" => memoryC0_uid50_sqrtTableGenerator_q <= "011111110011111101101111001001100110011110100101111101101";
WHEN "11111110" => memoryC0_uid50_sqrtTableGenerator_q <= "011111110111111110111111101111111010111110001111010110010";
WHEN "11111111" => memoryC0_uid50_sqrtTableGenerator_q <= "011111111011111111101111111101111111101011111100011111111";
WHEN OTHERS =>
memoryC0_uid50_sqrtTableGenerator_q <= "010000000000000000000000000000000000000000000000000000100";
END CASE;
-- End reserved scope level
END PROCESS;
--rndBit_uid82_sqrtPolynomialEvaluator(CONSTANT,81)
rndBit_uid82_sqrtPolynomialEvaluator_q <= "001";
--cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator(BITJOIN,82)@26
cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_q <= memoryC0_uid50_sqrtTableGenerator_q & rndBit_uid82_sqrtPolynomialEvaluator_q;
--reg_cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_0(REG,147)@26
reg_cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_0_q <= "000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_0_q <= cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_q;
END IF;
END PROCESS;
--ts5_uid84_sqrtPolynomialEvaluator(ADD,83)@27
ts5_uid84_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((60 downto 60 => reg_cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_0_q(59)) & reg_cIncludingRoundingBit_uid83_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_0_q);
ts5_uid84_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((60 downto 53 => reg_R_uid127_pT5_uid81_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_1_q(52)) & reg_R_uid127_pT5_uid81_sqrtPolynomialEvaluator_0_to_ts5_uid84_sqrtPolynomialEvaluator_1_q);
ts5_uid84_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid84_sqrtPolynomialEvaluator_a) + SIGNED(ts5_uid84_sqrtPolynomialEvaluator_b));
ts5_uid84_sqrtPolynomialEvaluator_q <= ts5_uid84_sqrtPolynomialEvaluator_o(60 downto 0);
--s5_uid85_sqrtPolynomialEvaluator(BITSELECT,84)@27
s5_uid85_sqrtPolynomialEvaluator_in <= ts5_uid84_sqrtPolynomialEvaluator_q;
s5_uid85_sqrtPolynomialEvaluator_b <= s5_uid85_sqrtPolynomialEvaluator_in(60 downto 1);
--fracR_uid35_fpSqrtTest(BITSELECT,34)@27
fracR_uid35_fpSqrtTest_in <= s5_uid85_sqrtPolynomialEvaluator_b(56 downto 0);
fracR_uid35_fpSqrtTest_b <= fracR_uid35_fpSqrtTest_in(56 downto 5);
--reg_fracR_uid35_fpSqrtTest_0_to_fracRPostExc_uid47_fpSqrtTest_3(REG,148)@27
reg_fracR_uid35_fpSqrtTest_0_to_fracRPostExc_uid47_fpSqrtTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid35_fpSqrtTest_0_to_fracRPostExc_uid47_fpSqrtTest_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_fracR_uid35_fpSqrtTest_0_to_fracRPostExc_uid47_fpSqrtTest_3_q <= fracR_uid35_fpSqrtTest_b;
END IF;
END PROCESS;
--fracInf_uid45_fpSqrtTest(CONSTANT,44)
fracInf_uid45_fpSqrtTest_q <= "0000000000000000000000000000000000000000000000000000";
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor(LOGICAL,344)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_b <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_sticky_ena_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_q <= not (ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_a or ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_b);
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_mem_top(CONSTANT,340)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_mem_top_q <= "011000";
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp(LOGICAL,341)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_a <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_mem_top_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_q);
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_q <= "1" when ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_a = ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_b else "0";
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmpReg(REG,342)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmpReg_q <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmp_q;
END IF;
END PROCESS;
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_sticky_ena(REG,345)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_nor_q = "1") THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_sticky_ena_q <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd(LOGICAL,346)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_a <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_sticky_ena_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_b <= VCC_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_q <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_a and ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_b;
--fracX_uid7_fpSqrtTest(BITSELECT,6)@0
fracX_uid7_fpSqrtTest_in <= xIn_0(51 downto 0);
fracX_uid7_fpSqrtTest_b <= fracX_uid7_fpSqrtTest_in(51 downto 0);
--fracIsZero_uid12_fpSqrtTest(LOGICAL,11)@0
fracIsZero_uid12_fpSqrtTest_a <= fracX_uid7_fpSqrtTest_b;
fracIsZero_uid12_fpSqrtTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000" & GND_q);
fracIsZero_uid12_fpSqrtTest_q <= "1" when fracIsZero_uid12_fpSqrtTest_a = fracIsZero_uid12_fpSqrtTest_b else "0";
--InvFracIsZero_uid16_fpSqrtTest(LOGICAL,15)@0
InvFracIsZero_uid16_fpSqrtTest_a <= fracIsZero_uid12_fpSqrtTest_q;
InvFracIsZero_uid16_fpSqrtTest_q <= not InvFracIsZero_uid16_fpSqrtTest_a;
--excNaN_uid17_fpSqrtTest(LOGICAL,16)@0
excNaN_uid17_fpSqrtTest_a <= cmpEQ_w11_uid11_fpSqrtTest_q;
excNaN_uid17_fpSqrtTest_b <= InvFracIsZero_uid16_fpSqrtTest_q;
excNaN_uid17_fpSqrtTest_q <= excNaN_uid17_fpSqrtTest_a and excNaN_uid17_fpSqrtTest_b;
--excInf_uid14_fpSqrtTest(LOGICAL,13)@0
excInf_uid14_fpSqrtTest_a <= cmpEQ_w11_uid11_fpSqrtTest_q;
excInf_uid14_fpSqrtTest_b <= fracIsZero_uid12_fpSqrtTest_q;
excInf_uid14_fpSqrtTest_q <= excInf_uid14_fpSqrtTest_a and excInf_uid14_fpSqrtTest_b;
--join_uid41_fpSqrtTest(BITJOIN,40)@0
join_uid41_fpSqrtTest_q <= excNaN_uid17_fpSqrtTest_q & excInf_uid14_fpSqrtTest_q & expZ_uid9_fpSqrtTest_q;
--fracSelIn_uid42_fpSqrtTest(BITJOIN,41)@0
fracSelIn_uid42_fpSqrtTest_q <= signX_uid8_fpSqrtTest_b & join_uid41_fpSqrtTest_q;
--reg_fracSelIn_uid42_fpSqrtTest_0_to_fracSel_uid43_fpSqrtTest_0(REG,129)@0
reg_fracSelIn_uid42_fpSqrtTest_0_to_fracSel_uid43_fpSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid42_fpSqrtTest_0_to_fracSel_uid43_fpSqrtTest_0_q <= "0000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_fracSelIn_uid42_fpSqrtTest_0_to_fracSel_uid43_fpSqrtTest_0_q <= fracSelIn_uid42_fpSqrtTest_q;
END IF;
END PROCESS;
--fracSel_uid43_fpSqrtTest(LOOKUP,42)@1
fracSel_uid43_fpSqrtTest: PROCESS (reg_fracSelIn_uid42_fpSqrtTest_0_to_fracSel_uid43_fpSqrtTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid42_fpSqrtTest_0_to_fracSel_uid43_fpSqrtTest_0_q) IS
WHEN "0000" => fracSel_uid43_fpSqrtTest_q <= "01";
WHEN "0001" => fracSel_uid43_fpSqrtTest_q <= "00";
WHEN "0010" => fracSel_uid43_fpSqrtTest_q <= "10";
WHEN "0011" => fracSel_uid43_fpSqrtTest_q <= "00";
WHEN "0100" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN "0101" => fracSel_uid43_fpSqrtTest_q <= "00";
WHEN "0110" => fracSel_uid43_fpSqrtTest_q <= "10";
WHEN "0111" => fracSel_uid43_fpSqrtTest_q <= "00";
WHEN "1000" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN "1001" => fracSel_uid43_fpSqrtTest_q <= "00";
WHEN "1010" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN "1011" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN "1100" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN "1101" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN "1110" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN "1111" => fracSel_uid43_fpSqrtTest_q <= "11";
WHEN OTHERS =>
fracSel_uid43_fpSqrtTest_q <= "01";
END CASE;
-- End reserved scope level
END PROCESS;
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt(COUNTER,336)
-- every=1, low=0, high=24, step=1, init=1
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i = 23 THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_eq = '1') THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i - 24;
ELSE
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_i,5));
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg(REG,337)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg_q <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux(MUX,338)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_s <= VCC_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux: PROCESS (ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_s, ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg_q, ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_q <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem(DUALMEM,335)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_reset0 <= areset;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_ia <= fracSel_uid43_fpSqrtTest_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_aa <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdreg_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_ab <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_rdmux_q;
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 5,
numwords_a => 25,
width_b => 2,
widthad_b => 5,
numwords_b => 25,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_iq,
address_a => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_aa,
data_a => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_ia
);
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_q <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_iq(1 downto 0);
--ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_outputreg(DELAY,334)
ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_outputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_replace_mem_q, xout => ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_outputreg_q, clk => clk, aclr => areset );
--fracRPostExc_uid47_fpSqrtTest(MUX,46)@28
fracRPostExc_uid47_fpSqrtTest_s <= ld_fracSel_uid43_fpSqrtTest_q_to_fracRPostExc_uid47_fpSqrtTest_b_outputreg_q;
fracRPostExc_uid47_fpSqrtTest: PROCESS (fracRPostExc_uid47_fpSqrtTest_s, reg_fracR_uid35_fpSqrtTest_0_to_fracRPostExc_uid47_fpSqrtTest_3_q)
BEGIN
CASE fracRPostExc_uid47_fpSqrtTest_s IS
WHEN "00" => fracRPostExc_uid47_fpSqrtTest_q <= fracInf_uid45_fpSqrtTest_q;
WHEN "01" => fracRPostExc_uid47_fpSqrtTest_q <= reg_fracR_uid35_fpSqrtTest_0_to_fracRPostExc_uid47_fpSqrtTest_3_q;
WHEN "10" => fracRPostExc_uid47_fpSqrtTest_q <= fracInf_uid45_fpSqrtTest_q;
WHEN "11" => fracRPostExc_uid47_fpSqrtTest_q <= fracNaN_uid44_fpSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid47_fpSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid48_fpSqrtTest(BITJOIN,47)@28
RSqrt_uid48_fpSqrtTest_q <= ld_excMZero_uid13_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_c_outputreg_q & ld_expRPostExc_uid40_fpSqrtTest_q_to_RSqrt_uid48_fpSqrtTest_b_replace_mem_q & fracRPostExc_uid47_fpSqrtTest_q;
--ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,322)
ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset;
ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c;
ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 26,
width_b => 8,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_c_to_xOut_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_c_to_xOut_c_replace_mem_iq,
address_a => ld_xIn_c_to_xOut_c_replace_mem_aa,
data_a => ld_xIn_c_to_xOut_c_replace_mem_ia
);
ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0);
--ld_xIn_c_to_xOut_c_outputreg(DELAY,321)
ld_xIn_c_to_xOut_c_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset );
--ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,309)
ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset;
ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v;
ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 26,
width_b => 1,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_v_to_xOut_v_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_v_to_xOut_v_replace_mem_iq,
address_a => ld_xIn_v_to_xOut_v_replace_mem_aa,
data_a => ld_xIn_v_to_xOut_v_replace_mem_ia
);
ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0);
--ld_xIn_v_to_xOut_v_outputreg(DELAY,308)
ld_xIn_v_to_xOut_v_outputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset );
--xOut(PORTOUT,4)@28
xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q;
xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q;
xOut_0 <= RSqrt_uid48_fpSqrtTest_q;
end normal;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_cordic_start1.vhd | 10 | 3284 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_START1.VHD ***
--*** ***
--*** Function: Table for Initial Value of X ***
--*** for SIN and COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_start1 IS
GENERIC (width : positive := 36);
PORT (
index : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
value : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_start1;
ARCHITECTURE rtl of fp_cordic_start1 IS
signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
pva: PROCESS (index)
BEGIN
CASE index IS
WHEN "0000" => valuenode <= x"26DD3B6A1";
WHEN "0001" => valuenode <= x"36F656C5A";
WHEN "0010" => valuenode <= x"3D731DFFB";
WHEN "0011" => valuenode <= x"3F5743B24";
WHEN "0100" => valuenode <= x"3FD574860";
WHEN "0101" => valuenode <= x"3FF557499";
WHEN "0110" => valuenode <= x"3FFD5574A";
WHEN "0111" => valuenode <= x"3FFF55575";
WHEN "1000" => valuenode <= x"3FFFD5557";
WHEN "1001" => valuenode <= x"3FFFF5555";
WHEN "1010" => valuenode <= x"3FFFFD555";
WHEN "1011" => valuenode <= x"3FFFFF555";
WHEN "1101" => valuenode <= x"3FFFFFD55";
WHEN "1100" => valuenode <= x"3FFFFFF55";
WHEN "1111" => valuenode <= x"3FFFFFFD5";
WHEN "1110" => valuenode <= x"3FFFFFFF5";
WHEN others => valuenode <= x"000000000";
END CASE;
END PROCESS;
value <= valuenode (36 DOWNTO 37-width);
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/CosDPStratixVf400_safe_path.vhd | 10 | 427 | -- safe_path for CosDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosDPStratixVf400_safe_path;
PACKAGE body CosDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosDPStratixVf400_safe_path;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/fp_exp_double_s5.vhd | 10 | 750433 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp_double_s5
-- VHDL created on Thu Apr 11 10:14:45 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBias_uid8_fpExpETest_q : std_logic_vector (10 downto 0);
signal cstZeroWE_uid11_fpExpETest_q : std_logic_vector (10 downto 0);
signal cstZeroWEP1_uid12_fpExpETest_q : std_logic_vector (11 downto 0);
signal cstBiasPWE_uid13_fpExpETest_q : std_logic_vector (10 downto 0);
signal cstBiasPWE_uid14_fpExpETest_q : std_logic_vector (6 downto 0);
signal cstAllOWE_uid15_fpExpETest_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid16_fpExpETest_q : std_logic_vector (51 downto 0);
signal exc_R_uid30_fpExpETest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpExpETest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpExpETest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpExpETest_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpExpETest_q : std_logic_vector(0 downto 0);
signal zY_uid60_fpExpETest_q : std_logic_vector (54 downto 0);
signal expRPostBiasPreExc0_uid69_fpExpETest_a : std_logic_vector(15 downto 0);
signal expRPostBiasPreExc0_uid69_fpExpETest_b : std_logic_vector(15 downto 0);
signal expRPostBiasPreExc0_uid69_fpExpETest_o : std_logic_vector (15 downto 0);
signal expRPostBiasPreExc0_uid69_fpExpETest_q : std_logic_vector (14 downto 0);
signal oneFracRPostExc2_uid90_fpExpETest_q : std_logic_vector (51 downto 0);
signal p8_uid109_constMult_q : std_logic_vector(61 downto 0);
signal p6_uid111_constMult_q : std_logic_vector(49 downto 0);
signal p4_uid113_constMult_q : std_logic_vector(37 downto 0);
signal p2_uid115_constMult_q : std_logic_vector(25 downto 0);
signal lev1_a0_uid118_constMult_a : std_logic_vector(63 downto 0);
signal lev1_a0_uid118_constMult_b : std_logic_vector(63 downto 0);
signal lev1_a0_uid118_constMult_o : std_logic_vector (63 downto 0);
signal lev1_a0_uid118_constMult_q : std_logic_vector (62 downto 0);
signal lev1_a2_uid120_constMult_a : std_logic_vector(38 downto 0);
signal lev1_a2_uid120_constMult_b : std_logic_vector(38 downto 0);
signal lev1_a2_uid120_constMult_o : std_logic_vector (38 downto 0);
signal lev1_a2_uid120_constMult_q : std_logic_vector (38 downto 0);
signal lev2_a0_uid122_constMult_a : std_logic_vector(64 downto 0);
signal lev2_a0_uid122_constMult_b : std_logic_vector(64 downto 0);
signal lev2_a0_uid122_constMult_o : std_logic_vector (64 downto 0);
signal lev2_a0_uid122_constMult_q : std_logic_vector (63 downto 0);
signal lev3_a0_uid124_constMult_a : std_logic_vector(65 downto 0);
signal lev3_a0_uid124_constMult_b : std_logic_vector(65 downto 0);
signal lev3_a0_uid124_constMult_o : std_logic_vector (65 downto 0);
signal lev3_a0_uid124_constMult_q : std_logic_vector (64 downto 0);
signal z_uid129_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (31 downto 0);
signal z_uid133_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (63 downto 0);
signal rightShiftStage0Idx3_uid137_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(68 downto 0);
signal rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(68 downto 0);
signal rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(68 downto 0);
signal rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(68 downto 0);
signal z_uid141_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(7 downto 0);
signal z_uid145_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(15 downto 0);
signal z_uid149_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(23 downto 0);
signal z_uid155_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(1 downto 0);
signal z_uid159_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (3 downto 0);
signal rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(3 downto 0);
signal z_uid163_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (5 downto 0);
signal rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(0 downto 0);
signal p2_uid179_constMult_q : std_logic_vector(76 downto 0);
signal lev1_a0_uid182_constMult_a : std_logic_vector(78 downto 0);
signal lev1_a0_uid182_constMult_b : std_logic_vector(78 downto 0);
signal lev1_a0_uid182_constMult_o : std_logic_vector (78 downto 0);
signal lev1_a0_uid182_constMult_q : std_logic_vector (77 downto 0);
signal rightShiftStage0Idx3_uid195_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(65 downto 0);
signal rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(65 downto 0);
signal rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(65 downto 0);
signal rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(65 downto 0);
signal rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(7 downto 0);
signal rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(15 downto 0);
signal rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(23 downto 0);
signal rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(23 downto 0);
signal rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(1 downto 0);
signal rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(3 downto 0);
signal rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(5 downto 0);
signal rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(5 downto 0);
signal rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_i : std_logic_vector(0 downto 0);
signal rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(0 downto 0);
signal memoryC0_uid234_exp10TabGen_q : std_logic_vector(39 downto 0);
signal memoryC0_uid235_exp10TabGen_q : std_logic_vector(17 downto 0);
signal memoryC1_uid237_exp10TabGen_q : std_logic_vector(39 downto 0);
signal memoryC1_uid238_exp10TabGen_q : std_logic_vector(10 downto 0);
signal memoryC2_uid240_exp10TabGen_q : std_logic_vector(39 downto 0);
signal memoryC2_uid241_exp10TabGen_q : std_logic_vector(2 downto 0);
signal memoryC3_uid243_exp10TabGen_q : std_logic_vector(34 downto 0);
signal memoryC4_uid245_exp10TabGen_q : std_logic_vector(24 downto 0);
signal memoryC5_uid247_exp10TabGen_q : std_logic_vector(15 downto 0);
signal rndBit_uid263_exp10PolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid275_exp10PolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid280_pT1_uid250_exp10PolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid280_pT1_uid250_exp10PolyEval_b : std_logic_vector (15 downto 0);
signal prodXY_uid280_pT1_uid250_exp10PolyEval_s1 : std_logic_vector (31 downto 0);
signal prodXY_uid280_pT1_uid250_exp10PolyEval_pr : SIGNED (32 downto 0);
signal prodXY_uid280_pT1_uid250_exp10PolyEval_q : std_logic_vector (31 downto 0);
signal prodXY_uid283_pT2_uid256_exp10PolyEval_a : std_logic_vector (24 downto 0);
signal prodXY_uid283_pT2_uid256_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal prodXY_uid283_pT2_uid256_exp10PolyEval_s1 : std_logic_vector (51 downto 0);
signal prodXY_uid283_pT2_uid256_exp10PolyEval_pr : SIGNED (52 downto 0);
signal prodXY_uid283_pT2_uid256_exp10PolyEval_q : std_logic_vector (51 downto 0);
signal topProd_uid288_pT3_uid262_exp10PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid288_pT3_uid262_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid288_pT3_uid262_exp10PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid288_pT3_uid262_exp10PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid288_pT3_uid262_exp10PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid305_pT4_uid268_exp10PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid305_pT4_uid268_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid305_pT4_uid268_exp10PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid305_pT4_uid268_exp10PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid305_pT4_uid268_exp10PolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid320_pT5_uid274_exp10PolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid320_pT5_uid274_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid320_pT5_uid274_exp10PolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid320_pT5_uid274_exp10PolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid320_pT5_uid274_exp10PolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid332_pT5_uid274_exp10PolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid332_pT5_uid274_exp10PolyEval_b : std_logic_vector (2 downto 0);
signal sm0_uid332_pT5_uid274_exp10PolyEval_s1 : std_logic_vector (5 downto 0);
signal sm0_uid332_pT5_uid274_exp10PolyEval_pr : UNSIGNED (5 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid332_pT5_uid274_exp10PolyEval_pr: signal is "logic";
signal sm0_uid332_pT5_uid274_exp10PolyEval_q : std_logic_vector (5 downto 0);
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a : signal is true;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c : signal is true;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l_type;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p_type;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_w : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_w_type;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_x : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_x_type;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_y : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_y_type;
type multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s : multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s_type;
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l_type;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p_type;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w_type;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x_type;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y_type;
type multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s : multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s_type;
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a : signal is true;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c : signal is true;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l_type;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p_type;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w_type;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x_type;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y_type;
type multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s : multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s_type;
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0_q : std_logic_vector (11 downto 0);
signal reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2_q : std_logic_vector (68 downto 0);
signal reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3_q : std_logic_vector (68 downto 0);
signal reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4_q : std_logic_vector (68 downto 0);
signal reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2_q : std_logic_vector (68 downto 0);
signal reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2_q : std_logic_vector (68 downto 0);
signal reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_q : std_logic_vector (0 downto 0);
signal reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q : std_logic_vector (13 downto 0);
signal reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2_q : std_logic_vector (65 downto 0);
signal reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3_q : std_logic_vector (65 downto 0);
signal reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4_q : std_logic_vector (65 downto 0);
signal reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2_q : std_logic_vector (65 downto 0);
signal reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2_q : std_logic_vector (65 downto 0);
signal reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q : std_logic_vector (0 downto 0);
signal reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0_q : std_logic_vector (1 downto 0);
signal reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0_q : std_logic_vector (73 downto 0);
signal reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1_q : std_logic_vector (74 downto 0);
signal reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1_q : std_logic_vector (0 downto 0);
signal reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2_q : std_logic_vector (54 downto 0);
signal reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_q : std_logic_vector (6 downto 0);
signal reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q : std_logic_vector (6 downto 0);
signal reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_q : std_logic_vector (24 downto 0);
signal reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1_q : std_logic_vector (36 downto 0);
signal reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0_q : std_logic_vector (52 downto 0);
signal reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q : std_logic_vector (2 downto 0);
signal reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0_q : std_logic_vector (60 downto 0);
signal reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1_q : std_logic_vector (54 downto 0);
signal reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1_q : std_logic_vector (0 downto 0);
signal reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q : std_logic_vector (15 downto 0);
signal reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0_q : std_logic_vector (2 downto 0);
signal ld_shiftUdf_uid42_fpExpETest_n_to_shiftVal_uid44_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_yRedPostMux_uid62_fpExpETest_q_to_yPPolyEval_uid65_fpExpETest_a_q : std_logic_vector (54 downto 0);
signal ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid24_fpExpETest_q_to_posInf_uid86_fpExpETest_a_q : std_logic_vector (0 downto 0);
signal ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_q : std_logic_vector (51 downto 0);
signal ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d_q : std_logic_vector (10 downto 0);
signal ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q_to_p6_uid111_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q_to_p4_uid113_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (60 downto 0);
signal ld_RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (52 downto 0);
signal ld_RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (44 downto 0);
signal ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (66 downto 0);
signal ld_RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (64 downto 0);
signal ld_RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_a_q : std_logic_vector (62 downto 0);
signal ld_reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (57 downto 0);
signal ld_RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (49 downto 0);
signal ld_RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (41 downto 0);
signal ld_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (1 downto 0);
signal ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (63 downto 0);
signal ld_RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (61 downto 0);
signal ld_RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_a_q : std_logic_vector (59 downto 0);
signal ld_rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_to_rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC4_uid245_exp10TabGen_0_q_to_memoryC4_uid245_exp10TabGen_a_q : std_logic_vector (6 downto 0);
signal ld_yT4_uid267_exp10PolyEval_b_to_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_yBottomBits_uid306_pT4_uid268_exp10PolyEval_b_to_spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_yBottomBits_uid321_pT5_uid274_exp10PolyEval_b_to_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_b_q : std_logic_vector (25 downto 0);
signal ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a_q : std_logic_vector (59 downto 0);
signal ld_xv5_uid105_constMult_b_to_reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_xv2_uid102_constMult_b_to_reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_xv1_uid101_constMult_b_to_reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_a_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_a_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_a_q : std_logic_vector (0 downto 0);
signal ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_a_q : std_logic_vector (1 downto 0);
signal ld_xv1_uid177_constMult_b_to_reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_xv0_uid176_constMult_b_to_reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b_to_reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_inputreg_q : std_logic_vector (6 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_reset0 : std_logic;
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_eq : std_logic;
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_mem_top_q : std_logic_vector (2 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q : signal is true;
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_reset0 : std_logic;
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_eq : std_logic;
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q : signal is true;
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_inputreg_q : std_logic_vector (13 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_reset0 : std_logic;
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q : signal is true;
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_reset0 : std_logic;
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_eq : std_logic;
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q : signal is true;
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_reset0 : std_logic;
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_eq : std_logic;
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q : signal is true;
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_reset0 : std_logic;
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q : signal is true;
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_reset0 : std_logic;
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q : signal is true;
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_reset0 : std_logic;
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q : signal is true;
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_reset0 : std_logic;
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q : signal is true;
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_reset0 : std_logic;
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q : signal is true;
signal ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_inputreg_q : std_logic_vector (51 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q : signal is true;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q : signal is true;
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_inputreg_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_reset0 : std_logic;
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q : signal is true;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_eq : std_logic;
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg_q : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q : signal is true;
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_inputreg_q : std_logic_vector (20 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ia : std_logic_vector (20 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_iq : std_logic_vector (20 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_q : std_logic_vector (20 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q : signal is true;
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_reset0 : std_logic;
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q : signal is true;
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg_q : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_eq : std_logic;
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q : signal is true;
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_inputreg_q : std_logic_vector (24 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ia : std_logic_vector (24 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_iq : std_logic_vector (24 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_q : std_logic_vector (24 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q : signal is true;
signal shiftUdf_uid42_fpExpETest_a : std_logic_vector(14 downto 0);
signal shiftUdf_uid42_fpExpETest_b : std_logic_vector(14 downto 0);
signal shiftUdf_uid42_fpExpETest_o : std_logic_vector (14 downto 0);
signal shiftUdf_uid42_fpExpETest_cin : std_logic_vector (0 downto 0);
signal shiftUdf_uid42_fpExpETest_n : std_logic_vector (0 downto 0);
signal expUdf_uid72_fpExpETest_a : std_logic_vector(18 downto 0);
signal expUdf_uid72_fpExpETest_b : std_logic_vector(18 downto 0);
signal expUdf_uid72_fpExpETest_o : std_logic_vector (18 downto 0);
signal expUdf_uid72_fpExpETest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid72_fpExpETest_n : std_logic_vector (0 downto 0);
signal expOvf_uid74_fpExpETest_a : std_logic_vector(18 downto 0);
signal expOvf_uid74_fpExpETest_b : std_logic_vector(18 downto 0);
signal expOvf_uid74_fpExpETest_o : std_logic_vector (18 downto 0);
signal expOvf_uid74_fpExpETest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid74_fpExpETest_n : std_logic_vector (0 downto 0);
signal spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_q : std_logic_vector (26 downto 0);
signal spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_q : std_logic_vector (26 downto 0);
signal pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_q : std_logic_vector (26 downto 0);
signal oFracXZwE_uid48_fpExpETest_q : std_logic_vector (65 downto 0);
signal InvExpOvfInitial_uid78_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvExpOvfInitial_uid78_fpExpETest_q : std_logic_vector(0 downto 0);
signal InvSignX_uid81_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid81_fpExpETest_q : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal expX_uid6_fpExpETest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpExpETest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpExpETest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpExpETest_b : std_logic_vector (0 downto 0);
signal frac_uid22_fpExpETest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpExpETest_b : std_logic_vector (51 downto 0);
signal expXIsZero_uid19_fpExpETest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpExpETest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpExpETest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpExpETest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpExpETest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpExpETest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid23_fpExpETest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpExpETest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpExpETest_q : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpExpETest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpExpETest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpExpETest_q : std_logic_vector(0 downto 0);
signal shiftValuePreSat_uid40_fpExpETest_a : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid40_fpExpETest_b : std_logic_vector(11 downto 0);
signal shiftValuePreSat_uid40_fpExpETest_o : std_logic_vector (11 downto 0);
signal shiftValuePreSat_uid40_fpExpETest_q : std_logic_vector (11 downto 0);
signal shiftVal_uid44_fpExpETest_s : std_logic_vector (0 downto 0);
signal shiftVal_uid44_fpExpETest_q : std_logic_vector (6 downto 0);
signal onesCmpFxpIn_uid49_fpExpETest_a : std_logic_vector(65 downto 0);
signal onesCmpFxpIn_uid49_fpExpETest_b : std_logic_vector(65 downto 0);
signal onesCmpFxpIn_uid49_fpExpETest_q : std_logic_vector(65 downto 0);
signal fxpInExt_uid50_fpExpETest_a : std_logic_vector(67 downto 0);
signal fxpInExt_uid50_fpExpETest_b : std_logic_vector(67 downto 0);
signal fxpInExt_uid50_fpExpETest_o : std_logic_vector (67 downto 0);
signal fxpInExt_uid50_fpExpETest_q : std_logic_vector (66 downto 0);
signal yExt_uid57_fpExpETest_a : std_logic_vector(75 downto 0);
signal yExt_uid57_fpExpETest_b : std_logic_vector(75 downto 0);
signal yExt_uid57_fpExpETest_o : std_logic_vector (75 downto 0);
signal yExt_uid57_fpExpETest_q : std_logic_vector (75 downto 0);
signal yRedPostMux_uid62_fpExpETest_s : std_logic_vector (0 downto 0);
signal yRedPostMux_uid62_fpExpETest_q : std_logic_vector (54 downto 0);
signal expRPostBiasPreExc_uid70_fpExpETest_a : std_logic_vector(16 downto 0);
signal expRPostBiasPreExc_uid70_fpExpETest_b : std_logic_vector(16 downto 0);
signal expRPostBiasPreExc_uid70_fpExpETest_o : std_logic_vector (16 downto 0);
signal expRPostBiasPreExc_uid70_fpExpETest_q : std_logic_vector (15 downto 0);
signal negInf_uid76_fpExpETest_a : std_logic_vector(0 downto 0);
signal negInf_uid76_fpExpETest_b : std_logic_vector(0 downto 0);
signal negInf_uid76_fpExpETest_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid77_fpExpETest_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid77_fpExpETest_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid77_fpExpETest_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndNeg_uid77_fpExpETest_q : std_logic_vector(0 downto 0);
signal regXAndUdf_uid79_fpExpETest_a : std_logic_vector(0 downto 0);
signal regXAndUdf_uid79_fpExpETest_b : std_logic_vector(0 downto 0);
signal regXAndUdf_uid79_fpExpETest_c : std_logic_vector(0 downto 0);
signal regXAndUdf_uid79_fpExpETest_q : std_logic_vector(0 downto 0);
signal excRZero_uid80_fpExpETest_a : std_logic_vector(0 downto 0);
signal excRZero_uid80_fpExpETest_b : std_logic_vector(0 downto 0);
signal excRZero_uid80_fpExpETest_c : std_logic_vector(0 downto 0);
signal excRZero_uid80_fpExpETest_q : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid82_fpExpETest_a : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid82_fpExpETest_b : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid82_fpExpETest_c : std_logic_vector(0 downto 0);
signal regXAndExpOverflowAndPos_uid82_fpExpETest_q : std_logic_vector(0 downto 0);
signal regInAndOvf_uid84_fpExpETest_a : std_logic_vector(0 downto 0);
signal regInAndOvf_uid84_fpExpETest_b : std_logic_vector(0 downto 0);
signal regInAndOvf_uid84_fpExpETest_c : std_logic_vector(0 downto 0);
signal regInAndOvf_uid84_fpExpETest_q : std_logic_vector(0 downto 0);
signal posInf_uid86_fpExpETest_a : std_logic_vector(0 downto 0);
signal posInf_uid86_fpExpETest_b : std_logic_vector(0 downto 0);
signal posInf_uid86_fpExpETest_q : std_logic_vector(0 downto 0);
signal excRInf_uid87_fpExpETest_a : std_logic_vector(0 downto 0);
signal excRInf_uid87_fpExpETest_b : std_logic_vector(0 downto 0);
signal excRInf_uid87_fpExpETest_c : std_logic_vector(0 downto 0);
signal excRInf_uid87_fpExpETest_q : std_logic_vector(0 downto 0);
signal excREnc_uid89_fpExpETest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid93_fpExpETest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid93_fpExpETest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid97_fpExpETest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid97_fpExpETest_q : std_logic_vector (10 downto 0);
signal p7_uid110_constMult_q : std_logic_vector(55 downto 0);
signal p5_uid112_constMult_q : std_logic_vector(43 downto 0);
signal p3_uid114_constMult_q : std_logic_vector(31 downto 0);
signal p1_uid116_constMult_q : std_logic_vector(19 downto 0);
signal p0_uid117_constMult_q : std_logic_vector(13 downto 0);
signal lev1_a1_uid119_constMult_a : std_logic_vector(50 downto 0);
signal lev1_a1_uid119_constMult_b : std_logic_vector(50 downto 0);
signal lev1_a1_uid119_constMult_o : std_logic_vector (50 downto 0);
signal lev1_a1_uid119_constMult_q : std_logic_vector (50 downto 0);
signal lev1_a3_uid121_constMult_a : std_logic_vector(26 downto 0);
signal lev1_a3_uid121_constMult_b : std_logic_vector(26 downto 0);
signal lev1_a3_uid121_constMult_o : std_logic_vector (26 downto 0);
signal lev1_a3_uid121_constMult_q : std_logic_vector (26 downto 0);
signal lev2_a1_uid123_constMult_a : std_logic_vector(39 downto 0);
signal lev2_a1_uid123_constMult_b : std_logic_vector(39 downto 0);
signal lev2_a1_uid123_constMult_o : std_logic_vector (39 downto 0);
signal lev2_a1_uid123_constMult_q : std_logic_vector (39 downto 0);
signal lev4_a0_uid125_constMult_a : std_logic_vector(66 downto 0);
signal lev4_a0_uid125_constMult_b : std_logic_vector(66 downto 0);
signal lev4_a0_uid125_constMult_o : std_logic_vector (66 downto 0);
signal lev4_a0_uid125_constMult_q : std_logic_vector (65 downto 0);
signal rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal p1_uid180_constMult_q : std_logic_vector(74 downto 0);
signal p0_uid181_constMult_q : std_logic_vector(68 downto 0);
signal lev2_a0_uid183_constMult_a : std_logic_vector(79 downto 0);
signal lev2_a0_uid183_constMult_b : std_logic_vector(79 downto 0);
signal lev2_a0_uid183_constMult_o : std_logic_vector (79 downto 0);
signal lev2_a0_uid183_constMult_q : std_logic_vector (78 downto 0);
signal rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal ts3_uid265_exp10PolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid265_exp10PolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid265_exp10PolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid265_exp10PolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid271_exp10PolyEval_a : std_logic_vector(53 downto 0);
signal ts4_uid271_exp10PolyEval_b : std_logic_vector(53 downto 0);
signal ts4_uid271_exp10PolyEval_o : std_logic_vector (53 downto 0);
signal ts4_uid271_exp10PolyEval_q : std_logic_vector (53 downto 0);
signal ts5_uid277_exp10PolyEval_a : std_logic_vector(61 downto 0);
signal ts5_uid277_exp10PolyEval_b : std_logic_vector(61 downto 0);
signal ts5_uid277_exp10PolyEval_o : std_logic_vector (61 downto 0);
signal ts5_uid277_exp10PolyEval_q : std_logic_vector (61 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal os_uid236_exp10TabGen_q : std_logic_vector (57 downto 0);
signal os_uid239_exp10TabGen_q : std_logic_vector (50 downto 0);
signal os_uid242_exp10TabGen_q : std_logic_vector (42 downto 0);
signal cIncludingRoundingBit_uid264_exp10PolyEval_q : std_logic_vector (44 downto 0);
signal cIncludingRoundingBit_uid270_exp10PolyEval_q : std_logic_vector (52 downto 0);
signal cIncludingRoundingBit_uid276_exp10PolyEval_q : std_logic_vector (60 downto 0);
signal prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_in : std_logic_vector (31 downto 0);
signal prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_b : std_logic_vector (16 downto 0);
signal prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_in : std_logic_vector (51 downto 0);
signal prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_b : std_logic_vector (27 downto 0);
signal TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q : std_logic_vector (59 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_b : std_logic_vector (29 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_b : std_logic_vector (53 downto 0);
signal rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal yPPolyEval_uid65_fpExpETest_in : std_logic_vector (47 downto 0);
signal yPPolyEval_uid65_fpExpETest_b : std_logic_vector (47 downto 0);
signal xTop27Bits_uid303_pT4_uid268_exp10PolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid303_pT4_uid268_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_a : std_logic_vector(2 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_b : std_logic_vector(2 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_q : std_logic_vector(0 downto 0);
signal concExc_uid88_fpExpETest_q : std_logic_vector (2 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_a : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_b : std_logic_vector(0 downto 0);
signal ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid261_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal yT3_uid261_exp10PolyEval_b : std_logic_vector (34 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid267_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal yT4_uid267_exp10PolyEval_b : std_logic_vector (42 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_uid32_fpExpETest_q : std_logic_vector (52 downto 0);
signal InvExpXIsZero_uid29_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpExpETest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpExpETest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpExpETest_q : std_logic_vector(0 downto 0);
signal expOvfInitial_uid41_fpExpETest_in : std_logic_vector (11 downto 0);
signal expOvfInitial_uid41_fpExpETest_b : std_logic_vector (0 downto 0);
signal shiftValuePreSatRed_uid43_fpExpETest_in : std_logic_vector (6 downto 0);
signal shiftValuePreSatRed_uid43_fpExpETest_b : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (6 downto 0);
signal rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (0 downto 0);
signal fxpInPreAlign_uid51_fpExpETest_in : std_logic_vector (65 downto 0);
signal fxpInPreAlign_uid51_fpExpETest_b : std_logic_vector (65 downto 0);
signal YExt75_uid59_fpExpETest_in : std_logic_vector (75 downto 0);
signal YExt75_uid59_fpExpETest_b : std_logic_vector (0 downto 0);
signal yRed_uid61_fpExpETest_in : std_logic_vector (60 downto 0);
signal yRed_uid61_fpExpETest_b : std_logic_vector (54 downto 0);
signal addr_uid64_fpExpETest_in : std_logic_vector (54 downto 0);
signal addr_uid64_fpExpETest_b : std_logic_vector (6 downto 0);
signal expR_uid75_fpExpETest_in : std_logic_vector (10 downto 0);
signal expR_uid75_fpExpETest_b : std_logic_vector (10 downto 0);
signal RExpE_uid98_fpExpETest_q : std_logic_vector (63 downto 0);
signal sR_uid126_constMult_in : std_logic_vector (61 downto 0);
signal sR_uid126_constMult_b : std_logic_vector (57 downto 0);
signal RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (60 downto 0);
signal RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (52 downto 0);
signal RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (44 downto 0);
signal sR_uid184_constMult_in : std_logic_vector (76 downto 0);
signal sR_uid184_constMult_b : std_logic_vector (74 downto 0);
signal RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (57 downto 0);
signal RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (49 downto 0);
signal RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (41 downto 0);
signal s3_uid266_exp10PolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid266_exp10PolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid272_exp10PolyEval_in : std_logic_vector (53 downto 0);
signal s4_uid272_exp10PolyEval_b : std_logic_vector (52 downto 0);
signal s5_uid278_exp10PolyEval_in : std_logic_vector (61 downto 0);
signal s5_uid278_exp10PolyEval_b : std_logic_vector (60 downto 0);
signal lowRangeB_uid251_exp10PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid251_exp10PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid252_exp10PolyEval_in : std_logic_vector (16 downto 0);
signal highBBits_uid252_exp10PolyEval_b : std_logic_vector (15 downto 0);
signal lowRangeB_uid257_exp10PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid257_exp10PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid258_exp10PolyEval_in : std_logic_vector (27 downto 0);
signal highBBits_uid258_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal lowRangeB_uid298_pT3_uid262_exp10PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid298_pT3_uid262_exp10PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid299_pT3_uid262_exp10PolyEval_in : std_logic_vector (29 downto 0);
signal highBBits_uid299_pT3_uid262_exp10PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid313_pT4_uid268_exp10PolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid313_pT4_uid268_exp10PolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid314_pT4_uid268_exp10PolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid314_pT4_uid268_exp10PolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid334_pT5_uid274_exp10PolyEval_in : std_logic_vector (18 downto 0);
signal lowRangeB_uid334_pT5_uid274_exp10PolyEval_b : std_logic_vector (18 downto 0);
signal highBBits_uid335_pT5_uid274_exp10PolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid335_pT5_uid274_exp10PolyEval_b : std_logic_vector (34 downto 0);
signal RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (66 downto 0);
signal RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (64 downto 0);
signal RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (62 downto 0);
signal RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (67 downto 0);
signal RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (63 downto 0);
signal RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (61 downto 0);
signal RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (59 downto 0);
signal RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (64 downto 0);
signal yT1_uid249_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal yT1_uid249_exp10PolyEval_b : std_logic_vector (15 downto 0);
signal yT2_uid255_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal yT2_uid255_exp10PolyEval_b : std_logic_vector (24 downto 0);
signal xTop27Bits_uid318_pT5_uid274_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal xBottomBits_uid322_pT5_uid274_exp10PolyEval_in : std_logic_vector (20 downto 0);
signal xBottomBits_uid322_pT5_uid274_exp10PolyEval_b : std_logic_vector (20 downto 0);
signal xTop26Bits_uid323_pT5_uid274_exp10PolyEval_in : std_logic_vector (47 downto 0);
signal xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0W_uid331_pT5_uid274_exp10PolyEval_in : std_logic_vector (20 downto 0);
signal sSM0W_uid331_pT5_uid274_exp10PolyEval_b : std_logic_vector (2 downto 0);
signal xTop27Bits_uid286_pT3_uid262_exp10PolyEval_in : std_logic_vector (34 downto 0);
signal xTop27Bits_uid286_pT3_uid262_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid289_pT3_uid262_exp10PolyEval_in : std_logic_vector (34 downto 0);
signal xTop18Bits_uid289_pT3_uid262_exp10PolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid291_pT3_uid262_exp10PolyEval_in : std_logic_vector (7 downto 0);
signal xBottomBits_uid291_pT3_uid262_exp10PolyEval_b : std_logic_vector (7 downto 0);
signal xBottomBits_uid307_pT4_uid268_exp10PolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid307_pT4_uid268_exp10PolyEval_b : std_logic_vector (15 downto 0);
signal oFracX_uid33_fpExpETest_q : std_logic_vector (53 downto 0);
signal exc_N_uid26_fpExpETest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpExpETest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpExpETest_q : std_logic_vector(0 downto 0);
signal msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (0 downto 0);
signal X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (33 downto 0);
signal X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_in : std_logic_vector (65 downto 0);
signal X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector (1 downto 0);
signal oFracXZwE_uid39_fpExpETest_q : std_logic_vector (68 downto 0);
signal yTop27Bits_uid304_pT4_uid268_exp10PolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid306_pT4_uid268_exp10PolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid306_pT4_uid268_exp10PolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid319_pT5_uid274_exp10PolyEval_in : std_logic_vector (52 downto 0);
signal yTop27Bits_uid319_pT5_uid274_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid321_pT5_uid274_exp10PolyEval_in : std_logic_vector (25 downto 0);
signal yBottomBits_uid321_pT5_uid274_exp10PolyEval_b : std_logic_vector (25 downto 0);
signal sSM0H_uid330_pT5_uid274_exp10PolyEval_in : std_logic_vector (25 downto 0);
signal sSM0H_uid330_pT5_uid274_exp10PolyEval_b : std_logic_vector (2 downto 0);
signal peOR_uid67_fpExpETest_in : std_logic_vector (57 downto 0);
signal peOR_uid67_fpExpETest_b : std_logic_vector (52 downto 0);
signal peORExpInc_uid68_fpExpETest_in : std_logic_vector (58 downto 0);
signal peORExpInc_uid68_fpExpETest_b : std_logic_vector (0 downto 0);
signal sumAHighB_uid253_exp10PolyEval_a : std_logic_vector(25 downto 0);
signal sumAHighB_uid253_exp10PolyEval_b : std_logic_vector(25 downto 0);
signal sumAHighB_uid253_exp10PolyEval_o : std_logic_vector (25 downto 0);
signal sumAHighB_uid253_exp10PolyEval_q : std_logic_vector (25 downto 0);
signal sumAHighB_uid259_exp10PolyEval_a : std_logic_vector(35 downto 0);
signal sumAHighB_uid259_exp10PolyEval_b : std_logic_vector(35 downto 0);
signal sumAHighB_uid259_exp10PolyEval_o : std_logic_vector (35 downto 0);
signal sumAHighB_uid259_exp10PolyEval_q : std_logic_vector (35 downto 0);
signal sumAHighB_uid300_pT3_uid262_exp10PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid300_pT3_uid262_exp10PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid300_pT3_uid262_exp10PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid300_pT3_uid262_exp10PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid315_pT4_uid268_exp10PolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid315_pT4_uid268_exp10PolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid315_pT4_uid268_exp10PolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid315_pT4_uid268_exp10PolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid336_pT5_uid274_exp10PolyEval_a : std_logic_vector(60 downto 0);
signal sumAHighB_uid336_pT5_uid274_exp10PolyEval_b : std_logic_vector(60 downto 0);
signal sumAHighB_uid336_pT5_uid274_exp10PolyEval_o : std_logic_vector (60 downto 0);
signal sumAHighB_uid336_pT5_uid274_exp10PolyEval_q : std_logic_vector (60 downto 0);
signal rightShiftStage3Idx1_uid172_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_q : std_logic_vector (25 downto 0);
signal onesCmpFxpInX_uid34_fpExpETest_a : std_logic_vector(53 downto 0);
signal onesCmpFxpInX_uid34_fpExpETest_b : std_logic_vector(53 downto 0);
signal onesCmpFxpInX_uid34_fpExpETest_q : std_logic_vector(53 downto 0);
signal InvExc_N_uid27_fpExpETest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpExpETest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal msbx_uid128_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (0 downto 0);
signal X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (36 downto 0);
signal X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_in : std_logic_vector (68 downto 0);
signal X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector (4 downto 0);
signal fracR_uid71_fpExpETest_in : std_logic_vector (51 downto 0);
signal fracR_uid71_fpExpETest_b : std_logic_vector (51 downto 0);
signal s1_uid251_uid254_exp10PolyEval_q : std_logic_vector (26 downto 0);
signal s2_uid257_uid260_exp10PolyEval_q : std_logic_vector (36 downto 0);
signal add0_uid298_uid301_pT3_uid262_exp10PolyEval_q : std_logic_vector (55 downto 0);
signal add0_uid313_uid316_pT4_uid268_exp10PolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid334_uid337_pT5_uid274_exp10PolyEval_q : std_logic_vector (79 downto 0);
signal rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_s : std_logic_vector (0 downto 0);
signal rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_q : std_logic_vector (65 downto 0);
signal fxpInExtX_uid35_fpExpETest_a : std_logic_vector(55 downto 0);
signal fxpInExtX_uid35_fpExpETest_b : std_logic_vector(55 downto 0);
signal fxpInExtX_uid35_fpExpETest_o : std_logic_vector (55 downto 0);
signal fxpInExtX_uid35_fpExpETest_q : std_logic_vector (54 downto 0);
signal rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(31 downto 0);
signal rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_a : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_b : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector(63 downto 0);
signal rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_q : std_logic_vector (68 downto 0);
signal yTop27Bits_uid287_pT3_uid262_exp10PolyEval_in : std_logic_vector (36 downto 0);
signal yTop27Bits_uid287_pT3_uid262_exp10PolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid290_pT3_uid262_exp10PolyEval_in : std_logic_vector (9 downto 0);
signal yBottomBits_uid290_pT3_uid262_exp10PolyEval_b : std_logic_vector (9 downto 0);
signal yTop18Bits_uid292_pT3_uid262_exp10PolyEval_in : std_logic_vector (36 downto 0);
signal yTop18Bits_uid292_pT3_uid262_exp10PolyEval_b : std_logic_vector (17 downto 0);
signal R_uid302_pT3_uid262_exp10PolyEval_in : std_logic_vector (54 downto 0);
signal R_uid302_pT3_uid262_exp10PolyEval_b : std_logic_vector (36 downto 0);
signal R_uid317_pT4_uid268_exp10PolyEval_in : std_logic_vector (71 downto 0);
signal R_uid317_pT4_uid268_exp10PolyEval_b : std_logic_vector (45 downto 0);
signal R_uid338_pT5_uid274_exp10PolyEval_in : std_logic_vector (78 downto 0);
signal R_uid338_pT5_uid274_exp10PolyEval_b : std_logic_vector (54 downto 0);
signal ePreRnd_uid46_fpExpETest_in : std_logic_vector (68 downto 0);
signal ePreRnd_uid46_fpExpETest_b : std_logic_vector (13 downto 0);
signal pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_q : std_logic_vector (73 downto 0);
signal fxpInPreAlign_uid36_fpExpETest_in : std_logic_vector (53 downto 0);
signal fxpInPreAlign_uid36_fpExpETest_b : std_logic_vector (53 downto 0);
signal spad_yBottomBits_uid290_uid293_pT3_uid262_exp10PolyEval_q : std_logic_vector (10 downto 0);
signal xv0_uid176_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid176_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid177_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid177_constMult_b : std_logic_vector (5 downto 0);
signal xv2_uid178_constMult_in : std_logic_vector (13 downto 0);
signal xv2_uid178_constMult_b : std_logic_vector (1 downto 0);
signal xv0_uid100_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid100_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid101_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid101_constMult_b : std_logic_vector (5 downto 0);
signal xv2_uid102_constMult_in : std_logic_vector (17 downto 0);
signal xv2_uid102_constMult_b : std_logic_vector (5 downto 0);
signal xv3_uid103_constMult_in : std_logic_vector (23 downto 0);
signal xv3_uid103_constMult_b : std_logic_vector (5 downto 0);
signal xv4_uid104_constMult_in : std_logic_vector (29 downto 0);
signal xv4_uid104_constMult_b : std_logic_vector (5 downto 0);
signal xv5_uid105_constMult_in : std_logic_vector (35 downto 0);
signal xv5_uid105_constMult_b : std_logic_vector (5 downto 0);
signal xv6_uid106_constMult_in : std_logic_vector (41 downto 0);
signal xv6_uid106_constMult_b : std_logic_vector (5 downto 0);
signal xv7_uid107_constMult_in : std_logic_vector (47 downto 0);
signal xv7_uid107_constMult_b : std_logic_vector (5 downto 0);
signal xv8_uid108_constMult_in : std_logic_vector (53 downto 0);
signal xv8_uid108_constMult_b : std_logic_vector (5 downto 0);
signal pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_q : std_logic_vector (17 downto 0);
begin
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid15_fpExpETest(CONSTANT,14)
cstAllOWE_uid15_fpExpETest_q <= "11111111111";
--zY_uid60_fpExpETest(CONSTANT,59)
zY_uid60_fpExpETest_q <= "0000000000000000000000000000000000000000000000000000000";
--signX_uid7_fpExpETest(BITSELECT,6)@0
signX_uid7_fpExpETest_in <= a;
signX_uid7_fpExpETest_b <= signX_uid7_fpExpETest_in(63 downto 63);
--frac_uid22_fpExpETest(BITSELECT,21)@0
frac_uid22_fpExpETest_in <= a(51 downto 0);
frac_uid22_fpExpETest_b <= frac_uid22_fpExpETest_in(51 downto 0);
--oFracX_uid32_uid32_fpExpETest(BITJOIN,31)@0
oFracX_uid32_uid32_fpExpETest_q <= VCC_q & frac_uid22_fpExpETest_b;
--oFracX_uid33_fpExpETest(BITJOIN,32)@0
oFracX_uid33_fpExpETest_q <= GND_q & oFracX_uid32_uid32_fpExpETest_q;
--onesCmpFxpInX_uid34_fpExpETest(LOGICAL,33)@0
onesCmpFxpInX_uid34_fpExpETest_a <= oFracX_uid33_fpExpETest_q;
onesCmpFxpInX_uid34_fpExpETest_b <= STD_LOGIC_VECTOR((53 downto 1 => signX_uid7_fpExpETest_b(0)) & signX_uid7_fpExpETest_b);
onesCmpFxpInX_uid34_fpExpETest_q <= onesCmpFxpInX_uid34_fpExpETest_a xor onesCmpFxpInX_uid34_fpExpETest_b;
--fxpInExtX_uid35_fpExpETest(ADD,34)@0
fxpInExtX_uid35_fpExpETest_a <= STD_LOGIC_VECTOR((55 downto 54 => onesCmpFxpInX_uid34_fpExpETest_q(53)) & onesCmpFxpInX_uid34_fpExpETest_q);
fxpInExtX_uid35_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000000000000000000000000000" & signX_uid7_fpExpETest_b);
fxpInExtX_uid35_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExtX_uid35_fpExpETest_a) + SIGNED(fxpInExtX_uid35_fpExpETest_b));
fxpInExtX_uid35_fpExpETest_q <= fxpInExtX_uid35_fpExpETest_o(54 downto 0);
--fxpInPreAlign_uid36_fpExpETest(BITSELECT,35)@0
fxpInPreAlign_uid36_fpExpETest_in <= fxpInExtX_uid35_fpExpETest_q(53 downto 0);
fxpInPreAlign_uid36_fpExpETest_b <= fxpInPreAlign_uid36_fpExpETest_in(53 downto 0);
--xv0_uid100_constMult(BITSELECT,99)@0
xv0_uid100_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(5 downto 0);
xv0_uid100_constMult_b <= xv0_uid100_constMult_in(5 downto 0);
--reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0(REG,350)@0
reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q <= xv0_uid100_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a(DELAY,529)@1
ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 4 )
PORT MAP ( xin => reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q, xout => ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid117_constMult(LOOKUP,116)@5
p0_uid117_constMult: PROCESS (ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid100_constMult_0_to_p0_uid117_constMult_0_q_to_p0_uid117_constMult_a_q) IS
WHEN "000000" => p0_uid117_constMult_q <= "00000000000000";
WHEN "000001" => p0_uid117_constMult_q <= "00000010111001";
WHEN "000010" => p0_uid117_constMult_q <= "00000101110001";
WHEN "000011" => p0_uid117_constMult_q <= "00001000101010";
WHEN "000100" => p0_uid117_constMult_q <= "00001011100011";
WHEN "000101" => p0_uid117_constMult_q <= "00001110011011";
WHEN "000110" => p0_uid117_constMult_q <= "00010001010100";
WHEN "000111" => p0_uid117_constMult_q <= "00010100001101";
WHEN "001000" => p0_uid117_constMult_q <= "00010111000101";
WHEN "001001" => p0_uid117_constMult_q <= "00011001111110";
WHEN "001010" => p0_uid117_constMult_q <= "00011100110111";
WHEN "001011" => p0_uid117_constMult_q <= "00011111101111";
WHEN "001100" => p0_uid117_constMult_q <= "00100010101000";
WHEN "001101" => p0_uid117_constMult_q <= "00100101100001";
WHEN "001110" => p0_uid117_constMult_q <= "00101000011001";
WHEN "001111" => p0_uid117_constMult_q <= "00101011010010";
WHEN "010000" => p0_uid117_constMult_q <= "00101110001011";
WHEN "010001" => p0_uid117_constMult_q <= "00110001000011";
WHEN "010010" => p0_uid117_constMult_q <= "00110011111100";
WHEN "010011" => p0_uid117_constMult_q <= "00110110110101";
WHEN "010100" => p0_uid117_constMult_q <= "00111001101101";
WHEN "010101" => p0_uid117_constMult_q <= "00111100100110";
WHEN "010110" => p0_uid117_constMult_q <= "00111111011111";
WHEN "010111" => p0_uid117_constMult_q <= "01000010010111";
WHEN "011000" => p0_uid117_constMult_q <= "01000101010000";
WHEN "011001" => p0_uid117_constMult_q <= "01001000001001";
WHEN "011010" => p0_uid117_constMult_q <= "01001011000001";
WHEN "011011" => p0_uid117_constMult_q <= "01001101111010";
WHEN "011100" => p0_uid117_constMult_q <= "01010000110011";
WHEN "011101" => p0_uid117_constMult_q <= "01010011101011";
WHEN "011110" => p0_uid117_constMult_q <= "01010110100100";
WHEN "011111" => p0_uid117_constMult_q <= "01011001011101";
WHEN "100000" => p0_uid117_constMult_q <= "01011100010101";
WHEN "100001" => p0_uid117_constMult_q <= "01011111001110";
WHEN "100010" => p0_uid117_constMult_q <= "01100010000111";
WHEN "100011" => p0_uid117_constMult_q <= "01100100111111";
WHEN "100100" => p0_uid117_constMult_q <= "01100111111000";
WHEN "100101" => p0_uid117_constMult_q <= "01101010110001";
WHEN "100110" => p0_uid117_constMult_q <= "01101101101001";
WHEN "100111" => p0_uid117_constMult_q <= "01110000100010";
WHEN "101000" => p0_uid117_constMult_q <= "01110011011011";
WHEN "101001" => p0_uid117_constMult_q <= "01110110010011";
WHEN "101010" => p0_uid117_constMult_q <= "01111001001100";
WHEN "101011" => p0_uid117_constMult_q <= "01111100000101";
WHEN "101100" => p0_uid117_constMult_q <= "01111110111101";
WHEN "101101" => p0_uid117_constMult_q <= "10000001110110";
WHEN "101110" => p0_uid117_constMult_q <= "10000100101111";
WHEN "101111" => p0_uid117_constMult_q <= "10000111100111";
WHEN "110000" => p0_uid117_constMult_q <= "10001010100000";
WHEN "110001" => p0_uid117_constMult_q <= "10001101011001";
WHEN "110010" => p0_uid117_constMult_q <= "10010000010001";
WHEN "110011" => p0_uid117_constMult_q <= "10010011001010";
WHEN "110100" => p0_uid117_constMult_q <= "10010110000011";
WHEN "110101" => p0_uid117_constMult_q <= "10011000111011";
WHEN "110110" => p0_uid117_constMult_q <= "10011011110100";
WHEN "110111" => p0_uid117_constMult_q <= "10011110101101";
WHEN "111000" => p0_uid117_constMult_q <= "10100001100101";
WHEN "111001" => p0_uid117_constMult_q <= "10100100011110";
WHEN "111010" => p0_uid117_constMult_q <= "10100111010111";
WHEN "111011" => p0_uid117_constMult_q <= "10101010001111";
WHEN "111100" => p0_uid117_constMult_q <= "10101101001000";
WHEN "111101" => p0_uid117_constMult_q <= "10110000000001";
WHEN "111110" => p0_uid117_constMult_q <= "10110010111001";
WHEN "111111" => p0_uid117_constMult_q <= "10110101110010";
WHEN OTHERS =>
p0_uid117_constMult_q <= "00000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid101_constMult(BITSELECT,100)@0
xv1_uid101_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(11 downto 0);
xv1_uid101_constMult_b <= xv1_uid101_constMult_in(11 downto 6);
--ld_xv1_uid101_constMult_b_to_reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_a(DELAY,803)@0
ld_xv1_uid101_constMult_b_to_reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 3 )
PORT MAP ( xin => xv1_uid101_constMult_b, xout => ld_xv1_uid101_constMult_b_to_reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0(REG,349)@3
reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_q <= ld_xv1_uid101_constMult_b_to_reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p1_uid116_constMult(LOOKUP,115)@4
p1_uid116_constMult: PROCESS (reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv1_uid101_constMult_0_to_p1_uid116_constMult_0_q) IS
WHEN "000000" => p1_uid116_constMult_q <= "00000000000000000000";
WHEN "000001" => p1_uid116_constMult_q <= "00000010111000101011";
WHEN "000010" => p1_uid116_constMult_q <= "00000101110001010101";
WHEN "000011" => p1_uid116_constMult_q <= "00001000101010000000";
WHEN "000100" => p1_uid116_constMult_q <= "00001011100010101010";
WHEN "000101" => p1_uid116_constMult_q <= "00001110011011010101";
WHEN "000110" => p1_uid116_constMult_q <= "00010001010011111111";
WHEN "000111" => p1_uid116_constMult_q <= "00010100001100101010";
WHEN "001000" => p1_uid116_constMult_q <= "00010111000101010100";
WHEN "001001" => p1_uid116_constMult_q <= "00011001111101111111";
WHEN "001010" => p1_uid116_constMult_q <= "00011100110110101010";
WHEN "001011" => p1_uid116_constMult_q <= "00011111101111010100";
WHEN "001100" => p1_uid116_constMult_q <= "00100010100111111111";
WHEN "001101" => p1_uid116_constMult_q <= "00100101100000101001";
WHEN "001110" => p1_uid116_constMult_q <= "00101000011001010100";
WHEN "001111" => p1_uid116_constMult_q <= "00101011010001111110";
WHEN "010000" => p1_uid116_constMult_q <= "00101110001010101001";
WHEN "010001" => p1_uid116_constMult_q <= "00110001000011010011";
WHEN "010010" => p1_uid116_constMult_q <= "00110011111011111110";
WHEN "010011" => p1_uid116_constMult_q <= "00110110110100101001";
WHEN "010100" => p1_uid116_constMult_q <= "00111001101101010011";
WHEN "010101" => p1_uid116_constMult_q <= "00111100100101111110";
WHEN "010110" => p1_uid116_constMult_q <= "00111111011110101000";
WHEN "010111" => p1_uid116_constMult_q <= "01000010010111010011";
WHEN "011000" => p1_uid116_constMult_q <= "01000101001111111101";
WHEN "011001" => p1_uid116_constMult_q <= "01001000001000101000";
WHEN "011010" => p1_uid116_constMult_q <= "01001011000001010011";
WHEN "011011" => p1_uid116_constMult_q <= "01001101111001111101";
WHEN "011100" => p1_uid116_constMult_q <= "01010000110010101000";
WHEN "011101" => p1_uid116_constMult_q <= "01010011101011010010";
WHEN "011110" => p1_uid116_constMult_q <= "01010110100011111101";
WHEN "011111" => p1_uid116_constMult_q <= "01011001011100100111";
WHEN "100000" => p1_uid116_constMult_q <= "01011100010101010010";
WHEN "100001" => p1_uid116_constMult_q <= "01011111001101111100";
WHEN "100010" => p1_uid116_constMult_q <= "01100010000110100111";
WHEN "100011" => p1_uid116_constMult_q <= "01100100111111010010";
WHEN "100100" => p1_uid116_constMult_q <= "01100111110111111100";
WHEN "100101" => p1_uid116_constMult_q <= "01101010110000100111";
WHEN "100110" => p1_uid116_constMult_q <= "01101101101001010001";
WHEN "100111" => p1_uid116_constMult_q <= "01110000100001111100";
WHEN "101000" => p1_uid116_constMult_q <= "01110011011010100110";
WHEN "101001" => p1_uid116_constMult_q <= "01110110010011010001";
WHEN "101010" => p1_uid116_constMult_q <= "01111001001011111011";
WHEN "101011" => p1_uid116_constMult_q <= "01111100000100100110";
WHEN "101100" => p1_uid116_constMult_q <= "01111110111101010001";
WHEN "101101" => p1_uid116_constMult_q <= "10000001110101111011";
WHEN "101110" => p1_uid116_constMult_q <= "10000100101110100110";
WHEN "101111" => p1_uid116_constMult_q <= "10000111100111010000";
WHEN "110000" => p1_uid116_constMult_q <= "10001010011111111011";
WHEN "110001" => p1_uid116_constMult_q <= "10001101011000100101";
WHEN "110010" => p1_uid116_constMult_q <= "10010000010001010000";
WHEN "110011" => p1_uid116_constMult_q <= "10010011001001111010";
WHEN "110100" => p1_uid116_constMult_q <= "10010110000010100101";
WHEN "110101" => p1_uid116_constMult_q <= "10011000111011010000";
WHEN "110110" => p1_uid116_constMult_q <= "10011011110011111010";
WHEN "110111" => p1_uid116_constMult_q <= "10011110101100100101";
WHEN "111000" => p1_uid116_constMult_q <= "10100001100101001111";
WHEN "111001" => p1_uid116_constMult_q <= "10100100011101111010";
WHEN "111010" => p1_uid116_constMult_q <= "10100111010110100100";
WHEN "111011" => p1_uid116_constMult_q <= "10101010001111001111";
WHEN "111100" => p1_uid116_constMult_q <= "10101101000111111001";
WHEN "111101" => p1_uid116_constMult_q <= "10110000000000100100";
WHEN "111110" => p1_uid116_constMult_q <= "10110010111001001111";
WHEN "111111" => p1_uid116_constMult_q <= "10110101110001111001";
WHEN OTHERS =>
p1_uid116_constMult_q <= "00000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv2_uid102_constMult(BITSELECT,101)@0
xv2_uid102_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(17 downto 0);
xv2_uid102_constMult_b <= xv2_uid102_constMult_in(17 downto 12);
--ld_xv2_uid102_constMult_b_to_reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_a(DELAY,802)@0
ld_xv2_uid102_constMult_b_to_reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 2 )
PORT MAP ( xin => xv2_uid102_constMult_b, xout => ld_xv2_uid102_constMult_b_to_reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0(REG,348)@2
reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_q <= ld_xv2_uid102_constMult_b_to_reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p2_uid115_constMult(LOOKUP,114)@3
p2_uid115_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p2_uid115_constMult_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv2_uid102_constMult_0_to_p2_uid115_constMult_0_q) IS
WHEN "000000" => p2_uid115_constMult_q <= "00000000000000000000000000";
WHEN "000001" => p2_uid115_constMult_q <= "00000010111000101010100100";
WHEN "000010" => p2_uid115_constMult_q <= "00000101110001010101000111";
WHEN "000011" => p2_uid115_constMult_q <= "00001000101001111111101011";
WHEN "000100" => p2_uid115_constMult_q <= "00001011100010101010001111";
WHEN "000101" => p2_uid115_constMult_q <= "00001110011011010100110010";
WHEN "000110" => p2_uid115_constMult_q <= "00010001010011111111010110";
WHEN "000111" => p2_uid115_constMult_q <= "00010100001100101001111010";
WHEN "001000" => p2_uid115_constMult_q <= "00010111000101010100011110";
WHEN "001001" => p2_uid115_constMult_q <= "00011001111101111111000001";
WHEN "001010" => p2_uid115_constMult_q <= "00011100110110101001100101";
WHEN "001011" => p2_uid115_constMult_q <= "00011111101111010100001001";
WHEN "001100" => p2_uid115_constMult_q <= "00100010100111111110101100";
WHEN "001101" => p2_uid115_constMult_q <= "00100101100000101001010000";
WHEN "001110" => p2_uid115_constMult_q <= "00101000011001010011110100";
WHEN "001111" => p2_uid115_constMult_q <= "00101011010001111110010111";
WHEN "010000" => p2_uid115_constMult_q <= "00101110001010101000111011";
WHEN "010001" => p2_uid115_constMult_q <= "00110001000011010011011111";
WHEN "010010" => p2_uid115_constMult_q <= "00110011111011111110000011";
WHEN "010011" => p2_uid115_constMult_q <= "00110110110100101000100110";
WHEN "010100" => p2_uid115_constMult_q <= "00111001101101010011001010";
WHEN "010101" => p2_uid115_constMult_q <= "00111100100101111101101110";
WHEN "010110" => p2_uid115_constMult_q <= "00111111011110101000010001";
WHEN "010111" => p2_uid115_constMult_q <= "01000010010111010010110101";
WHEN "011000" => p2_uid115_constMult_q <= "01000101001111111101011001";
WHEN "011001" => p2_uid115_constMult_q <= "01001000001000100111111100";
WHEN "011010" => p2_uid115_constMult_q <= "01001011000001010010100000";
WHEN "011011" => p2_uid115_constMult_q <= "01001101111001111101000100";
WHEN "011100" => p2_uid115_constMult_q <= "01010000110010100111101000";
WHEN "011101" => p2_uid115_constMult_q <= "01010011101011010010001011";
WHEN "011110" => p2_uid115_constMult_q <= "01010110100011111100101111";
WHEN "011111" => p2_uid115_constMult_q <= "01011001011100100111010011";
WHEN "100000" => p2_uid115_constMult_q <= "01011100010101010001110110";
WHEN "100001" => p2_uid115_constMult_q <= "01011111001101111100011010";
WHEN "100010" => p2_uid115_constMult_q <= "01100010000110100110111110";
WHEN "100011" => p2_uid115_constMult_q <= "01100100111111010001100001";
WHEN "100100" => p2_uid115_constMult_q <= "01100111110111111100000101";
WHEN "100101" => p2_uid115_constMult_q <= "01101010110000100110101001";
WHEN "100110" => p2_uid115_constMult_q <= "01101101101001010001001101";
WHEN "100111" => p2_uid115_constMult_q <= "01110000100001111011110000";
WHEN "101000" => p2_uid115_constMult_q <= "01110011011010100110010100";
WHEN "101001" => p2_uid115_constMult_q <= "01110110010011010000111000";
WHEN "101010" => p2_uid115_constMult_q <= "01111001001011111011011011";
WHEN "101011" => p2_uid115_constMult_q <= "01111100000100100101111111";
WHEN "101100" => p2_uid115_constMult_q <= "01111110111101010000100011";
WHEN "101101" => p2_uid115_constMult_q <= "10000001110101111011000110";
WHEN "101110" => p2_uid115_constMult_q <= "10000100101110100101101010";
WHEN "101111" => p2_uid115_constMult_q <= "10000111100111010000001110";
WHEN "110000" => p2_uid115_constMult_q <= "10001010011111111010110001";
WHEN "110001" => p2_uid115_constMult_q <= "10001101011000100101010101";
WHEN "110010" => p2_uid115_constMult_q <= "10010000010001001111111001";
WHEN "110011" => p2_uid115_constMult_q <= "10010011001001111010011101";
WHEN "110100" => p2_uid115_constMult_q <= "10010110000010100101000000";
WHEN "110101" => p2_uid115_constMult_q <= "10011000111011001111100100";
WHEN "110110" => p2_uid115_constMult_q <= "10011011110011111010001000";
WHEN "110111" => p2_uid115_constMult_q <= "10011110101100100100101011";
WHEN "111000" => p2_uid115_constMult_q <= "10100001100101001111001111";
WHEN "111001" => p2_uid115_constMult_q <= "10100100011101111001110011";
WHEN "111010" => p2_uid115_constMult_q <= "10100111010110100100010110";
WHEN "111011" => p2_uid115_constMult_q <= "10101010001111001110111010";
WHEN "111100" => p2_uid115_constMult_q <= "10101101000111111001011110";
WHEN "111101" => p2_uid115_constMult_q <= "10110000000000100100000010";
WHEN "111110" => p2_uid115_constMult_q <= "10110010111001001110100101";
WHEN "111111" => p2_uid115_constMult_q <= "10110101110001111001001001";
WHEN OTHERS =>
p2_uid115_constMult_q <= "00000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a3_uid121_constMult(ADD,120)@4
lev1_a3_uid121_constMult_a <= STD_LOGIC_VECTOR("0" & p2_uid115_constMult_q);
lev1_a3_uid121_constMult_b <= STD_LOGIC_VECTOR("0000000" & p1_uid116_constMult_q);
lev1_a3_uid121_constMult_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a3_uid121_constMult_a) + UNSIGNED(lev1_a3_uid121_constMult_b));
lev1_a3_uid121_constMult_q <= lev1_a3_uid121_constMult_o(26 downto 0);
--xv3_uid103_constMult(BITSELECT,102)@0
xv3_uid103_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(23 downto 0);
xv3_uid103_constMult_b <= xv3_uid103_constMult_in(23 downto 18);
--reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0(REG,347)@0
reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q <= xv3_uid103_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a(DELAY,526)@1
ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 2 )
PORT MAP ( xin => reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q, xout => ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p3_uid114_constMult(LOOKUP,113)@3
p3_uid114_constMult: PROCESS (ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv3_uid103_constMult_0_to_p3_uid114_constMult_0_q_to_p3_uid114_constMult_a_q) IS
WHEN "000000" => p3_uid114_constMult_q <= "00000000000000000000000000000000";
WHEN "000001" => p3_uid114_constMult_q <= "00000010111000101010100011101101";
WHEN "000010" => p3_uid114_constMult_q <= "00000101110001010101000111011001";
WHEN "000011" => p3_uid114_constMult_q <= "00001000101001111111101011000110";
WHEN "000100" => p3_uid114_constMult_q <= "00001011100010101010001110110011";
WHEN "000101" => p3_uid114_constMult_q <= "00001110011011010100110010011111";
WHEN "000110" => p3_uid114_constMult_q <= "00010001010011111111010110001100";
WHEN "000111" => p3_uid114_constMult_q <= "00010100001100101001111001111001";
WHEN "001000" => p3_uid114_constMult_q <= "00010111000101010100011101100101";
WHEN "001001" => p3_uid114_constMult_q <= "00011001111101111111000001010010";
WHEN "001010" => p3_uid114_constMult_q <= "00011100110110101001100100111110";
WHEN "001011" => p3_uid114_constMult_q <= "00011111101111010100001000101011";
WHEN "001100" => p3_uid114_constMult_q <= "00100010100111111110101100011000";
WHEN "001101" => p3_uid114_constMult_q <= "00100101100000101001010000000100";
WHEN "001110" => p3_uid114_constMult_q <= "00101000011001010011110011110001";
WHEN "001111" => p3_uid114_constMult_q <= "00101011010001111110010111011110";
WHEN "010000" => p3_uid114_constMult_q <= "00101110001010101000111011001010";
WHEN "010001" => p3_uid114_constMult_q <= "00110001000011010011011110110111";
WHEN "010010" => p3_uid114_constMult_q <= "00110011111011111110000010100100";
WHEN "010011" => p3_uid114_constMult_q <= "00110110110100101000100110010000";
WHEN "010100" => p3_uid114_constMult_q <= "00111001101101010011001001111101";
WHEN "010101" => p3_uid114_constMult_q <= "00111100100101111101101101101010";
WHEN "010110" => p3_uid114_constMult_q <= "00111111011110101000010001010110";
WHEN "010111" => p3_uid114_constMult_q <= "01000010010111010010110101000011";
WHEN "011000" => p3_uid114_constMult_q <= "01000101001111111101011000110000";
WHEN "011001" => p3_uid114_constMult_q <= "01001000001000100111111100011100";
WHEN "011010" => p3_uid114_constMult_q <= "01001011000001010010100000001001";
WHEN "011011" => p3_uid114_constMult_q <= "01001101111001111101000011110101";
WHEN "011100" => p3_uid114_constMult_q <= "01010000110010100111100111100010";
WHEN "011101" => p3_uid114_constMult_q <= "01010011101011010010001011001111";
WHEN "011110" => p3_uid114_constMult_q <= "01010110100011111100101110111011";
WHEN "011111" => p3_uid114_constMult_q <= "01011001011100100111010010101000";
WHEN "100000" => p3_uid114_constMult_q <= "01011100010101010001110110010101";
WHEN "100001" => p3_uid114_constMult_q <= "01011111001101111100011010000001";
WHEN "100010" => p3_uid114_constMult_q <= "01100010000110100110111101101110";
WHEN "100011" => p3_uid114_constMult_q <= "01100100111111010001100001011011";
WHEN "100100" => p3_uid114_constMult_q <= "01100111110111111100000101000111";
WHEN "100101" => p3_uid114_constMult_q <= "01101010110000100110101000110100";
WHEN "100110" => p3_uid114_constMult_q <= "01101101101001010001001100100001";
WHEN "100111" => p3_uid114_constMult_q <= "01110000100001111011110000001101";
WHEN "101000" => p3_uid114_constMult_q <= "01110011011010100110010011111010";
WHEN "101001" => p3_uid114_constMult_q <= "01110110010011010000110111100110";
WHEN "101010" => p3_uid114_constMult_q <= "01111001001011111011011011010011";
WHEN "101011" => p3_uid114_constMult_q <= "01111100000100100101111111000000";
WHEN "101100" => p3_uid114_constMult_q <= "01111110111101010000100010101100";
WHEN "101101" => p3_uid114_constMult_q <= "10000001110101111011000110011001";
WHEN "101110" => p3_uid114_constMult_q <= "10000100101110100101101010000110";
WHEN "101111" => p3_uid114_constMult_q <= "10000111100111010000001101110010";
WHEN "110000" => p3_uid114_constMult_q <= "10001010011111111010110001011111";
WHEN "110001" => p3_uid114_constMult_q <= "10001101011000100101010101001100";
WHEN "110010" => p3_uid114_constMult_q <= "10010000010001001111111000111000";
WHEN "110011" => p3_uid114_constMult_q <= "10010011001001111010011100100101";
WHEN "110100" => p3_uid114_constMult_q <= "10010110000010100101000000010010";
WHEN "110101" => p3_uid114_constMult_q <= "10011000111011001111100011111110";
WHEN "110110" => p3_uid114_constMult_q <= "10011011110011111010000111101011";
WHEN "110111" => p3_uid114_constMult_q <= "10011110101100100100101011011000";
WHEN "111000" => p3_uid114_constMult_q <= "10100001100101001111001111000100";
WHEN "111001" => p3_uid114_constMult_q <= "10100100011101111001110010110001";
WHEN "111010" => p3_uid114_constMult_q <= "10100111010110100100010110011101";
WHEN "111011" => p3_uid114_constMult_q <= "10101010001111001110111010001010";
WHEN "111100" => p3_uid114_constMult_q <= "10101101000111111001011101110111";
WHEN "111101" => p3_uid114_constMult_q <= "10110000000000100100000001100011";
WHEN "111110" => p3_uid114_constMult_q <= "10110010111001001110100101010000";
WHEN "111111" => p3_uid114_constMult_q <= "10110101110001111001001000111101";
WHEN OTHERS =>
p3_uid114_constMult_q <= "00000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv4_uid104_constMult(BITSELECT,103)@0
xv4_uid104_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(29 downto 0);
xv4_uid104_constMult_b <= xv4_uid104_constMult_in(29 downto 24);
--reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0(REG,346)@0
reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q <= xv4_uid104_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q_to_p4_uid113_constMult_a(DELAY,525)@1
ld_reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q_to_p4_uid113_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q, xout => ld_reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q_to_p4_uid113_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p4_uid113_constMult(LOOKUP,112)@2
p4_uid113_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p4_uid113_constMult_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_xv4_uid104_constMult_0_to_p4_uid113_constMult_0_q_to_p4_uid113_constMult_a_q) IS
WHEN "000000" => p4_uid113_constMult_q <= "00000000000000000000000000000000000000";
WHEN "000001" => p4_uid113_constMult_q <= "00000010111000101010100011101100101001";
WHEN "000010" => p4_uid113_constMult_q <= "00000101110001010101000111011001010011";
WHEN "000011" => p4_uid113_constMult_q <= "00001000101001111111101011000101111100";
WHEN "000100" => p4_uid113_constMult_q <= "00001011100010101010001110110010100101";
WHEN "000101" => p4_uid113_constMult_q <= "00001110011011010100110010011111001111";
WHEN "000110" => p4_uid113_constMult_q <= "00010001010011111111010110001011111000";
WHEN "000111" => p4_uid113_constMult_q <= "00010100001100101001111001111000100010";
WHEN "001000" => p4_uid113_constMult_q <= "00010111000101010100011101100101001011";
WHEN "001001" => p4_uid113_constMult_q <= "00011001111101111111000001010001110100";
WHEN "001010" => p4_uid113_constMult_q <= "00011100110110101001100100111110011110";
WHEN "001011" => p4_uid113_constMult_q <= "00011111101111010100001000101011000111";
WHEN "001100" => p4_uid113_constMult_q <= "00100010100111111110101100010111110000";
WHEN "001101" => p4_uid113_constMult_q <= "00100101100000101001010000000100011010";
WHEN "001110" => p4_uid113_constMult_q <= "00101000011001010011110011110001000011";
WHEN "001111" => p4_uid113_constMult_q <= "00101011010001111110010111011101101100";
WHEN "010000" => p4_uid113_constMult_q <= "00101110001010101000111011001010010110";
WHEN "010001" => p4_uid113_constMult_q <= "00110001000011010011011110110110111111";
WHEN "010010" => p4_uid113_constMult_q <= "00110011111011111110000010100011101000";
WHEN "010011" => p4_uid113_constMult_q <= "00110110110100101000100110010000010010";
WHEN "010100" => p4_uid113_constMult_q <= "00111001101101010011001001111100111011";
WHEN "010101" => p4_uid113_constMult_q <= "00111100100101111101101101101001100101";
WHEN "010110" => p4_uid113_constMult_q <= "00111111011110101000010001010110001110";
WHEN "010111" => p4_uid113_constMult_q <= "01000010010111010010110101000010110111";
WHEN "011000" => p4_uid113_constMult_q <= "01000101001111111101011000101111100001";
WHEN "011001" => p4_uid113_constMult_q <= "01001000001000100111111100011100001010";
WHEN "011010" => p4_uid113_constMult_q <= "01001011000001010010100000001000110011";
WHEN "011011" => p4_uid113_constMult_q <= "01001101111001111101000011110101011101";
WHEN "011100" => p4_uid113_constMult_q <= "01010000110010100111100111100010000110";
WHEN "011101" => p4_uid113_constMult_q <= "01010011101011010010001011001110101111";
WHEN "011110" => p4_uid113_constMult_q <= "01010110100011111100101110111011011001";
WHEN "011111" => p4_uid113_constMult_q <= "01011001011100100111010010101000000010";
WHEN "100000" => p4_uid113_constMult_q <= "01011100010101010001110110010100101100";
WHEN "100001" => p4_uid113_constMult_q <= "01011111001101111100011010000001010101";
WHEN "100010" => p4_uid113_constMult_q <= "01100010000110100110111101101101111110";
WHEN "100011" => p4_uid113_constMult_q <= "01100100111111010001100001011010101000";
WHEN "100100" => p4_uid113_constMult_q <= "01100111110111111100000101000111010001";
WHEN "100101" => p4_uid113_constMult_q <= "01101010110000100110101000110011111010";
WHEN "100110" => p4_uid113_constMult_q <= "01101101101001010001001100100000100100";
WHEN "100111" => p4_uid113_constMult_q <= "01110000100001111011110000001101001101";
WHEN "101000" => p4_uid113_constMult_q <= "01110011011010100110010011111001110110";
WHEN "101001" => p4_uid113_constMult_q <= "01110110010011010000110111100110100000";
WHEN "101010" => p4_uid113_constMult_q <= "01111001001011111011011011010011001001";
WHEN "101011" => p4_uid113_constMult_q <= "01111100000100100101111110111111110010";
WHEN "101100" => p4_uid113_constMult_q <= "01111110111101010000100010101100011100";
WHEN "101101" => p4_uid113_constMult_q <= "10000001110101111011000110011001000101";
WHEN "101110" => p4_uid113_constMult_q <= "10000100101110100101101010000101101111";
WHEN "101111" => p4_uid113_constMult_q <= "10000111100111010000001101110010011000";
WHEN "110000" => p4_uid113_constMult_q <= "10001010011111111010110001011111000001";
WHEN "110001" => p4_uid113_constMult_q <= "10001101011000100101010101001011101011";
WHEN "110010" => p4_uid113_constMult_q <= "10010000010001001111111000111000010100";
WHEN "110011" => p4_uid113_constMult_q <= "10010011001001111010011100100100111101";
WHEN "110100" => p4_uid113_constMult_q <= "10010110000010100101000000010001100111";
WHEN "110101" => p4_uid113_constMult_q <= "10011000111011001111100011111110010000";
WHEN "110110" => p4_uid113_constMult_q <= "10011011110011111010000111101010111001";
WHEN "110111" => p4_uid113_constMult_q <= "10011110101100100100101011010111100011";
WHEN "111000" => p4_uid113_constMult_q <= "10100001100101001111001111000100001100";
WHEN "111001" => p4_uid113_constMult_q <= "10100100011101111001110010110000110110";
WHEN "111010" => p4_uid113_constMult_q <= "10100111010110100100010110011101011111";
WHEN "111011" => p4_uid113_constMult_q <= "10101010001111001110111010001010001000";
WHEN "111100" => p4_uid113_constMult_q <= "10101101000111111001011101110110110010";
WHEN "111101" => p4_uid113_constMult_q <= "10110000000000100100000001100011011011";
WHEN "111110" => p4_uid113_constMult_q <= "10110010111001001110100101010000000100";
WHEN "111111" => p4_uid113_constMult_q <= "10110101110001111001001000111100101110";
WHEN OTHERS =>
p4_uid113_constMult_q <= "00000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a2_uid120_constMult(ADD,119)@3
lev1_a2_uid120_constMult_a <= STD_LOGIC_VECTOR("0" & p4_uid113_constMult_q);
lev1_a2_uid120_constMult_b <= STD_LOGIC_VECTOR("0000000" & p3_uid114_constMult_q);
lev1_a2_uid120_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev1_a2_uid120_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev1_a2_uid120_constMult_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a2_uid120_constMult_a) + UNSIGNED(lev1_a2_uid120_constMult_b));
END IF;
END IF;
END PROCESS;
lev1_a2_uid120_constMult_q <= lev1_a2_uid120_constMult_o(38 downto 0);
--lev2_a1_uid123_constMult(ADD,122)@4
lev2_a1_uid123_constMult_a <= STD_LOGIC_VECTOR("0" & lev1_a2_uid120_constMult_q);
lev2_a1_uid123_constMult_b <= STD_LOGIC_VECTOR("0000000000000" & lev1_a3_uid121_constMult_q);
lev2_a1_uid123_constMult_o <= STD_LOGIC_VECTOR(UNSIGNED(lev2_a1_uid123_constMult_a) + UNSIGNED(lev2_a1_uid123_constMult_b));
lev2_a1_uid123_constMult_q <= lev2_a1_uid123_constMult_o(39 downto 0);
--xv5_uid105_constMult(BITSELECT,104)@0
xv5_uid105_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(35 downto 0);
xv5_uid105_constMult_b <= xv5_uid105_constMult_in(35 downto 30);
--ld_xv5_uid105_constMult_b_to_reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_a(DELAY,799)@0
ld_xv5_uid105_constMult_b_to_reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 2 )
PORT MAP ( xin => xv5_uid105_constMult_b, xout => ld_xv5_uid105_constMult_b_to_reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0(REG,345)@2
reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_q <= ld_xv5_uid105_constMult_b_to_reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p5_uid112_constMult(LOOKUP,111)@3
p5_uid112_constMult: PROCESS (reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv5_uid105_constMult_0_to_p5_uid112_constMult_0_q) IS
WHEN "000000" => p5_uid112_constMult_q <= "00000000000000000000000000000000000000000000";
WHEN "000001" => p5_uid112_constMult_q <= "00000010111000101010100011101100101001010111";
WHEN "000010" => p5_uid112_constMult_q <= "00000101110001010101000111011001010010101110";
WHEN "000011" => p5_uid112_constMult_q <= "00001000101001111111101011000101111100000101";
WHEN "000100" => p5_uid112_constMult_q <= "00001011100010101010001110110010100101011100";
WHEN "000101" => p5_uid112_constMult_q <= "00001110011011010100110010011111001110110011";
WHEN "000110" => p5_uid112_constMult_q <= "00010001010011111111010110001011111000001010";
WHEN "000111" => p5_uid112_constMult_q <= "00010100001100101001111001111000100001100001";
WHEN "001000" => p5_uid112_constMult_q <= "00010111000101010100011101100101001010111000";
WHEN "001001" => p5_uid112_constMult_q <= "00011001111101111111000001010001110100001111";
WHEN "001010" => p5_uid112_constMult_q <= "00011100110110101001100100111110011101100110";
WHEN "001011" => p5_uid112_constMult_q <= "00011111101111010100001000101011000110111101";
WHEN "001100" => p5_uid112_constMult_q <= "00100010100111111110101100010111110000010100";
WHEN "001101" => p5_uid112_constMult_q <= "00100101100000101001010000000100011001101011";
WHEN "001110" => p5_uid112_constMult_q <= "00101000011001010011110011110001000011000010";
WHEN "001111" => p5_uid112_constMult_q <= "00101011010001111110010111011101101100011001";
WHEN "010000" => p5_uid112_constMult_q <= "00101110001010101000111011001010010101110000";
WHEN "010001" => p5_uid112_constMult_q <= "00110001000011010011011110110110111111000111";
WHEN "010010" => p5_uid112_constMult_q <= "00110011111011111110000010100011101000011110";
WHEN "010011" => p5_uid112_constMult_q <= "00110110110100101000100110010000010001110101";
WHEN "010100" => p5_uid112_constMult_q <= "00111001101101010011001001111100111011001100";
WHEN "010101" => p5_uid112_constMult_q <= "00111100100101111101101101101001100100100011";
WHEN "010110" => p5_uid112_constMult_q <= "00111111011110101000010001010110001101111011";
WHEN "010111" => p5_uid112_constMult_q <= "01000010010111010010110101000010110111010010";
WHEN "011000" => p5_uid112_constMult_q <= "01000101001111111101011000101111100000101001";
WHEN "011001" => p5_uid112_constMult_q <= "01001000001000100111111100011100001010000000";
WHEN "011010" => p5_uid112_constMult_q <= "01001011000001010010100000001000110011010111";
WHEN "011011" => p5_uid112_constMult_q <= "01001101111001111101000011110101011100101110";
WHEN "011100" => p5_uid112_constMult_q <= "01010000110010100111100111100010000110000101";
WHEN "011101" => p5_uid112_constMult_q <= "01010011101011010010001011001110101111011100";
WHEN "011110" => p5_uid112_constMult_q <= "01010110100011111100101110111011011000110011";
WHEN "011111" => p5_uid112_constMult_q <= "01011001011100100111010010101000000010001010";
WHEN "100000" => p5_uid112_constMult_q <= "01011100010101010001110110010100101011100001";
WHEN "100001" => p5_uid112_constMult_q <= "01011111001101111100011010000001010100111000";
WHEN "100010" => p5_uid112_constMult_q <= "01100010000110100110111101101101111110001111";
WHEN "100011" => p5_uid112_constMult_q <= "01100100111111010001100001011010100111100110";
WHEN "100100" => p5_uid112_constMult_q <= "01100111110111111100000101000111010000111101";
WHEN "100101" => p5_uid112_constMult_q <= "01101010110000100110101000110011111010010100";
WHEN "100110" => p5_uid112_constMult_q <= "01101101101001010001001100100000100011101011";
WHEN "100111" => p5_uid112_constMult_q <= "01110000100001111011110000001101001101000010";
WHEN "101000" => p5_uid112_constMult_q <= "01110011011010100110010011111001110110011001";
WHEN "101001" => p5_uid112_constMult_q <= "01110110010011010000110111100110011111110000";
WHEN "101010" => p5_uid112_constMult_q <= "01111001001011111011011011010011001001000111";
WHEN "101011" => p5_uid112_constMult_q <= "01111100000100100101111110111111110010011110";
WHEN "101100" => p5_uid112_constMult_q <= "01111110111101010000100010101100011011110101";
WHEN "101101" => p5_uid112_constMult_q <= "10000001110101111011000110011001000101001100";
WHEN "101110" => p5_uid112_constMult_q <= "10000100101110100101101010000101101110100011";
WHEN "101111" => p5_uid112_constMult_q <= "10000111100111010000001101110010010111111010";
WHEN "110000" => p5_uid112_constMult_q <= "10001010011111111010110001011111000001010001";
WHEN "110001" => p5_uid112_constMult_q <= "10001101011000100101010101001011101010101000";
WHEN "110010" => p5_uid112_constMult_q <= "10010000010001001111111000111000010011111111";
WHEN "110011" => p5_uid112_constMult_q <= "10010011001001111010011100100100111101010110";
WHEN "110100" => p5_uid112_constMult_q <= "10010110000010100101000000010001100110101101";
WHEN "110101" => p5_uid112_constMult_q <= "10011000111011001111100011111110010000000100";
WHEN "110110" => p5_uid112_constMult_q <= "10011011110011111010000111101010111001011011";
WHEN "110111" => p5_uid112_constMult_q <= "10011110101100100100101011010111100010110010";
WHEN "111000" => p5_uid112_constMult_q <= "10100001100101001111001111000100001100001001";
WHEN "111001" => p5_uid112_constMult_q <= "10100100011101111001110010110000110101100000";
WHEN "111010" => p5_uid112_constMult_q <= "10100111010110100100010110011101011110110111";
WHEN "111011" => p5_uid112_constMult_q <= "10101010001111001110111010001010001000001110";
WHEN "111100" => p5_uid112_constMult_q <= "10101101000111111001011101110110110001100101";
WHEN "111101" => p5_uid112_constMult_q <= "10110000000000100100000001100011011010111100";
WHEN "111110" => p5_uid112_constMult_q <= "10110010111001001110100101010000000100010011";
WHEN "111111" => p5_uid112_constMult_q <= "10110101110001111001001000111100101101101010";
WHEN OTHERS =>
p5_uid112_constMult_q <= "00000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv6_uid106_constMult(BITSELECT,105)@0
xv6_uid106_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(41 downto 0);
xv6_uid106_constMult_b <= xv6_uid106_constMult_in(41 downto 36);
--reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0(REG,344)@0
reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q <= xv6_uid106_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q_to_p6_uid111_constMult_a(DELAY,523)@1
ld_reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q_to_p6_uid111_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q, xout => ld_reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q_to_p6_uid111_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p6_uid111_constMult(LOOKUP,110)@2
p6_uid111_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p6_uid111_constMult_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_xv6_uid106_constMult_0_to_p6_uid111_constMult_0_q_to_p6_uid111_constMult_a_q) IS
WHEN "000000" => p6_uid111_constMult_q <= "00000000000000000000000000000000000000000000000000";
WHEN "000001" => p6_uid111_constMult_q <= "00000010111000101010100011101100101001010111000001";
WHEN "000010" => p6_uid111_constMult_q <= "00000101110001010101000111011001010010101110000011";
WHEN "000011" => p6_uid111_constMult_q <= "00001000101001111111101011000101111100000101000100";
WHEN "000100" => p6_uid111_constMult_q <= "00001011100010101010001110110010100101011100000110";
WHEN "000101" => p6_uid111_constMult_q <= "00001110011011010100110010011111001110110011000111";
WHEN "000110" => p6_uid111_constMult_q <= "00010001010011111111010110001011111000001010001001";
WHEN "000111" => p6_uid111_constMult_q <= "00010100001100101001111001111000100001100001001010";
WHEN "001000" => p6_uid111_constMult_q <= "00010111000101010100011101100101001010111000001100";
WHEN "001001" => p6_uid111_constMult_q <= "00011001111101111111000001010001110100001111001101";
WHEN "001010" => p6_uid111_constMult_q <= "00011100110110101001100100111110011101100110001111";
WHEN "001011" => p6_uid111_constMult_q <= "00011111101111010100001000101011000110111101010000";
WHEN "001100" => p6_uid111_constMult_q <= "00100010100111111110101100010111110000010100010010";
WHEN "001101" => p6_uid111_constMult_q <= "00100101100000101001010000000100011001101011010011";
WHEN "001110" => p6_uid111_constMult_q <= "00101000011001010011110011110001000011000010010101";
WHEN "001111" => p6_uid111_constMult_q <= "00101011010001111110010111011101101100011001010110";
WHEN "010000" => p6_uid111_constMult_q <= "00101110001010101000111011001010010101110000011000";
WHEN "010001" => p6_uid111_constMult_q <= "00110001000011010011011110110110111111000111011001";
WHEN "010010" => p6_uid111_constMult_q <= "00110011111011111110000010100011101000011110011011";
WHEN "010011" => p6_uid111_constMult_q <= "00110110110100101000100110010000010001110101011100";
WHEN "010100" => p6_uid111_constMult_q <= "00111001101101010011001001111100111011001100011110";
WHEN "010101" => p6_uid111_constMult_q <= "00111100100101111101101101101001100100100011011111";
WHEN "010110" => p6_uid111_constMult_q <= "00111111011110101000010001010110001101111010100001";
WHEN "010111" => p6_uid111_constMult_q <= "01000010010111010010110101000010110111010001100010";
WHEN "011000" => p6_uid111_constMult_q <= "01000101001111111101011000101111100000101000100100";
WHEN "011001" => p6_uid111_constMult_q <= "01001000001000100111111100011100001001111111100101";
WHEN "011010" => p6_uid111_constMult_q <= "01001011000001010010100000001000110011010110100111";
WHEN "011011" => p6_uid111_constMult_q <= "01001101111001111101000011110101011100101101101000";
WHEN "011100" => p6_uid111_constMult_q <= "01010000110010100111100111100010000110000100101010";
WHEN "011101" => p6_uid111_constMult_q <= "01010011101011010010001011001110101111011011101011";
WHEN "011110" => p6_uid111_constMult_q <= "01010110100011111100101110111011011000110010101101";
WHEN "011111" => p6_uid111_constMult_q <= "01011001011100100111010010101000000010001001101110";
WHEN "100000" => p6_uid111_constMult_q <= "01011100010101010001110110010100101011100000110000";
WHEN "100001" => p6_uid111_constMult_q <= "01011111001101111100011010000001010100110111110001";
WHEN "100010" => p6_uid111_constMult_q <= "01100010000110100110111101101101111110001110110011";
WHEN "100011" => p6_uid111_constMult_q <= "01100100111111010001100001011010100111100101110100";
WHEN "100100" => p6_uid111_constMult_q <= "01100111110111111100000101000111010000111100110110";
WHEN "100101" => p6_uid111_constMult_q <= "01101010110000100110101000110011111010010011110111";
WHEN "100110" => p6_uid111_constMult_q <= "01101101101001010001001100100000100011101010111001";
WHEN "100111" => p6_uid111_constMult_q <= "01110000100001111011110000001101001101000001111010";
WHEN "101000" => p6_uid111_constMult_q <= "01110011011010100110010011111001110110011000111100";
WHEN "101001" => p6_uid111_constMult_q <= "01110110010011010000110111100110011111101111111101";
WHEN "101010" => p6_uid111_constMult_q <= "01111001001011111011011011010011001001000110111111";
WHEN "101011" => p6_uid111_constMult_q <= "01111100000100100101111110111111110010011110000000";
WHEN "101100" => p6_uid111_constMult_q <= "01111110111101010000100010101100011011110101000010";
WHEN "101101" => p6_uid111_constMult_q <= "10000001110101111011000110011001000101001100000011";
WHEN "101110" => p6_uid111_constMult_q <= "10000100101110100101101010000101101110100011000101";
WHEN "101111" => p6_uid111_constMult_q <= "10000111100111010000001101110010010111111010000110";
WHEN "110000" => p6_uid111_constMult_q <= "10001010011111111010110001011111000001010001001000";
WHEN "110001" => p6_uid111_constMult_q <= "10001101011000100101010101001011101010101000001001";
WHEN "110010" => p6_uid111_constMult_q <= "10010000010001001111111000111000010011111111001011";
WHEN "110011" => p6_uid111_constMult_q <= "10010011001001111010011100100100111101010110001100";
WHEN "110100" => p6_uid111_constMult_q <= "10010110000010100101000000010001100110101101001110";
WHEN "110101" => p6_uid111_constMult_q <= "10011000111011001111100011111110010000000100001111";
WHEN "110110" => p6_uid111_constMult_q <= "10011011110011111010000111101010111001011011010001";
WHEN "110111" => p6_uid111_constMult_q <= "10011110101100100100101011010111100010110010010010";
WHEN "111000" => p6_uid111_constMult_q <= "10100001100101001111001111000100001100001001010100";
WHEN "111001" => p6_uid111_constMult_q <= "10100100011101111001110010110000110101100000010101";
WHEN "111010" => p6_uid111_constMult_q <= "10100111010110100100010110011101011110110111010111";
WHEN "111011" => p6_uid111_constMult_q <= "10101010001111001110111010001010001000001110011000";
WHEN "111100" => p6_uid111_constMult_q <= "10101101000111111001011101110110110001100101011010";
WHEN "111101" => p6_uid111_constMult_q <= "10110000000000100100000001100011011010111100011011";
WHEN "111110" => p6_uid111_constMult_q <= "10110010111001001110100101010000000100010011011101";
WHEN "111111" => p6_uid111_constMult_q <= "10110101110001111001001000111100101101101010011110";
WHEN OTHERS =>
p6_uid111_constMult_q <= "00000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a1_uid119_constMult(ADD,118)@3
lev1_a1_uid119_constMult_a <= STD_LOGIC_VECTOR("0" & p6_uid111_constMult_q);
lev1_a1_uid119_constMult_b <= STD_LOGIC_VECTOR("0000000" & p5_uid112_constMult_q);
lev1_a1_uid119_constMult_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a1_uid119_constMult_a) + UNSIGNED(lev1_a1_uid119_constMult_b));
lev1_a1_uid119_constMult_q <= lev1_a1_uid119_constMult_o(50 downto 0);
--xv7_uid107_constMult(BITSELECT,106)@0
xv7_uid107_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b(47 downto 0);
xv7_uid107_constMult_b <= xv7_uid107_constMult_in(47 downto 42);
--reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0(REG,343)@0
reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q <= xv7_uid107_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a(DELAY,522)@1
ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q, xout => ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p7_uid110_constMult(LOOKUP,109)@2
p7_uid110_constMult: PROCESS (ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv7_uid107_constMult_0_to_p7_uid110_constMult_0_q_to_p7_uid110_constMult_a_q) IS
WHEN "000000" => p7_uid110_constMult_q <= "00000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p7_uid110_constMult_q <= "00000010111000101010100011101100101001010111000001100000";
WHEN "000010" => p7_uid110_constMult_q <= "00000101110001010101000111011001010010101110000011000000";
WHEN "000011" => p7_uid110_constMult_q <= "00001000101001111111101011000101111100000101000100011111";
WHEN "000100" => p7_uid110_constMult_q <= "00001011100010101010001110110010100101011100000101111111";
WHEN "000101" => p7_uid110_constMult_q <= "00001110011011010100110010011111001110110011000111011111";
WHEN "000110" => p7_uid110_constMult_q <= "00010001010011111111010110001011111000001010001000111111";
WHEN "000111" => p7_uid110_constMult_q <= "00010100001100101001111001111000100001100001001010011110";
WHEN "001000" => p7_uid110_constMult_q <= "00010111000101010100011101100101001010111000001011111110";
WHEN "001001" => p7_uid110_constMult_q <= "00011001111101111111000001010001110100001111001101011110";
WHEN "001010" => p7_uid110_constMult_q <= "00011100110110101001100100111110011101100110001110111110";
WHEN "001011" => p7_uid110_constMult_q <= "00011111101111010100001000101011000110111101010000011101";
WHEN "001100" => p7_uid110_constMult_q <= "00100010100111111110101100010111110000010100010001111101";
WHEN "001101" => p7_uid110_constMult_q <= "00100101100000101001010000000100011001101011010011011101";
WHEN "001110" => p7_uid110_constMult_q <= "00101000011001010011110011110001000011000010010100111101";
WHEN "001111" => p7_uid110_constMult_q <= "00101011010001111110010111011101101100011001010110011100";
WHEN "010000" => p7_uid110_constMult_q <= "00101110001010101000111011001010010101110000010111111100";
WHEN "010001" => p7_uid110_constMult_q <= "00110001000011010011011110110110111111000111011001011100";
WHEN "010010" => p7_uid110_constMult_q <= "00110011111011111110000010100011101000011110011010111100";
WHEN "010011" => p7_uid110_constMult_q <= "00110110110100101000100110010000010001110101011100011011";
WHEN "010100" => p7_uid110_constMult_q <= "00111001101101010011001001111100111011001100011101111011";
WHEN "010101" => p7_uid110_constMult_q <= "00111100100101111101101101101001100100100011011111011011";
WHEN "010110" => p7_uid110_constMult_q <= "00111111011110101000010001010110001101111010100000111011";
WHEN "010111" => p7_uid110_constMult_q <= "01000010010111010010110101000010110111010001100010011011";
WHEN "011000" => p7_uid110_constMult_q <= "01000101001111111101011000101111100000101000100011111010";
WHEN "011001" => p7_uid110_constMult_q <= "01001000001000100111111100011100001001111111100101011010";
WHEN "011010" => p7_uid110_constMult_q <= "01001011000001010010100000001000110011010110100110111010";
WHEN "011011" => p7_uid110_constMult_q <= "01001101111001111101000011110101011100101101101000011010";
WHEN "011100" => p7_uid110_constMult_q <= "01010000110010100111100111100010000110000100101001111001";
WHEN "011101" => p7_uid110_constMult_q <= "01010011101011010010001011001110101111011011101011011001";
WHEN "011110" => p7_uid110_constMult_q <= "01010110100011111100101110111011011000110010101100111001";
WHEN "011111" => p7_uid110_constMult_q <= "01011001011100100111010010101000000010001001101110011001";
WHEN "100000" => p7_uid110_constMult_q <= "01011100010101010001110110010100101011100000101111111000";
WHEN "100001" => p7_uid110_constMult_q <= "01011111001101111100011010000001010100110111110001011000";
WHEN "100010" => p7_uid110_constMult_q <= "01100010000110100110111101101101111110001110110010111000";
WHEN "100011" => p7_uid110_constMult_q <= "01100100111111010001100001011010100111100101110100011000";
WHEN "100100" => p7_uid110_constMult_q <= "01100111110111111100000101000111010000111100110101110111";
WHEN "100101" => p7_uid110_constMult_q <= "01101010110000100110101000110011111010010011110111010111";
WHEN "100110" => p7_uid110_constMult_q <= "01101101101001010001001100100000100011101010111000110111";
WHEN "100111" => p7_uid110_constMult_q <= "01110000100001111011110000001101001101000001111010010111";
WHEN "101000" => p7_uid110_constMult_q <= "01110011011010100110010011111001110110011000111011110110";
WHEN "101001" => p7_uid110_constMult_q <= "01110110010011010000110111100110011111101111111101010110";
WHEN "101010" => p7_uid110_constMult_q <= "01111001001011111011011011010011001001000110111110110110";
WHEN "101011" => p7_uid110_constMult_q <= "01111100000100100101111110111111110010011110000000010110";
WHEN "101100" => p7_uid110_constMult_q <= "01111110111101010000100010101100011011110101000001110110";
WHEN "101101" => p7_uid110_constMult_q <= "10000001110101111011000110011001000101001100000011010101";
WHEN "101110" => p7_uid110_constMult_q <= "10000100101110100101101010000101101110100011000100110101";
WHEN "101111" => p7_uid110_constMult_q <= "10000111100111010000001101110010010111111010000110010101";
WHEN "110000" => p7_uid110_constMult_q <= "10001010011111111010110001011111000001010001000111110101";
WHEN "110001" => p7_uid110_constMult_q <= "10001101011000100101010101001011101010101000001001010100";
WHEN "110010" => p7_uid110_constMult_q <= "10010000010001001111111000111000010011111111001010110100";
WHEN "110011" => p7_uid110_constMult_q <= "10010011001001111010011100100100111101010110001100010100";
WHEN "110100" => p7_uid110_constMult_q <= "10010110000010100101000000010001100110101101001101110100";
WHEN "110101" => p7_uid110_constMult_q <= "10011000111011001111100011111110010000000100001111010011";
WHEN "110110" => p7_uid110_constMult_q <= "10011011110011111010000111101010111001011011010000110011";
WHEN "110111" => p7_uid110_constMult_q <= "10011110101100100100101011010111100010110010010010010011";
WHEN "111000" => p7_uid110_constMult_q <= "10100001100101001111001111000100001100001001010011110011";
WHEN "111001" => p7_uid110_constMult_q <= "10100100011101111001110010110000110101100000010101010010";
WHEN "111010" => p7_uid110_constMult_q <= "10100111010110100100010110011101011110110111010110110010";
WHEN "111011" => p7_uid110_constMult_q <= "10101010001111001110111010001010001000001110011000010010";
WHEN "111100" => p7_uid110_constMult_q <= "10101101000111111001011101110110110001100101011001110010";
WHEN "111101" => p7_uid110_constMult_q <= "10110000000000100100000001100011011010111100011011010001";
WHEN "111110" => p7_uid110_constMult_q <= "10110010111001001110100101010000000100010011011100110001";
WHEN "111111" => p7_uid110_constMult_q <= "10110101110001111001001000111100101101101010011110010001";
WHEN OTHERS =>
p7_uid110_constMult_q <= "00000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv8_uid108_constMult(BITSELECT,107)@0
xv8_uid108_constMult_in <= fxpInPreAlign_uid36_fpExpETest_b;
xv8_uid108_constMult_b <= xv8_uid108_constMult_in(53 downto 48);
--reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0(REG,342)@0
reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0_q <= xv8_uid108_constMult_b;
END IF;
END IF;
END PROCESS;
--p8_uid109_constMult(LOOKUP,108)@1
p8_uid109_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p8_uid109_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv8_uid108_constMult_0_to_p8_uid109_constMult_0_q) IS
WHEN "000000" => p8_uid109_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p8_uid109_constMult_q <= "00000010111000101010100011101100101001010111000001011111110001";
WHEN "000010" => p8_uid109_constMult_q <= "00000101110001010101000111011001010010101110000010111111100010";
WHEN "000011" => p8_uid109_constMult_q <= "00001000101001111111101011000101111100000101000100011111010010";
WHEN "000100" => p8_uid109_constMult_q <= "00001011100010101010001110110010100101011100000101111111000011";
WHEN "000101" => p8_uid109_constMult_q <= "00001110011011010100110010011111001110110011000111011110110100";
WHEN "000110" => p8_uid109_constMult_q <= "00010001010011111111010110001011111000001010001000111110100100";
WHEN "000111" => p8_uid109_constMult_q <= "00010100001100101001111001111000100001100001001010011110010101";
WHEN "001000" => p8_uid109_constMult_q <= "00010111000101010100011101100101001010111000001011111110000110";
WHEN "001001" => p8_uid109_constMult_q <= "00011001111101111111000001010001110100001111001101011101110111";
WHEN "001010" => p8_uid109_constMult_q <= "00011100110110101001100100111110011101100110001110111101101000";
WHEN "001011" => p8_uid109_constMult_q <= "00011111101111010100001000101011000110111101010000011101011000";
WHEN "001100" => p8_uid109_constMult_q <= "00100010100111111110101100010111110000010100010001111101001001";
WHEN "001101" => p8_uid109_constMult_q <= "00100101100000101001010000000100011001101011010011011100111010";
WHEN "001110" => p8_uid109_constMult_q <= "00101000011001010011110011110001000011000010010100111100101010";
WHEN "001111" => p8_uid109_constMult_q <= "00101011010001111110010111011101101100011001010110011100011011";
WHEN "010000" => p8_uid109_constMult_q <= "00101110001010101000111011001010010101110000010111111100001100";
WHEN "010001" => p8_uid109_constMult_q <= "00110001000011010011011110110110111111000111011001011011111101";
WHEN "010010" => p8_uid109_constMult_q <= "00110011111011111110000010100011101000011110011010111011101110";
WHEN "010011" => p8_uid109_constMult_q <= "00110110110100101000100110010000010001110101011100011011011110";
WHEN "010100" => p8_uid109_constMult_q <= "00111001101101010011001001111100111011001100011101111011001111";
WHEN "010101" => p8_uid109_constMult_q <= "00111100100101111101101101101001100100100011011111011011000000";
WHEN "010110" => p8_uid109_constMult_q <= "00111111011110101000010001010110001101111010100000111010110000";
WHEN "010111" => p8_uid109_constMult_q <= "01000010010111010010110101000010110111010001100010011010100001";
WHEN "011000" => p8_uid109_constMult_q <= "01000101001111111101011000101111100000101000100011111010010010";
WHEN "011001" => p8_uid109_constMult_q <= "01001000001000100111111100011100001001111111100101011010000011";
WHEN "011010" => p8_uid109_constMult_q <= "01001011000001010010100000001000110011010110100110111001110100";
WHEN "011011" => p8_uid109_constMult_q <= "01001101111001111101000011110101011100101101101000011001100100";
WHEN "011100" => p8_uid109_constMult_q <= "01010000110010100111100111100010000110000100101001111001010101";
WHEN "011101" => p8_uid109_constMult_q <= "01010011101011010010001011001110101111011011101011011001000110";
WHEN "011110" => p8_uid109_constMult_q <= "01010110100011111100101110111011011000110010101100111000110110";
WHEN "011111" => p8_uid109_constMult_q <= "01011001011100100111010010101000000010001001101110011000100111";
WHEN "100000" => p8_uid109_constMult_q <= "10100011101010101110001001101011010100011111010000000111101000";
WHEN "100001" => p8_uid109_constMult_q <= "10100110100011011000101101010111111101110110010001100111011001";
WHEN "100010" => p8_uid109_constMult_q <= "10101001011100000011010001000100100111001101010011000111001010";
WHEN "100011" => p8_uid109_constMult_q <= "10101100010100101101110100110001010000100100010100100110111010";
WHEN "100100" => p8_uid109_constMult_q <= "10101111001101011000011000011101111001111011010110000110101011";
WHEN "100101" => p8_uid109_constMult_q <= "10110010000110000010111100001010100011010010010111100110011100";
WHEN "100110" => p8_uid109_constMult_q <= "10110100111110101101011111110111001100101001011001000110001100";
WHEN "100111" => p8_uid109_constMult_q <= "10110111110111011000000011100011110110000000011010100101111101";
WHEN "101000" => p8_uid109_constMult_q <= "10111010110000000010100111010000011111010111011100000101101110";
WHEN "101001" => p8_uid109_constMult_q <= "10111101101000101101001010111101001000101110011101100101011111";
WHEN "101010" => p8_uid109_constMult_q <= "11000000100001010111101110101001110010000101011111000101010000";
WHEN "101011" => p8_uid109_constMult_q <= "11000011011010000010010010010110011011011100100000100101000000";
WHEN "101100" => p8_uid109_constMult_q <= "11000110010010101100110110000011000100110011100010000100110001";
WHEN "101101" => p8_uid109_constMult_q <= "11001001001011010111011001101111101110001010100011100100100010";
WHEN "101110" => p8_uid109_constMult_q <= "11001100000100000001111101011100010111100001100101000100010010";
WHEN "101111" => p8_uid109_constMult_q <= "11001110111100101100100001001001000000111000100110100100000011";
WHEN "110000" => p8_uid109_constMult_q <= "11010001110101010111000100110101101010001111101000000011110100";
WHEN "110001" => p8_uid109_constMult_q <= "11010100101110000001101000100010010011100110101001100011100101";
WHEN "110010" => p8_uid109_constMult_q <= "11010111100110101100001100001110111100111101101011000011010110";
WHEN "110011" => p8_uid109_constMult_q <= "11011010011111010110101111111011100110010100101100100011000110";
WHEN "110100" => p8_uid109_constMult_q <= "11011101011000000001010011101000001111101011101110000010110111";
WHEN "110101" => p8_uid109_constMult_q <= "11100000010000101011110111010100111001000010101111100010101000";
WHEN "110110" => p8_uid109_constMult_q <= "11100011001001010110011011000001100010011001110001000010011000";
WHEN "110111" => p8_uid109_constMult_q <= "11100110000010000000111110101110001011110000110010100010001001";
WHEN "111000" => p8_uid109_constMult_q <= "11101000111010101011100010011010110101000111110100000001111010";
WHEN "111001" => p8_uid109_constMult_q <= "11101011110011010110000110000111011110011110110101100001101011";
WHEN "111010" => p8_uid109_constMult_q <= "11101110101100000000101001110100000111110101110111000001011100";
WHEN "111011" => p8_uid109_constMult_q <= "11110001100100101011001101100000110001001100111000100001001100";
WHEN "111100" => p8_uid109_constMult_q <= "11110100011101010101110001001101011010100011111010000000111101";
WHEN "111101" => p8_uid109_constMult_q <= "11110111010110000000010100111010000011111010111011100000101110";
WHEN "111110" => p8_uid109_constMult_q <= "11111010001110101010111000100110101101010001111101000000011110";
WHEN "111111" => p8_uid109_constMult_q <= "11111101000111010101011100010011010110101000111110100000001111";
WHEN OTHERS =>
p8_uid109_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid118_constMult(ADD,117)@2
lev1_a0_uid118_constMult_a <= STD_LOGIC_VECTOR((63 downto 62 => p8_uid109_constMult_q(61)) & p8_uid109_constMult_q);
lev1_a0_uid118_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p7_uid110_constMult_q);
lev1_a0_uid118_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev1_a0_uid118_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev1_a0_uid118_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid118_constMult_a) + SIGNED(lev1_a0_uid118_constMult_b));
END IF;
END IF;
END PROCESS;
lev1_a0_uid118_constMult_q <= lev1_a0_uid118_constMult_o(62 downto 0);
--lev2_a0_uid122_constMult(ADD,121)@3
lev2_a0_uid122_constMult_a <= STD_LOGIC_VECTOR((64 downto 63 => lev1_a0_uid118_constMult_q(62)) & lev1_a0_uid118_constMult_q);
lev2_a0_uid122_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000000000" & lev1_a1_uid119_constMult_q);
lev2_a0_uid122_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev2_a0_uid122_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev2_a0_uid122_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev2_a0_uid122_constMult_a) + SIGNED(lev2_a0_uid122_constMult_b));
END IF;
END IF;
END PROCESS;
lev2_a0_uid122_constMult_q <= lev2_a0_uid122_constMult_o(63 downto 0);
--lev3_a0_uid124_constMult(ADD,123)@4
lev3_a0_uid124_constMult_a <= STD_LOGIC_VECTOR((65 downto 64 => lev2_a0_uid122_constMult_q(63)) & lev2_a0_uid122_constMult_q);
lev3_a0_uid124_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000" & lev2_a1_uid123_constMult_q);
lev3_a0_uid124_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev3_a0_uid124_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev3_a0_uid124_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev3_a0_uid124_constMult_a) + SIGNED(lev3_a0_uid124_constMult_b));
END IF;
END IF;
END PROCESS;
lev3_a0_uid124_constMult_q <= lev3_a0_uid124_constMult_o(64 downto 0);
--lev4_a0_uid125_constMult(ADD,124)@5
lev4_a0_uid125_constMult_a <= STD_LOGIC_VECTOR((66 downto 65 => lev3_a0_uid124_constMult_q(64)) & lev3_a0_uid124_constMult_q);
lev4_a0_uid125_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000000000000000000000000000000000000000000000000" & p0_uid117_constMult_q);
lev4_a0_uid125_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev4_a0_uid125_constMult_a) + SIGNED(lev4_a0_uid125_constMult_b));
lev4_a0_uid125_constMult_q <= lev4_a0_uid125_constMult_o(65 downto 0);
--sR_uid126_constMult(BITSELECT,125)@5
sR_uid126_constMult_in <= lev4_a0_uid125_constMult_q(61 downto 0);
sR_uid126_constMult_b <= sR_uid126_constMult_in(61 downto 4);
--oFracXZwE_uid39_fpExpETest(BITJOIN,38)@5
oFracXZwE_uid39_fpExpETest_q <= sR_uid126_constMult_b & cstZeroWE_uid11_fpExpETest_q;
--msbx_uid128_fxpInPostAlign_uid45_fpExpETest(BITSELECT,127)@5
msbx_uid128_fxpInPostAlign_uid45_fpExpETest_in <= oFracXZwE_uid39_fpExpETest_q;
msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b <= msbx_uid128_fxpInPostAlign_uid45_fpExpETest_in(68 downto 68);
--ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b(DELAY,581)@5
ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest(LOGICAL,169)@7
rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_a <= GND_q;
rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_b <= ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q;
rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest(BITSELECT,170)@8
RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_in(68 downto 1);
--rightShiftStage3Idx1_uid172_fxpInPostAlign_uid45_fpExpETest(BITJOIN,171)@8
rightShiftStage3Idx1_uid172_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage3Idx1Pad1_uid170_fxpInPostAlign_uid45_fpExpETest_q & RightShiftStage268dto1_uid171_fxpInPostAlign_uid45_fpExpETest_b;
--z_uid163_fxpInPostAlign_uid45_fpExpETest(CONSTANT,162)
z_uid163_fxpInPostAlign_uid45_fpExpETest_q <= "000000";
--rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest(LOGICAL,163)@7
rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_a <= z_uid163_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b(DELAY,563)@5
ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--z_uid149_fxpInPostAlign_uid45_fpExpETest(CONSTANT,148)
z_uid149_fxpInPostAlign_uid45_fpExpETest_q <= "000000000000000000000000";
--rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest(LOGICAL,149)@6
rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_a <= z_uid149_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid137_fxpInPostAlign_uid45_fpExpETest(CONSTANT,136)
rightShiftStage0Idx3_uid137_fxpInPostAlign_uid45_fpExpETest_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest(LOGICAL,137)@5
rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_a <= rightShiftStage0Idx3_uid137_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((68 downto 1 => msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b(0)) & msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b);
rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 69, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--z_uid133_fxpInPostAlign_uid45_fpExpETest(CONSTANT,132)
z_uid133_fxpInPostAlign_uid45_fpExpETest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest(LOGICAL,133)@5
rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_a <= z_uid133_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b(0)) & msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b);
rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_b;
--X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest(BITSELECT,134)@5
X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_in <= oFracXZwE_uid39_fpExpETest_q;
X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_b <= X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_in(68 downto 64);
--rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest(BITJOIN,135)@5
rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage0Idx2Pad64_uid134_fxpInPostAlign_uid45_fpExpETest_q & X68dto64_uid135_fxpInPostAlign_uid45_fpExpETest_b;
--reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4(REG,354)@5
reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4_q <= rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--z_uid129_fxpInPostAlign_uid45_fpExpETest(CONSTANT,128)
z_uid129_fxpInPostAlign_uid45_fpExpETest_q <= "00000000000000000000000000000000";
--rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest(LOGICAL,129)@5
rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_a <= z_uid129_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b(0)) & msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b);
rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_b;
--X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest(BITSELECT,130)@5
X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_in <= oFracXZwE_uid39_fpExpETest_q;
X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_b <= X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_in(68 downto 32);
--rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest(BITJOIN,131)@5
rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage0Idx1Pad32_uid130_fxpInPostAlign_uid45_fpExpETest_q & X68dto32_uid131_fxpInPostAlign_uid45_fpExpETest_b;
--reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3(REG,353)@5
reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3_q <= rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2(REG,352)@5
reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2_q <= oFracXZwE_uid39_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--cstBiasPWE_uid14_fpExpETest(CONSTANT,13)
cstBiasPWE_uid14_fpExpETest_q <= "1000001";
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable(LOGICAL,884)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_a <= en;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q <= not ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_a;
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor(LOGICAL,885)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_b <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_q <= not (ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_a or ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_b);
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_mem_top(CONSTANT,881)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_mem_top_q <= "010";
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp(LOGICAL,882)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_mem_top_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q);
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_q <= "1" when ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_a = ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_b else "0";
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg(REG,883)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena(REG,886)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_nor_q = "1") THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd(LOGICAL,887)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_sticky_ena_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_b <= en;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_a and ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_b;
--expX_uid6_fpExpETest(BITSELECT,5)@0
expX_uid6_fpExpETest_in <= a(62 downto 0);
expX_uid6_fpExpETest_b <= expX_uid6_fpExpETest_in(62 downto 52);
--cstBiasPWE_uid13_fpExpETest(CONSTANT,12)
cstBiasPWE_uid13_fpExpETest_q <= "10000001010";
--shiftValuePreSat_uid40_fpExpETest(SUB,39)@0
shiftValuePreSat_uid40_fpExpETest_a <= STD_LOGIC_VECTOR("0" & cstBiasPWE_uid13_fpExpETest_q);
shiftValuePreSat_uid40_fpExpETest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpExpETest_b);
shiftValuePreSat_uid40_fpExpETest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePreSat_uid40_fpExpETest_a) - UNSIGNED(shiftValuePreSat_uid40_fpExpETest_b));
shiftValuePreSat_uid40_fpExpETest_q <= shiftValuePreSat_uid40_fpExpETest_o(11 downto 0);
--shiftValuePreSatRed_uid43_fpExpETest(BITSELECT,42)@0
shiftValuePreSatRed_uid43_fpExpETest_in <= shiftValuePreSat_uid40_fpExpETest_q(6 downto 0);
shiftValuePreSatRed_uid43_fpExpETest_b <= shiftValuePreSatRed_uid43_fpExpETest_in(6 downto 0);
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_inputreg(DELAY,875)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => shiftValuePreSatRed_uid43_fpExpETest_b, xout => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt(COUNTER,877)
-- every=1, low=0, high=2, step=1, init=1
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i = 1 THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_eq <= '1';
ELSE
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_eq = '1') THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i - 2;
ELSE
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_i,2));
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg(REG,878)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux(MUX,879)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_s <= en;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux: PROCESS (ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_s, ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q, ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_q)
BEGIN
CASE ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_s IS
WHEN "0" => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q;
WHEN "1" => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdcnt_q;
WHEN OTHERS => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem(DUALMEM,876)
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ia <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_inputreg_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_aa <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdreg_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ab <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_rdmux_q;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 2,
numwords_a => 3,
width_b => 7,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_iq,
address_a => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_aa,
data_a => ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_ia
);
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_reset0 <= areset;
ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_iq(6 downto 0);
--reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0(REG,341)@0
reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0_q <= shiftValuePreSat_uid40_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--shiftUdf_uid42_fpExpETest(COMPARE,41)@1
shiftUdf_uid42_fpExpETest_cin <= GND_q;
shiftUdf_uid42_fpExpETest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0_q(11)) & reg_shiftValuePreSat_uid40_fpExpETest_0_to_shiftUdf_uid42_fpExpETest_0_q) & '0';
shiftUdf_uid42_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "000000" & cstBiasPWE_uid14_fpExpETest_q) & shiftUdf_uid42_fpExpETest_cin(0);
shiftUdf_uid42_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(shiftUdf_uid42_fpExpETest_a) - SIGNED(shiftUdf_uid42_fpExpETest_b));
shiftUdf_uid42_fpExpETest_n(0) <= not shiftUdf_uid42_fpExpETest_o(14);
--ld_shiftUdf_uid42_fpExpETest_n_to_shiftVal_uid44_fpExpETest_b(DELAY,451)@1
ld_shiftUdf_uid42_fpExpETest_n_to_shiftVal_uid44_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => shiftUdf_uid42_fpExpETest_n, xout => ld_shiftUdf_uid42_fpExpETest_n_to_shiftVal_uid44_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--shiftVal_uid44_fpExpETest(MUX,43)@5
shiftVal_uid44_fpExpETest_s <= ld_shiftUdf_uid42_fpExpETest_n_to_shiftVal_uid44_fpExpETest_b_q;
shiftVal_uid44_fpExpETest: PROCESS (shiftVal_uid44_fpExpETest_s, en, ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_q, cstBiasPWE_uid14_fpExpETest_q)
BEGIN
CASE shiftVal_uid44_fpExpETest_s IS
WHEN "0" => shiftVal_uid44_fpExpETest_q <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_replace_mem_q;
WHEN "1" => shiftVal_uid44_fpExpETest_q <= cstBiasPWE_uid14_fpExpETest_q;
WHEN OTHERS => shiftVal_uid44_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest(BITSELECT,138)@5
rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_in <= shiftVal_uid44_fpExpETest_q;
rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_b <= rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_in(6 downto 5);
--reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1(REG,351)@5
reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1_q <= rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest(MUX,139)@6
rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_s <= reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1_q;
rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest: PROCESS (rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_s, en, reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2_q, reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3_q, reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4_q, rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q)
BEGIN
CASE rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_s IS
WHEN "00" => rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q <= reg_oFracXZwE_uid39_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_2_q;
WHEN "01" => rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q <= reg_rightShiftStage0Idx1_uid132_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_3_q;
WHEN "10" => rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q <= reg_rightShiftStage0Idx2_uid136_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_4_q;
WHEN "11" => rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage0Idx3_uid138_fxpInPostAlign_uid45_fpExpETest_q;
WHEN OTHERS => rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest(BITSELECT,150)@6
RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_in(68 downto 24);
--ld_RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_a(DELAY,573)@6
ld_RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest(BITJOIN,151)@7
rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx3Pad24_uid150_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage068dto24_uid151_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_a_q;
--z_uid145_fxpInPostAlign_uid45_fpExpETest(CONSTANT,144)
z_uid145_fxpInPostAlign_uid45_fpExpETest_q <= "0000000000000000";
--rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest(LOGICAL,145)@6
rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_a <= z_uid145_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest(BITSELECT,146)@6
RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_in(68 downto 16);
--ld_RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_a(DELAY,569)@6
ld_RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest(BITJOIN,147)@7
rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx2Pad16_uid146_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage068dto16_uid147_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_a_q;
--z_uid141_fxpInPostAlign_uid45_fpExpETest(CONSTANT,140)
z_uid141_fxpInPostAlign_uid45_fpExpETest_q <= "00000000";
--rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest(LOGICAL,141)@6
rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_a <= z_uid141_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest(BITSELECT,142)@6
RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_in(68 downto 8);
--ld_RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_a(DELAY,565)@6
ld_RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest(BITJOIN,143)@7
rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx1Pad8_uid142_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage068dto8_uid143_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_a_q;
--reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2(REG,356)@6
reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2_q <= rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest(BITSELECT,152)@5
rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_in <= shiftVal_uid44_fpExpETest_q(4 downto 0);
rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b <= rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_in(4 downto 3);
--ld_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_a(DELAY,809)@5
ld_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1(REG,355)@6
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_q <= ld_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest(MUX,153)@7
rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_s <= reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_1_q;
rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest: PROCESS (rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_s, en, reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2_q, rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_q, rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_q, rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_q)
BEGIN
CASE rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_s IS
WHEN "00" => rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q <= reg_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_2_q;
WHEN "01" => rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx1_uid144_fxpInPostAlign_uid45_fpExpETest_q;
WHEN "10" => rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx2_uid148_fxpInPostAlign_uid45_fpExpETest_q;
WHEN "11" => rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage1Idx3_uid152_fxpInPostAlign_uid45_fpExpETest_q;
WHEN OTHERS => rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest(BITSELECT,164)@7
RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_in(68 downto 6);
--ld_RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_a(DELAY,591)@7
ld_RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest(BITJOIN,165)@8
rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx3Pad6_uid164_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage168dto6_uid165_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_a_q;
--z_uid159_fxpInPostAlign_uid45_fpExpETest(CONSTANT,158)
z_uid159_fxpInPostAlign_uid45_fpExpETest_q <= "0000";
--rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest(LOGICAL,159)@7
rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_a <= z_uid159_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest(BITSELECT,160)@7
RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_in(68 downto 4);
--ld_RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_a(DELAY,587)@7
ld_RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest(BITJOIN,161)@8
rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx2Pad4_uid160_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage168dto4_uid161_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_a_q;
--z_uid155_fxpInPostAlign_uid45_fpExpETest(CONSTANT,154)
z_uid155_fxpInPostAlign_uid45_fpExpETest_q <= "00";
--rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest(LOGICAL,155)@7
rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_a <= z_uid155_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q(0)) & ld_msbx_uid128_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b_q);
rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q_i <= rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_a or rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_b;
rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q, xin => rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest(BITSELECT,156)@7
RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_in <= rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q;
RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b <= RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_in(68 downto 2);
--ld_RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_a(DELAY,583)@7
ld_RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest(BITJOIN,157)@8
rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx1Pad2_uid156_fxpInPostAlign_uid45_fpExpETest_q & ld_RightShiftStage168dto2_uid157_fxpInPostAlign_uid45_fpExpETest_b_to_rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_a_q;
--reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2(REG,358)@7
reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2_q <= rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest(BITSELECT,166)@5
rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_in <= shiftVal_uid44_fpExpETest_q(2 downto 0);
rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b <= rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_in(2 downto 1);
--ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_a(DELAY,811)@5
ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1(REG,357)@7
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_q <= ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest(MUX,167)@8
rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_s <= reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_1_q;
rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest: PROCESS (rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_s, en, reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2_q, rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_q, rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_q, rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_q)
BEGIN
CASE rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_s IS
WHEN "00" => rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q <= reg_rightShiftStage1_uid154_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_2_q;
WHEN "01" => rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx1_uid158_fxpInPostAlign_uid45_fpExpETest_q;
WHEN "10" => rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx2_uid162_fxpInPostAlign_uid45_fpExpETest_q;
WHEN "11" => rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2Idx3_uid166_fxpInPostAlign_uid45_fpExpETest_q;
WHEN OTHERS => rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest(BITSELECT,172)@5
rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_in <= shiftVal_uid44_fpExpETest_q(0 downto 0);
rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b <= rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_in(0 downto 0);
--ld_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_a(DELAY,813)@5
ld_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1(REG,359)@7
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_q <= ld_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest(MUX,173)@8
rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_s <= reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_1_q;
rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest: PROCESS (rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_s, en, rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q, rightShiftStage3Idx1_uid172_fxpInPostAlign_uid45_fpExpETest_q)
BEGIN
CASE rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_s IS
WHEN "0" => rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage2_uid168_fxpInPostAlign_uid45_fpExpETest_q;
WHEN "1" => rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_q <= rightShiftStage3Idx1_uid172_fxpInPostAlign_uid45_fpExpETest_q;
WHEN OTHERS => rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--ePreRnd_uid46_fpExpETest(BITSELECT,45)@8
ePreRnd_uid46_fpExpETest_in <= rightShiftStage3_uid174_fxpInPostAlign_uid45_fpExpETest_q;
ePreRnd_uid46_fpExpETest_b <= ePreRnd_uid46_fpExpETest_in(68 downto 55);
--xv0_uid176_constMult(BITSELECT,175)@8
xv0_uid176_constMult_in <= ePreRnd_uid46_fpExpETest_b(5 downto 0);
xv0_uid176_constMult_b <= xv0_uid176_constMult_in(5 downto 0);
--ld_xv0_uid176_constMult_b_to_reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_a(DELAY,826)@8
ld_xv0_uid176_constMult_b_to_reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 2 )
PORT MAP ( xin => xv0_uid176_constMult_b, xout => ld_xv0_uid176_constMult_b_to_reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0(REG,372)@10
reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_q <= ld_xv0_uid176_constMult_b_to_reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p0_uid181_constMult(LOOKUP,180)@11
p0_uid181_constMult: PROCESS (reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv0_uid176_constMult_0_to_p0_uid181_constMult_0_q) IS
WHEN "000000" => p0_uid181_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid181_constMult_q <= "000000101100010111001000010111111101111101000111001111011110011010110";
WHEN "000010" => p0_uid181_constMult_q <= "000001011000101110010000101111111011111010001110011110111100110101100";
WHEN "000011" => p0_uid181_constMult_q <= "000010000101000101011001000111111001110111010101101110011011010000010";
WHEN "000100" => p0_uid181_constMult_q <= "000010110001011100100001011111110111110100011100111101111001101011000";
WHEN "000101" => p0_uid181_constMult_q <= "000011011101110011101001110111110101110001100100001101011000000101110";
WHEN "000110" => p0_uid181_constMult_q <= "000100001010001010110010001111110011101110101011011100110110100000100";
WHEN "000111" => p0_uid181_constMult_q <= "000100110110100001111010100111110001101011110010101100010100111011010";
WHEN "001000" => p0_uid181_constMult_q <= "000101100010111001000010111111101111101000111001111011110011010110000";
WHEN "001001" => p0_uid181_constMult_q <= "000110001111010000001011010111101101100110000001001011010001110000110";
WHEN "001010" => p0_uid181_constMult_q <= "000110111011100111010011101111101011100011001000011010110000001011100";
WHEN "001011" => p0_uid181_constMult_q <= "000111100111111110011100000111101001100000001111101010001110100110010";
WHEN "001100" => p0_uid181_constMult_q <= "001000010100010101100100011111100111011101010110111001101101000001000";
WHEN "001101" => p0_uid181_constMult_q <= "001001000000101100101100110111100101011010011110001001001011011011110";
WHEN "001110" => p0_uid181_constMult_q <= "001001101101000011110101001111100011010111100101011000101001110110100";
WHEN "001111" => p0_uid181_constMult_q <= "001010011001011010111101100111100001010100101100101000001000010001010";
WHEN "010000" => p0_uid181_constMult_q <= "001011000101110010000101111111011111010001110011110111100110101100000";
WHEN "010001" => p0_uid181_constMult_q <= "001011110010001001001110010111011101001110111011000111000101000110110";
WHEN "010010" => p0_uid181_constMult_q <= "001100011110100000010110101111011011001100000010010110100011100001100";
WHEN "010011" => p0_uid181_constMult_q <= "001101001010110111011111000111011001001001001001100110000001111100010";
WHEN "010100" => p0_uid181_constMult_q <= "001101110111001110100111011111010111000110010000110101100000010111000";
WHEN "010101" => p0_uid181_constMult_q <= "001110100011100101101111110111010101000011011000000100111110110001110";
WHEN "010110" => p0_uid181_constMult_q <= "001111001111111100111000001111010011000000011111010100011101001100100";
WHEN "010111" => p0_uid181_constMult_q <= "001111111100010100000000100111010000111101100110100011111011100111010";
WHEN "011000" => p0_uid181_constMult_q <= "010000101000101011001000111111001110111010101101110011011010000010000";
WHEN "011001" => p0_uid181_constMult_q <= "010001010101000010010001010111001100110111110101000010111000011100110";
WHEN "011010" => p0_uid181_constMult_q <= "010010000001011001011001101111001010110100111100010010010110110111100";
WHEN "011011" => p0_uid181_constMult_q <= "010010101101110000100010000111001000110010000011100001110101010010010";
WHEN "011100" => p0_uid181_constMult_q <= "010011011010000111101010011111000110101111001010110001010011101101000";
WHEN "011101" => p0_uid181_constMult_q <= "010100000110011110110010110111000100101100010010000000110010000111110";
WHEN "011110" => p0_uid181_constMult_q <= "010100110010110101111011001111000010101001011001010000010000100010100";
WHEN "011111" => p0_uid181_constMult_q <= "010101011111001101000011100111000000100110100000011111101110111101010";
WHEN "100000" => p0_uid181_constMult_q <= "010110001011100100001011111110111110100011100111101111001101011000000";
WHEN "100001" => p0_uid181_constMult_q <= "010110110111111011010100010110111100100000101110111110101011110010110";
WHEN "100010" => p0_uid181_constMult_q <= "010111100100010010011100101110111010011101110110001110001010001101100";
WHEN "100011" => p0_uid181_constMult_q <= "011000010000101001100101000110111000011010111101011101101000101000010";
WHEN "100100" => p0_uid181_constMult_q <= "011000111101000000101101011110110110011000000100101101000111000011000";
WHEN "100101" => p0_uid181_constMult_q <= "011001101001010111110101110110110100010101001011111100100101011101110";
WHEN "100110" => p0_uid181_constMult_q <= "011010010101101110111110001110110010010010010011001100000011111000100";
WHEN "100111" => p0_uid181_constMult_q <= "011011000010000110000110100110110000001111011010011011100010010011010";
WHEN "101000" => p0_uid181_constMult_q <= "011011101110011101001110111110101110001100100001101011000000101110000";
WHEN "101001" => p0_uid181_constMult_q <= "011100011010110100010111010110101100001001101000111010011111001000110";
WHEN "101010" => p0_uid181_constMult_q <= "011101000111001011011111101110101010000110110000001001111101100011100";
WHEN "101011" => p0_uid181_constMult_q <= "011101110011100010101000000110101000000011110111011001011011111110010";
WHEN "101100" => p0_uid181_constMult_q <= "011110011111111001110000011110100110000000111110101000111010011001000";
WHEN "101101" => p0_uid181_constMult_q <= "011111001100010000111000110110100011111110000101111000011000110011110";
WHEN "101110" => p0_uid181_constMult_q <= "011111111000101000000001001110100001111011001101000111110111001110100";
WHEN "101111" => p0_uid181_constMult_q <= "100000100100111111001001100110011111111000010100010111010101101001010";
WHEN "110000" => p0_uid181_constMult_q <= "100001010001010110010001111110011101110101011011100110110100000100000";
WHEN "110001" => p0_uid181_constMult_q <= "100001111101101101011010010110011011110010100010110110010010011110110";
WHEN "110010" => p0_uid181_constMult_q <= "100010101010000100100010101110011001101111101010000101110000111001100";
WHEN "110011" => p0_uid181_constMult_q <= "100011010110011011101011000110010111101100110001010101001111010100010";
WHEN "110100" => p0_uid181_constMult_q <= "100100000010110010110011011110010101101001111000100100101101101111000";
WHEN "110101" => p0_uid181_constMult_q <= "100100101111001001111011110110010011100110111111110100001100001001110";
WHEN "110110" => p0_uid181_constMult_q <= "100101011011100001000100001110010001100100000111000011101010100100100";
WHEN "110111" => p0_uid181_constMult_q <= "100110000111111000001100100110001111100001001110010011001000111111010";
WHEN "111000" => p0_uid181_constMult_q <= "100110110100001111010100111110001101011110010101100010100111011010000";
WHEN "111001" => p0_uid181_constMult_q <= "100111100000100110011101010110001011011011011100110010000101110100110";
WHEN "111010" => p0_uid181_constMult_q <= "101000001100111101100101101110001001011000100100000001100100001111100";
WHEN "111011" => p0_uid181_constMult_q <= "101000111001010100101110000110000111010101101011010001000010101010010";
WHEN "111100" => p0_uid181_constMult_q <= "101001100101101011110110011110000101010010110010100000100001000101000";
WHEN "111101" => p0_uid181_constMult_q <= "101010010010000010111110110110000011001111111001101111111111011111110";
WHEN "111110" => p0_uid181_constMult_q <= "101010111110011010000111001110000001001101000000111111011101111010100";
WHEN "111111" => p0_uid181_constMult_q <= "101011101010110001001111100101111111001010001000001110111100010101010";
WHEN OTHERS =>
p0_uid181_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid177_constMult(BITSELECT,176)@8
xv1_uid177_constMult_in <= ePreRnd_uid46_fpExpETest_b(11 downto 0);
xv1_uid177_constMult_b <= xv1_uid177_constMult_in(11 downto 6);
--ld_xv1_uid177_constMult_b_to_reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_a(DELAY,825)@8
ld_xv1_uid177_constMult_b_to_reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => xv1_uid177_constMult_b, xout => ld_xv1_uid177_constMult_b_to_reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0(REG,371)@9
reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_q <= ld_xv1_uid177_constMult_b_to_reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p1_uid180_constMult(LOOKUP,179)@10
p1_uid180_constMult: PROCESS (reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv1_uid177_constMult_0_to_p1_uid180_constMult_0_q) IS
WHEN "000000" => p1_uid180_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid180_constMult_q <= "000000101100010111001000010111111101111101000111001111011110011010110000000";
WHEN "000010" => p1_uid180_constMult_q <= "000001011000101110010000101111111011111010001110011110111100110101100000000";
WHEN "000011" => p1_uid180_constMult_q <= "000010000101000101011001000111111001110111010101101110011011010000010000000";
WHEN "000100" => p1_uid180_constMult_q <= "000010110001011100100001011111110111110100011100111101111001101011000000000";
WHEN "000101" => p1_uid180_constMult_q <= "000011011101110011101001110111110101110001100100001101011000000101110000000";
WHEN "000110" => p1_uid180_constMult_q <= "000100001010001010110010001111110011101110101011011100110110100000100000000";
WHEN "000111" => p1_uid180_constMult_q <= "000100110110100001111010100111110001101011110010101100010100111011010000000";
WHEN "001000" => p1_uid180_constMult_q <= "000101100010111001000010111111101111101000111001111011110011010110000000000";
WHEN "001001" => p1_uid180_constMult_q <= "000110001111010000001011010111101101100110000001001011010001110000110000000";
WHEN "001010" => p1_uid180_constMult_q <= "000110111011100111010011101111101011100011001000011010110000001011100000000";
WHEN "001011" => p1_uid180_constMult_q <= "000111100111111110011100000111101001100000001111101010001110100110010000000";
WHEN "001100" => p1_uid180_constMult_q <= "001000010100010101100100011111100111011101010110111001101101000001000000000";
WHEN "001101" => p1_uid180_constMult_q <= "001001000000101100101100110111100101011010011110001001001011011011110000000";
WHEN "001110" => p1_uid180_constMult_q <= "001001101101000011110101001111100011010111100101011000101001110110100000000";
WHEN "001111" => p1_uid180_constMult_q <= "001010011001011010111101100111100001010100101100101000001000010001010000000";
WHEN "010000" => p1_uid180_constMult_q <= "001011000101110010000101111111011111010001110011110111100110101100000000000";
WHEN "010001" => p1_uid180_constMult_q <= "001011110010001001001110010111011101001110111011000111000101000110110000000";
WHEN "010010" => p1_uid180_constMult_q <= "001100011110100000010110101111011011001100000010010110100011100001100000000";
WHEN "010011" => p1_uid180_constMult_q <= "001101001010110111011111000111011001001001001001100110000001111100010000000";
WHEN "010100" => p1_uid180_constMult_q <= "001101110111001110100111011111010111000110010000110101100000010111000000000";
WHEN "010101" => p1_uid180_constMult_q <= "001110100011100101101111110111010101000011011000000100111110110001110000000";
WHEN "010110" => p1_uid180_constMult_q <= "001111001111111100111000001111010011000000011111010100011101001100100000000";
WHEN "010111" => p1_uid180_constMult_q <= "001111111100010100000000100111010000111101100110100011111011100111010000000";
WHEN "011000" => p1_uid180_constMult_q <= "010000101000101011001000111111001110111010101101110011011010000010000000000";
WHEN "011001" => p1_uid180_constMult_q <= "010001010101000010010001010111001100110111110101000010111000011100110000000";
WHEN "011010" => p1_uid180_constMult_q <= "010010000001011001011001101111001010110100111100010010010110110111100000000";
WHEN "011011" => p1_uid180_constMult_q <= "010010101101110000100010000111001000110010000011100001110101010010010000000";
WHEN "011100" => p1_uid180_constMult_q <= "010011011010000111101010011111000110101111001010110001010011101101000000000";
WHEN "011101" => p1_uid180_constMult_q <= "010100000110011110110010110111000100101100010010000000110010000111110000000";
WHEN "011110" => p1_uid180_constMult_q <= "010100110010110101111011001111000010101001011001010000010000100010100000000";
WHEN "011111" => p1_uid180_constMult_q <= "010101011111001101000011100111000000100110100000011111101110111101010000000";
WHEN "100000" => p1_uid180_constMult_q <= "010110001011100100001011111110111110100011100111101111001101011000000000000";
WHEN "100001" => p1_uid180_constMult_q <= "010110110111111011010100010110111100100000101110111110101011110010110000000";
WHEN "100010" => p1_uid180_constMult_q <= "010111100100010010011100101110111010011101110110001110001010001101100000000";
WHEN "100011" => p1_uid180_constMult_q <= "011000010000101001100101000110111000011010111101011101101000101000010000000";
WHEN "100100" => p1_uid180_constMult_q <= "011000111101000000101101011110110110011000000100101101000111000011000000000";
WHEN "100101" => p1_uid180_constMult_q <= "011001101001010111110101110110110100010101001011111100100101011101110000000";
WHEN "100110" => p1_uid180_constMult_q <= "011010010101101110111110001110110010010010010011001100000011111000100000000";
WHEN "100111" => p1_uid180_constMult_q <= "011011000010000110000110100110110000001111011010011011100010010011010000000";
WHEN "101000" => p1_uid180_constMult_q <= "011011101110011101001110111110101110001100100001101011000000101110000000000";
WHEN "101001" => p1_uid180_constMult_q <= "011100011010110100010111010110101100001001101000111010011111001000110000000";
WHEN "101010" => p1_uid180_constMult_q <= "011101000111001011011111101110101010000110110000001001111101100011100000000";
WHEN "101011" => p1_uid180_constMult_q <= "011101110011100010101000000110101000000011110111011001011011111110010000000";
WHEN "101100" => p1_uid180_constMult_q <= "011110011111111001110000011110100110000000111110101000111010011001000000000";
WHEN "101101" => p1_uid180_constMult_q <= "011111001100010000111000110110100011111110000101111000011000110011110000000";
WHEN "101110" => p1_uid180_constMult_q <= "011111111000101000000001001110100001111011001101000111110111001110100000000";
WHEN "101111" => p1_uid180_constMult_q <= "100000100100111111001001100110011111111000010100010111010101101001010000000";
WHEN "110000" => p1_uid180_constMult_q <= "100001010001010110010001111110011101110101011011100110110100000100000000000";
WHEN "110001" => p1_uid180_constMult_q <= "100001111101101101011010010110011011110010100010110110010010011110110000000";
WHEN "110010" => p1_uid180_constMult_q <= "100010101010000100100010101110011001101111101010000101110000111001100000000";
WHEN "110011" => p1_uid180_constMult_q <= "100011010110011011101011000110010111101100110001010101001111010100010000000";
WHEN "110100" => p1_uid180_constMult_q <= "100100000010110010110011011110010101101001111000100100101101101111000000000";
WHEN "110101" => p1_uid180_constMult_q <= "100100101111001001111011110110010011100110111111110100001100001001110000000";
WHEN "110110" => p1_uid180_constMult_q <= "100101011011100001000100001110010001100100000111000011101010100100100000000";
WHEN "110111" => p1_uid180_constMult_q <= "100110000111111000001100100110001111100001001110010011001000111111010000000";
WHEN "111000" => p1_uid180_constMult_q <= "100110110100001111010100111110001101011110010101100010100111011010000000000";
WHEN "111001" => p1_uid180_constMult_q <= "100111100000100110011101010110001011011011011100110010000101110100110000000";
WHEN "111010" => p1_uid180_constMult_q <= "101000001100111101100101101110001001011000100100000001100100001111100000000";
WHEN "111011" => p1_uid180_constMult_q <= "101000111001010100101110000110000111010101101011010001000010101010010000000";
WHEN "111100" => p1_uid180_constMult_q <= "101001100101101011110110011110000101010010110010100000100001000101000000000";
WHEN "111101" => p1_uid180_constMult_q <= "101010010010000010111110110110000011001111111001101111111111011111110000000";
WHEN "111110" => p1_uid180_constMult_q <= "101010111110011010000111001110000001001101000000111111011101111010100000000";
WHEN "111111" => p1_uid180_constMult_q <= "101011101010110001001111100101111111001010001000001110111100010101010000000";
WHEN OTHERS =>
p1_uid180_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv2_uid178_constMult(BITSELECT,177)@8
xv2_uid178_constMult_in <= ePreRnd_uid46_fpExpETest_b;
xv2_uid178_constMult_b <= xv2_uid178_constMult_in(13 downto 12);
--reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0(REG,370)@8
reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0_q <= xv2_uid178_constMult_b;
END IF;
END IF;
END PROCESS;
--p2_uid179_constMult(LOOKUP,178)@9
p2_uid179_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p2_uid179_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv2_uid178_constMult_0_to_p2_uid179_constMult_0_q) IS
WHEN "00" => p2_uid179_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "01" => p2_uid179_constMult_q <= "00101100010111001000010111111101111101000111001111011110011010110000000000000";
WHEN "10" => p2_uid179_constMult_q <= "10100111010001101111010000000100000101110001100001000011001010100000000000000";
WHEN "11" => p2_uid179_constMult_q <= "11010011101000110111101000000010000010111000110000100001100101010000000000000";
WHEN OTHERS =>
p2_uid179_constMult_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid182_constMult(ADD,181)@10
lev1_a0_uid182_constMult_a <= STD_LOGIC_VECTOR((78 downto 77 => p2_uid179_constMult_q(76)) & p2_uid179_constMult_q);
lev1_a0_uid182_constMult_b <= STD_LOGIC_VECTOR('0' & "000" & p1_uid180_constMult_q);
lev1_a0_uid182_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
lev1_a0_uid182_constMult_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
lev1_a0_uid182_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid182_constMult_a) + SIGNED(lev1_a0_uid182_constMult_b));
END IF;
END IF;
END PROCESS;
lev1_a0_uid182_constMult_q <= lev1_a0_uid182_constMult_o(77 downto 0);
--lev2_a0_uid183_constMult(ADD,182)@11
lev2_a0_uid183_constMult_a <= STD_LOGIC_VECTOR((79 downto 78 => lev1_a0_uid182_constMult_q(77)) & lev1_a0_uid182_constMult_q);
lev2_a0_uid183_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000000" & p0_uid181_constMult_q);
lev2_a0_uid183_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev2_a0_uid183_constMult_a) + SIGNED(lev2_a0_uid183_constMult_b));
lev2_a0_uid183_constMult_q <= lev2_a0_uid183_constMult_o(78 downto 0);
--sR_uid184_constMult(BITSELECT,183)@11
sR_uid184_constMult_in <= lev2_a0_uid183_constMult_q(76 downto 0);
sR_uid184_constMult_b <= sR_uid184_constMult_in(76 downto 2);
--reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1(REG,374)@11
reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1_q <= sR_uid184_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b(DELAY,456)@0
ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 8 )
PORT MAP ( xin => signX_uid7_fpExpETest_b, xout => ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor(LOGICAL,898)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_b <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_q <= not (ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_a or ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_b);
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_mem_top(CONSTANT,894)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_mem_top_q <= "0101";
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp(LOGICAL,895)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_a <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_mem_top_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q);
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_q <= "1" when ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_a = ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_b else "0";
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg(REG,896)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena(REG,899)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_nor_q = "1") THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd(LOGICAL,900)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_a <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_sticky_ena_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_b <= en;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_a and ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_b;
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_inputreg(DELAY,888)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oFracX_uid32_uid32_fpExpETest_q, xout => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt(COUNTER,890)
-- every=1, low=0, high=5, step=1, init=1
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i = 4 THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_eq <= '1';
ELSE
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_eq = '1') THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i - 5;
ELSE
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_i,3));
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg(REG,891)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux(MUX,892)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_s <= en;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux: PROCESS (ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_s, ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q, ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_q)
BEGIN
CASE ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_s IS
WHEN "0" => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q;
WHEN "1" => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdcnt_q;
WHEN OTHERS => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem(DUALMEM,889)
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ia <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_inputreg_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_aa <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ab <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 6,
width_b => 53,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_iq,
address_a => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_aa,
data_a => ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_ia
);
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_reset0 <= areset;
ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_iq(52 downto 0);
--cstZeroWEP1_uid12_fpExpETest(CONSTANT,11)
cstZeroWEP1_uid12_fpExpETest_q <= "000000000000";
--oFracXZwE_uid48_fpExpETest(BITJOIN,47)@8
oFracXZwE_uid48_fpExpETest_q <= GND_q & ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_mem_q & cstZeroWEP1_uid12_fpExpETest_q;
--onesCmpFxpIn_uid49_fpExpETest(LOGICAL,48)@8
onesCmpFxpIn_uid49_fpExpETest_a <= oFracXZwE_uid48_fpExpETest_q;
onesCmpFxpIn_uid49_fpExpETest_b <= STD_LOGIC_VECTOR((65 downto 1 => ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b_q(0)) & ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b_q);
onesCmpFxpIn_uid49_fpExpETest_q <= onesCmpFxpIn_uid49_fpExpETest_a xor onesCmpFxpIn_uid49_fpExpETest_b;
--fxpInExt_uid50_fpExpETest(ADD,49)@8
fxpInExt_uid50_fpExpETest_a <= STD_LOGIC_VECTOR((67 downto 66 => onesCmpFxpIn_uid49_fpExpETest_q(65)) & onesCmpFxpIn_uid49_fpExpETest_q);
fxpInExt_uid50_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000000000000000000000000000000000000000" & ld_signX_uid7_fpExpETest_b_to_onesCmpFxpIn_uid49_fpExpETest_b_q);
fxpInExt_uid50_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(fxpInExt_uid50_fpExpETest_a) + SIGNED(fxpInExt_uid50_fpExpETest_b));
fxpInExt_uid50_fpExpETest_q <= fxpInExt_uid50_fpExpETest_o(66 downto 0);
--fxpInPreAlign_uid51_fpExpETest(BITSELECT,50)@8
fxpInPreAlign_uid51_fpExpETest_in <= fxpInExt_uid50_fpExpETest_q(65 downto 0);
fxpInPreAlign_uid51_fpExpETest_b <= fxpInPreAlign_uid51_fpExpETest_in(65 downto 0);
--msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,185)@8
msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_in <= fxpInPreAlign_uid51_fpExpETest_b;
msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b <= msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 65);
--rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,227)@8
rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_a <= GND_q;
rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_b <= msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_to_rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,670)@9
ld_rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_to_rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q, xout => ld_rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_to_rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,228)@11
RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 1);
--rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,229)@11
rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_q <= ld_rightShiftStage3Idx1Pad1_uid228_fxpInPostAlign_X_uid56_fpExpETest_q_to_rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_b_q & RightShiftStage265dto1_uid229_fxpInPostAlign_X_uid56_fpExpETest_b;
--ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,650)@8
ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,221)@10
rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid163_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((5 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 6, depth => 1)
PORT MAP (xout => rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,633)@8
ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,207)@9
rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid149_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((23 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 24, depth => 1)
PORT MAP (xout => rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx3_uid195_fxpInPostAlign_X_uid56_fpExpETest(CONSTANT,194)
rightShiftStage0Idx3_uid195_fxpInPostAlign_X_uid56_fpExpETest_q <= "000000000000000000000000000000000000000000000000000000000000000000";
--rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,195)@8
rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_a <= rightShiftStage0Idx3_uid195_fxpInPostAlign_X_uid56_fpExpETest_q;
rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((65 downto 1 => msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b(0)) & msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b);
rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 66, depth => 1)
PORT MAP (xout => rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,191)@8
rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid133_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((63 downto 1 => msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b(0)) & msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b);
rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_b;
--X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,192)@8
X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_in <= fxpInPreAlign_uid51_fpExpETest_b;
X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_b <= X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 64);
--rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,193)@8
rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage0Idx2Pad64_uid192_fxpInPostAlign_X_uid56_fpExpETest_q & X65dto64_uid193_fxpInPostAlign_X_uid56_fpExpETest_b;
--reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4(REG,364)@8
reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4_q <= rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,187)@8
rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid129_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((31 downto 1 => msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b(0)) & msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b);
rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_b;
--X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,188)@8
X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_in <= fxpInPreAlign_uid51_fpExpETest_b;
X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_b <= X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 32);
--rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,189)@8
rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage0Idx1Pad32_uid188_fxpInPostAlign_X_uid56_fpExpETest_q & X65dto32_uid189_fxpInPostAlign_X_uid56_fpExpETest_b;
--reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3(REG,363)@8
reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3_q <= rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2(REG,362)@8
reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2_q <= fxpInPreAlign_uid51_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,628)@6
ld_reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 3 )
PORT MAP ( xin => reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid140_fxpInPostAlign_uid45_fpExpETest_1_q, xout => ld_reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest(MUX,197)@9
rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_s <= ld_reg_rightShiftStageSel6Dto5_uid139_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_b_q;
rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest: PROCESS (rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_s, en, reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2_q, reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3_q, reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4_q, rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q)
BEGIN
CASE rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_s IS
WHEN "00" => rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q <= reg_fxpInPreAlign_uid51_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_2_q;
WHEN "01" => rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q <= reg_rightShiftStage0Idx1_uid190_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_3_q;
WHEN "10" => rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q <= reg_rightShiftStage0Idx2_uid194_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_4_q;
WHEN "11" => rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage0Idx3_uid196_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN OTHERS => rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,208)@9
RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 24);
--ld_RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,643)@9
ld_RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 42, depth => 1 )
PORT MAP ( xin => RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,209)@10
rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx3Pad24_uid208_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage065dto24_uid209_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,203)@9
rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid145_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((15 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 16, depth => 1)
PORT MAP (xout => rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,204)@9
RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 16);
--ld_RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,639)@9
ld_RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 50, depth => 1 )
PORT MAP ( xin => RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,205)@10
rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx2Pad16_uid204_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage065dto16_uid205_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,199)@9
rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid141_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((7 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 8, depth => 1)
PORT MAP (xout => rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,200)@9
RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 8);
--ld_RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,635)@9
ld_RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,201)@10
rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx1Pad8_uid200_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage065dto8_uid201_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2(REG,366)@9
reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2_q <= rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1(REG,365)@5
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q <= rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,645)@6
ld_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 4 )
PORT MAP ( xin => reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q, xout => ld_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest(MUX,211)@10
rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_s <= ld_reg_rightShiftStageSel4Dto3_uid153_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_b_q;
rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest: PROCESS (rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_s, en, reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2_q, rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_q, rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_q, rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_q)
BEGIN
CASE rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_s IS
WHEN "00" => rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q <= reg_rightShiftStage0_uid198_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_2_q;
WHEN "01" => rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx1_uid202_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN "10" => rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx2_uid206_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN "11" => rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage1Idx3_uid210_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN OTHERS => rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,222)@10
RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 6);
--ld_RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,660)@10
ld_RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,223)@11
rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx3Pad6_uid222_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage165dto6_uid223_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,217)@10
rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid159_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((3 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 4, depth => 1)
PORT MAP (xout => rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,218)@10
RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 4);
--ld_RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,656)@10
ld_RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,219)@11
rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx2Pad4_uid218_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage165dto4_uid219_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest(LOGICAL,213)@10
rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_a <= z_uid155_fxpInPostAlign_uid45_fpExpETest_q;
rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b <= STD_LOGIC_VECTOR((1 downto 1 => ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q(0)) & ld_msbx_uid186_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b_q);
rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q_i <= rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_a or rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_b;
rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 2, depth => 1)
PORT MAP (xout => rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q, xin => rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest(BITSELECT,214)@10
RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_in <= rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q;
RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b <= RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_in(65 downto 2);
--ld_RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_a(DELAY,652)@10
ld_RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b, xout => ld_RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest(BITJOIN,215)@11
rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx1Pad2_uid214_fxpInPostAlign_X_uid56_fpExpETest_q & ld_RightShiftStage165dto2_uid215_fxpInPostAlign_X_uid56_fpExpETest_b_to_rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_a_q;
--reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2(REG,368)@10
reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2_q <= rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_a(DELAY,821)@5
ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 5 )
PORT MAP ( xin => rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b, xout => ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1(REG,367)@10
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_q <= ld_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_b_to_reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest(MUX,225)@11
rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_s <= reg_rightShiftStageSel2Dto1_uid167_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_1_q;
rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest: PROCESS (rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_s, en, reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2_q, rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_q, rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_q, rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_q)
BEGIN
CASE rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_s IS
WHEN "00" => rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q <= reg_rightShiftStage1_uid212_fxpInPostAlign_X_uid56_fpExpETest_0_to_rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_2_q;
WHEN "01" => rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx1_uid216_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN "10" => rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx2_uid220_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN "11" => rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2Idx3_uid224_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN OTHERS => rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1(REG,369)@5
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q <= rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_b(DELAY,671)@6
ld_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest(MUX,231)@11
rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_s <= ld_reg_rightShiftStageSel0Dto0_uid173_fxpInPostAlign_uid45_fpExpETest_0_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_1_q_to_rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_b_q;
rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest: PROCESS (rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_s, en, rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q, rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_q)
BEGIN
CASE rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_s IS
WHEN "0" => rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage2_uid226_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN "1" => rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_q <= rightShiftStage3Idx1_uid230_fxpInPostAlign_X_uid56_fpExpETest_q;
WHEN OTHERS => rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest(BITJOIN,56)@11
pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_q <= rightShiftStage3_uid232_fxpInPostAlign_X_uid56_fpExpETest_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0(REG,373)@11
reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0_q <= pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--yExt_uid57_fpExpETest(SUB,57)@12
yExt_uid57_fpExpETest_a <= STD_LOGIC_VECTOR((75 downto 74 => reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0_q(73)) & reg_pad_fxpInPostAlignR_X_uid57_uid57_fpExpETest_0_to_yExt_uid57_fpExpETest_0_q);
yExt_uid57_fpExpETest_b <= STD_LOGIC_VECTOR((75 downto 75 => reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1_q(74)) & reg_sR_uid184_constMult_0_to_yExt_uid57_fpExpETest_1_q);
yExt_uid57_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(yExt_uid57_fpExpETest_a) - SIGNED(yExt_uid57_fpExpETest_b));
yExt_uid57_fpExpETest_q <= yExt_uid57_fpExpETest_o(75 downto 0);
--yRed_uid61_fpExpETest(BITSELECT,60)@12
yRed_uid61_fpExpETest_in <= yExt_uid57_fpExpETest_q(60 downto 0);
yRed_uid61_fpExpETest_b <= yRed_uid61_fpExpETest_in(60 downto 6);
--reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2(REG,376)@12
reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2_q <= yRed_uid61_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--YExt75_uid59_fpExpETest(BITSELECT,58)@12
YExt75_uid59_fpExpETest_in <= yExt_uid57_fpExpETest_q;
YExt75_uid59_fpExpETest_b <= YExt75_uid59_fpExpETest_in(75 downto 75);
--reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1(REG,375)@12
reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1_q <= YExt75_uid59_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--yRedPostMux_uid62_fpExpETest(MUX,61)@13
yRedPostMux_uid62_fpExpETest_s <= reg_YExt75_uid59_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_1_q;
yRedPostMux_uid62_fpExpETest: PROCESS (yRedPostMux_uid62_fpExpETest_s, en, reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2_q, zY_uid60_fpExpETest_q)
BEGIN
CASE yRedPostMux_uid62_fpExpETest_s IS
WHEN "0" => yRedPostMux_uid62_fpExpETest_q <= reg_yRed_uid61_fpExpETest_0_to_yRedPostMux_uid62_fpExpETest_2_q;
WHEN "1" => yRedPostMux_uid62_fpExpETest_q <= zY_uid60_fpExpETest_q;
WHEN OTHERS => yRedPostMux_uid62_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid64_fpExpETest(BITSELECT,63)@13
addr_uid64_fpExpETest_in <= yRedPostMux_uid62_fpExpETest_q;
addr_uid64_fpExpETest_b <= addr_uid64_fpExpETest_in(54 downto 48);
--reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0(REG,378)@13
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q <= addr_uid64_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--memoryC5_uid247_exp10TabGen(LOOKUP,246)@14
memoryC5_uid247_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC5_uid247_exp10TabGen_q <= "0010001001000001";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC5_uid247_exp10TabGen_q <= "0010001001000001";
WHEN "0000001" => memoryC5_uid247_exp10TabGen_q <= "0010001001001000";
WHEN "0000010" => memoryC5_uid247_exp10TabGen_q <= "0010001010101001";
WHEN "0000011" => memoryC5_uid247_exp10TabGen_q <= "0010001011011100";
WHEN "0000100" => memoryC5_uid247_exp10TabGen_q <= "0010001101001010";
WHEN "0000101" => memoryC5_uid247_exp10TabGen_q <= "0010001110011101";
WHEN "0000110" => memoryC5_uid247_exp10TabGen_q <= "0010001111011110";
WHEN "0000111" => memoryC5_uid247_exp10TabGen_q <= "0010010000100001";
WHEN "0001000" => memoryC5_uid247_exp10TabGen_q <= "0010010001111001";
WHEN "0001001" => memoryC5_uid247_exp10TabGen_q <= "0010010010110011";
WHEN "0001010" => memoryC5_uid247_exp10TabGen_q <= "0010010100011101";
WHEN "0001011" => memoryC5_uid247_exp10TabGen_q <= "0010010110010001";
WHEN "0001100" => memoryC5_uid247_exp10TabGen_q <= "0010010110110101";
WHEN "0001101" => memoryC5_uid247_exp10TabGen_q <= "0010010111001010";
WHEN "0001110" => memoryC5_uid247_exp10TabGen_q <= "0010011000110010";
WHEN "0001111" => memoryC5_uid247_exp10TabGen_q <= "0010011010111110";
WHEN "0010000" => memoryC5_uid247_exp10TabGen_q <= "0010011010111110";
WHEN "0010001" => memoryC5_uid247_exp10TabGen_q <= "0010011100001100";
WHEN "0010010" => memoryC5_uid247_exp10TabGen_q <= "0010011110000010";
WHEN "0010011" => memoryC5_uid247_exp10TabGen_q <= "0010011110101001";
WHEN "0010100" => memoryC5_uid247_exp10TabGen_q <= "0010100001000000";
WHEN "0010101" => memoryC5_uid247_exp10TabGen_q <= "0010100001011000";
WHEN "0010110" => memoryC5_uid247_exp10TabGen_q <= "0010100011000011";
WHEN "0010111" => memoryC5_uid247_exp10TabGen_q <= "0010100011110110";
WHEN "0011000" => memoryC5_uid247_exp10TabGen_q <= "0010100101111001";
WHEN "0011001" => memoryC5_uid247_exp10TabGen_q <= "0010100111010011";
WHEN "0011010" => memoryC5_uid247_exp10TabGen_q <= "0010100111110111";
WHEN "0011011" => memoryC5_uid247_exp10TabGen_q <= "0010101001011010";
WHEN "0011100" => memoryC5_uid247_exp10TabGen_q <= "0010101011000110";
WHEN "0011101" => memoryC5_uid247_exp10TabGen_q <= "0010101100100101";
WHEN "0011110" => memoryC5_uid247_exp10TabGen_q <= "0010101110000010";
WHEN "0011111" => memoryC5_uid247_exp10TabGen_q <= "0010101110001011";
WHEN "0100000" => memoryC5_uid247_exp10TabGen_q <= "0010110000000101";
WHEN "0100001" => memoryC5_uid247_exp10TabGen_q <= "0010110001011010";
WHEN "0100010" => memoryC5_uid247_exp10TabGen_q <= "0010110010000000";
WHEN "0100011" => memoryC5_uid247_exp10TabGen_q <= "0010110011110100";
WHEN "0100100" => memoryC5_uid247_exp10TabGen_q <= "0010110101111111";
WHEN "0100101" => memoryC5_uid247_exp10TabGen_q <= "0010110110001011";
WHEN "0100110" => memoryC5_uid247_exp10TabGen_q <= "0010111000011100";
WHEN "0100111" => memoryC5_uid247_exp10TabGen_q <= "0010111001101110";
WHEN "0101000" => memoryC5_uid247_exp10TabGen_q <= "0010111010111100";
WHEN "0101001" => memoryC5_uid247_exp10TabGen_q <= "0010111100100000";
WHEN "0101010" => memoryC5_uid247_exp10TabGen_q <= "0010111111001011";
WHEN "0101011" => memoryC5_uid247_exp10TabGen_q <= "0010111111101000";
WHEN "0101100" => memoryC5_uid247_exp10TabGen_q <= "0011000001111110";
WHEN "0101101" => memoryC5_uid247_exp10TabGen_q <= "0011000010101011";
WHEN "0101110" => memoryC5_uid247_exp10TabGen_q <= "0011000011100011";
WHEN "0101111" => memoryC5_uid247_exp10TabGen_q <= "0011000110001011";
WHEN "0110000" => memoryC5_uid247_exp10TabGen_q <= "0011000111101010";
WHEN "0110001" => memoryC5_uid247_exp10TabGen_q <= "0011001001011010";
WHEN "0110010" => memoryC5_uid247_exp10TabGen_q <= "0011001010111110";
WHEN "0110011" => memoryC5_uid247_exp10TabGen_q <= "0011001100101111";
WHEN "0110100" => memoryC5_uid247_exp10TabGen_q <= "0011001101111011";
WHEN "0110101" => memoryC5_uid247_exp10TabGen_q <= "0011001110111001";
WHEN "0110110" => memoryC5_uid247_exp10TabGen_q <= "0011010001010100";
WHEN "0110111" => memoryC5_uid247_exp10TabGen_q <= "0011010011001110";
WHEN "0111000" => memoryC5_uid247_exp10TabGen_q <= "0011010100011010";
WHEN "0111001" => memoryC5_uid247_exp10TabGen_q <= "0011010110001011";
WHEN "0111010" => memoryC5_uid247_exp10TabGen_q <= "0011010111100000";
WHEN "0111011" => memoryC5_uid247_exp10TabGen_q <= "0011011000111110";
WHEN "0111100" => memoryC5_uid247_exp10TabGen_q <= "0011011010100100";
WHEN "0111101" => memoryC5_uid247_exp10TabGen_q <= "0011011100101101";
WHEN "0111110" => memoryC5_uid247_exp10TabGen_q <= "0011011110000100";
WHEN "0111111" => memoryC5_uid247_exp10TabGen_q <= "0011100000111010";
WHEN "1000000" => memoryC5_uid247_exp10TabGen_q <= "0011100010101001";
WHEN "1000001" => memoryC5_uid247_exp10TabGen_q <= "0011100011011011";
WHEN "1000010" => memoryC5_uid247_exp10TabGen_q <= "0011100100101101";
WHEN "1000011" => memoryC5_uid247_exp10TabGen_q <= "0011100111101001";
WHEN "1000100" => memoryC5_uid247_exp10TabGen_q <= "0011101001001000";
WHEN "1000101" => memoryC5_uid247_exp10TabGen_q <= "0011101010110010";
WHEN "1000110" => memoryC5_uid247_exp10TabGen_q <= "0011101101011011";
WHEN "1000111" => memoryC5_uid247_exp10TabGen_q <= "0011101110010100";
WHEN "1001000" => memoryC5_uid247_exp10TabGen_q <= "0011110000111010";
WHEN "1001001" => memoryC5_uid247_exp10TabGen_q <= "0011110010100100";
WHEN "1001010" => memoryC5_uid247_exp10TabGen_q <= "0011110100011110";
WHEN "1001011" => memoryC5_uid247_exp10TabGen_q <= "0011110101101011";
WHEN "1001100" => memoryC5_uid247_exp10TabGen_q <= "0011110111101011";
WHEN "1001101" => memoryC5_uid247_exp10TabGen_q <= "0011111001110000";
WHEN "1001110" => memoryC5_uid247_exp10TabGen_q <= "0011111100000010";
WHEN "1001111" => memoryC5_uid247_exp10TabGen_q <= "0011111110001010";
WHEN "1010000" => memoryC5_uid247_exp10TabGen_q <= "0011111111110011";
WHEN "1010001" => memoryC5_uid247_exp10TabGen_q <= "0100000010000111";
WHEN "1010010" => memoryC5_uid247_exp10TabGen_q <= "0100000011100011";
WHEN "1010011" => memoryC5_uid247_exp10TabGen_q <= "0100000101110000";
WHEN "1010100" => memoryC5_uid247_exp10TabGen_q <= "0100000111111001";
WHEN "1010101" => memoryC5_uid247_exp10TabGen_q <= "0100001010101100";
WHEN "1010110" => memoryC5_uid247_exp10TabGen_q <= "0100001100100110";
WHEN "1010111" => memoryC5_uid247_exp10TabGen_q <= "0100001110000000";
WHEN "1011000" => memoryC5_uid247_exp10TabGen_q <= "0100010000010100";
WHEN "1011001" => memoryC5_uid247_exp10TabGen_q <= "0100010010100001";
WHEN "1011010" => memoryC5_uid247_exp10TabGen_q <= "0100010101011001";
WHEN "1011011" => memoryC5_uid247_exp10TabGen_q <= "0100011000000001";
WHEN "1011100" => memoryC5_uid247_exp10TabGen_q <= "0100011000101011";
WHEN "1011101" => memoryC5_uid247_exp10TabGen_q <= "0100011011000001";
WHEN "1011110" => memoryC5_uid247_exp10TabGen_q <= "0100011110001011";
WHEN "1011111" => memoryC5_uid247_exp10TabGen_q <= "0100100000010001";
WHEN "1100000" => memoryC5_uid247_exp10TabGen_q <= "0100100010001001";
WHEN "1100001" => memoryC5_uid247_exp10TabGen_q <= "0100100100101000";
WHEN "1100010" => memoryC5_uid247_exp10TabGen_q <= "0100100111010100";
WHEN "1100011" => memoryC5_uid247_exp10TabGen_q <= "0100101000111000";
WHEN "1100100" => memoryC5_uid247_exp10TabGen_q <= "0100101011100001";
WHEN "1100101" => memoryC5_uid247_exp10TabGen_q <= "0100101110010110";
WHEN "1100110" => memoryC5_uid247_exp10TabGen_q <= "0100110000100110";
WHEN "1100111" => memoryC5_uid247_exp10TabGen_q <= "0100110011000110";
WHEN "1101000" => memoryC5_uid247_exp10TabGen_q <= "0100110100111001";
WHEN "1101001" => memoryC5_uid247_exp10TabGen_q <= "0100110111010000";
WHEN "1101010" => memoryC5_uid247_exp10TabGen_q <= "0100111010100101";
WHEN "1101011" => memoryC5_uid247_exp10TabGen_q <= "0100111011110011";
WHEN "1101100" => memoryC5_uid247_exp10TabGen_q <= "0100111110000101";
WHEN "1101101" => memoryC5_uid247_exp10TabGen_q <= "0101000001001101";
WHEN "1101110" => memoryC5_uid247_exp10TabGen_q <= "0101000100000110";
WHEN "1101111" => memoryC5_uid247_exp10TabGen_q <= "0101000101110010";
WHEN "1110000" => memoryC5_uid247_exp10TabGen_q <= "0101001000100011";
WHEN "1110001" => memoryC5_uid247_exp10TabGen_q <= "0101001011000111";
WHEN "1110010" => memoryC5_uid247_exp10TabGen_q <= "0101001101110100";
WHEN "1110011" => memoryC5_uid247_exp10TabGen_q <= "0101010000111001";
WHEN "1110100" => memoryC5_uid247_exp10TabGen_q <= "0101010010100101";
WHEN "1110101" => memoryC5_uid247_exp10TabGen_q <= "0101010110001010";
WHEN "1110110" => memoryC5_uid247_exp10TabGen_q <= "0101011000010010";
WHEN "1110111" => memoryC5_uid247_exp10TabGen_q <= "0101011010111100";
WHEN "1111000" => memoryC5_uid247_exp10TabGen_q <= "0101011110010101";
WHEN "1111001" => memoryC5_uid247_exp10TabGen_q <= "0101011111111010";
WHEN "1111010" => memoryC5_uid247_exp10TabGen_q <= "0101100011000011";
WHEN "1111011" => memoryC5_uid247_exp10TabGen_q <= "0101100101011100";
WHEN "1111100" => memoryC5_uid247_exp10TabGen_q <= "0101101000101110";
WHEN "1111101" => memoryC5_uid247_exp10TabGen_q <= "0101101011100111";
WHEN "1111110" => memoryC5_uid247_exp10TabGen_q <= "0101101111011111";
WHEN "1111111" => memoryC5_uid247_exp10TabGen_q <= "0101110001010100";
WHEN OTHERS =>
memoryC5_uid247_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_yRedPostMux_uid62_fpExpETest_q_to_yPPolyEval_uid65_fpExpETest_a(DELAY,468)@13
ld_yRedPostMux_uid62_fpExpETest_q_to_yPPolyEval_uid65_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => yRedPostMux_uid62_fpExpETest_q, xout => ld_yRedPostMux_uid62_fpExpETest_q_to_yPPolyEval_uid65_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid65_fpExpETest(BITSELECT,64)@14
yPPolyEval_uid65_fpExpETest_in <= ld_yRedPostMux_uid62_fpExpETest_q_to_yPPolyEval_uid65_fpExpETest_a_q(47 downto 0);
yPPolyEval_uid65_fpExpETest_b <= yPPolyEval_uid65_fpExpETest_in(47 downto 0);
--yT1_uid249_exp10PolyEval(BITSELECT,248)@14
yT1_uid249_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b;
yT1_uid249_exp10PolyEval_b <= yT1_uid249_exp10PolyEval_in(47 downto 32);
--reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0(REG,384)@14
reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0_q <= yT1_uid249_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid280_pT1_uid250_exp10PolyEval(MULT,279)@15
prodXY_uid280_pT1_uid250_exp10PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid280_pT1_uid250_exp10PolyEval_a),17)) * SIGNED(prodXY_uid280_pT1_uid250_exp10PolyEval_b);
prodXY_uid280_pT1_uid250_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid280_pT1_uid250_exp10PolyEval_a <= (others => '0');
prodXY_uid280_pT1_uid250_exp10PolyEval_b <= (others => '0');
prodXY_uid280_pT1_uid250_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid280_pT1_uid250_exp10PolyEval_a <= reg_yT1_uid249_exp10PolyEval_0_to_prodXY_uid280_pT1_uid250_exp10PolyEval_0_q;
prodXY_uid280_pT1_uid250_exp10PolyEval_b <= memoryC5_uid247_exp10TabGen_q;
prodXY_uid280_pT1_uid250_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid280_pT1_uid250_exp10PolyEval_pr,32));
END IF;
END IF;
END PROCESS;
prodXY_uid280_pT1_uid250_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid280_pT1_uid250_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid280_pT1_uid250_exp10PolyEval_q <= prodXY_uid280_pT1_uid250_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval(BITSELECT,280)@18
prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_in <= prodXY_uid280_pT1_uid250_exp10PolyEval_q;
prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_b <= prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_in(31 downto 15);
--highBBits_uid252_exp10PolyEval(BITSELECT,251)@18
highBBits_uid252_exp10PolyEval_in <= prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_b;
highBBits_uid252_exp10PolyEval_b <= highBBits_uid252_exp10PolyEval_in(16 downto 1);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC4_uid245_exp10TabGen_0_q_to_memoryC4_uid245_exp10TabGen_a(DELAY,687)@14
ld_reg_addr_uid64_fpExpETest_0_to_memoryC4_uid245_exp10TabGen_0_q_to_memoryC4_uid245_exp10TabGen_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q, xout => ld_reg_addr_uid64_fpExpETest_0_to_memoryC4_uid245_exp10TabGen_0_q_to_memoryC4_uid245_exp10TabGen_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC4_uid245_exp10TabGen(LOOKUP,244)@17
memoryC4_uid245_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC4_uid245_exp10TabGen_q <= "0010101010101010100110111";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid64_fpExpETest_0_to_memoryC4_uid245_exp10TabGen_0_q_to_memoryC4_uid245_exp10TabGen_a_q) IS
WHEN "0000000" => memoryC4_uid245_exp10TabGen_q <= "0010101010101010100110111";
WHEN "0000001" => memoryC4_uid245_exp10TabGen_q <= "0010101100000000100101110";
WHEN "0000010" => memoryC4_uid245_exp10TabGen_q <= "0010101101010110110010011";
WHEN "0000011" => memoryC4_uid245_exp10TabGen_q <= "0010101110101101111001001";
WHEN "0000100" => memoryC4_uid245_exp10TabGen_q <= "0010110000000101011001111";
WHEN "0000101" => memoryC4_uid245_exp10TabGen_q <= "0010110001011101101101111";
WHEN "0000110" => memoryC4_uid245_exp10TabGen_q <= "0010110010110110110100011";
WHEN "0000111" => memoryC4_uid245_exp10TabGen_q <= "0010110100010000101001111";
WHEN "0001000" => memoryC4_uid245_exp10TabGen_q <= "0010110101101011000011010";
WHEN "0001001" => memoryC4_uid245_exp10TabGen_q <= "0010110111000110010011101";
WHEN "0001010" => memoryC4_uid245_exp10TabGen_q <= "0010111000100010000011100";
WHEN "0001011" => memoryC4_uid245_exp10TabGen_q <= "0010111001111110011110010";
WHEN "0001100" => memoryC4_uid245_exp10TabGen_q <= "0010111011011100000001001";
WHEN "0001101" => memoryC4_uid245_exp10TabGen_q <= "0010111100111010011010011";
WHEN "0001110" => memoryC4_uid245_exp10TabGen_q <= "0010111110011001000101000";
WHEN "0001111" => memoryC4_uid245_exp10TabGen_q <= "0010111111111000010100011";
WHEN "0010000" => memoryC4_uid245_exp10TabGen_q <= "0011000001011001000010010";
WHEN "0010001" => memoryC4_uid245_exp10TabGen_q <= "0011000010111010001000011";
WHEN "0010010" => memoryC4_uid245_exp10TabGen_q <= "0011000100011011101101111";
WHEN "0010011" => memoryC4_uid245_exp10TabGen_q <= "0011000101111110100011110";
WHEN "0010100" => memoryC4_uid245_exp10TabGen_q <= "0011000111100001100011000";
WHEN "0010101" => memoryC4_uid245_exp10TabGen_q <= "0011001001000101111111111";
WHEN "0010110" => memoryC4_uid245_exp10TabGen_q <= "0011001010101010110100100";
WHEN "0010111" => memoryC4_uid245_exp10TabGen_q <= "0011001100010000101101011";
WHEN "0011000" => memoryC4_uid245_exp10TabGen_q <= "0011001101110110111101111";
WHEN "0011001" => memoryC4_uid245_exp10TabGen_q <= "0011001111011110010000111";
WHEN "0011010" => memoryC4_uid245_exp10TabGen_q <= "0011010001000110101010101";
WHEN "0011011" => memoryC4_uid245_exp10TabGen_q <= "0011010010101111100100001";
WHEN "0011100" => memoryC4_uid245_exp10TabGen_q <= "0011010100011001001101011";
WHEN "0011101" => memoryC4_uid245_exp10TabGen_q <= "0011010110000011110001011";
WHEN "0011110" => memoryC4_uid245_exp10TabGen_q <= "0011010111101111001100101";
WHEN "0011111" => memoryC4_uid245_exp10TabGen_q <= "0011011001011011111000011";
WHEN "0100000" => memoryC4_uid245_exp10TabGen_q <= "0011011011001000110101101";
WHEN "0100001" => memoryC4_uid245_exp10TabGen_q <= "0011011100110110110111000";
WHEN "0100010" => memoryC4_uid245_exp10TabGen_q <= "0011011110100101111111111";
WHEN "0100011" => memoryC4_uid245_exp10TabGen_q <= "0011100000010101100111000";
WHEN "0100100" => memoryC4_uid245_exp10TabGen_q <= "0011100010000101111100000";
WHEN "0100101" => memoryC4_uid245_exp10TabGen_q <= "0011100011110111110110010";
WHEN "0100110" => memoryC4_uid245_exp10TabGen_q <= "0011100101101001111011110";
WHEN "0100111" => memoryC4_uid245_exp10TabGen_q <= "0011100111011101010011110";
WHEN "0101000" => memoryC4_uid245_exp10TabGen_q <= "0011101001010001100010110";
WHEN "0101001" => memoryC4_uid245_exp10TabGen_q <= "0011101011000110101000000";
WHEN "0101010" => memoryC4_uid245_exp10TabGen_q <= "0011101100111100001111000";
WHEN "0101011" => memoryC4_uid245_exp10TabGen_q <= "0011101110110011100001000";
WHEN "0101100" => memoryC4_uid245_exp10TabGen_q <= "0011110000101011000101111";
WHEN "0101101" => memoryC4_uid245_exp10TabGen_q <= "0011110010100100001011000";
WHEN "0101110" => memoryC4_uid245_exp10TabGen_q <= "0011110100011110001001010";
WHEN "0101111" => memoryC4_uid245_exp10TabGen_q <= "0011110110011000011111110";
WHEN "0110000" => memoryC4_uid245_exp10TabGen_q <= "0011111000010100001101010";
WHEN "0110001" => memoryC4_uid245_exp10TabGen_q <= "0011111010010000110001010";
WHEN "0110010" => memoryC4_uid245_exp10TabGen_q <= "0011111100001110011011010";
WHEN "0110011" => memoryC4_uid245_exp10TabGen_q <= "0011111110001100111101101";
WHEN "0110100" => memoryC4_uid245_exp10TabGen_q <= "0100000000001100101011001";
WHEN "0110101" => memoryC4_uid245_exp10TabGen_q <= "0100000010001101100001011";
WHEN "0110110" => memoryC4_uid245_exp10TabGen_q <= "0100000100001110111000001";
WHEN "0110111" => memoryC4_uid245_exp10TabGen_q <= "0100000110010001011001101";
WHEN "0111000" => memoryC4_uid245_exp10TabGen_q <= "0100001000010101001110001";
WHEN "0111001" => memoryC4_uid245_exp10TabGen_q <= "0100001010011001110101000";
WHEN "0111010" => memoryC4_uid245_exp10TabGen_q <= "0100001100011111101101100";
WHEN "0111011" => memoryC4_uid245_exp10TabGen_q <= "0100001110100110100010011";
WHEN "0111100" => memoryC4_uid245_exp10TabGen_q <= "0100010000101110011010110";
WHEN "0111101" => memoryC4_uid245_exp10TabGen_q <= "0100010010110111001010011";
WHEN "0111110" => memoryC4_uid245_exp10TabGen_q <= "0100010101000001010010000";
WHEN "0111111" => memoryC4_uid245_exp10TabGen_q <= "0100010111001011111100111";
WHEN "1000000" => memoryC4_uid245_exp10TabGen_q <= "0100011001011000000110010";
WHEN "1000001" => memoryC4_uid245_exp10TabGen_q <= "0100011011100101101010011";
WHEN "1000010" => memoryC4_uid245_exp10TabGen_q <= "0100011101110100001011000";
WHEN "1000011" => memoryC4_uid245_exp10TabGen_q <= "0100100000000011010000011";
WHEN "1000100" => memoryC4_uid245_exp10TabGen_q <= "0100100010010011111101000";
WHEN "1000101" => memoryC4_uid245_exp10TabGen_q <= "0100100100100101110001011";
WHEN "1000110" => memoryC4_uid245_exp10TabGen_q <= "0100100110111000010110111";
WHEN "1000111" => memoryC4_uid245_exp10TabGen_q <= "0100101001001100101100000";
WHEN "1001000" => memoryC4_uid245_exp10TabGen_q <= "0100101011100001101000110";
WHEN "1001001" => memoryC4_uid245_exp10TabGen_q <= "0100101101111000000100100";
WHEN "1001010" => memoryC4_uid245_exp10TabGen_q <= "0100110000001111100110101";
WHEN "1001011" => memoryC4_uid245_exp10TabGen_q <= "0100110010101000100001110";
WHEN "1001100" => memoryC4_uid245_exp10TabGen_q <= "0100110101000010011011010";
WHEN "1001101" => memoryC4_uid245_exp10TabGen_q <= "0100110111011101100001110";
WHEN "1001110" => memoryC4_uid245_exp10TabGen_q <= "0100111001111001101111111";
WHEN "1001111" => memoryC4_uid245_exp10TabGen_q <= "0100111100010111010001010";
WHEN "1010000" => memoryC4_uid245_exp10TabGen_q <= "0100111110110110001011011";
WHEN "1010001" => memoryC4_uid245_exp10TabGen_q <= "0101000001010110000111110";
WHEN "1010010" => memoryC4_uid245_exp10TabGen_q <= "0101000011110111101000110";
WHEN "1010011" => memoryC4_uid245_exp10TabGen_q <= "0101000110011010000111110";
WHEN "1010100" => memoryC4_uid245_exp10TabGen_q <= "0101001000111101111101011";
WHEN "1010101" => memoryC4_uid245_exp10TabGen_q <= "0101001011100010110100011";
WHEN "1010110" => memoryC4_uid245_exp10TabGen_q <= "0101001110001001010100001";
WHEN "1010111" => memoryC4_uid245_exp10TabGen_q <= "0101010000110001010011000";
WHEN "1011000" => memoryC4_uid245_exp10TabGen_q <= "0101010011011010010000001";
WHEN "1011001" => memoryC4_uid245_exp10TabGen_q <= "0101010110000100101000010";
WHEN "1011010" => memoryC4_uid245_exp10TabGen_q <= "0101011000110000000100011";
WHEN "1011011" => memoryC4_uid245_exp10TabGen_q <= "0101011011011100111110111";
WHEN "1011100" => memoryC4_uid245_exp10TabGen_q <= "0101011110001011111000111";
WHEN "1011101" => memoryC4_uid245_exp10TabGen_q <= "0101100000111011101001000";
WHEN "1011110" => memoryC4_uid245_exp10TabGen_q <= "0101100011101100011101001";
WHEN "1011111" => memoryC4_uid245_exp10TabGen_q <= "0101100110011111000100111";
WHEN "1100000" => memoryC4_uid245_exp10TabGen_q <= "0101101001010011001001110";
WHEN "1100001" => memoryC4_uid245_exp10TabGen_q <= "0101101100001000011001111";
WHEN "1100010" => memoryC4_uid245_exp10TabGen_q <= "0101101110111111000101011";
WHEN "1100011" => memoryC4_uid245_exp10TabGen_q <= "0101110001110111100010111";
WHEN "1100100" => memoryC4_uid245_exp10TabGen_q <= "0101110100110001000110101";
WHEN "1100101" => memoryC4_uid245_exp10TabGen_q <= "0101110111101100000011000";
WHEN "1100110" => memoryC4_uid245_exp10TabGen_q <= "0101111010101000101010001";
WHEN "1100111" => memoryC4_uid245_exp10TabGen_q <= "0101111101100110101011001";
WHEN "1101000" => memoryC4_uid245_exp10TabGen_q <= "0110000000100110011100100";
WHEN "1101001" => memoryC4_uid245_exp10TabGen_q <= "0110000011100111100001001";
WHEN "1101010" => memoryC4_uid245_exp10TabGen_q <= "0110000110101001110010101";
WHEN "1101011" => memoryC4_uid245_exp10TabGen_q <= "0110001001101110010010001";
WHEN "1101100" => memoryC4_uid245_exp10TabGen_q <= "0110001100110011111111000";
WHEN "1101101" => memoryC4_uid245_exp10TabGen_q <= "0110001111111010111100010";
WHEN "1101110" => memoryC4_uid245_exp10TabGen_q <= "0110010011000011100101011";
WHEN "1101111" => memoryC4_uid245_exp10TabGen_q <= "0110010110001110001010101";
WHEN "1110000" => memoryC4_uid245_exp10TabGen_q <= "0110011001011010000010001";
WHEN "1110001" => memoryC4_uid245_exp10TabGen_q <= "0110011100100111100001011";
WHEN "1110010" => memoryC4_uid245_exp10TabGen_q <= "0110011111110110101000110";
WHEN "1110011" => memoryC4_uid245_exp10TabGen_q <= "0110100011000111001100001";
WHEN "1110100" => memoryC4_uid245_exp10TabGen_q <= "0110100110011001111010000";
WHEN "1110101" => memoryC4_uid245_exp10TabGen_q <= "0110101001101101101000011";
WHEN "1110110" => memoryC4_uid245_exp10TabGen_q <= "0110101101000011011111100";
WHEN "1110111" => memoryC4_uid245_exp10TabGen_q <= "0110110000011010111001111";
WHEN "1111000" => memoryC4_uid245_exp10TabGen_q <= "0110110011110011101100100";
WHEN "1111001" => memoryC4_uid245_exp10TabGen_q <= "0110110111001110110110100";
WHEN "1111010" => memoryC4_uid245_exp10TabGen_q <= "0110111010101011001101011";
WHEN "1111011" => memoryC4_uid245_exp10TabGen_q <= "0110111110001001100010010";
WHEN "1111100" => memoryC4_uid245_exp10TabGen_q <= "0111000001101001010101001";
WHEN "1111101" => memoryC4_uid245_exp10TabGen_q <= "0111000101001011000010001";
WHEN "1111110" => memoryC4_uid245_exp10TabGen_q <= "0111001000101110001001100";
WHEN "1111111" => memoryC4_uid245_exp10TabGen_q <= "0111001100010011101111011";
WHEN OTHERS =>
memoryC4_uid245_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid253_exp10PolyEval(ADD,252)@18
sumAHighB_uid253_exp10PolyEval_a <= STD_LOGIC_VECTOR((25 downto 25 => memoryC4_uid245_exp10TabGen_q(24)) & memoryC4_uid245_exp10TabGen_q);
sumAHighB_uid253_exp10PolyEval_b <= STD_LOGIC_VECTOR((25 downto 16 => highBBits_uid252_exp10PolyEval_b(15)) & highBBits_uid252_exp10PolyEval_b);
sumAHighB_uid253_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid253_exp10PolyEval_a) + SIGNED(sumAHighB_uid253_exp10PolyEval_b));
sumAHighB_uid253_exp10PolyEval_q <= sumAHighB_uid253_exp10PolyEval_o(25 downto 0);
--lowRangeB_uid251_exp10PolyEval(BITSELECT,250)@18
lowRangeB_uid251_exp10PolyEval_in <= prodXYTruncFR_uid281_pT1_uid250_exp10PolyEval_b(0 downto 0);
lowRangeB_uid251_exp10PolyEval_b <= lowRangeB_uid251_exp10PolyEval_in(0 downto 0);
--s1_uid251_uid254_exp10PolyEval(BITJOIN,253)@18
s1_uid251_uid254_exp10PolyEval_q <= sumAHighB_uid253_exp10PolyEval_q & lowRangeB_uid251_exp10PolyEval_b;
--reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1(REG,387)@18
reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1_q <= s1_uid251_uid254_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor(LOGICAL,1157)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_b <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_q <= not (ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_a or ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_b);
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg(REG,1155)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena(REG,1158)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_nor_q = "1") THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd(LOGICAL,1159)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_a <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_sticky_ena_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_b <= en;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_a and ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_b;
--yT2_uid255_exp10PolyEval(BITSELECT,254)@14
yT2_uid255_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b;
yT2_uid255_exp10PolyEval_b <= yT2_uid255_exp10PolyEval_in(47 downto 23);
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_inputreg(DELAY,1149)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => yT2_uid255_exp10PolyEval_b, xout => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt(COUNTER,1151)
-- every=1, low=0, high=1, step=1, init=1
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_i <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_i,1));
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg(REG,1152)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux(MUX,1153)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_s <= en;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux: PROCESS (ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_s, ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q, ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem(DUALMEM,1150)
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ia <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_inputreg_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_aa <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdreg_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ab <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_rdmux_q;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 25,
widthad_a => 1,
numwords_a => 2,
width_b => 25,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_iq,
address_a => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_aa,
data_a => ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_ia
);
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_reset0 <= areset;
ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_iq(24 downto 0);
--reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0(REG,386)@18
reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_q <= "0000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_q <= ld_yT2_uid255_exp10PolyEval_b_to_reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid283_pT2_uid256_exp10PolyEval(MULT,282)@19
prodXY_uid283_pT2_uid256_exp10PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid283_pT2_uid256_exp10PolyEval_a),26)) * SIGNED(prodXY_uid283_pT2_uid256_exp10PolyEval_b);
prodXY_uid283_pT2_uid256_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid283_pT2_uid256_exp10PolyEval_a <= (others => '0');
prodXY_uid283_pT2_uid256_exp10PolyEval_b <= (others => '0');
prodXY_uid283_pT2_uid256_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid283_pT2_uid256_exp10PolyEval_a <= reg_yT2_uid255_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_0_q;
prodXY_uid283_pT2_uid256_exp10PolyEval_b <= reg_s1_uid251_uid254_exp10PolyEval_0_to_prodXY_uid283_pT2_uid256_exp10PolyEval_1_q;
prodXY_uid283_pT2_uid256_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid283_pT2_uid256_exp10PolyEval_pr,52));
END IF;
END IF;
END PROCESS;
prodXY_uid283_pT2_uid256_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid283_pT2_uid256_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid283_pT2_uid256_exp10PolyEval_q <= prodXY_uid283_pT2_uid256_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval(BITSELECT,283)@22
prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_in <= prodXY_uid283_pT2_uid256_exp10PolyEval_q;
prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_b <= prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_in(51 downto 24);
--highBBits_uid258_exp10PolyEval(BITSELECT,257)@22
highBBits_uid258_exp10PolyEval_in <= prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_b;
highBBits_uid258_exp10PolyEval_b <= highBBits_uid258_exp10PolyEval_in(27 downto 1);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor(LOGICAL,1055)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_b <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_q <= not (ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_a or ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_b);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_mem_top(CONSTANT,1051)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_mem_top_q <= "0100";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp(LOGICAL,1052)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_mem_top_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_q <= "1" when ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_a = ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_b else "0";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg(REG,1053)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena(REG,1056)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd(LOGICAL,1057)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_a and ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_b;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg(DELAY,1006)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q, xout => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt(COUNTER,1047)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i = 3 THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i - 4;
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_i,3));
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg(REG,1048)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux(MUX,1049)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_s, ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q, ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem(DUALMEM,1046)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ia <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_aa <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ab <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_rdmux_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 5,
width_b => 7,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_ia
);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_iq(6 downto 0);
--memoryC3_uid243_exp10TabGen(LOOKUP,242)@21
memoryC3_uid243_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC3_uid243_exp10TabGen_q <= "00101010101010101010101010101101111";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid64_fpExpETest_0_to_memoryC3_uid243_exp10TabGen_0_q_to_memoryC3_uid243_exp10TabGen_a_replace_mem_q) IS
WHEN "0000000" => memoryC3_uid243_exp10TabGen_q <= "00101010101010101010101010101101111";
WHEN "0000001" => memoryC3_uid243_exp10TabGen_q <= "00101011000000000101010101101011011";
WHEN "0000010" => memoryC3_uid243_exp10TabGen_q <= "00101011010101101010110001100001111";
WHEN "0000011" => memoryC3_uid243_exp10TabGen_q <= "00101011101011011011000010011000001";
WHEN "0000100" => memoryC3_uid243_exp10TabGen_q <= "00101100000001010110001110100011110";
WHEN "0000101" => memoryC3_uid243_exp10TabGen_q <= "00101100010111011100011010111011100";
WHEN "0000110" => memoryC3_uid243_exp10TabGen_q <= "00101100101101101101101100111110101";
WHEN "0000111" => memoryC3_uid243_exp10TabGen_q <= "00101101000100001010001010010011010";
WHEN "0001000" => memoryC3_uid243_exp10TabGen_q <= "00101101011010110001111001000001100";
WHEN "0001001" => memoryC3_uid243_exp10TabGen_q <= "00101101110001100100111110001011000";
WHEN "0001010" => memoryC3_uid243_exp10TabGen_q <= "00101110001000100011100000000110101";
WHEN "0001011" => memoryC3_uid243_exp10TabGen_q <= "00101110011111101101100100010001111";
WHEN "0001100" => memoryC3_uid243_exp10TabGen_q <= "00101110110111000011001111101001101";
WHEN "0001101" => memoryC3_uid243_exp10TabGen_q <= "00101111001110100100101000011111000";
WHEN "0001110" => memoryC3_uid243_exp10TabGen_q <= "00101111100110010001110101111100101";
WHEN "0001111" => memoryC3_uid243_exp10TabGen_q <= "00101111111110001010111101010010000";
WHEN "0010000" => memoryC3_uid243_exp10TabGen_q <= "00110000010110010000000010110000111";
WHEN "0010001" => memoryC3_uid243_exp10TabGen_q <= "00110000101110100001001110011111001";
WHEN "0010010" => memoryC3_uid243_exp10TabGen_q <= "00110001000110111110100110100000011";
WHEN "0010011" => memoryC3_uid243_exp10TabGen_q <= "00110001011111101000001111001011001";
WHEN "0010100" => memoryC3_uid243_exp10TabGen_q <= "00110001111000011110010001000100010";
WHEN "0010101" => memoryC3_uid243_exp10TabGen_q <= "00110010010001100000101111101110000";
WHEN "0010110" => memoryC3_uid243_exp10TabGen_q <= "00110010101010101111110011100001100";
WHEN "0010111" => memoryC3_uid243_exp10TabGen_q <= "00110011000100001011100001100001111";
WHEN "0011000" => memoryC3_uid243_exp10TabGen_q <= "00110011011101110100000001011100101";
WHEN "0011001" => memoryC3_uid243_exp10TabGen_q <= "00110011110111101001011000010101000";
WHEN "0011010" => memoryC3_uid243_exp10TabGen_q <= "00110100010001101011101100100010010";
WHEN "0011011" => memoryC3_uid243_exp10TabGen_q <= "00110100101011111011000101110001111";
WHEN "0011100" => memoryC3_uid243_exp10TabGen_q <= "00110101000110010111101010001110011";
WHEN "0011101" => memoryC3_uid243_exp10TabGen_q <= "00110101100001000001100000000100001";
WHEN "0011110" => memoryC3_uid243_exp10TabGen_q <= "00110101111011111000101110000101010";
WHEN "0011111" => memoryC3_uid243_exp10TabGen_q <= "00110110010110111101011010010100110";
WHEN "0100000" => memoryC3_uid243_exp10TabGen_q <= "00110110110010001111101101011010010";
WHEN "0100001" => memoryC3_uid243_exp10TabGen_q <= "00110111001101101111101100101000101";
WHEN "0100010" => memoryC3_uid243_exp10TabGen_q <= "00110111101001011101011110110010101";
WHEN "0100011" => memoryC3_uid243_exp10TabGen_q <= "00111000000101011001001100000100111";
WHEN "0100100" => memoryC3_uid243_exp10TabGen_q <= "00111000100001100010111011000111001";
WHEN "0100101" => memoryC3_uid243_exp10TabGen_q <= "00111000111101111010110001000111010";
WHEN "0100110" => memoryC3_uid243_exp10TabGen_q <= "00111001011010100000111000000010011";
WHEN "0100111" => memoryC3_uid243_exp10TabGen_q <= "00111001110111010101010100101101100";
WHEN "0101000" => memoryC3_uid243_exp10TabGen_q <= "00111010010100011000001111011100111";
WHEN "0101001" => memoryC3_uid243_exp10TabGen_q <= "00111010110001101001101111010100011";
WHEN "0101010" => memoryC3_uid243_exp10TabGen_q <= "00111011001111001001111100011010010";
WHEN "0101011" => memoryC3_uid243_exp10TabGen_q <= "00111011101100111000111011110110001";
WHEN "0101100" => memoryC3_uid243_exp10TabGen_q <= "00111100001010110110110111110001010";
WHEN "0101101" => memoryC3_uid243_exp10TabGen_q <= "00111100101001000011110101010010101";
WHEN "0101110" => memoryC3_uid243_exp10TabGen_q <= "00111101000111011111111101001100100";
WHEN "0101111" => memoryC3_uid243_exp10TabGen_q <= "00111101100110001011011000000101100";
WHEN "0110000" => memoryC3_uid243_exp10TabGen_q <= "00111110000101000110001011101110111";
WHEN "0110001" => memoryC3_uid243_exp10TabGen_q <= "00111110100100010000100000111101010";
WHEN "0110010" => memoryC3_uid243_exp10TabGen_q <= "00111111000011101010011110111011001";
WHEN "0110011" => memoryC3_uid243_exp10TabGen_q <= "00111111100011010100001110000110011";
WHEN "0110100" => memoryC3_uid243_exp10TabGen_q <= "01000000000011001101110101110010101";
WHEN "0110101" => memoryC3_uid243_exp10TabGen_q <= "01000000100011010111011101111010000";
WHEN "0110110" => memoryC3_uid243_exp10TabGen_q <= "01000001000011110001001111111000011";
WHEN "0110111" => memoryC3_uid243_exp10TabGen_q <= "01000001100100011011010010100100000";
WHEN "0111000" => memoryC3_uid243_exp10TabGen_q <= "01000010000101010101101101110001001";
WHEN "0111001" => memoryC3_uid243_exp10TabGen_q <= "01000010100110100000101010111010001";
WHEN "0111010" => memoryC3_uid243_exp10TabGen_q <= "01000011000111111100010001000011010";
WHEN "0111011" => memoryC3_uid243_exp10TabGen_q <= "01000011101001101000101001100001011";
WHEN "0111100" => memoryC3_uid243_exp10TabGen_q <= "01000100001011100101111100010101100";
WHEN "0111101" => memoryC3_uid243_exp10TabGen_q <= "01000100101101110100010010011111111";
WHEN "0111110" => memoryC3_uid243_exp10TabGen_q <= "01000101010000010011110011011101011";
WHEN "0111111" => memoryC3_uid243_exp10TabGen_q <= "01000101110011000100101001100111101";
WHEN "1000000" => memoryC3_uid243_exp10TabGen_q <= "01000110010110000110111011110001110";
WHEN "1000001" => memoryC3_uid243_exp10TabGen_q <= "01000110111001011010110010110111001";
WHEN "1000010" => memoryC3_uid243_exp10TabGen_q <= "01000111011101000000011000100111110";
WHEN "1000011" => memoryC3_uid243_exp10TabGen_q <= "01001000000000110111110110101011010";
WHEN "1000100" => memoryC3_uid243_exp10TabGen_q <= "01001000100101000001010100000000111";
WHEN "1000101" => memoryC3_uid243_exp10TabGen_q <= "01001001001001011100111010100011101";
WHEN "1000110" => memoryC3_uid243_exp10TabGen_q <= "01001001101110001010110100010011010";
WHEN "1000111" => memoryC3_uid243_exp10TabGen_q <= "01001010010011001011001000011100000";
WHEN "1001000" => memoryC3_uid243_exp10TabGen_q <= "01001010111000011110000010011000010";
WHEN "1001001" => memoryC3_uid243_exp10TabGen_q <= "01001011011110000011101001110110000";
WHEN "1001010" => memoryC3_uid243_exp10TabGen_q <= "01001100000011111100001000111111000";
WHEN "1001011" => memoryC3_uid243_exp10TabGen_q <= "01001100101010000111101000110011011";
WHEN "1001100" => memoryC3_uid243_exp10TabGen_q <= "01001101010000100110010011100000101";
WHEN "1001101" => memoryC3_uid243_exp10TabGen_q <= "01001101110111011000010010010110010";
WHEN "1001110" => memoryC3_uid243_exp10TabGen_q <= "01001110011110011101101111010011000";
WHEN "1001111" => memoryC3_uid243_exp10TabGen_q <= "01001111000101110110110011101100000";
WHEN "1010000" => memoryC3_uid243_exp10TabGen_q <= "01001111101101100011101001010010100";
WHEN "1010001" => memoryC3_uid243_exp10TabGen_q <= "01010000010101100100011010101011011";
WHEN "1010010" => memoryC3_uid243_exp10TabGen_q <= "01010000111101111001010000110011110";
WHEN "1010011" => memoryC3_uid243_exp10TabGen_q <= "01010001100110100010010111000101101";
WHEN "1010100" => memoryC3_uid243_exp10TabGen_q <= "01010010001111011111110110110000001";
WHEN "1010101" => memoryC3_uid243_exp10TabGen_q <= "01010010111000110001111010111010000";
WHEN "1010110" => memoryC3_uid243_exp10TabGen_q <= "01010011100010011000101100100001011";
WHEN "1010111" => memoryC3_uid243_exp10TabGen_q <= "01010100001100010100010110011000000";
WHEN "1011000" => memoryC3_uid243_exp10TabGen_q <= "01010100110110100101000100000100011";
WHEN "1011001" => memoryC3_uid243_exp10TabGen_q <= "01010101100001001010111111000111101";
WHEN "1011010" => memoryC3_uid243_exp10TabGen_q <= "01010110001100000110010011000111011";
WHEN "1011011" => memoryC3_uid243_exp10TabGen_q <= "01010110110111010111001001110100000";
WHEN "1011100" => memoryC3_uid243_exp10TabGen_q <= "01010111100010111101101101001011111";
WHEN "1011101" => memoryC3_uid243_exp10TabGen_q <= "01011000001110111010001010001111101";
WHEN "1011110" => memoryC3_uid243_exp10TabGen_q <= "01011000111011001100101011110000010";
WHEN "1011111" => memoryC3_uid243_exp10TabGen_q <= "01011001100111110101011011001001100";
WHEN "1100000" => memoryC3_uid243_exp10TabGen_q <= "01011010010100110100100100011100111";
WHEN "1100001" => memoryC3_uid243_exp10TabGen_q <= "01011011000010001010010011100000000";
WHEN "1100010" => memoryC3_uid243_exp10TabGen_q <= "01011011101111110110110010111100110";
WHEN "1100011" => memoryC3_uid243_exp10TabGen_q <= "01011100011101111010001101110001000";
WHEN "1100100" => memoryC3_uid243_exp10TabGen_q <= "01011101001100010100110000101110011";
WHEN "1100101" => memoryC3_uid243_exp10TabGen_q <= "01011101111011000110100110111100011";
WHEN "1100110" => memoryC3_uid243_exp10TabGen_q <= "01011110101010001111111011100011011";
WHEN "1100111" => memoryC3_uid243_exp10TabGen_q <= "01011111011001110000111010111000000";
WHEN "1101000" => memoryC3_uid243_exp10TabGen_q <= "01100000001001101001110000000101000";
WHEN "1101001" => memoryC3_uid243_exp10TabGen_q <= "01100000111001111010101000001000101";
WHEN "1101010" => memoryC3_uid243_exp10TabGen_q <= "01100001101010100011101111010001110";
WHEN "1101011" => memoryC3_uid243_exp10TabGen_q <= "01100010011011100101001111110000101";
WHEN "1101100" => memoryC3_uid243_exp10TabGen_q <= "01100011001100111111010111101111110";
WHEN "1101101" => memoryC3_uid243_exp10TabGen_q <= "01100011111110110010010011100110010";
WHEN "1101110" => memoryC3_uid243_exp10TabGen_q <= "01100100110000111110001110110101100";
WHEN "1101111" => memoryC3_uid243_exp10TabGen_q <= "01100101100011100011010101101101001";
WHEN "1110000" => memoryC3_uid243_exp10TabGen_q <= "01100110010110100001110101111100110";
WHEN "1110001" => memoryC3_uid243_exp10TabGen_q <= "01100111001001111001111011111001101";
WHEN "1110010" => memoryC3_uid243_exp10TabGen_q <= "01100111111101101011110100001100011";
WHEN "1110011" => memoryC3_uid243_exp10TabGen_q <= "01101000110001110111101100011010111";
WHEN "1110100" => memoryC3_uid243_exp10TabGen_q <= "01101001100110011101101111111111000";
WHEN "1110101" => memoryC3_uid243_exp10TabGen_q <= "01101010011011011110001110011101010";
WHEN "1110110" => memoryC3_uid243_exp10TabGen_q <= "01101011010000111001010010111011001";
WHEN "1110111" => memoryC3_uid243_exp10TabGen_q <= "01101100000110101111001011110001101";
WHEN "1111000" => memoryC3_uid243_exp10TabGen_q <= "01101100111101000000000111000100011";
WHEN "1111001" => memoryC3_uid243_exp10TabGen_q <= "01101101110011101100010000001110111";
WHEN "1111010" => memoryC3_uid243_exp10TabGen_q <= "01101110101010110011110111010100111";
WHEN "1111011" => memoryC3_uid243_exp10TabGen_q <= "01101111100010010111001000101100111";
WHEN "1111100" => memoryC3_uid243_exp10TabGen_q <= "01110000011010010110010011001011011";
WHEN "1111101" => memoryC3_uid243_exp10TabGen_q <= "01110001010010110001100011111011011";
WHEN "1111110" => memoryC3_uid243_exp10TabGen_q <= "01110010001011101001001010001001100";
WHEN "1111111" => memoryC3_uid243_exp10TabGen_q <= "01110011000100111101010001111100100";
WHEN OTHERS =>
memoryC3_uid243_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid259_exp10PolyEval(ADD,258)@22
sumAHighB_uid259_exp10PolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid243_exp10TabGen_q(34)) & memoryC3_uid243_exp10TabGen_q);
sumAHighB_uid259_exp10PolyEval_b <= STD_LOGIC_VECTOR((35 downto 27 => highBBits_uid258_exp10PolyEval_b(26)) & highBBits_uid258_exp10PolyEval_b);
sumAHighB_uid259_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_exp10PolyEval_a) + SIGNED(sumAHighB_uid259_exp10PolyEval_b));
sumAHighB_uid259_exp10PolyEval_q <= sumAHighB_uid259_exp10PolyEval_o(35 downto 0);
--lowRangeB_uid257_exp10PolyEval(BITSELECT,256)@22
lowRangeB_uid257_exp10PolyEval_in <= prodXYTruncFR_uid284_pT2_uid256_exp10PolyEval_b(0 downto 0);
lowRangeB_uid257_exp10PolyEval_b <= lowRangeB_uid257_exp10PolyEval_in(0 downto 0);
--s2_uid257_uid260_exp10PolyEval(BITJOIN,259)@22
s2_uid257_uid260_exp10PolyEval_q <= sumAHighB_uid259_exp10PolyEval_q & lowRangeB_uid257_exp10PolyEval_b;
--yTop18Bits_uid292_pT3_uid262_exp10PolyEval(BITSELECT,291)@22
yTop18Bits_uid292_pT3_uid262_exp10PolyEval_in <= s2_uid257_uid260_exp10PolyEval_q;
yTop18Bits_uid292_pT3_uid262_exp10PolyEval_b <= yTop18Bits_uid292_pT3_uid262_exp10PolyEval_in(36 downto 19);
--reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9(REG,392)@22
reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9_q <= yTop18Bits_uid292_pT3_uid262_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor(LOGICAL,1068)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_b <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_q <= not (ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_a or ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_b);
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena(REG,1069)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd(LOGICAL,1070)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_a and ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg(DELAY,1058)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid65_fpExpETest_b, xout => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem(DUALMEM,1059)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_aa <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdreg_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ab <= ld_oFracX_uid32_uid32_fpExpETest_q_to_oFracXZwE_uid48_fpExpETest_b_replace_rdmux_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 3,
numwords_a => 6,
width_b => 48,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_iq(47 downto 0);
--yT3_uid261_exp10PolyEval(BITSELECT,260)@22
yT3_uid261_exp10PolyEval_in <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_replace_mem_q;
yT3_uid261_exp10PolyEval_b <= yT3_uid261_exp10PolyEval_in(47 downto 13);
--xBottomBits_uid291_pT3_uid262_exp10PolyEval(BITSELECT,290)@22
xBottomBits_uid291_pT3_uid262_exp10PolyEval_in <= yT3_uid261_exp10PolyEval_b(7 downto 0);
xBottomBits_uid291_pT3_uid262_exp10PolyEval_b <= xBottomBits_uid291_pT3_uid262_exp10PolyEval_in(7 downto 0);
--pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval(BITJOIN,293)@22
pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_q <= xBottomBits_uid291_pT3_uid262_exp10PolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7(REG,391)@22
reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7_q <= pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid290_pT3_uid262_exp10PolyEval(BITSELECT,289)@22
yBottomBits_uid290_pT3_uid262_exp10PolyEval_in <= s2_uid257_uid260_exp10PolyEval_q(9 downto 0);
yBottomBits_uid290_pT3_uid262_exp10PolyEval_b <= yBottomBits_uid290_pT3_uid262_exp10PolyEval_in(9 downto 0);
--spad_yBottomBits_uid290_uid293_pT3_uid262_exp10PolyEval(BITJOIN,292)@22
spad_yBottomBits_uid290_uid293_pT3_uid262_exp10PolyEval_q <= GND_q & yBottomBits_uid290_pT3_uid262_exp10PolyEval_b;
--pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval(BITJOIN,294)@22
pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_q <= spad_yBottomBits_uid290_uid293_pT3_uid262_exp10PolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6(REG,390)@22
reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6_q <= pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid289_pT3_uid262_exp10PolyEval(BITSELECT,288)@22
xTop18Bits_uid289_pT3_uid262_exp10PolyEval_in <= yT3_uid261_exp10PolyEval_b;
xTop18Bits_uid289_pT3_uid262_exp10PolyEval_b <= xTop18Bits_uid289_pT3_uid262_exp10PolyEval_in(34 downto 17);
--reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4(REG,389)@22
reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4_q <= xTop18Bits_uid289_pT3_uid262_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma(CHAINMULTADD,338)@23
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a(0),19));
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a(1),19));
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p(0) <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l(0) * multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c(0);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p(1) <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_l(1) * multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c(1);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_p(1),38);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_x(0) <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_w(0);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_y(0) <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_x(0);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid289_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_4_q),18);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid291_uid294_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_7_q),18);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid290_uid295_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_6_q),18);
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid292_pT3_uid262_exp10PolyEval_0_to_multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s(0) <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval(BITSELECT,296)@26
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_in <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_cma_q;
multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_b <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_in(36 downto 7);
--highBBits_uid299_pT3_uid262_exp10PolyEval(BITSELECT,298)@26
highBBits_uid299_pT3_uid262_exp10PolyEval_in <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_b;
highBBits_uid299_pT3_uid262_exp10PolyEval_b <= highBBits_uid299_pT3_uid262_exp10PolyEval_in(29 downto 1);
--yTop27Bits_uid287_pT3_uid262_exp10PolyEval(BITSELECT,286)@22
yTop27Bits_uid287_pT3_uid262_exp10PolyEval_in <= s2_uid257_uid260_exp10PolyEval_q;
yTop27Bits_uid287_pT3_uid262_exp10PolyEval_b <= yTop27Bits_uid287_pT3_uid262_exp10PolyEval_in(36 downto 10);
--reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1(REG,394)@22
reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1_q <= yTop27Bits_uid287_pT3_uid262_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid286_pT3_uid262_exp10PolyEval(BITSELECT,285)@22
xTop27Bits_uid286_pT3_uid262_exp10PolyEval_in <= yT3_uid261_exp10PolyEval_b;
xTop27Bits_uid286_pT3_uid262_exp10PolyEval_b <= xTop27Bits_uid286_pT3_uid262_exp10PolyEval_in(34 downto 8);
--reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0(REG,393)@22
reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0_q <= xTop27Bits_uid286_pT3_uid262_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid288_pT3_uid262_exp10PolyEval(MULT,287)@23
topProd_uid288_pT3_uid262_exp10PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid288_pT3_uid262_exp10PolyEval_a),28)) * SIGNED(topProd_uid288_pT3_uid262_exp10PolyEval_b);
topProd_uid288_pT3_uid262_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid288_pT3_uid262_exp10PolyEval_a <= (others => '0');
topProd_uid288_pT3_uid262_exp10PolyEval_b <= (others => '0');
topProd_uid288_pT3_uid262_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid288_pT3_uid262_exp10PolyEval_a <= reg_xTop27Bits_uid286_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_0_q;
topProd_uid288_pT3_uid262_exp10PolyEval_b <= reg_yTop27Bits_uid287_pT3_uid262_exp10PolyEval_0_to_topProd_uid288_pT3_uid262_exp10PolyEval_1_q;
topProd_uid288_pT3_uid262_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid288_pT3_uid262_exp10PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid288_pT3_uid262_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid288_pT3_uid262_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid288_pT3_uid262_exp10PolyEval_q <= topProd_uid288_pT3_uid262_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid300_pT3_uid262_exp10PolyEval(ADD,299)@26
sumAHighB_uid300_pT3_uid262_exp10PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid288_pT3_uid262_exp10PolyEval_q(53)) & topProd_uid288_pT3_uid262_exp10PolyEval_q);
sumAHighB_uid300_pT3_uid262_exp10PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid299_pT3_uid262_exp10PolyEval_b(28)) & highBBits_uid299_pT3_uid262_exp10PolyEval_b);
sumAHighB_uid300_pT3_uid262_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid300_pT3_uid262_exp10PolyEval_a) + SIGNED(sumAHighB_uid300_pT3_uid262_exp10PolyEval_b));
sumAHighB_uid300_pT3_uid262_exp10PolyEval_q <= sumAHighB_uid300_pT3_uid262_exp10PolyEval_o(54 downto 0);
--lowRangeB_uid298_pT3_uid262_exp10PolyEval(BITSELECT,297)@26
lowRangeB_uid298_pT3_uid262_exp10PolyEval_in <= multSumOfTwo18_uid293_pT3_uid262_exp10PolyEval_b(0 downto 0);
lowRangeB_uid298_pT3_uid262_exp10PolyEval_b <= lowRangeB_uid298_pT3_uid262_exp10PolyEval_in(0 downto 0);
--add0_uid298_uid301_pT3_uid262_exp10PolyEval(BITJOIN,300)@26
add0_uid298_uid301_pT3_uid262_exp10PolyEval_q <= sumAHighB_uid300_pT3_uid262_exp10PolyEval_q & lowRangeB_uid298_pT3_uid262_exp10PolyEval_b;
--R_uid302_pT3_uid262_exp10PolyEval(BITSELECT,301)@26
R_uid302_pT3_uid262_exp10PolyEval_in <= add0_uid298_uid301_pT3_uid262_exp10PolyEval_q(54 downto 0);
R_uid302_pT3_uid262_exp10PolyEval_b <= R_uid302_pT3_uid262_exp10PolyEval_in(54 downto 18);
--reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1(REG,396)@26
reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1_q <= R_uid302_pT3_uid262_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor(LOGICAL,1042)
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_b <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_q <= not (ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_a or ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_b);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_mem_top(CONSTANT,1025)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_mem_top_q <= "01000";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp(LOGICAL,1026)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_mem_top_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_q <= "1" when ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_a = ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_b else "0";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg(REG,1027)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena(REG,1043)
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_nor_q = "1") THEN
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd(LOGICAL,1044)
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_a <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_sticky_ena_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_b <= en;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_q <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_a and ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_b;
--memoryC2_uid241_exp10TabGen(LOOKUP,240)@14
memoryC2_uid241_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid241_exp10TabGen_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC2_uid241_exp10TabGen_q <= "000";
WHEN "0000001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0000111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0001111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0010111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0011111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0100111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0101111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0110111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "0111111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1000111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1001111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010001" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010010" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010011" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010100" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010101" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010110" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1010111" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1011000" => memoryC2_uid241_exp10TabGen_q <= "001";
WHEN "1011001" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011010" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011011" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011100" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011101" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011110" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1011111" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100000" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100001" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100010" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100011" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100100" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100101" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100110" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1100111" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101000" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101001" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101010" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101011" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101100" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101101" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101110" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1101111" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110000" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110001" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110010" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110011" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110100" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110101" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110110" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1110111" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111000" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111001" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111010" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111011" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111100" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111101" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111110" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN "1111111" => memoryC2_uid241_exp10TabGen_q <= "010";
WHEN OTHERS =>
memoryC2_uid241_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_inputreg(DELAY,1032)
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => memoryC2_uid241_exp10TabGen_q, xout => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt(COUNTER,1021)
-- every=1, low=0, high=8, step=1, init=1
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i = 7 THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i - 8;
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_i,4));
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg(REG,1022)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux(MUX,1023)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_s, ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q, ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem(DUALMEM,1033)
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ia <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_inputreg_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_aa <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ab <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 9,
width_b => 3,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_iq,
address_a => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_aa,
data_a => ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_ia
);
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_reset0 <= areset;
ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_q <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_iq(2 downto 0);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor(LOGICAL,1029)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_b <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_q <= not (ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_a or ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_b);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena(REG,1030)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd(LOGICAL,1031)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_a and ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_b;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem(DUALMEM,1020)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ia <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_aa <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ab <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_rdmux_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 4,
numwords_a => 9,
width_b => 7,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_ia
);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_iq(6 downto 0);
--memoryC2_uid240_exp10TabGen(LOOKUP,239)@25
memoryC2_uid240_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC2_uid240_exp10TabGen_q <= "1111111111111111111111111111111111111110";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid64_fpExpETest_0_to_memoryC2_uid240_exp10TabGen_0_q_to_memoryC2_uid240_exp10TabGen_a_replace_mem_q) IS
WHEN "0000000" => memoryC2_uid240_exp10TabGen_q <= "1111111111111111111111111111111111111110";
WHEN "0000001" => memoryC2_uid240_exp10TabGen_q <= "0000001000000010000000010101011000111101";
WHEN "0000010" => memoryC2_uid240_exp10TabGen_q <= "0000010000001000000010101011010101111110";
WHEN "0000011" => memoryC2_uid240_exp10TabGen_q <= "0000011000010010001001000011011001110000";
WHEN "0000100" => memoryC2_uid240_exp10TabGen_q <= "0000100000100000010101100000000100100100";
WHEN "0000101" => memoryC2_uid240_exp10TabGen_q <= "0000101000110010101010000100111010011000";
WHEN "0000110" => memoryC2_uid240_exp10TabGen_q <= "0000110001001001001000110110100000100101";
WHEN "0000111" => memoryC2_uid240_exp10TabGen_q <= "0000111001100011110011111010011111000001";
WHEN "0001000" => memoryC2_uid240_exp10TabGen_q <= "0001000010000010101101010111011111010100";
WHEN "0001001" => memoryC2_uid240_exp10TabGen_q <= "0001001010100101110111010101010001000100";
WHEN "0001010" => memoryC2_uid240_exp10TabGen_q <= "0001010011001101010011111100100101110011";
WHEN "0001011" => memoryC2_uid240_exp10TabGen_q <= "0001011011111001000101010111010101000111";
WHEN "0001100" => memoryC2_uid240_exp10TabGen_q <= "0001100100101001001101110000011100110000";
WHEN "0001101" => memoryC2_uid240_exp10TabGen_q <= "0001101101011101101111010011111110010110";
WHEN "0001110" => memoryC2_uid240_exp10TabGen_q <= "0001110110010110101100001110111111110111";
WHEN "0001111" => memoryC2_uid240_exp10TabGen_q <= "0001111111010100000110101111110001111100";
WHEN "0010000" => memoryC2_uid240_exp10TabGen_q <= "0010001000010110000001000101101110000011";
WHEN "0010001" => memoryC2_uid240_exp10TabGen_q <= "0010010001011100011101100001001111011100";
WHEN "0010010" => memoryC2_uid240_exp10TabGen_q <= "0010011010100111011110010011111100111011";
WHEN "0010011" => memoryC2_uid240_exp10TabGen_q <= "0010100011110111000101110000101010010001";
WHEN "0010100" => memoryC2_uid240_exp10TabGen_q <= "0010101101001011010110001011001100110101";
WHEN "0010101" => memoryC2_uid240_exp10TabGen_q <= "0010110110100100010001111000101101100011";
WHEN "0010110" => memoryC2_uid240_exp10TabGen_q <= "0011000000000001111011001111010111110010";
WHEN "0010111" => memoryC2_uid240_exp10TabGen_q <= "0011001001100100010100100110100111111010";
WHEN "0011000" => memoryC2_uid240_exp10TabGen_q <= "0011010011001011100000010111000010000011";
WHEN "0011001" => memoryC2_uid240_exp10TabGen_q <= "0011011100110111100000111010011011101000";
WHEN "0011010" => memoryC2_uid240_exp10TabGen_q <= "0011100110101000011000101011110100111100";
WHEN "0011011" => memoryC2_uid240_exp10TabGen_q <= "0011110000011110001010000111011001111100";
WHEN "0011100" => memoryC2_uid240_exp10TabGen_q <= "0011111010011000110111101010100111100101";
WHEN "0011101" => memoryC2_uid240_exp10TabGen_q <= "0100000100011000100011110100001010001010";
WHEN "0011110" => memoryC2_uid240_exp10TabGen_q <= "0100001110011101010001000011111100100101";
WHEN "0011111" => memoryC2_uid240_exp10TabGen_q <= "0100011000100111000001111011001011001100";
WHEN "0100000" => memoryC2_uid240_exp10TabGen_q <= "0100100010110101111000111100001111001111";
WHEN "0100001" => memoryC2_uid240_exp10TabGen_q <= "0100101101001001111000101010111001001000";
WHEN "0100010" => memoryC2_uid240_exp10TabGen_q <= "0100110111100011000011101100001000111111";
WHEN "0100011" => memoryC2_uid240_exp10TabGen_q <= "0101000010000001011100100110001111011101";
WHEN "0100100" => memoryC2_uid240_exp10TabGen_q <= "0101001100100101000110000000110011010000";
WHEN "0100101" => memoryC2_uid240_exp10TabGen_q <= "0101010111001110000010100100110010001010";
WHEN "0100110" => memoryC2_uid240_exp10TabGen_q <= "0101100001111100010100111100010110010011";
WHEN "0100111" => memoryC2_uid240_exp10TabGen_q <= "0101101100101111111111110011001000100100";
WHEN "0101000" => memoryC2_uid240_exp10TabGen_q <= "0101110111101001000101110110000001011000";
WHEN "0101001" => memoryC2_uid240_exp10TabGen_q <= "0110000010100111101001110011010011000100";
WHEN "0101010" => memoryC2_uid240_exp10TabGen_q <= "0110001101101011101110011010100101000110";
WHEN "0101011" => memoryC2_uid240_exp10TabGen_q <= "0110011000110101010110011100111100100110";
WHEN "0101100" => memoryC2_uid240_exp10TabGen_q <= "0110100100000100100100101100101110111111";
WHEN "0101101" => memoryC2_uid240_exp10TabGen_q <= "0110101111011001011011111101110100000010";
WHEN "0101110" => memoryC2_uid240_exp10TabGen_q <= "0110111010110011111111000101010111011100";
WHEN "0101111" => memoryC2_uid240_exp10TabGen_q <= "0111000110010100010000111010000000011010";
WHEN "0110000" => memoryC2_uid240_exp10TabGen_q <= "0111010001111010010100010011110110101100";
WHEN "0110001" => memoryC2_uid240_exp10TabGen_q <= "0111011101100110001100001100011001001011";
WHEN "0110010" => memoryC2_uid240_exp10TabGen_q <= "0111101001010111111011011110100111010001";
WHEN "0110011" => memoryC2_uid240_exp10TabGen_q <= "0111110101001111100101000110111011011110";
WHEN "0110100" => memoryC2_uid240_exp10TabGen_q <= "1000000001001101001100000011010001011000";
WHEN "0110101" => memoryC2_uid240_exp10TabGen_q <= "1000001101010000110011010011000011001011";
WHEN "0110110" => memoryC2_uid240_exp10TabGen_q <= "1000011001011010011101110111001000000101";
WHEN "0110111" => memoryC2_uid240_exp10TabGen_q <= "1000100101101010001110110001111100111001";
WHEN "0111000" => memoryC2_uid240_exp10TabGen_q <= "1000110010000000001001000111011110101101";
WHEN "0111001" => memoryC2_uid240_exp10TabGen_q <= "1000111110011100001111111101001001110101";
WHEN "0111010" => memoryC2_uid240_exp10TabGen_q <= "1001001010111110100110011010000010101010";
WHEN "0111011" => memoryC2_uid240_exp10TabGen_q <= "1001010111100111001111100110101100101010";
WHEN "0111100" => memoryC2_uid240_exp10TabGen_q <= "1001100100010110001110101101010011010010";
WHEN "0111101" => memoryC2_uid240_exp10TabGen_q <= "1001110001001011100110111001100101010000";
WHEN "0111110" => memoryC2_uid240_exp10TabGen_q <= "1001111110000111011011011000111010110011";
WHEN "0111111" => memoryC2_uid240_exp10TabGen_q <= "1010001011001001101111011010001101110011";
WHEN "1000000" => memoryC2_uid240_exp10TabGen_q <= "1010011000010010100110001110000110110000";
WHEN "1000001" => memoryC2_uid240_exp10TabGen_q <= "1010100101100010000011000110110011000011";
WHEN "1000010" => memoryC2_uid240_exp10TabGen_q <= "1010110010111000001001011000001000011101";
WHEN "1000011" => memoryC2_uid240_exp10TabGen_q <= "1011000000010100111100010111100111011010";
WHEN "1000100" => memoryC2_uid240_exp10TabGen_q <= "1011001101111000011111011100100000000010";
WHEN "1000101" => memoryC2_uid240_exp10TabGen_q <= "1011011011100010110101111111101001110101";
WHEN "1000110" => memoryC2_uid240_exp10TabGen_q <= "1011101001010100000011011011101000101011";
WHEN "1000111" => memoryC2_uid240_exp10TabGen_q <= "1011110111001100001011001100110011100100";
WHEN "1001000" => memoryC2_uid240_exp10TabGen_q <= "1100000101001011010000110001001000111011";
WHEN "1001001" => memoryC2_uid240_exp10TabGen_q <= "1100010011010001010111101000011100110101";
WHEN "1001010" => memoryC2_uid240_exp10TabGen_q <= "1100100001011110100011010100001111110100";
WHEN "1001011" => memoryC2_uid240_exp10TabGen_q <= "1100101111110010110111010111110101100001";
WHEN "1001100" => memoryC2_uid240_exp10TabGen_q <= "1100111110001110010111011000010010001101";
WHEN "1001101" => memoryC2_uid240_exp10TabGen_q <= "1101001100110001000110111100011110011111";
WHEN "1001110" => memoryC2_uid240_exp10TabGen_q <= "1101011011011011001001101101000101101011";
WHEN "1001111" => memoryC2_uid240_exp10TabGen_q <= "1101101010001100100011010100101001011110";
WHEN "1010000" => memoryC2_uid240_exp10TabGen_q <= "1101111001000101010111011111100000010111";
WHEN "1010001" => memoryC2_uid240_exp10TabGen_q <= "1110001000000101101001111011110110011101";
WHEN "1010010" => memoryC2_uid240_exp10TabGen_q <= "1110010111001101011110011001110010010001";
WHEN "1010011" => memoryC2_uid240_exp10TabGen_q <= "1110100110011100111000101011001110100000";
WHEN "1010100" => memoryC2_uid240_exp10TabGen_q <= "1110110101110011111100100100000011101110";
WHEN "1010101" => memoryC2_uid240_exp10TabGen_q <= "1111000101010010101101111010000001001010";
WHEN "1010110" => memoryC2_uid240_exp10TabGen_q <= "1111010100111001010000100100110101110101";
WHEN "1010111" => memoryC2_uid240_exp10TabGen_q <= "1111100100100111101000011110001001101110";
WHEN "1011000" => memoryC2_uid240_exp10TabGen_q <= "1111110100011101111001100001100000110101";
WHEN "1011001" => memoryC2_uid240_exp10TabGen_q <= "0000000100011100000111101100100001100111";
WHEN "1011010" => memoryC2_uid240_exp10TabGen_q <= "0000010100100010010110111110101101101101";
WHEN "1011011" => memoryC2_uid240_exp10TabGen_q <= "0000100100110000101011011001101011000010";
WHEN "1011100" => memoryC2_uid240_exp10TabGen_q <= "0000110101000111001001000000111111111100";
WHEN "1011101" => memoryC2_uid240_exp10TabGen_q <= "0001000101100101110011111010010000100110";
WHEN "1011110" => memoryC2_uid240_exp10TabGen_q <= "0001010110001100110000001101000111110111";
WHEN "1011111" => memoryC2_uid240_exp10TabGen_q <= "0001100110111100000010000011011000000011";
WHEN "1100000" => memoryC2_uid240_exp10TabGen_q <= "0001110111110011101101101000110011111110";
WHEN "1100001" => memoryC2_uid240_exp10TabGen_q <= "0010001000110011110111001011010101100011";
WHEN "1100010" => memoryC2_uid240_exp10TabGen_q <= "0010011001111100100010111011000000110011";
WHEN "1100011" => memoryC2_uid240_exp10TabGen_q <= "0010101011001101110101001010000001001001";
WHEN "1100100" => memoryC2_uid240_exp10TabGen_q <= "0010111100100111110010001100101001010000";
WHEN "1100101" => memoryC2_uid240_exp10TabGen_q <= "0011001110001010011110011001011001001101";
WHEN "1100110" => memoryC2_uid240_exp10TabGen_q <= "0011011111110101111110001000111101001011";
WHEN "1100111" => memoryC2_uid240_exp10TabGen_q <= "0011110001101010010101110110001100010001";
WHEN "1101000" => memoryC2_uid240_exp10TabGen_q <= "0100000011100111101001111110001101110100";
WHEN "1101001" => memoryC2_uid240_exp10TabGen_q <= "0100010101101101111111000000010101000100";
WHEN "1101010" => memoryC2_uid240_exp10TabGen_q <= "0100100111111101011001011110000111001011";
WHEN "1101011" => memoryC2_uid240_exp10TabGen_q <= "0100111010010101111101111011011110000001";
WHEN "1101100" => memoryC2_uid240_exp10TabGen_q <= "0101001100110111110000111110011111101100";
WHEN "1101101" => memoryC2_uid240_exp10TabGen_q <= "0101011111100010110111001111101000111010";
WHEN "1101110" => memoryC2_uid240_exp10TabGen_q <= "0101110010010111010101011001101101000111";
WHEN "1101111" => memoryC2_uid240_exp10TabGen_q <= "0110000101010101010000001001110100001010";
WHEN "1110000" => memoryC2_uid240_exp10TabGen_q <= "0110011000011100101100001111011011010100";
WHEN "1110001" => memoryC2_uid240_exp10TabGen_q <= "0110101011101101101110011100011010000001";
WHEN "1110010" => memoryC2_uid240_exp10TabGen_q <= "0110111111001000011011100101000001101011";
WHEN "1110011" => memoryC2_uid240_exp10TabGen_q <= "0111010010101100111000011111111100000111";
WHEN "1110100" => memoryC2_uid240_exp10TabGen_q <= "0111100110011011001010000110010011111010";
WHEN "1110101" => memoryC2_uid240_exp10TabGen_q <= "0111111010010011010101010011101001001100";
WHEN "1110110" => memoryC2_uid240_exp10TabGen_q <= "1000001110010101011111000110000010100010";
WHEN "1110111" => memoryC2_uid240_exp10TabGen_q <= "1000100010100001101100011110000000111101";
WHEN "1111000" => memoryC2_uid240_exp10TabGen_q <= "1000110110111000000010011110100110011111";
WHEN "1111001" => memoryC2_uid240_exp10TabGen_q <= "1001001011011000100110001101011100110010";
WHEN "1111010" => memoryC2_uid240_exp10TabGen_q <= "1001100000000011011100110010101000101011";
WHEN "1111011" => memoryC2_uid240_exp10TabGen_q <= "1001110100111000101011011000111010010001";
WHEN "1111100" => memoryC2_uid240_exp10TabGen_q <= "1010001001111000010111001101100011110110";
WHEN "1111101" => memoryC2_uid240_exp10TabGen_q <= "1010011111000010100101100000100001111000";
WHEN "1111110" => memoryC2_uid240_exp10TabGen_q <= "1010110100010111011011100100010110000001";
WHEN "1111111" => memoryC2_uid240_exp10TabGen_q <= "1011001001110110111110101110010001100110";
WHEN OTHERS =>
memoryC2_uid240_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--os_uid242_exp10TabGen(BITJOIN,241)@26
os_uid242_exp10TabGen_q <= ld_memoryC2_uid241_exp10TabGen_q_to_os_uid242_exp10TabGen_b_replace_mem_q & memoryC2_uid240_exp10TabGen_q;
--rndBit_uid263_exp10PolyEval(CONSTANT,262)
rndBit_uid263_exp10PolyEval_q <= "01";
--cIncludingRoundingBit_uid264_exp10PolyEval(BITJOIN,263)@26
cIncludingRoundingBit_uid264_exp10PolyEval_q <= os_uid242_exp10TabGen_q & rndBit_uid263_exp10PolyEval_q;
--reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0(REG,395)@26
reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0_q <= cIncludingRoundingBit_uid264_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid265_exp10PolyEval(ADD,264)@27
ts3_uid265_exp10PolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid264_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_0_q);
ts3_uid265_exp10PolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1_q(36)) & reg_R_uid302_pT3_uid262_exp10PolyEval_0_to_ts3_uid265_exp10PolyEval_1_q);
ts3_uid265_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid265_exp10PolyEval_a) + SIGNED(ts3_uid265_exp10PolyEval_b));
ts3_uid265_exp10PolyEval_q <= ts3_uid265_exp10PolyEval_o(45 downto 0);
--s3_uid266_exp10PolyEval(BITSELECT,265)@27
s3_uid266_exp10PolyEval_in <= ts3_uid265_exp10PolyEval_q;
s3_uid266_exp10PolyEval_b <= s3_uid266_exp10PolyEval_in(45 downto 1);
--yTop27Bits_uid304_pT4_uid268_exp10PolyEval(BITSELECT,303)@27
yTop27Bits_uid304_pT4_uid268_exp10PolyEval_in <= s3_uid266_exp10PolyEval_b;
yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b <= yTop27Bits_uid304_pT4_uid268_exp10PolyEval_in(44 downto 18);
--reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9(REG,400)@27
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9_q <= yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor(LOGICAL,1081)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_b <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_q <= not (ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_a or ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_b);
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_mem_top(CONSTANT,1077)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_mem_top_q <= "01010";
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp(LOGICAL,1078)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_a <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_mem_top_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q);
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_q <= "1" when ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_a = ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_b else "0";
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg(REG,1079)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena(REG,1082)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_nor_q = "1") THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd(LOGICAL,1083)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_a <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_sticky_ena_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_b <= en;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_a and ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_b;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt(COUNTER,1073)
-- every=1, low=0, high=10, step=1, init=1
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i = 9 THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i - 10;
ELSE
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_i,4));
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg(REG,1074)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux(MUX,1075)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_s, ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q, ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem(DUALMEM,1072)
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ia <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT3_uid261_exp10PolyEval_a_inputreg_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_aa <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdreg_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ab <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_rdmux_q;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_ia
);
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_q <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_iq(47 downto 0);
--yT4_uid267_exp10PolyEval(BITSELECT,266)@27
yT4_uid267_exp10PolyEval_in <= ld_yPPolyEval_uid65_fpExpETest_b_to_yT4_uid267_exp10PolyEval_a_replace_mem_q;
yT4_uid267_exp10PolyEval_b <= yT4_uid267_exp10PolyEval_in(47 downto 5);
--xBottomBits_uid307_pT4_uid268_exp10PolyEval(BITSELECT,306)@27
xBottomBits_uid307_pT4_uid268_exp10PolyEval_in <= yT4_uid267_exp10PolyEval_b(15 downto 0);
xBottomBits_uid307_pT4_uid268_exp10PolyEval_b <= xBottomBits_uid307_pT4_uid268_exp10PolyEval_in(15 downto 0);
--pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval(BITJOIN,308)@27
pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_q <= xBottomBits_uid307_pT4_uid268_exp10PolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7(REG,399)@27
reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7_q <= pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid306_pT4_uid268_exp10PolyEval(BITSELECT,305)@27
yBottomBits_uid306_pT4_uid268_exp10PolyEval_in <= s3_uid266_exp10PolyEval_b(17 downto 0);
yBottomBits_uid306_pT4_uid268_exp10PolyEval_b <= yBottomBits_uid306_pT4_uid268_exp10PolyEval_in(17 downto 0);
--ld_yBottomBits_uid306_pT4_uid268_exp10PolyEval_b_to_spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_a(DELAY,748)@27
ld_yBottomBits_uid306_pT4_uid268_exp10PolyEval_b_to_spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid306_pT4_uid268_exp10PolyEval_b, xout => ld_yBottomBits_uid306_pT4_uid268_exp10PolyEval_b_to_spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval(BITJOIN,307)@28
spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_q <= GND_q & ld_yBottomBits_uid306_pT4_uid268_exp10PolyEval_b_to_spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_a_q;
--pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval(BITJOIN,309)@28
pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_q <= spad_yBottomBits_uid306_uid308_pT4_uid268_exp10PolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6(REG,398)@28
reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6_q <= pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yT4_uid267_exp10PolyEval_b_to_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_a(DELAY,742)@27
ld_yT4_uid267_exp10PolyEval_b_to_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid267_exp10PolyEval_b, xout => ld_yT4_uid267_exp10PolyEval_b_to_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--xTop27Bits_uid303_pT4_uid268_exp10PolyEval(BITSELECT,302)@28
xTop27Bits_uid303_pT4_uid268_exp10PolyEval_in <= ld_yT4_uid267_exp10PolyEval_b_to_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_a_q;
xTop27Bits_uid303_pT4_uid268_exp10PolyEval_b <= xTop27Bits_uid303_pT4_uid268_exp10PolyEval_in(42 downto 16);
--reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4(REG,397)@28
reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4_q <= xTop27Bits_uid303_pT4_uid268_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma(CHAINMULTADD,339)@29
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a(0),28));
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a(1),28));
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p(0) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l(0) * multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c(0);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p(1) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_l(1) * multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c(1);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p(0),56);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_p(1),56);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x(0) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w(0);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x(1) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_w(1);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y(0) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s(1) + multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x(0);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y(1) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_x(1);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4_q),27);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid307_uid309_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_7_q),27);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid306_uid310_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_6_q),27);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s(0) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y(0);
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s(1) <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval(BITSELECT,311)@32
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_in <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_q;
multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_b <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_in(54 downto 8);
--highBBits_uid314_pT4_uid268_exp10PolyEval(BITSELECT,313)@32
highBBits_uid314_pT4_uid268_exp10PolyEval_in <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_b;
highBBits_uid314_pT4_uid268_exp10PolyEval_b <= highBBits_uid314_pT4_uid268_exp10PolyEval_in(46 downto 18);
--ld_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b_to_reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_a(DELAY,856)@27
ld_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b_to_reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b, xout => ld_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b_to_reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1(REG,402)@28
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_q <= ld_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_b_to_reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid305_pT4_uid268_exp10PolyEval(MULT,304)@29
topProd_uid305_pT4_uid268_exp10PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid305_pT4_uid268_exp10PolyEval_a),28)) * SIGNED(topProd_uid305_pT4_uid268_exp10PolyEval_b);
topProd_uid305_pT4_uid268_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid305_pT4_uid268_exp10PolyEval_a <= (others => '0');
topProd_uid305_pT4_uid268_exp10PolyEval_b <= (others => '0');
topProd_uid305_pT4_uid268_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid305_pT4_uid268_exp10PolyEval_a <= reg_xTop27Bits_uid303_pT4_uid268_exp10PolyEval_0_to_multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_cma_4_q;
topProd_uid305_pT4_uid268_exp10PolyEval_b <= reg_yTop27Bits_uid304_pT4_uid268_exp10PolyEval_0_to_topProd_uid305_pT4_uid268_exp10PolyEval_1_q;
topProd_uid305_pT4_uid268_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid305_pT4_uid268_exp10PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid305_pT4_uid268_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid305_pT4_uid268_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid305_pT4_uid268_exp10PolyEval_q <= topProd_uid305_pT4_uid268_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid315_pT4_uid268_exp10PolyEval(ADD,314)@32
sumAHighB_uid315_pT4_uid268_exp10PolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid305_pT4_uid268_exp10PolyEval_q(53)) & topProd_uid305_pT4_uid268_exp10PolyEval_q);
sumAHighB_uid315_pT4_uid268_exp10PolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid314_pT4_uid268_exp10PolyEval_b(28)) & highBBits_uid314_pT4_uid268_exp10PolyEval_b);
sumAHighB_uid315_pT4_uid268_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid315_pT4_uid268_exp10PolyEval_a) + SIGNED(sumAHighB_uid315_pT4_uid268_exp10PolyEval_b));
sumAHighB_uid315_pT4_uid268_exp10PolyEval_q <= sumAHighB_uid315_pT4_uid268_exp10PolyEval_o(54 downto 0);
--lowRangeB_uid313_pT4_uid268_exp10PolyEval(BITSELECT,312)@32
lowRangeB_uid313_pT4_uid268_exp10PolyEval_in <= multSumOfTwo27_uid308_pT4_uid268_exp10PolyEval_b(17 downto 0);
lowRangeB_uid313_pT4_uid268_exp10PolyEval_b <= lowRangeB_uid313_pT4_uid268_exp10PolyEval_in(17 downto 0);
--add0_uid313_uid316_pT4_uid268_exp10PolyEval(BITJOIN,315)@32
add0_uid313_uid316_pT4_uid268_exp10PolyEval_q <= sumAHighB_uid315_pT4_uid268_exp10PolyEval_q & lowRangeB_uid313_pT4_uid268_exp10PolyEval_b;
--R_uid317_pT4_uid268_exp10PolyEval(BITSELECT,316)@32
R_uid317_pT4_uid268_exp10PolyEval_in <= add0_uid313_uid316_pT4_uid268_exp10PolyEval_q(71 downto 0);
R_uid317_pT4_uid268_exp10PolyEval_b <= R_uid317_pT4_uid268_exp10PolyEval_in(71 downto 26);
--reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1(REG,404)@32
reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1_q <= R_uid317_pT4_uid268_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor(LOGICAL,1146)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_b <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_q <= not (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_a or ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_b);
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_mem_top(CONSTANT,1142)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_mem_top_q <= "01110";
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp(LOGICAL,1143)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_a <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_mem_top_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q);
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_q <= "1" when ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_a = ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_b else "0";
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg(REG,1144)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena(REG,1147)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_nor_q = "1") THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd(LOGICAL,1148)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_a <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_sticky_ena_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_b <= en;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_a and ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_b;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg(DELAY,1123)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => addr_uid64_fpExpETest_b, xout => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt(COUNTER,1138)
-- every=1, low=0, high=14, step=1, init=1
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i = 13 THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_eq = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i - 14;
ELSE
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_i,4));
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg(REG,1139)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux(MUX,1140)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_s <= en;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux: PROCESS (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_s, ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q, ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_q)
BEGIN
CASE ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_s IS
WHEN "0" => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q;
WHEN "1" => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem(DUALMEM,1137)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ia <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_aa <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdreg_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ab <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_rdmux_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 4,
numwords_a => 15,
width_b => 7,
widthad_b => 4,
numwords_b => 15,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_ia
);
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_iq(6 downto 0);
--reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0(REG,379)@30
reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid238_exp10TabGen(LOOKUP,237)@31
memoryC1_uid238_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid238_exp10TabGen_q <= "00100000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC1_uid238_exp10TabGen_q <= "00100000000";
WHEN "0000001" => memoryC1_uid238_exp10TabGen_q <= "00100000010";
WHEN "0000010" => memoryC1_uid238_exp10TabGen_q <= "00100000100";
WHEN "0000011" => memoryC1_uid238_exp10TabGen_q <= "00100000110";
WHEN "0000100" => memoryC1_uid238_exp10TabGen_q <= "00100001000";
WHEN "0000101" => memoryC1_uid238_exp10TabGen_q <= "00100001010";
WHEN "0000110" => memoryC1_uid238_exp10TabGen_q <= "00100001100";
WHEN "0000111" => memoryC1_uid238_exp10TabGen_q <= "00100001110";
WHEN "0001000" => memoryC1_uid238_exp10TabGen_q <= "00100010000";
WHEN "0001001" => memoryC1_uid238_exp10TabGen_q <= "00100010010";
WHEN "0001010" => memoryC1_uid238_exp10TabGen_q <= "00100010100";
WHEN "0001011" => memoryC1_uid238_exp10TabGen_q <= "00100010110";
WHEN "0001100" => memoryC1_uid238_exp10TabGen_q <= "00100011001";
WHEN "0001101" => memoryC1_uid238_exp10TabGen_q <= "00100011011";
WHEN "0001110" => memoryC1_uid238_exp10TabGen_q <= "00100011101";
WHEN "0001111" => memoryC1_uid238_exp10TabGen_q <= "00100011111";
WHEN "0010000" => memoryC1_uid238_exp10TabGen_q <= "00100100010";
WHEN "0010001" => memoryC1_uid238_exp10TabGen_q <= "00100100100";
WHEN "0010010" => memoryC1_uid238_exp10TabGen_q <= "00100100110";
WHEN "0010011" => memoryC1_uid238_exp10TabGen_q <= "00100101000";
WHEN "0010100" => memoryC1_uid238_exp10TabGen_q <= "00100101011";
WHEN "0010101" => memoryC1_uid238_exp10TabGen_q <= "00100101101";
WHEN "0010110" => memoryC1_uid238_exp10TabGen_q <= "00100110000";
WHEN "0010111" => memoryC1_uid238_exp10TabGen_q <= "00100110010";
WHEN "0011000" => memoryC1_uid238_exp10TabGen_q <= "00100110100";
WHEN "0011001" => memoryC1_uid238_exp10TabGen_q <= "00100110111";
WHEN "0011010" => memoryC1_uid238_exp10TabGen_q <= "00100111001";
WHEN "0011011" => memoryC1_uid238_exp10TabGen_q <= "00100111100";
WHEN "0011100" => memoryC1_uid238_exp10TabGen_q <= "00100111110";
WHEN "0011101" => memoryC1_uid238_exp10TabGen_q <= "00101000001";
WHEN "0011110" => memoryC1_uid238_exp10TabGen_q <= "00101000011";
WHEN "0011111" => memoryC1_uid238_exp10TabGen_q <= "00101000110";
WHEN "0100000" => memoryC1_uid238_exp10TabGen_q <= "00101001000";
WHEN "0100001" => memoryC1_uid238_exp10TabGen_q <= "00101001011";
WHEN "0100010" => memoryC1_uid238_exp10TabGen_q <= "00101001101";
WHEN "0100011" => memoryC1_uid238_exp10TabGen_q <= "00101010000";
WHEN "0100100" => memoryC1_uid238_exp10TabGen_q <= "00101010011";
WHEN "0100101" => memoryC1_uid238_exp10TabGen_q <= "00101010101";
WHEN "0100110" => memoryC1_uid238_exp10TabGen_q <= "00101011000";
WHEN "0100111" => memoryC1_uid238_exp10TabGen_q <= "00101011011";
WHEN "0101000" => memoryC1_uid238_exp10TabGen_q <= "00101011101";
WHEN "0101001" => memoryC1_uid238_exp10TabGen_q <= "00101100000";
WHEN "0101010" => memoryC1_uid238_exp10TabGen_q <= "00101100011";
WHEN "0101011" => memoryC1_uid238_exp10TabGen_q <= "00101100110";
WHEN "0101100" => memoryC1_uid238_exp10TabGen_q <= "00101101001";
WHEN "0101101" => memoryC1_uid238_exp10TabGen_q <= "00101101011";
WHEN "0101110" => memoryC1_uid238_exp10TabGen_q <= "00101101110";
WHEN "0101111" => memoryC1_uid238_exp10TabGen_q <= "00101110001";
WHEN "0110000" => memoryC1_uid238_exp10TabGen_q <= "00101110100";
WHEN "0110001" => memoryC1_uid238_exp10TabGen_q <= "00101110111";
WHEN "0110010" => memoryC1_uid238_exp10TabGen_q <= "00101111010";
WHEN "0110011" => memoryC1_uid238_exp10TabGen_q <= "00101111101";
WHEN "0110100" => memoryC1_uid238_exp10TabGen_q <= "00110000000";
WHEN "0110101" => memoryC1_uid238_exp10TabGen_q <= "00110000011";
WHEN "0110110" => memoryC1_uid238_exp10TabGen_q <= "00110000110";
WHEN "0110111" => memoryC1_uid238_exp10TabGen_q <= "00110001001";
WHEN "0111000" => memoryC1_uid238_exp10TabGen_q <= "00110001100";
WHEN "0111001" => memoryC1_uid238_exp10TabGen_q <= "00110001111";
WHEN "0111010" => memoryC1_uid238_exp10TabGen_q <= "00110010010";
WHEN "0111011" => memoryC1_uid238_exp10TabGen_q <= "00110010101";
WHEN "0111100" => memoryC1_uid238_exp10TabGen_q <= "00110011001";
WHEN "0111101" => memoryC1_uid238_exp10TabGen_q <= "00110011100";
WHEN "0111110" => memoryC1_uid238_exp10TabGen_q <= "00110011111";
WHEN "0111111" => memoryC1_uid238_exp10TabGen_q <= "00110100010";
WHEN "1000000" => memoryC1_uid238_exp10TabGen_q <= "00110100110";
WHEN "1000001" => memoryC1_uid238_exp10TabGen_q <= "00110101001";
WHEN "1000010" => memoryC1_uid238_exp10TabGen_q <= "00110101100";
WHEN "1000011" => memoryC1_uid238_exp10TabGen_q <= "00110110000";
WHEN "1000100" => memoryC1_uid238_exp10TabGen_q <= "00110110011";
WHEN "1000101" => memoryC1_uid238_exp10TabGen_q <= "00110110110";
WHEN "1000110" => memoryC1_uid238_exp10TabGen_q <= "00110111010";
WHEN "1000111" => memoryC1_uid238_exp10TabGen_q <= "00110111101";
WHEN "1001000" => memoryC1_uid238_exp10TabGen_q <= "00111000001";
WHEN "1001001" => memoryC1_uid238_exp10TabGen_q <= "00111000100";
WHEN "1001010" => memoryC1_uid238_exp10TabGen_q <= "00111001000";
WHEN "1001011" => memoryC1_uid238_exp10TabGen_q <= "00111001011";
WHEN "1001100" => memoryC1_uid238_exp10TabGen_q <= "00111001111";
WHEN "1001101" => memoryC1_uid238_exp10TabGen_q <= "00111010011";
WHEN "1001110" => memoryC1_uid238_exp10TabGen_q <= "00111010110";
WHEN "1001111" => memoryC1_uid238_exp10TabGen_q <= "00111011010";
WHEN "1010000" => memoryC1_uid238_exp10TabGen_q <= "00111011110";
WHEN "1010001" => memoryC1_uid238_exp10TabGen_q <= "00111100010";
WHEN "1010010" => memoryC1_uid238_exp10TabGen_q <= "00111100101";
WHEN "1010011" => memoryC1_uid238_exp10TabGen_q <= "00111101001";
WHEN "1010100" => memoryC1_uid238_exp10TabGen_q <= "00111101101";
WHEN "1010101" => memoryC1_uid238_exp10TabGen_q <= "00111110001";
WHEN "1010110" => memoryC1_uid238_exp10TabGen_q <= "00111110101";
WHEN "1010111" => memoryC1_uid238_exp10TabGen_q <= "00111111001";
WHEN "1011000" => memoryC1_uid238_exp10TabGen_q <= "00111111101";
WHEN "1011001" => memoryC1_uid238_exp10TabGen_q <= "01000000001";
WHEN "1011010" => memoryC1_uid238_exp10TabGen_q <= "01000000101";
WHEN "1011011" => memoryC1_uid238_exp10TabGen_q <= "01000001001";
WHEN "1011100" => memoryC1_uid238_exp10TabGen_q <= "01000001101";
WHEN "1011101" => memoryC1_uid238_exp10TabGen_q <= "01000010001";
WHEN "1011110" => memoryC1_uid238_exp10TabGen_q <= "01000010101";
WHEN "1011111" => memoryC1_uid238_exp10TabGen_q <= "01000011001";
WHEN "1100000" => memoryC1_uid238_exp10TabGen_q <= "01000011101";
WHEN "1100001" => memoryC1_uid238_exp10TabGen_q <= "01000100010";
WHEN "1100010" => memoryC1_uid238_exp10TabGen_q <= "01000100110";
WHEN "1100011" => memoryC1_uid238_exp10TabGen_q <= "01000101010";
WHEN "1100100" => memoryC1_uid238_exp10TabGen_q <= "01000101111";
WHEN "1100101" => memoryC1_uid238_exp10TabGen_q <= "01000110011";
WHEN "1100110" => memoryC1_uid238_exp10TabGen_q <= "01000110111";
WHEN "1100111" => memoryC1_uid238_exp10TabGen_q <= "01000111100";
WHEN "1101000" => memoryC1_uid238_exp10TabGen_q <= "01001000000";
WHEN "1101001" => memoryC1_uid238_exp10TabGen_q <= "01001000101";
WHEN "1101010" => memoryC1_uid238_exp10TabGen_q <= "01001001001";
WHEN "1101011" => memoryC1_uid238_exp10TabGen_q <= "01001001110";
WHEN "1101100" => memoryC1_uid238_exp10TabGen_q <= "01001010011";
WHEN "1101101" => memoryC1_uid238_exp10TabGen_q <= "01001010111";
WHEN "1101110" => memoryC1_uid238_exp10TabGen_q <= "01001011100";
WHEN "1101111" => memoryC1_uid238_exp10TabGen_q <= "01001100001";
WHEN "1110000" => memoryC1_uid238_exp10TabGen_q <= "01001100110";
WHEN "1110001" => memoryC1_uid238_exp10TabGen_q <= "01001101010";
WHEN "1110010" => memoryC1_uid238_exp10TabGen_q <= "01001101111";
WHEN "1110011" => memoryC1_uid238_exp10TabGen_q <= "01001110100";
WHEN "1110100" => memoryC1_uid238_exp10TabGen_q <= "01001111001";
WHEN "1110101" => memoryC1_uid238_exp10TabGen_q <= "01001111110";
WHEN "1110110" => memoryC1_uid238_exp10TabGen_q <= "01010000011";
WHEN "1110111" => memoryC1_uid238_exp10TabGen_q <= "01010001000";
WHEN "1111000" => memoryC1_uid238_exp10TabGen_q <= "01010001101";
WHEN "1111001" => memoryC1_uid238_exp10TabGen_q <= "01010010010";
WHEN "1111010" => memoryC1_uid238_exp10TabGen_q <= "01010011000";
WHEN "1111011" => memoryC1_uid238_exp10TabGen_q <= "01010011101";
WHEN "1111100" => memoryC1_uid238_exp10TabGen_q <= "01010100010";
WHEN "1111101" => memoryC1_uid238_exp10TabGen_q <= "01010100111";
WHEN "1111110" => memoryC1_uid238_exp10TabGen_q <= "01010101101";
WHEN "1111111" => memoryC1_uid238_exp10TabGen_q <= "01010110010";
WHEN OTHERS =>
memoryC1_uid238_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--memoryC1_uid237_exp10TabGen(LOOKUP,236)@31
memoryC1_uid237_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC1_uid237_exp10TabGen_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid64_fpExpETest_0_to_memoryC1_uid237_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC1_uid237_exp10TabGen_q <= "0000000000000000000000000000000000000000";
WHEN "0000001" => memoryC1_uid237_exp10TabGen_q <= "0000001000000001010101100000000000111010";
WHEN "0000010" => memoryC1_uid237_exp10TabGen_q <= "0000100000001010101101010101110111011110";
WHEN "0000011" => memoryC1_uid237_exp10TabGen_q <= "0001001000100100001101100100000100000110";
WHEN "0000100" => memoryC1_uid237_exp10TabGen_q <= "0010000001010110000000010001001001111011";
WHEN "0000101" => memoryC1_uid237_exp10TabGen_q <= "0011001010101000010011101001110000100000";
WHEN "0000110" => memoryC1_uid237_exp10TabGen_q <= "0100100100100011011010000010100111101010";
WHEN "0000111" => memoryC1_uid237_exp10TabGen_q <= "0110001111001111101001111010101100000101";
WHEN "0001000" => memoryC1_uid237_exp10TabGen_q <= "1000001010110101011101111101001101001110";
WHEN "0001001" => memoryC1_uid237_exp10TabGen_q <= "1010010111011101010101000011110011001011";
WHEN "0001010" => memoryC1_uid237_exp10TabGen_q <= "1100110101001111110010011000100111010001";
WHEN "0001011" => memoryC1_uid237_exp10TabGen_q <= "1111100100010101011101011000011100010001";
WHEN "0001100" => memoryC1_uid237_exp10TabGen_q <= "0010100100110111000001110100111000010010";
WHEN "0001101" => memoryC1_uid237_exp10TabGen_q <= "0101110110111101001111110110100000001001";
WHEN "0001110" => memoryC1_uid237_exp10TabGen_q <= "1001011010110000111011111111000011100110";
WHEN "0001111" => memoryC1_uid237_exp10TabGen_q <= "1101010000011010111111001011101001010000";
WHEN "0010000" => memoryC1_uid237_exp10TabGen_q <= "0001011000000100010110110110111101011001";
WHEN "0010001" => memoryC1_uid237_exp10TabGen_q <= "0101110001110110000100111011100010100010";
WHEN "0010010" => memoryC1_uid237_exp10TabGen_q <= "1010011101111001001111110110000000011101";
WHEN "0010011" => memoryC1_uid237_exp10TabGen_q <= "1111011100010111000010100111010101011010";
WHEN "0010100" => memoryC1_uid237_exp10TabGen_q <= "0100101101011000101100110111001011010010";
WHEN "0010101" => memoryC1_uid237_exp10TabGen_q <= "1010010001000111100010110110001000001100";
WHEN "0010110" => memoryC1_uid237_exp10TabGen_q <= "0000000111101100111101100000000110110001";
WHEN "0010111" => memoryC1_uid237_exp10TabGen_q <= "0110010001010010011010011110101001111111";
WHEN "0011000" => memoryC1_uid237_exp10TabGen_q <= "1100101110000001011100001011010110001100";
WHEN "0011001" => memoryC1_uid237_exp10TabGen_q <= "0011011110000011101001110010001000001011";
WHEN "0011010" => memoryC1_uid237_exp10TabGen_q <= "1010100001100010101111010011110000010000";
WHEN "0011011" => memoryC1_uid237_exp10TabGen_q <= "0001111000101000011101101000001101001011";
WHEN "0011100" => memoryC1_uid237_exp10TabGen_q <= "1001100011011110101010100001000111100100";
WHEN "0011101" => memoryC1_uid237_exp10TabGen_q <= "0001100010001111010000101100001111101101";
WHEN "0011110" => memoryC1_uid237_exp10TabGen_q <= "1001110101000100001111110101111100011111";
WHEN "0011111" => memoryC1_uid237_exp10TabGen_q <= "0010011100000111101100101011101010111111";
WHEN "0100000" => memoryC1_uid237_exp10TabGen_q <= "1011010111100011110000111110100000011101";
WHEN "0100001" => memoryC1_uid237_exp10TabGen_q <= "0100100111100010101011100101101011001010";
WHEN "0100010" => memoryC1_uid237_exp10TabGen_q <= "1110001100001110110000100001000111011110";
WHEN "0100011" => memoryC1_uid237_exp10TabGen_q <= "1000000101110010011000111100000100110111";
WHEN "0100100" => memoryC1_uid237_exp10TabGen_q <= "0010010100011000000011001111101011010111";
WHEN "0100101" => memoryC1_uid237_exp10TabGen_q <= "1100111000001010010011000101100010111111";
WHEN "0100110" => memoryC1_uid237_exp10TabGen_q <= "0111110001010011110001011010011110110011";
WHEN "0100111" => memoryC1_uid237_exp10TabGen_q <= "0010111111111111001100100001000011111001";
WHEN "0101000" => memoryC1_uid237_exp10TabGen_q <= "1110100100010111011000000100010111111100";
WHEN "0101001" => memoryC1_uid237_exp10TabGen_q <= "1010011110100111001101001010101100001001";
WHEN "0101010" => memoryC1_uid237_exp10TabGen_q <= "0110101110111001101010011000001100101111";
WHEN "0101011" => memoryC1_uid237_exp10TabGen_q <= "0011010101011001110011110001101111000101";
WHEN "0101100" => memoryC1_uid237_exp10TabGen_q <= "0000010010010010110010111111100101001101";
WHEN "0101101" => memoryC1_uid237_exp10TabGen_q <= "1101100101101111110111010000001101001010";
WHEN "0101110" => memoryC1_uid237_exp10TabGen_q <= "1011001111111100010101011011000111100000";
WHEN "0101111" => memoryC1_uid237_exp10TabGen_q <= "1001010001000011101000000011101011010001";
WHEN "0110000" => memoryC1_uid237_exp10TabGen_q <= "0111101001010001001111011011111011111001";
WHEN "0110001" => memoryC1_uid237_exp10TabGen_q <= "0110011000110000110001100111100011000100";
WHEN "0110010" => memoryC1_uid237_exp10TabGen_q <= "0101011111101101111010011110101000100111";
WHEN "0110011" => memoryC1_uid237_exp10TabGen_q <= "0100111110010100011011110000101110110000";
WHEN "0110100" => memoryC1_uid237_exp10TabGen_q <= "0100110100110000001101000111101101011011";
WHEN "0110101" => memoryC1_uid237_exp10TabGen_q <= "0101000011001101001100001010110000110011";
WHEN "0110110" => memoryC1_uid237_exp10TabGen_q <= "0101101001110111011100100001011001001110";
WHEN "0110111" => memoryC1_uid237_exp10TabGen_q <= "0110101000111011000111110110011010101000";
WHEN "0111000" => memoryC1_uid237_exp10TabGen_q <= "1000000000100100011101111011000000000000";
WHEN "0111001" => memoryC1_uid237_exp10TabGen_q <= "1001110000111111110100101001101111110010";
WHEN "0111010" => memoryC1_uid237_exp10TabGen_q <= "1011111010011001101000001001101111101100";
WHEN "0111011" => memoryC1_uid237_exp10TabGen_q <= "1110011100111110011010110001101101110011";
WHEN "0111100" => memoryC1_uid237_exp10TabGen_q <= "0001011000111010110101001011000111010110";
WHEN "0111101" => memoryC1_uid237_exp10TabGen_q <= "0100101110011011100110010101010100001010";
WHEN "0111110" => memoryC1_uid237_exp10TabGen_q <= "1000011101101101100011101000110001001110";
WHEN "0111111" => memoryC1_uid237_exp10TabGen_q <= "1100100110111101101000111010001111101111";
WHEN "1000000" => memoryC1_uid237_exp10TabGen_q <= "0001001010011000111000011110000001110001";
WHEN "1000001" => memoryC1_uid237_exp10TabGen_q <= "0110001000001100011011001011001100110100";
WHEN "1000010" => memoryC1_uid237_exp10TabGen_q <= "1011100000100101100000011110111011011101";
WHEN "1000011" => memoryC1_uid237_exp10TabGen_q <= "0001010011110001011110011111110001000001";
WHEN "1000100" => memoryC1_uid237_exp10TabGen_q <= "0111100001111101110010000000111110011000";
WHEN "1000101" => memoryC1_uid237_exp10TabGen_q <= "1110001011010111111110100101111010101100";
WHEN "1000110" => memoryC1_uid237_exp10TabGen_q <= "0101010000001101101110100101011011101100";
WHEN "1000111" => memoryC1_uid237_exp10TabGen_q <= "1100110000101100110011001101001111000101";
WHEN "1001000" => memoryC1_uid237_exp10TabGen_q <= "0100101101000011000100100101011001001000";
WHEN "1001001" => memoryC1_uid237_exp10TabGen_q <= "1101000101011110100001110011110000011001";
WHEN "1001010" => memoryC1_uid237_exp10TabGen_q <= "0101111010001101010000111111011111001100";
WHEN "1001011" => memoryC1_uid237_exp10TabGen_q <= "1111001011011101011111010100100100001011";
WHEN "1001100" => memoryC1_uid237_exp10TabGen_q <= "1000111001011101100001000111010110000110";
WHEN "1001101" => memoryC1_uid237_exp10TabGen_q <= "0011000100011011110001111000001000100101";
WHEN "1001110" => memoryC1_uid237_exp10TabGen_q <= "1101101100100110110100010110110011010110";
WHEN "1001111" => memoryC1_uid237_exp10TabGen_q <= "1000110010001101010010100110011010010111";
WHEN "1010000" => memoryC1_uid237_exp10TabGen_q <= "0100010101011101111110000000111000111010";
WHEN "1010001" => memoryC1_uid237_exp10TabGen_q <= "0000010110100111101111011010101101110110";
WHEN "1010010" => memoryC1_uid237_exp10TabGen_q <= "1100110101111001100111000110101001001101";
WHEN "1010011" => memoryC1_uid237_exp10TabGen_q <= "1001110011100010101100111001011101100011";
WHEN "1010100" => memoryC1_uid237_exp10TabGen_q <= "0111001111110010010000001101110000010000";
WHEN "1010101" => memoryC1_uid237_exp10TabGen_q <= "0101001010110111101000000111101111000000";
WHEN "1010110" => memoryC1_uid237_exp10TabGen_q <= "0011100101000010010011011001000011111010";
WHEN "1010111" => memoryC1_uid237_exp10TabGen_q <= "0010011110100001111000100100101110110000";
WHEN "1011000" => memoryC1_uid237_exp10TabGen_q <= "0001110111100110000110000010111110001011";
WHEN "1011001" => memoryC1_uid237_exp10TabGen_q <= "0001110000011110110010000101001010010000";
WHEN "1011010" => memoryC1_uid237_exp10TabGen_q <= "0010001001011011111010111001110011101101";
WHEN "1011011" => memoryC1_uid237_exp10TabGen_q <= "0011000010101101100110110000100001110010";
WHEN "1011100" => memoryC1_uid237_exp10TabGen_q <= "0100011100100100000011111110000100111100";
WHEN "1011101" => memoryC1_uid237_exp10TabGen_q <= "0110010111001111101001000000011010110011";
WHEN "1011110" => memoryC1_uid237_exp10TabGen_q <= "1000110011000000110100100010110010101001";
WHEN "1011111" => memoryC1_uid237_exp10TabGen_q <= "1011110000001000001101100001110100111001";
WHEN "1100000" => memoryC1_uid237_exp10TabGen_q <= "1111001110110110100011001111101110011101";
WHEN "1100001" => memoryC1_uid237_exp10TabGen_q <= "0011001111011100101101011000011011011101";
WHEN "1100010" => memoryC1_uid237_exp10TabGen_q <= "0111110010001011101100000101110100110000";
WHEN "1100011" => memoryC1_uid237_exp10TabGen_q <= "1100110111010100101000000100000000111000";
WHEN "1100100" => memoryC1_uid237_exp10TabGen_q <= "0010011111001000110010100101100110001010";
WHEN "1100101" => memoryC1_uid237_exp10TabGen_q <= "1000101001111001100101100111111110010101";
WHEN "1100110" => memoryC1_uid237_exp10TabGen_q <= "1111010111111000100011110111101101010110";
WHEN "1100111" => memoryC1_uid237_exp10TabGen_q <= "0110101001010111011000110100111010100000";
WHEN "1101000" => memoryC1_uid237_exp10TabGen_q <= "1110011110100111111000110111101010100011";
WHEN "1101001" => memoryC1_uid237_exp10TabGen_q <= "0110110111111100000001010100011101110011";
WHEN "1101010" => memoryC1_uid237_exp10TabGen_q <= "1111110101100101111000100000101110100001";
WHEN "1101011" => memoryC1_uid237_exp10TabGen_q <= "1001010111110111101101110111010010010010";
WHEN "1101100" => memoryC1_uid237_exp10TabGen_q <= "0011011111000011111001111100111111011110";
WHEN "1101101" => memoryC1_uid237_exp10TabGen_q <= "1110001011011100111110100101010001110110";
WHEN "1101110" => memoryC1_uid237_exp10TabGen_q <= "1001011101010101100110110110110011001000";
WHEN "1101111" => memoryC1_uid237_exp10TabGen_q <= "0101010101000000100111010000000110011111";
WHEN "1110000" => memoryC1_uid237_exp10TabGen_q <= "0001110010110000111101101100010101100001";
WHEN "1110001" => memoryC1_uid237_exp10TabGen_q <= "1110110110111001110001100111111111010101";
WHEN "1110010" => memoryC1_uid237_exp10TabGen_q <= "1100100001101110010100000101101010011001";
WHEN "1110011" => memoryC1_uid237_exp10TabGen_q <= "1010110011100001111111110010111001100100";
WHEN "1110100" => memoryC1_uid237_exp10TabGen_q <= "1001101100101000011001001101000001001110";
WHEN "1110101" => memoryC1_uid237_exp10TabGen_q <= "1001001101010101001110100110000010110100";
WHEN "1110110" => memoryC1_uid237_exp10TabGen_q <= "1001010101111100011000001001100101100100";
WHEN "1110111" => memoryC1_uid237_exp10TabGen_q <= "1010000110110001111000000001110110110011";
WHEN "1111000" => memoryC1_uid237_exp10TabGen_q <= "1011100000001001111010011100101001101110";
WHEN "1111001" => memoryC1_uid237_exp10TabGen_q <= "1101100010011000110101110000011001010011";
WHEN "1111010" => memoryC1_uid237_exp10TabGen_q <= "0000001101110011001010100001010000011101";
WHEN "1111011" => memoryC1_uid237_exp10TabGen_q <= "0011100010101101100011100110001111100011";
WHEN "1111100" => memoryC1_uid237_exp10TabGen_q <= "0111100001011100110110001110011000110111";
WHEN "1111101" => memoryC1_uid237_exp10TabGen_q <= "1100001010010110000010000101111100110011";
WHEN "1111110" => memoryC1_uid237_exp10TabGen_q <= "0001011101101110010001011011101010111011";
WHEN "1111111" => memoryC1_uid237_exp10TabGen_q <= "0111011011111010111001000110000010110110";
WHEN OTHERS =>
memoryC1_uid237_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--os_uid239_exp10TabGen(BITJOIN,238)@32
os_uid239_exp10TabGen_q <= memoryC1_uid238_exp10TabGen_q & memoryC1_uid237_exp10TabGen_q;
--cIncludingRoundingBit_uid270_exp10PolyEval(BITJOIN,269)@32
cIncludingRoundingBit_uid270_exp10PolyEval_q <= os_uid239_exp10TabGen_q & rndBit_uid263_exp10PolyEval_q;
--reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0(REG,403)@32
reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0_q <= cIncludingRoundingBit_uid270_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid271_exp10PolyEval(ADD,270)@33
ts4_uid271_exp10PolyEval_a <= STD_LOGIC_VECTOR((53 downto 53 => reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0_q(52)) & reg_cIncludingRoundingBit_uid270_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_0_q);
ts4_uid271_exp10PolyEval_b <= STD_LOGIC_VECTOR((53 downto 46 => reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1_q(45)) & reg_R_uid317_pT4_uid268_exp10PolyEval_0_to_ts4_uid271_exp10PolyEval_1_q);
ts4_uid271_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid271_exp10PolyEval_a) + SIGNED(ts4_uid271_exp10PolyEval_b));
ts4_uid271_exp10PolyEval_q <= ts4_uid271_exp10PolyEval_o(53 downto 0);
--s4_uid272_exp10PolyEval(BITSELECT,271)@33
s4_uid272_exp10PolyEval_in <= ts4_uid271_exp10PolyEval_q;
s4_uid272_exp10PolyEval_b <= s4_uid272_exp10PolyEval_in(53 downto 1);
--yTop27Bits_uid319_pT5_uid274_exp10PolyEval(BITSELECT,318)@33
yTop27Bits_uid319_pT5_uid274_exp10PolyEval_in <= s4_uid272_exp10PolyEval_b;
yTop27Bits_uid319_pT5_uid274_exp10PolyEval_b <= yTop27Bits_uid319_pT5_uid274_exp10PolyEval_in(52 downto 26);
--reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9(REG,408)@33
reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9_q <= yTop27Bits_uid319_pT5_uid274_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor(LOGICAL,1107)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_b <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_q <= not (ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_a or ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_b);
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_mem_top(CONSTANT,1103)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_mem_top_q <= "010000";
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp(LOGICAL,1104)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_a <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_mem_top_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_a = ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg(REG,1105)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena(REG,1108)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd(LOGICAL,1109)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_a <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_sticky_ena_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_a and ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_b;
--xBottomBits_uid322_pT5_uid274_exp10PolyEval(BITSELECT,321)@14
xBottomBits_uid322_pT5_uid274_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b(20 downto 0);
xBottomBits_uid322_pT5_uid274_exp10PolyEval_b <= xBottomBits_uid322_pT5_uid274_exp10PolyEval_in(20 downto 0);
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_inputreg(DELAY,1097)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 21, depth => 1 )
PORT MAP ( xin => xBottomBits_uid322_pT5_uid274_exp10PolyEval_b, xout => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt(COUNTER,1099)
-- every=1, low=0, high=16, step=1, init=1
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i = 15 THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg(REG,1100)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux(MUX,1101)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_s, ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q, ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem(DUALMEM,1098)
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ia <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_inputreg_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 5,
numwords_a => 17,
width_b => 21,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_iq(20 downto 0);
--pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval(BITJOIN,325)@33
pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((4 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7(REG,407)@33
reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7_q <= pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor(LOGICAL,1094)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_b <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_q <= not (ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_a or ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_b);
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_mem_top(CONSTANT,1090)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_mem_top_q <= "010001";
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp(LOGICAL,1091)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_a <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_mem_top_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q);
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_q <= "1" when ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_a = ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_b else "0";
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg(REG,1092)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena(REG,1095)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_nor_q = "1") THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd(LOGICAL,1096)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_a <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_sticky_ena_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_b <= en;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_a and ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_b;
--xTop26Bits_uid323_pT5_uid274_exp10PolyEval(BITSELECT,322)@14
xTop26Bits_uid323_pT5_uid274_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b;
xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b <= xTop26Bits_uid323_pT5_uid274_exp10PolyEval_in(47 downto 22);
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_inputreg(DELAY,1084)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b, xout => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt(COUNTER,1086)
-- every=1, low=0, high=17, step=1, init=1
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i = 16 THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i - 17;
ELSE
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_i,5));
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg(REG,1087)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux(MUX,1088)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_s <= en;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux: PROCESS (ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_s, ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q, ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem(DUALMEM,1085)
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ia <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_inputreg_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_aa <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdreg_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ab <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_rdmux_q;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 5,
numwords_a => 18,
width_b => 26,
widthad_b => 5,
numwords_b => 18,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_iq,
address_a => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_aa,
data_a => ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_ia
);
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_reset0 <= areset;
ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_q <= ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_iq(25 downto 0);
--spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval(BITJOIN,324)@34
spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_q <= GND_q & ld_xTop26Bits_uid323_pT5_uid274_exp10PolyEval_b_to_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_a_replace_mem_q;
--reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6(REG,406)@34
reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6_q <= spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid321_pT5_uid274_exp10PolyEval(BITSELECT,320)@33
yBottomBits_uid321_pT5_uid274_exp10PolyEval_in <= s4_uid272_exp10PolyEval_b(25 downto 0);
yBottomBits_uid321_pT5_uid274_exp10PolyEval_b <= yBottomBits_uid321_pT5_uid274_exp10PolyEval_in(25 downto 0);
--ld_yBottomBits_uid321_pT5_uid274_exp10PolyEval_b_to_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_b(DELAY,768)@33
ld_yBottomBits_uid321_pT5_uid274_exp10PolyEval_b_to_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_b : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => yBottomBits_uid321_pT5_uid274_exp10PolyEval_b, xout => ld_yBottomBits_uid321_pT5_uid274_exp10PolyEval_b_to_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval(BITJOIN,326)@34
pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_q <= ld_yBottomBits_uid321_pT5_uid274_exp10PolyEval_b_to_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_b_q & GND_q;
--reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4(REG,405)@34
reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4_q <= pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--VCC(CONSTANT,1)
VCC_q <= "1";
--multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma(CHAINMULTADD,340)@35
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a(0),28));
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a(1),28));
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p(0) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l(0) * multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c(0);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p(1) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_l(1) * multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c(1);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p(0),56);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_p(1),56);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x(0) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w(0);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x(1) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_w(1);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y(0) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s(1) + multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x(0);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y(1) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_x(1);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_pad_yBottomBits_uid321_uid327_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_4_q),27);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_7_q),27);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c(0) <= RESIZE(SIGNED(reg_spad_xTop26Bits_uid323_uid325_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_6_q),27);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s(0) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y(0);
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s(1) <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval(BITSELECT,328)@38
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_in <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_q;
multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_b <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_in(54 downto 1);
--highBBits_uid335_pT5_uid274_exp10PolyEval(BITSELECT,334)@38
highBBits_uid335_pT5_uid274_exp10PolyEval_in <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_b;
highBBits_uid335_pT5_uid274_exp10PolyEval_b <= highBBits_uid335_pT5_uid274_exp10PolyEval_in(53 downto 19);
--ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor(LOGICAL,1170)
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_b <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_a or ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_b);
--ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena(REG,1171)
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd(LOGICAL,1172)
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_b;
--xTop27Bits_uid318_pT5_uid274_exp10PolyEval(BITSELECT,317)@14
xTop27Bits_uid318_pT5_uid274_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b;
xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b <= xTop27Bits_uid318_pT5_uid274_exp10PolyEval_in(47 downto 21);
--ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_inputreg(DELAY,1160)
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b, xout => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem(DUALMEM,1161)
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_aa <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ab <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 5,
numwords_a => 17,
width_b => 27,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0(REG,411)@33
reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_q <= ld_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_b_to_reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid320_pT5_uid274_exp10PolyEval(MULT,319)@34
topProd_uid320_pT5_uid274_exp10PolyEval_pr <= signed(resize(UNSIGNED(topProd_uid320_pT5_uid274_exp10PolyEval_a),28)) * SIGNED(topProd_uid320_pT5_uid274_exp10PolyEval_b);
topProd_uid320_pT5_uid274_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid320_pT5_uid274_exp10PolyEval_a <= (others => '0');
topProd_uid320_pT5_uid274_exp10PolyEval_b <= (others => '0');
topProd_uid320_pT5_uid274_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid320_pT5_uid274_exp10PolyEval_a <= reg_xTop27Bits_uid318_pT5_uid274_exp10PolyEval_0_to_topProd_uid320_pT5_uid274_exp10PolyEval_0_q;
topProd_uid320_pT5_uid274_exp10PolyEval_b <= reg_yTop27Bits_uid319_pT5_uid274_exp10PolyEval_0_to_multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_cma_9_q;
topProd_uid320_pT5_uid274_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid320_pT5_uid274_exp10PolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid320_pT5_uid274_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid320_pT5_uid274_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid320_pT5_uid274_exp10PolyEval_q <= topProd_uid320_pT5_uid274_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor(LOGICAL,1120)
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_b <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_q <= not (ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_a or ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_b);
--ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena(REG,1121)
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_nor_q = "1") THEN
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd(LOGICAL,1122)
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_a <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_sticky_ena_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_b <= en;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_q <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_a and ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_b;
--sSM0W_uid331_pT5_uid274_exp10PolyEval(BITSELECT,330)@14
sSM0W_uid331_pT5_uid274_exp10PolyEval_in <= yPPolyEval_uid65_fpExpETest_b(20 downto 0);
sSM0W_uid331_pT5_uid274_exp10PolyEval_b <= sSM0W_uid331_pT5_uid274_exp10PolyEval_in(20 downto 18);
--reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1(REG,410)@14
reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q <= sSM0W_uid331_pT5_uid274_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_inputreg(DELAY,1110)
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q, xout => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem(DUALMEM,1111)
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ia <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_inputreg_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_aa <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdreg_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ab <= ld_xBottomBits_uid322_pT5_uid274_exp10PolyEval_b_to_pad_xBottomBits_uid322_uid326_pT5_uid274_exp10PolyEval_b_replace_rdmux_q;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 17,
width_b => 3,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_iq,
address_a => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_aa,
data_a => ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_ia
);
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_reset0 <= areset;
ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_q <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_iq(2 downto 0);
--sSM0H_uid330_pT5_uid274_exp10PolyEval(BITSELECT,329)@33
sSM0H_uid330_pT5_uid274_exp10PolyEval_in <= s4_uid272_exp10PolyEval_b(25 downto 0);
sSM0H_uid330_pT5_uid274_exp10PolyEval_b <= sSM0H_uid330_pT5_uid274_exp10PolyEval_in(25 downto 23);
--reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0(REG,409)@33
reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0_q <= sSM0H_uid330_pT5_uid274_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid332_pT5_uid274_exp10PolyEval(MULT,331)@34
sm0_uid332_pT5_uid274_exp10PolyEval_pr <= UNSIGNED(sm0_uid332_pT5_uid274_exp10PolyEval_a) * UNSIGNED(sm0_uid332_pT5_uid274_exp10PolyEval_b);
sm0_uid332_pT5_uid274_exp10PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid332_pT5_uid274_exp10PolyEval_a <= (others => '0');
sm0_uid332_pT5_uid274_exp10PolyEval_b <= (others => '0');
sm0_uid332_pT5_uid274_exp10PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid332_pT5_uid274_exp10PolyEval_a <= reg_sSM0H_uid330_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_0_q;
sm0_uid332_pT5_uid274_exp10PolyEval_b <= ld_reg_sSM0W_uid331_pT5_uid274_exp10PolyEval_0_to_sm0_uid332_pT5_uid274_exp10PolyEval_1_q_to_sm0_uid332_pT5_uid274_exp10PolyEval_b_replace_mem_q;
sm0_uid332_pT5_uid274_exp10PolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid332_pT5_uid274_exp10PolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid332_pT5_uid274_exp10PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid332_pT5_uid274_exp10PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid332_pT5_uid274_exp10PolyEval_q <= sm0_uid332_pT5_uid274_exp10PolyEval_s1;
END IF;
END IF;
END PROCESS;
--TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval(BITJOIN,332)@37
TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q <= topProd_uid320_pT5_uid274_exp10PolyEval_q & sm0_uid332_pT5_uid274_exp10PolyEval_q;
--ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a(DELAY,778)@37
ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q, xout => ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--sumAHighB_uid336_pT5_uid274_exp10PolyEval(ADD,335)@38
sumAHighB_uid336_pT5_uid274_exp10PolyEval_a <= STD_LOGIC_VECTOR((60 downto 60 => ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a_q(59)) & ld_TtopProdConcSoftProd_uid333_pT5_uid274_exp10PolyEval_q_to_sumAHighB_uid336_pT5_uid274_exp10PolyEval_a_q);
sumAHighB_uid336_pT5_uid274_exp10PolyEval_b <= STD_LOGIC_VECTOR((60 downto 35 => highBBits_uid335_pT5_uid274_exp10PolyEval_b(34)) & highBBits_uid335_pT5_uid274_exp10PolyEval_b);
sumAHighB_uid336_pT5_uid274_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid336_pT5_uid274_exp10PolyEval_a) + SIGNED(sumAHighB_uid336_pT5_uid274_exp10PolyEval_b));
sumAHighB_uid336_pT5_uid274_exp10PolyEval_q <= sumAHighB_uid336_pT5_uid274_exp10PolyEval_o(60 downto 0);
--lowRangeB_uid334_pT5_uid274_exp10PolyEval(BITSELECT,333)@38
lowRangeB_uid334_pT5_uid274_exp10PolyEval_in <= multSumOfTwo27_uid325_pT5_uid274_exp10PolyEval_b(18 downto 0);
lowRangeB_uid334_pT5_uid274_exp10PolyEval_b <= lowRangeB_uid334_pT5_uid274_exp10PolyEval_in(18 downto 0);
--add0_uid334_uid337_pT5_uid274_exp10PolyEval(BITJOIN,336)@38
add0_uid334_uid337_pT5_uid274_exp10PolyEval_q <= sumAHighB_uid336_pT5_uid274_exp10PolyEval_q & lowRangeB_uid334_pT5_uid274_exp10PolyEval_b;
--R_uid338_pT5_uid274_exp10PolyEval(BITSELECT,337)@38
R_uid338_pT5_uid274_exp10PolyEval_in <= add0_uid334_uid337_pT5_uid274_exp10PolyEval_q(78 downto 0);
R_uid338_pT5_uid274_exp10PolyEval_b <= R_uid338_pT5_uid274_exp10PolyEval_in(78 downto 24);
--reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1(REG,414)@38
reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1_q <= "0000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1_q <= R_uid338_pT5_uid274_exp10PolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor(LOGICAL,1016)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_b <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_q <= not (ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_a or ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_b);
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_mem_top(CONSTANT,1012)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_mem_top_q <= "010100";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp(LOGICAL,1013)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_mem_top_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_q <= "1" when ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_a = ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_b else "0";
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg(REG,1014)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena(REG,1017)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_nor_q = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd(LOGICAL,1018)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_a <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_sticky_ena_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_b <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_a and ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_b;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt(COUNTER,1008)
-- every=1, low=0, high=20, step=1, init=1
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i = 19 THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_eq = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i - 20;
ELSE
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_i,5));
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg(REG,1009)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux(MUX,1010)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_s <= en;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux: PROCESS (ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_s, ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q, ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_s IS
WHEN "0" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q;
WHEN "1" => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem(DUALMEM,1007)
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ia <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_inputreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_aa <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ab <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 21,
width_b => 7,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_iq,
address_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_aa,
data_a => ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_ia
);
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_iq(6 downto 0);
--memoryC0_uid235_exp10TabGen(LOOKUP,234)@37
memoryC0_uid235_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid235_exp10TabGen_q <= "001000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_mem_q) IS
WHEN "0000000" => memoryC0_uid235_exp10TabGen_q <= "001000000000000000";
WHEN "0000001" => memoryC0_uid235_exp10TabGen_q <= "001000000100000001";
WHEN "0000010" => memoryC0_uid235_exp10TabGen_q <= "001000001000000100";
WHEN "0000011" => memoryC0_uid235_exp10TabGen_q <= "001000001100001001";
WHEN "0000100" => memoryC0_uid235_exp10TabGen_q <= "001000010000010000";
WHEN "0000101" => memoryC0_uid235_exp10TabGen_q <= "001000010100011001";
WHEN "0000110" => memoryC0_uid235_exp10TabGen_q <= "001000011000100100";
WHEN "0000111" => memoryC0_uid235_exp10TabGen_q <= "001000011100110001";
WHEN "0001000" => memoryC0_uid235_exp10TabGen_q <= "001000100001000001";
WHEN "0001001" => memoryC0_uid235_exp10TabGen_q <= "001000100101010010";
WHEN "0001010" => memoryC0_uid235_exp10TabGen_q <= "001000101001100110";
WHEN "0001011" => memoryC0_uid235_exp10TabGen_q <= "001000101101111100";
WHEN "0001100" => memoryC0_uid235_exp10TabGen_q <= "001000110010010100";
WHEN "0001101" => memoryC0_uid235_exp10TabGen_q <= "001000110110101110";
WHEN "0001110" => memoryC0_uid235_exp10TabGen_q <= "001000111011001011";
WHEN "0001111" => memoryC0_uid235_exp10TabGen_q <= "001000111111101010";
WHEN "0010000" => memoryC0_uid235_exp10TabGen_q <= "001001000100001011";
WHEN "0010001" => memoryC0_uid235_exp10TabGen_q <= "001001001000101110";
WHEN "0010010" => memoryC0_uid235_exp10TabGen_q <= "001001001101010011";
WHEN "0010011" => memoryC0_uid235_exp10TabGen_q <= "001001010001111011";
WHEN "0010100" => memoryC0_uid235_exp10TabGen_q <= "001001010110100101";
WHEN "0010101" => memoryC0_uid235_exp10TabGen_q <= "001001011011010010";
WHEN "0010110" => memoryC0_uid235_exp10TabGen_q <= "001001100000000000";
WHEN "0010111" => memoryC0_uid235_exp10TabGen_q <= "001001100100110010";
WHEN "0011000" => memoryC0_uid235_exp10TabGen_q <= "001001101001100101";
WHEN "0011001" => memoryC0_uid235_exp10TabGen_q <= "001001101110011011";
WHEN "0011010" => memoryC0_uid235_exp10TabGen_q <= "001001110011010100";
WHEN "0011011" => memoryC0_uid235_exp10TabGen_q <= "001001111000001111";
WHEN "0011100" => memoryC0_uid235_exp10TabGen_q <= "001001111101001100";
WHEN "0011101" => memoryC0_uid235_exp10TabGen_q <= "001010000010001100";
WHEN "0011110" => memoryC0_uid235_exp10TabGen_q <= "001010000111001110";
WHEN "0011111" => memoryC0_uid235_exp10TabGen_q <= "001010001100010011";
WHEN "0100000" => memoryC0_uid235_exp10TabGen_q <= "001010010001011010";
WHEN "0100001" => memoryC0_uid235_exp10TabGen_q <= "001010010110100100";
WHEN "0100010" => memoryC0_uid235_exp10TabGen_q <= "001010011011110001";
WHEN "0100011" => memoryC0_uid235_exp10TabGen_q <= "001010100001000000";
WHEN "0100100" => memoryC0_uid235_exp10TabGen_q <= "001010100110010010";
WHEN "0100101" => memoryC0_uid235_exp10TabGen_q <= "001010101011100111";
WHEN "0100110" => memoryC0_uid235_exp10TabGen_q <= "001010110000111110";
WHEN "0100111" => memoryC0_uid235_exp10TabGen_q <= "001010110110010111";
WHEN "0101000" => memoryC0_uid235_exp10TabGen_q <= "001010111011110100";
WHEN "0101001" => memoryC0_uid235_exp10TabGen_q <= "001011000001010011";
WHEN "0101010" => memoryC0_uid235_exp10TabGen_q <= "001011000110110101";
WHEN "0101011" => memoryC0_uid235_exp10TabGen_q <= "001011001100011010";
WHEN "0101100" => memoryC0_uid235_exp10TabGen_q <= "001011010010000010";
WHEN "0101101" => memoryC0_uid235_exp10TabGen_q <= "001011010111101100";
WHEN "0101110" => memoryC0_uid235_exp10TabGen_q <= "001011011101011001";
WHEN "0101111" => memoryC0_uid235_exp10TabGen_q <= "001011100011001010";
WHEN "0110000" => memoryC0_uid235_exp10TabGen_q <= "001011101000111101";
WHEN "0110001" => memoryC0_uid235_exp10TabGen_q <= "001011101110110011";
WHEN "0110010" => memoryC0_uid235_exp10TabGen_q <= "001011110100101011";
WHEN "0110011" => memoryC0_uid235_exp10TabGen_q <= "001011111010100111";
WHEN "0110100" => memoryC0_uid235_exp10TabGen_q <= "001100000000100110";
WHEN "0110101" => memoryC0_uid235_exp10TabGen_q <= "001100000110101000";
WHEN "0110110" => memoryC0_uid235_exp10TabGen_q <= "001100001100101101";
WHEN "0110111" => memoryC0_uid235_exp10TabGen_q <= "001100010010110101";
WHEN "0111000" => memoryC0_uid235_exp10TabGen_q <= "001100011001000000";
WHEN "0111001" => memoryC0_uid235_exp10TabGen_q <= "001100011111001110";
WHEN "0111010" => memoryC0_uid235_exp10TabGen_q <= "001100100101011111";
WHEN "0111011" => memoryC0_uid235_exp10TabGen_q <= "001100101011110011";
WHEN "0111100" => memoryC0_uid235_exp10TabGen_q <= "001100110010001011";
WHEN "0111101" => memoryC0_uid235_exp10TabGen_q <= "001100111000100101";
WHEN "0111110" => memoryC0_uid235_exp10TabGen_q <= "001100111111000011";
WHEN "0111111" => memoryC0_uid235_exp10TabGen_q <= "001101000101100100";
WHEN "1000000" => memoryC0_uid235_exp10TabGen_q <= "001101001100001001";
WHEN "1000001" => memoryC0_uid235_exp10TabGen_q <= "001101010010110001";
WHEN "1000010" => memoryC0_uid235_exp10TabGen_q <= "001101011001011100";
WHEN "1000011" => memoryC0_uid235_exp10TabGen_q <= "001101100000001010";
WHEN "1000100" => memoryC0_uid235_exp10TabGen_q <= "001101100110111100";
WHEN "1000101" => memoryC0_uid235_exp10TabGen_q <= "001101101101110001";
WHEN "1000110" => memoryC0_uid235_exp10TabGen_q <= "001101110100101010";
WHEN "1000111" => memoryC0_uid235_exp10TabGen_q <= "001101111011100110";
WHEN "1001000" => memoryC0_uid235_exp10TabGen_q <= "001110000010100101";
WHEN "1001001" => memoryC0_uid235_exp10TabGen_q <= "001110001001101000";
WHEN "1001010" => memoryC0_uid235_exp10TabGen_q <= "001110010000101111";
WHEN "1001011" => memoryC0_uid235_exp10TabGen_q <= "001110010111111001";
WHEN "1001100" => memoryC0_uid235_exp10TabGen_q <= "001110011111000111";
WHEN "1001101" => memoryC0_uid235_exp10TabGen_q <= "001110100110011000";
WHEN "1001110" => memoryC0_uid235_exp10TabGen_q <= "001110101101101101";
WHEN "1001111" => memoryC0_uid235_exp10TabGen_q <= "001110110101000110";
WHEN "1010000" => memoryC0_uid235_exp10TabGen_q <= "001110111100100010";
WHEN "1010001" => memoryC0_uid235_exp10TabGen_q <= "001111000100000010";
WHEN "1010010" => memoryC0_uid235_exp10TabGen_q <= "001111001011100110";
WHEN "1010011" => memoryC0_uid235_exp10TabGen_q <= "001111010011001110";
WHEN "1010100" => memoryC0_uid235_exp10TabGen_q <= "001111011010111001";
WHEN "1010101" => memoryC0_uid235_exp10TabGen_q <= "001111100010101001";
WHEN "1010110" => memoryC0_uid235_exp10TabGen_q <= "001111101010011100";
WHEN "1010111" => memoryC0_uid235_exp10TabGen_q <= "001111110010010011";
WHEN "1011000" => memoryC0_uid235_exp10TabGen_q <= "001111111010001110";
WHEN "1011001" => memoryC0_uid235_exp10TabGen_q <= "010000000010001110";
WHEN "1011010" => memoryC0_uid235_exp10TabGen_q <= "010000001010010001";
WHEN "1011011" => memoryC0_uid235_exp10TabGen_q <= "010000010010011000";
WHEN "1011100" => memoryC0_uid235_exp10TabGen_q <= "010000011010100011";
WHEN "1011101" => memoryC0_uid235_exp10TabGen_q <= "010000100010110010";
WHEN "1011110" => memoryC0_uid235_exp10TabGen_q <= "010000101011000110";
WHEN "1011111" => memoryC0_uid235_exp10TabGen_q <= "010000110011011110";
WHEN "1100000" => memoryC0_uid235_exp10TabGen_q <= "010000111011111001";
WHEN "1100001" => memoryC0_uid235_exp10TabGen_q <= "010001000100011001";
WHEN "1100010" => memoryC0_uid235_exp10TabGen_q <= "010001001100111110";
WHEN "1100011" => memoryC0_uid235_exp10TabGen_q <= "010001010101100110";
WHEN "1100100" => memoryC0_uid235_exp10TabGen_q <= "010001011110010011";
WHEN "1100101" => memoryC0_uid235_exp10TabGen_q <= "010001100111000101";
WHEN "1100110" => memoryC0_uid235_exp10TabGen_q <= "010001101111111010";
WHEN "1100111" => memoryC0_uid235_exp10TabGen_q <= "010001111000110101";
WHEN "1101000" => memoryC0_uid235_exp10TabGen_q <= "010010000001110011";
WHEN "1101001" => memoryC0_uid235_exp10TabGen_q <= "010010001010110110";
WHEN "1101010" => memoryC0_uid235_exp10TabGen_q <= "010010010011111110";
WHEN "1101011" => memoryC0_uid235_exp10TabGen_q <= "010010011101001010";
WHEN "1101100" => memoryC0_uid235_exp10TabGen_q <= "010010100110011011";
WHEN "1101101" => memoryC0_uid235_exp10TabGen_q <= "010010101111110001";
WHEN "1101110" => memoryC0_uid235_exp10TabGen_q <= "010010111001001011";
WHEN "1101111" => memoryC0_uid235_exp10TabGen_q <= "010011000010101010";
WHEN "1110000" => memoryC0_uid235_exp10TabGen_q <= "010011001100001110";
WHEN "1110001" => memoryC0_uid235_exp10TabGen_q <= "010011010101110110";
WHEN "1110010" => memoryC0_uid235_exp10TabGen_q <= "010011011111100100";
WHEN "1110011" => memoryC0_uid235_exp10TabGen_q <= "010011101001010110";
WHEN "1110100" => memoryC0_uid235_exp10TabGen_q <= "010011110011001101";
WHEN "1110101" => memoryC0_uid235_exp10TabGen_q <= "010011111101001001";
WHEN "1110110" => memoryC0_uid235_exp10TabGen_q <= "010100000111001010";
WHEN "1110111" => memoryC0_uid235_exp10TabGen_q <= "010100010001010000";
WHEN "1111000" => memoryC0_uid235_exp10TabGen_q <= "010100011011011100";
WHEN "1111001" => memoryC0_uid235_exp10TabGen_q <= "010100100101101100";
WHEN "1111010" => memoryC0_uid235_exp10TabGen_q <= "010100110000000001";
WHEN "1111011" => memoryC0_uid235_exp10TabGen_q <= "010100111010011100";
WHEN "1111100" => memoryC0_uid235_exp10TabGen_q <= "010101000100111100";
WHEN "1111101" => memoryC0_uid235_exp10TabGen_q <= "010101001111100001";
WHEN "1111110" => memoryC0_uid235_exp10TabGen_q <= "010101011010001011";
WHEN "1111111" => memoryC0_uid235_exp10TabGen_q <= "010101100100111011";
WHEN OTHERS =>
memoryC0_uid235_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor(LOGICAL,1133)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_b <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_q <= not (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_a or ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_b);
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena(REG,1134)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_nor_q = "1") THEN
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd(LOGICAL,1135)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_a <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_sticky_ena_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_b <= en;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_a and ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_b;
--ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem(DUALMEM,1124)
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ia <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_inputreg_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_aa <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdreg_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ab <= ld_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid235_exp10TabGen_0_q_to_memoryC0_uid235_exp10TabGen_a_replace_rdmux_q;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 21,
width_b => 7,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_iq,
address_a => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_aa,
data_a => ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_ia
);
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_reset0 <= areset;
ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_iq(6 downto 0);
--reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0(REG,377)@36
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_q <= ld_addr_uid64_fpExpETest_b_to_reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid234_exp10TabGen(LOOKUP,233)@37
memoryC0_uid234_exp10TabGen: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC0_uid234_exp10TabGen_q <= "0000000000000000000000000000000000000100";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addr_uid64_fpExpETest_0_to_memoryC0_uid234_exp10TabGen_0_q) IS
WHEN "0000000" => memoryC0_uid234_exp10TabGen_q <= "0000000000000000000000000000000000000100";
WHEN "0000001" => memoryC0_uid234_exp10TabGen_q <= "0000000010101011000000000010001000110010";
WHEN "0000010" => memoryC0_uid234_exp10TabGen_q <= "0000010101011010101011101111000111001101";
WHEN "0000011" => memoryC0_uid234_exp10TabGen_q <= "0001001000011011001000001000011011101101";
WHEN "0000100" => memoryC0_uid234_exp10TabGen_q <= "0010101100000000100010010011111101101001";
WHEN "0000101" => memoryC0_uid234_exp10TabGen_q <= "0101010000100111010011100000111110110000";
WHEN "0000110" => memoryC0_uid234_exp10TabGen_q <= "1001000110110100000101001111010001100010";
WHEN "0000111" => memoryC0_uid234_exp10TabGen_q <= "1110011111010011110101011000010011101101";
WHEN "0001000" => memoryC0_uid234_exp10TabGen_q <= "0101101010111011111010011010011101110000";
WHEN "0001001" => memoryC0_uid234_exp10TabGen_q <= "1110111010101010000111100110011000101011";
WHEN "0001010" => memoryC0_uid234_exp10TabGen_q <= "1010011111100100110001001110011010110110";
WHEN "0001011" => memoryC0_uid234_exp10TabGen_q <= "1000101010111010110000111000001101001101";
WHEN "0001100" => memoryC0_uid234_exp10TabGen_q <= "1001101110000011101001110000011001101111";
WHEN "0001101" => memoryC0_uid234_exp10TabGen_q <= "1101111010011111101101000000100100010110";
WHEN "0001110" => memoryC0_uid234_exp10TabGen_q <= "0101100001110111111110000111001111001110";
WHEN "0001111" => memoryC0_uid234_exp10TabGen_q <= "0000110101111110010111010010001011110111";
WHEN "0010000" => memoryC0_uid234_exp10TabGen_q <= "0000001000101101101101111010111001101100";
WHEN "0010001" => memoryC0_uid234_exp10TabGen_q <= "0011101100001001110111000101010011011100";
WHEN "0010010" => memoryC0_uid234_exp10TabGen_q <= "1011110010011111101100000000101100100101";
WHEN "0010011" => memoryC0_uid234_exp10TabGen_q <= "1000101110000101001110101010111111110000";
WHEN "0010100" => memoryC0_uid234_exp10TabGen_q <= "1010110001011001101110010110001111001110";
WHEN "0010101" => memoryC0_uid234_exp10TabGen_q <= "0010001111000101101100010000011000111110";
WHEN "0010110" => memoryC0_uid234_exp10TabGen_q <= "1111011001111011000000001101011110111100";
WHEN "0010111" => memoryC0_uid234_exp10TabGen_q <= "0010100100110100111101010100000101001100";
WHEN "0011000" => memoryC0_uid234_exp10TabGen_q <= "1100000010111000010110101100000110101101";
WHEN "0011001" => memoryC0_uid234_exp10TabGen_q <= "1100000111010011100100010000000010010110";
WHEN "0011010" => memoryC0_uid234_exp10TabGen_q <= "0011000101011110100111100000100000110111";
WHEN "0011011" => memoryC0_uid234_exp10TabGen_q <= "0001010000111011010000011010010101011000";
WHEN "0011100" => memoryC0_uid234_exp10TabGen_q <= "0110111101010101000010001110111001100001";
WHEN "0011101" => memoryC0_uid234_exp10TabGen_q <= "0100011110100001011000011111000110010100";
WHEN "0011110" => memoryC0_uid234_exp10TabGen_q <= "1010001000011111101011111000101011001011";
WHEN "0011111" => memoryC0_uid234_exp10TabGen_q <= "1000001111011001010111010110000100001011";
WHEN "0100000" => memoryC0_uid234_exp10TabGen_q <= "1111000111100001111101000000110000110111";
WHEN "0100001" => memoryC0_uid234_exp10TabGen_q <= "1111000101010111001011010110001100111110";
WHEN "0100010" => memoryC0_uid234_exp10TabGen_q <= "1000011101100001000010001111001100000101";
WHEN "0100011" => memoryC0_uid234_exp10TabGen_q <= "1011100100110001111000001001111001101100";
WHEN "0100100" => memoryC0_uid234_exp10TabGen_q <= "1000110000000110011111010110011110111111";
WHEN "0100101" => memoryC0_uid234_exp10TabGen_q <= "0000010100100110001011000110001111100010";
WHEN "0100110" => memoryC0_uid234_exp10TabGen_q <= "0010100111100010110100111101011110000101";
WHEN "0100111" => memoryC0_uid234_exp10TabGen_q <= "1111111110011001000010000111111011001111";
WHEN "0101000" => memoryC0_uid234_exp10TabGen_q <= "1000101110110000001000101111111110101110";
WHEN "0101001" => memoryC0_uid234_exp10TabGen_q <= "1101001110011010010101011000011101001000";
WHEN "0101010" => memoryC0_uid234_exp10TabGen_q <= "1101110011010100110000011001001011000110";
WHEN "0101011" => memoryC0_uid234_exp10TabGen_q <= "1010110011100111100011011110001111100111";
WHEN "0101100" => memoryC0_uid234_exp10TabGen_q <= "0100100101100101111111001010000110011010";
WHEN "0101101" => memoryC0_uid234_exp10TabGen_q <= "1011011111101110100000011010010100011000";
WHEN "0101110" => memoryC0_uid234_exp10TabGen_q <= "1111111000101010110110001111001110110010";
WHEN "0101111" => memoryC0_uid234_exp10TabGen_q <= "0010000111010000000111010110010111001101";
WHEN "0110000" => memoryC0_uid234_exp10TabGen_q <= "0010100010011110110111110111101101010111";
WHEN "0110001" => memoryC0_uid234_exp10TabGen_q <= "0001100001100011001111000101111000001011";
WHEN "0110010" => memoryC0_uid234_exp10TabGen_q <= "1111011011110100111101010001000111110011";
WHEN "0110011" => memoryC0_uid234_exp10TabGen_q <= "1100101000110111100001011101010001101111";
WHEN "0110100" => memoryC0_uid234_exp10TabGen_q <= "1001100000011010001111011010101000110010";
WHEN "0110101" => memoryC0_uid234_exp10TabGen_q <= "0110011010011000010101100001110010000100";
WHEN "0110110" => memoryC0_uid234_exp10TabGen_q <= "0011101110111001000010110010011000101110";
WHEN "0110111" => memoryC0_uid234_exp10TabGen_q <= "0001110110001111101100110101000001110111";
WHEN "0111000" => memoryC0_uid234_exp10TabGen_q <= "0001001000111011110110000000000010000011";
WHEN "0111001" => memoryC0_uid234_exp10TabGen_q <= "0001111111101001010011011111010101111111";
WHEN "0111010" => memoryC0_uid234_exp10TabGen_q <= "0100110011010000010011011111100000000010";
WHEN "0111011" => memoryC0_uid234_exp10TabGen_q <= "1001111100110101100011011011101011110001";
WHEN "0111100" => memoryC0_uid234_exp10TabGen_q <= "0001110101101010010110001110111001100101";
WHEN "0111101" => memoryC0_uid234_exp10TabGen_q <= "1100110111001100101010101000010011011101";
WHEN "0111110" => memoryC0_uid234_exp10TabGen_q <= "1011011011000111010001100010101100110111";
WHEN "0111111" => memoryC0_uid234_exp10TabGen_q <= "1101111011010001110100011111001111000001";
WHEN "1000000" => memoryC0_uid234_exp10TabGen_q <= "0100110001110000111100000011010011100010";
WHEN "1000001" => memoryC0_uid234_exp10TabGen_q <= "0000011000110110010110011001101110100101";
WHEN "1000010" => memoryC0_uid234_exp10TabGen_q <= "0001001011000000111101110111001010100111";
WHEN "1000011" => memoryC0_uid234_exp10TabGen_q <= "0111100010111100111111100001110111000101";
WHEN "1000100" => memoryC0_uid234_exp10TabGen_q <= "0011111011100100000001111100101011111001";
WHEN "1000101" => memoryC0_uid234_exp10TabGen_q <= "0110101111111101001011110101100011000111";
WHEN "1000110" => memoryC0_uid234_exp10TabGen_q <= "0000011011011101001010110111001010110011";
WHEN "1000111" => memoryC0_uid234_exp10TabGen_q <= "0001011001100110011010011110010000101001";
WHEN "1001000" => memoryC0_uid234_exp10TabGen_q <= "1010000110001001001010110010001000110110";
WHEN "1001001" => memoryC0_uid234_exp10TabGen_q <= "1010111101000011100111100000110010011010";
WHEN "1001010" => memoryC0_uid234_exp10TabGen_q <= "0100011010100001111110111110011010001000";
WHEN "1001011" => memoryC0_uid234_exp10TabGen_q <= "0110111010111110101001001000011110010111";
WHEN "1001100" => memoryC0_uid234_exp10TabGen_q <= "0010111011000010001110101100010101001010";
WHEN "1001101" => memoryC0_uid234_exp10TabGen_q <= "1000110111100011110000010001010110100101";
WHEN "1001110" => memoryC0_uid234_exp10TabGen_q <= "1001001101101000101101100110101101000000";
WHEN "1001111" => memoryC0_uid234_exp10TabGen_q <= "0100011010100101001100110100101101001110";
WHEN "1010000" => memoryC0_uid234_exp10TabGen_q <= "1010111011111100000001110001111000000111";
WHEN "1010001" => memoryC0_uid234_exp10TabGen_q <= "1101001111011110110101011011100111110000";
WHEN "1010010" => memoryC0_uid234_exp10TabGen_q <= "1011110011001110001101010010101001110110";
WHEN "1010011" => memoryC0_uid234_exp10TabGen_q <= "0111000101011001110010111011001001001100";
WHEN "1010100" => memoryC0_uid234_exp10TabGen_q <= "1111100100100000011011100000101000010100";
WHEN "1010101" => memoryC0_uid234_exp10TabGen_q <= "0101101111010000001111011101101110110110";
WHEN "1010110" => memoryC0_uid234_exp10TabGen_q <= "1010000100100110110010000111101011110111";
WHEN "1010111" => memoryC0_uid234_exp10TabGen_q <= "1101000011110001001001011101101110110011";
WHEN "1011000" => memoryC0_uid234_exp10TabGen_q <= "1111001100001100000101111100011001001001";
WHEN "1011001" => memoryC0_uid234_exp10TabGen_q <= "0000111101100100001010010100101010110000";
WHEN "1011010" => memoryC0_uid234_exp10TabGen_q <= "0010110111110101110011100111001010101000";
WHEN "1011011" => memoryC0_uid234_exp10TabGen_q <= "0101011011001101100001000011001110011011";
WHEN "1011100" => memoryC0_uid234_exp10TabGen_q <= "1001001000000111111100001010000010010111";
WHEN "1011101" => memoryC0_uid234_exp10TabGen_q <= "1110011111010010000000110101110011110001";
WHEN "1011110" => memoryC0_uid234_exp10TabGen_q <= "0110000001101001000101100101000000010001";
WHEN "1011111" => memoryC0_uid234_exp10TabGen_q <= "0000010000011011000011101001101011100110";
WHEN "1100000" => memoryC0_uid234_exp10TabGen_q <= "1101101101000110011111011100111110000000";
WHEN "1100001" => memoryC0_uid234_exp10TabGen_q <= "1110111001011010110000110110101101100101";
WHEN "1100010" => memoryC0_uid234_exp10TabGen_q <= "0100010111011000001011101001010100011100";
WHEN "1100011" => memoryC0_uid234_exp10TabGen_q <= "1110101001010000001000000001110101110001";
WHEN "1100100" => memoryC0_uid234_exp10TabGen_q <= "1110010001100101001011001100010100000101";
WHEN "1100101" => memoryC0_uid234_exp10TabGen_q <= "0011110011001011001111111100011010101110";
WHEN "1100110" => memoryC0_uid234_exp10TabGen_q <= "1111110001000111101111011010011100101111";
WHEN "1100111" => memoryC0_uid234_exp10TabGen_q <= "0010101110110001101001110100101011010100";
WHEN "1101000" => memoryC0_uid234_exp10TabGen_q <= "1101001111110001101111010101000110000100";
WHEN "1101001" => memoryC0_uid234_exp10TabGen_q <= "1111111000000010101000111011100111001100";
WHEN "1101010" => memoryC0_uid234_exp10TabGen_q <= "1011001011110001000001011100101101111110";
WHEN "1101011" => memoryC0_uid234_exp10TabGen_q <= "1111101111011011101110100100101001101011";
WHEN "1101100" => memoryC0_uid234_exp10TabGen_q <= "1110000111110011111001111111000111000101";
WHEN "1101101" => memoryC0_uid234_exp10TabGen_q <= "0110111001111101001010100011100011001011";
WHEN "1101110" => memoryC0_uid234_exp10TabGen_q <= "1010101011001101101101100110000101000011";
WHEN "1101111" => memoryC0_uid234_exp10TabGen_q <= "1010000001001110100000001101000001011001";
WHEN "1110000" => memoryC0_uid234_exp10TabGen_q <= "0101100001111011011000101011001001111110";
WHEN "1110001" => memoryC0_uid234_exp10TabGen_q <= "1101110011100011001111111110101011011010";
WHEN "1110010" => memoryC0_uid234_exp10TabGen_q <= "0011011100101000001011010100111011101001";
WHEN "1110011" => memoryC0_uid234_exp10TabGen_q <= "0111000011111111100101110010111011011000";
WHEN "1110100" => memoryC0_uid234_exp10TabGen_q <= "1001010000110010011010000010101101001001";
WHEN "1110101" => memoryC0_uid234_exp10TabGen_q <= "1010101010011101001100000101100100000010";
WHEN "1110110" => memoryC0_uid234_exp10TabGen_q <= "1011111000110000010011001011001101000100";
WHEN "1110111" => memoryC0_uid234_exp10TabGen_q <= "1101100011110000000011101101110101000101";
WHEN "1111000" => memoryC0_uid234_exp10TabGen_q <= "0000010011110100111001010011001110000110";
WHEN "1111001" => memoryC0_uid234_exp10TabGen_q <= "0100110001101011100000110010110110011110";
WHEN "1111010" => memoryC0_uid234_exp10TabGen_q <= "1011100110010101000010100001000100001101";
WHEN "1111011" => memoryC0_uid234_exp10TabGen_q <= "0101011011000111001100011111010111010111";
WHEN "1111100" => memoryC0_uid234_exp10TabGen_q <= "0010111001101100011100110001110101101101";
WHEN "1111101" => memoryC0_uid234_exp10TabGen_q <= "0100101100000100001011111001110010011111";
WHEN "1111110" => memoryC0_uid234_exp10TabGen_q <= "1011011100100010110111010101100100101111";
WHEN "1111111" => memoryC0_uid234_exp10TabGen_q <= "0111110101110010001100000101101110111100";
WHEN OTHERS =>
memoryC0_uid234_exp10TabGen_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--os_uid236_exp10TabGen(BITJOIN,235)@38
os_uid236_exp10TabGen_q <= memoryC0_uid235_exp10TabGen_q & memoryC0_uid234_exp10TabGen_q;
--rndBit_uid275_exp10PolyEval(CONSTANT,274)
rndBit_uid275_exp10PolyEval_q <= "001";
--cIncludingRoundingBit_uid276_exp10PolyEval(BITJOIN,275)@38
cIncludingRoundingBit_uid276_exp10PolyEval_q <= os_uid236_exp10TabGen_q & rndBit_uid275_exp10PolyEval_q;
--reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0(REG,413)@38
reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0_q <= cIncludingRoundingBit_uid276_exp10PolyEval_q;
END IF;
END IF;
END PROCESS;
--ts5_uid277_exp10PolyEval(ADD,276)@39
ts5_uid277_exp10PolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid276_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_0_q);
ts5_uid277_exp10PolyEval_b <= STD_LOGIC_VECTOR((61 downto 55 => reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1_q(54)) & reg_R_uid338_pT5_uid274_exp10PolyEval_0_to_ts5_uid277_exp10PolyEval_1_q);
ts5_uid277_exp10PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid277_exp10PolyEval_a) + SIGNED(ts5_uid277_exp10PolyEval_b));
ts5_uid277_exp10PolyEval_q <= ts5_uid277_exp10PolyEval_o(61 downto 0);
--s5_uid278_exp10PolyEval(BITSELECT,277)@39
s5_uid278_exp10PolyEval_in <= ts5_uid277_exp10PolyEval_q;
s5_uid278_exp10PolyEval_b <= s5_uid278_exp10PolyEval_in(61 downto 1);
--peORExpInc_uid68_fpExpETest(BITSELECT,67)@39
peORExpInc_uid68_fpExpETest_in <= s5_uid278_exp10PolyEval_b(58 downto 0);
peORExpInc_uid68_fpExpETest_b <= peORExpInc_uid68_fpExpETest_in(58 downto 58);
--reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1(REG,415)@39
reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1_q <= peORExpInc_uid68_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--cstBias_uid8_fpExpETest(CONSTANT,7)
cstBias_uid8_fpExpETest_q <= "01111111111";
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor(LOGICAL,911)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_b <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_q <= not (ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_a or ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_b);
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_mem_top(CONSTANT,907)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_mem_top_q <= "011011";
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp(LOGICAL,908)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_a <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_mem_top_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q);
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_q <= "1" when ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_a = ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_b else "0";
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg(REG,909)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena(REG,912)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_nor_q = "1") THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd(LOGICAL,913)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_a <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_sticky_ena_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_b <= en;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_a and ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_b;
--reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0(REG,360)@8
reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q <= ePreRnd_uid46_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_inputreg(DELAY,901)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q, xout => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt(COUNTER,903)
-- every=1, low=0, high=27, step=1, init=1
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i = 26 THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_eq = '1') THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i - 27;
ELSE
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_i,5));
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg(REG,904)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux(MUX,905)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_s <= en;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux: PROCESS (ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_s, ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q, ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q;
WHEN "1" => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem(DUALMEM,902)
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ia <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_inputreg_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_aa <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdreg_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ab <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_rdmux_q;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 5,
numwords_a => 28,
width_b => 14,
widthad_b => 5,
numwords_b => 28,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_iq,
address_a => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_aa,
data_a => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_ia
);
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_reset0 <= areset;
ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_q <= ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_iq(13 downto 0);
--expRPostBiasPreExc0_uid69_fpExpETest(ADD,68)@39
expRPostBiasPreExc0_uid69_fpExpETest_a <= STD_LOGIC_VECTOR((15 downto 14 => ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_q(13)) & ld_reg_ePreRnd_uid46_fpExpETest_0_to_expRPostBiasPreExc0_uid69_fpExpETest_0_q_to_expRPostBiasPreExc0_uid69_fpExpETest_a_replace_mem_q);
expRPostBiasPreExc0_uid69_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "0000" & cstBias_uid8_fpExpETest_q);
expRPostBiasPreExc0_uid69_fpExpETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostBiasPreExc0_uid69_fpExpETest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expRPostBiasPreExc0_uid69_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc0_uid69_fpExpETest_a) + SIGNED(expRPostBiasPreExc0_uid69_fpExpETest_b));
END IF;
END IF;
END PROCESS;
expRPostBiasPreExc0_uid69_fpExpETest_q <= expRPostBiasPreExc0_uid69_fpExpETest_o(14 downto 0);
--expRPostBiasPreExc_uid70_fpExpETest(ADD,69)@40
expRPostBiasPreExc_uid70_fpExpETest_a <= STD_LOGIC_VECTOR((16 downto 15 => expRPostBiasPreExc0_uid69_fpExpETest_q(14)) & expRPostBiasPreExc0_uid69_fpExpETest_q);
expRPostBiasPreExc_uid70_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "000000000000000" & reg_peORExpInc_uid68_fpExpETest_0_to_expRPostBiasPreExc_uid70_fpExpETest_1_q);
expRPostBiasPreExc_uid70_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(expRPostBiasPreExc_uid70_fpExpETest_a) + SIGNED(expRPostBiasPreExc_uid70_fpExpETest_b));
expRPostBiasPreExc_uid70_fpExpETest_q <= expRPostBiasPreExc_uid70_fpExpETest_o(15 downto 0);
--expR_uid75_fpExpETest(BITSELECT,74)@40
expR_uid75_fpExpETest_in <= expRPostBiasPreExc_uid70_fpExpETest_q(10 downto 0);
expR_uid75_fpExpETest_b <= expR_uid75_fpExpETest_in(10 downto 0);
--ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d(DELAY,509)@40
ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expR_uid75_fpExpETest_b, xout => ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d_q, ena => en(0), clk => clk, aclr => areset );
--cstZeroWE_uid11_fpExpETest(CONSTANT,10)
cstZeroWE_uid11_fpExpETest_q <= "00000000000";
--ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor(LOGICAL,1002)
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_b <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_q <= not (ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_a or ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_b);
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_mem_top(CONSTANT,920)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_mem_top_q <= "0100110";
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp(LOGICAL,921)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_a <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_mem_top_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q);
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_q <= "1" when ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_a = ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_b else "0";
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg(REG,922)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena(REG,1003)
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_nor_q = "1") THEN
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd(LOGICAL,1004)
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_a <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_sticky_ena_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_b <= en;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_q <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_a and ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_b;
--cstAllZWF_uid16_fpExpETest(CONSTANT,15)
cstAllZWF_uid16_fpExpETest_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid23_fpExpETest(LOGICAL,22)@0
fracXIsZero_uid23_fpExpETest_a <= frac_uid22_fpExpETest_b;
fracXIsZero_uid23_fpExpETest_b <= cstAllZWF_uid16_fpExpETest_q;
fracXIsZero_uid23_fpExpETest_q <= "1" when fracXIsZero_uid23_fpExpETest_a = fracXIsZero_uid23_fpExpETest_b else "0";
--InvFracXIsZero_uid25_fpExpETest(LOGICAL,24)@0
InvFracXIsZero_uid25_fpExpETest_a <= fracXIsZero_uid23_fpExpETest_q;
InvFracXIsZero_uid25_fpExpETest_q <= not InvFracXIsZero_uid25_fpExpETest_a;
--expXIsMax_uid21_fpExpETest(LOGICAL,20)@0
expXIsMax_uid21_fpExpETest_a <= expX_uid6_fpExpETest_b;
expXIsMax_uid21_fpExpETest_b <= cstAllOWE_uid15_fpExpETest_q;
expXIsMax_uid21_fpExpETest_q <= "1" when expXIsMax_uid21_fpExpETest_a = expXIsMax_uid21_fpExpETest_b else "0";
--exc_N_uid26_fpExpETest(LOGICAL,25)@0
exc_N_uid26_fpExpETest_a <= expXIsMax_uid21_fpExpETest_q;
exc_N_uid26_fpExpETest_b <= InvFracXIsZero_uid25_fpExpETest_q;
exc_N_uid26_fpExpETest_q <= exc_N_uid26_fpExpETest_a and exc_N_uid26_fpExpETest_b;
--ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_inputreg(DELAY,992)
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_N_uid26_fpExpETest_q, xout => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt(COUNTER,916)
-- every=1, low=0, high=38, step=1, init=1
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i = 37 THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_eq = '1') THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i - 38;
ELSE
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_i,6));
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg(REG,917)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux(MUX,918)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_s <= en;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux: PROCESS (ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_s, ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q, ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_q)
BEGIN
CASE ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_s IS
WHEN "0" => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q;
WHEN "1" => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem(DUALMEM,993)
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ia <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_inputreg_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_aa <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ab <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 39,
width_b => 1,
widthad_b => 6,
numwords_b => 39,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_iq,
address_a => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_aa,
data_a => ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_ia
);
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_reset0 <= areset;
ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_q <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_iq(0 downto 0);
--ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor(LOGICAL,989)
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_b <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_q <= not (ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_a or ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_b);
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_mem_top(CONSTANT,933)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_mem_top_q <= "0100101";
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp(LOGICAL,934)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_a <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_mem_top_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q);
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_q <= "1" when ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_a = ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_b else "0";
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg(REG,935)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena(REG,990)
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_nor_q = "1") THEN
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd(LOGICAL,991)
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_a <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_sticky_ena_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_b <= en;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_q <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_a and ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_b;
--ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c(DELAY,482)@0
ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpExpETest_b, xout => ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvSignX_uid81_fpExpETest(LOGICAL,80)@1
InvSignX_uid81_fpExpETest_a <= ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c_q;
InvSignX_uid81_fpExpETest_q <= not InvSignX_uid81_fpExpETest_a;
--expOvfInitial_uid41_fpExpETest(BITSELECT,40)@0
expOvfInitial_uid41_fpExpETest_in <= shiftValuePreSat_uid40_fpExpETest_q;
expOvfInitial_uid41_fpExpETest_b <= expOvfInitial_uid41_fpExpETest_in(11 downto 11);
--reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2(REG,417)@0
reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2_q <= expOvfInitial_uid41_fpExpETest_b;
END IF;
END IF;
END PROCESS;
--InvExc_N_uid27_fpExpETest(LOGICAL,26)@0
InvExc_N_uid27_fpExpETest_a <= exc_N_uid26_fpExpETest_q;
InvExc_N_uid27_fpExpETest_q <= not InvExc_N_uid27_fpExpETest_a;
--exc_I_uid24_fpExpETest(LOGICAL,23)@0
exc_I_uid24_fpExpETest_a <= expXIsMax_uid21_fpExpETest_q;
exc_I_uid24_fpExpETest_b <= fracXIsZero_uid23_fpExpETest_q;
exc_I_uid24_fpExpETest_q <= exc_I_uid24_fpExpETest_a and exc_I_uid24_fpExpETest_b;
--InvExc_I_uid28_fpExpETest(LOGICAL,27)@0
InvExc_I_uid28_fpExpETest_a <= exc_I_uid24_fpExpETest_q;
InvExc_I_uid28_fpExpETest_q <= not InvExc_I_uid28_fpExpETest_a;
--expXIsZero_uid19_fpExpETest(LOGICAL,18)@0
expXIsZero_uid19_fpExpETest_a <= expX_uid6_fpExpETest_b;
expXIsZero_uid19_fpExpETest_b <= cstZeroWE_uid11_fpExpETest_q;
expXIsZero_uid19_fpExpETest_q <= "1" when expXIsZero_uid19_fpExpETest_a = expXIsZero_uid19_fpExpETest_b else "0";
--InvExpXIsZero_uid29_fpExpETest(LOGICAL,28)@0
InvExpXIsZero_uid29_fpExpETest_a <= expXIsZero_uid19_fpExpETest_q;
InvExpXIsZero_uid29_fpExpETest_q <= not InvExpXIsZero_uid29_fpExpETest_a;
--exc_R_uid30_fpExpETest(LOGICAL,29)@0
exc_R_uid30_fpExpETest_a <= InvExpXIsZero_uid29_fpExpETest_q;
exc_R_uid30_fpExpETest_b <= InvExc_I_uid28_fpExpETest_q;
exc_R_uid30_fpExpETest_c <= InvExc_N_uid27_fpExpETest_q;
exc_R_uid30_fpExpETest_q_i <= exc_R_uid30_fpExpETest_a and exc_R_uid30_fpExpETest_b and exc_R_uid30_fpExpETest_c;
exc_R_uid30_fpExpETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid30_fpExpETest_q, xin => exc_R_uid30_fpExpETest_q_i, clk => clk, ena => en(0), aclr => areset);
--regXAndExpOverflowAndPos_uid82_fpExpETest(LOGICAL,81)@1
regXAndExpOverflowAndPos_uid82_fpExpETest_a <= exc_R_uid30_fpExpETest_q;
regXAndExpOverflowAndPos_uid82_fpExpETest_b <= reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2_q;
regXAndExpOverflowAndPos_uid82_fpExpETest_c <= InvSignX_uid81_fpExpETest_q;
regXAndExpOverflowAndPos_uid82_fpExpETest_q <= regXAndExpOverflowAndPos_uid82_fpExpETest_a and regXAndExpOverflowAndPos_uid82_fpExpETest_b and regXAndExpOverflowAndPos_uid82_fpExpETest_c;
--ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_inputreg(DELAY,979)
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => regXAndExpOverflowAndPos_uid82_fpExpETest_q, xout => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt(COUNTER,929)
-- every=1, low=0, high=37, step=1, init=1
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i = 36 THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_eq = '1') THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i - 37;
ELSE
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_i,6));
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg(REG,930)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux(MUX,931)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_s <= en;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux: PROCESS (ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_s, ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q, ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_q)
BEGIN
CASE ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_s IS
WHEN "0" => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q;
WHEN "1" => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem(DUALMEM,980)
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ia <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_inputreg_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_aa <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ab <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_iq,
address_a => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_aa,
data_a => ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_ia
);
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_reset0 <= areset;
ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_q <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_iq(0 downto 0);
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor(LOGICAL,924)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_b <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_q <= not (ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_a or ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_b);
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena(REG,925)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_nor_q = "1") THEN
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd(LOGICAL,926)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_a <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_sticky_ena_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_b <= en;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_a and ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_b;
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_inputreg(DELAY,914)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOvfInitial_uid41_fpExpETest_b, xout => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem(DUALMEM,915)
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ia <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_inputreg_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_aa <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ab <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 39,
width_b => 1,
widthad_b => 6,
numwords_b => 39,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_iq,
address_a => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_aa,
data_a => ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_ia
);
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_reset0 <= areset;
ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_iq(0 downto 0);
--InvExpOvfInitial_uid78_fpExpETest(LOGICAL,77)@41
InvExpOvfInitial_uid78_fpExpETest_a <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_mem_q;
InvExpOvfInitial_uid78_fpExpETest_q <= not InvExpOvfInitial_uid78_fpExpETest_a;
--reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1(REG,416)@40
reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q <= expRPostBiasPreExc_uid70_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--expOvf_uid74_fpExpETest(COMPARE,73)@41
expOvf_uid74_fpExpETest_cin <= GND_q;
expOvf_uid74_fpExpETest_a <= STD_LOGIC_VECTOR((17 downto 16 => reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q(15)) & reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q) & '0';
expOvf_uid74_fpExpETest_b <= STD_LOGIC_VECTOR('0' & "000000" & cstAllOWE_uid15_fpExpETest_q) & expOvf_uid74_fpExpETest_cin(0);
expOvf_uid74_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid74_fpExpETest_a) - SIGNED(expOvf_uid74_fpExpETest_b));
expOvf_uid74_fpExpETest_n(0) <= not expOvf_uid74_fpExpETest_o(18);
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor(LOGICAL,937)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_b <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_q <= not (ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_a or ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_b);
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena(REG,938)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_nor_q = "1") THEN
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd(LOGICAL,939)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_a <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_sticky_ena_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_b <= en;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_a and ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_b;
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_inputreg(DELAY,927)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_R_uid30_fpExpETest_q, xout => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem(DUALMEM,928)
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ia <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_inputreg_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_aa <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ab <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_iq,
address_a => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_aa,
data_a => ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_ia
);
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_reset0 <= areset;
ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_iq(0 downto 0);
--regInAndOvf_uid84_fpExpETest(LOGICAL,83)@41
regInAndOvf_uid84_fpExpETest_a <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_q;
regInAndOvf_uid84_fpExpETest_b <= expOvf_uid74_fpExpETest_n;
regInAndOvf_uid84_fpExpETest_c <= InvExpOvfInitial_uid78_fpExpETest_q;
regInAndOvf_uid84_fpExpETest_q <= regInAndOvf_uid84_fpExpETest_a and regInAndOvf_uid84_fpExpETest_b and regInAndOvf_uid84_fpExpETest_c;
--ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor(LOGICAL,976)
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_b <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_q <= not (ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_a or ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_b);
--ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena(REG,977)
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_nor_q = "1") THEN
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd(LOGICAL,978)
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_a <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_sticky_ena_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_b <= en;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_q <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_a and ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_b;
--ld_exc_I_uid24_fpExpETest_q_to_posInf_uid86_fpExpETest_a(DELAY,497)@0
ld_exc_I_uid24_fpExpETest_q_to_posInf_uid86_fpExpETest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid24_fpExpETest_q, xout => ld_exc_I_uid24_fpExpETest_q_to_posInf_uid86_fpExpETest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid86_fpExpETest(LOGICAL,85)@1
posInf_uid86_fpExpETest_a <= ld_exc_I_uid24_fpExpETest_q_to_posInf_uid86_fpExpETest_a_q;
posInf_uid86_fpExpETest_b <= InvSignX_uid81_fpExpETest_q;
posInf_uid86_fpExpETest_q <= posInf_uid86_fpExpETest_a and posInf_uid86_fpExpETest_b;
--ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_inputreg(DELAY,966)
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => posInf_uid86_fpExpETest_q, xout => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem(DUALMEM,967)
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ia <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_inputreg_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_aa <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ab <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_iq,
address_a => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_aa,
data_a => ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_ia
);
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_reset0 <= areset;
ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_q <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_iq(0 downto 0);
--excRInf_uid87_fpExpETest(LOGICAL,86)@41
excRInf_uid87_fpExpETest_a <= ld_posInf_uid86_fpExpETest_q_to_excRInf_uid87_fpExpETest_a_replace_mem_q;
excRInf_uid87_fpExpETest_b <= regInAndOvf_uid84_fpExpETest_q;
excRInf_uid87_fpExpETest_c <= ld_regXAndExpOverflowAndPos_uid82_fpExpETest_q_to_excRInf_uid87_fpExpETest_c_replace_mem_q;
excRInf_uid87_fpExpETest_q <= excRInf_uid87_fpExpETest_a or excRInf_uid87_fpExpETest_b or excRInf_uid87_fpExpETest_c;
--ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor(LOGICAL,963)
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_b <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_q <= not (ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_a or ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_b);
--ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena(REG,964)
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_nor_q = "1") THEN
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd(LOGICAL,965)
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_a <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_sticky_ena_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_b <= en;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_q <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_a and ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_b;
--negInf_uid76_fpExpETest(LOGICAL,75)@0
negInf_uid76_fpExpETest_a <= exc_I_uid24_fpExpETest_q;
negInf_uid76_fpExpETest_b <= signX_uid7_fpExpETest_b;
negInf_uid76_fpExpETest_q <= negInf_uid76_fpExpETest_a and negInf_uid76_fpExpETest_b;
--ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_inputreg(DELAY,953)
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => negInf_uid76_fpExpETest_q, xout => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem(DUALMEM,954)
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ia <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_inputreg_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_aa <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdreg_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ab <= ld_expOvfInitial_uid41_fpExpETest_b_to_InvExpOvfInitial_uid78_fpExpETest_a_replace_rdmux_q;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 39,
width_b => 1,
widthad_b => 6,
numwords_b => 39,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_iq,
address_a => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_aa,
data_a => ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_ia
);
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_reset0 <= areset;
ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_q <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_iq(0 downto 0);
--ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor(LOGICAL,950)
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_a <= ld_shiftValuePreSatRed_uid43_fpExpETest_b_to_shiftVal_uid44_fpExpETest_c_notEnable_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_b <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_q <= not (ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_a or ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_b);
--ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena(REG,951)
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_nor_q = "1") THEN
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd(LOGICAL,952)
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_a <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_sticky_ena_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_b <= en;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_q <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_a and ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_b;
--regXAndExpOverflowAndNeg_uid77_fpExpETest(LOGICAL,76)@1
regXAndExpOverflowAndNeg_uid77_fpExpETest_a <= exc_R_uid30_fpExpETest_q;
regXAndExpOverflowAndNeg_uid77_fpExpETest_b <= reg_expOvfInitial_uid41_fpExpETest_0_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_2_q;
regXAndExpOverflowAndNeg_uid77_fpExpETest_c <= ld_signX_uid7_fpExpETest_b_to_regXAndExpOverflowAndNeg_uid77_fpExpETest_c_q;
regXAndExpOverflowAndNeg_uid77_fpExpETest_q <= regXAndExpOverflowAndNeg_uid77_fpExpETest_a and regXAndExpOverflowAndNeg_uid77_fpExpETest_b and regXAndExpOverflowAndNeg_uid77_fpExpETest_c;
--ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_inputreg(DELAY,940)
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => regXAndExpOverflowAndNeg_uid77_fpExpETest_q, xout => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem(DUALMEM,941)
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ia <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_inputreg_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_aa <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdreg_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ab <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_rdmux_q;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_iq,
address_a => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_aa,
data_a => ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_ia
);
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_reset0 <= areset;
ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_q <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_iq(0 downto 0);
--expUdf_uid72_fpExpETest(COMPARE,71)@41
expUdf_uid72_fpExpETest_cin <= GND_q;
expUdf_uid72_fpExpETest_a <= STD_LOGIC_VECTOR('0' & "0000000000000000" & GND_q) & '0';
expUdf_uid72_fpExpETest_b <= STD_LOGIC_VECTOR((17 downto 16 => reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q(15)) & reg_expRPostBiasPreExc_uid70_fpExpETest_0_to_expUdf_uid72_fpExpETest_1_q) & expUdf_uid72_fpExpETest_cin(0);
expUdf_uid72_fpExpETest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid72_fpExpETest_a) - SIGNED(expUdf_uid72_fpExpETest_b));
expUdf_uid72_fpExpETest_n(0) <= not expUdf_uid72_fpExpETest_o(18);
--regXAndUdf_uid79_fpExpETest(LOGICAL,78)@41
regXAndUdf_uid79_fpExpETest_a <= ld_exc_R_uid30_fpExpETest_q_to_regXAndUdf_uid79_fpExpETest_a_replace_mem_q;
regXAndUdf_uid79_fpExpETest_b <= expUdf_uid72_fpExpETest_n;
regXAndUdf_uid79_fpExpETest_c <= InvExpOvfInitial_uid78_fpExpETest_q;
regXAndUdf_uid79_fpExpETest_q <= regXAndUdf_uid79_fpExpETest_a and regXAndUdf_uid79_fpExpETest_b and regXAndUdf_uid79_fpExpETest_c;
--excRZero_uid80_fpExpETest(LOGICAL,79)@41
excRZero_uid80_fpExpETest_a <= regXAndUdf_uid79_fpExpETest_q;
excRZero_uid80_fpExpETest_b <= ld_regXAndExpOverflowAndNeg_uid77_fpExpETest_q_to_excRZero_uid80_fpExpETest_b_replace_mem_q;
excRZero_uid80_fpExpETest_c <= ld_negInf_uid76_fpExpETest_q_to_excRZero_uid80_fpExpETest_c_replace_mem_q;
excRZero_uid80_fpExpETest_q <= excRZero_uid80_fpExpETest_a or excRZero_uid80_fpExpETest_b or excRZero_uid80_fpExpETest_c;
--concExc_uid88_fpExpETest(BITJOIN,87)@41
concExc_uid88_fpExpETest_q <= ld_exc_N_uid26_fpExpETest_q_to_concExc_uid88_fpExpETest_c_replace_mem_q & excRInf_uid87_fpExpETest_q & excRZero_uid80_fpExpETest_q;
--reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0(REG,420)@41
reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0_q <= concExc_uid88_fpExpETest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid89_fpExpETest(LOOKUP,88)@42
excREnc_uid89_fpExpETest: PROCESS (reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid88_fpExpETest_0_to_excREnc_uid89_fpExpETest_0_q) IS
WHEN "000" => excREnc_uid89_fpExpETest_q <= "01";
WHEN "001" => excREnc_uid89_fpExpETest_q <= "00";
WHEN "010" => excREnc_uid89_fpExpETest_q <= "10";
WHEN "011" => excREnc_uid89_fpExpETest_q <= "00";
WHEN "100" => excREnc_uid89_fpExpETest_q <= "11";
WHEN "101" => excREnc_uid89_fpExpETest_q <= "00";
WHEN "110" => excREnc_uid89_fpExpETest_q <= "00";
WHEN "111" => excREnc_uid89_fpExpETest_q <= "00";
WHEN OTHERS =>
excREnc_uid89_fpExpETest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--xIn(GPIN,3)@0
--expRPostExc_uid97_fpExpETest(MUX,96)@42
expRPostExc_uid97_fpExpETest_s <= excREnc_uid89_fpExpETest_q;
expRPostExc_uid97_fpExpETest: PROCESS (expRPostExc_uid97_fpExpETest_s, en, cstZeroWE_uid11_fpExpETest_q, ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d_q, cstAllOWE_uid15_fpExpETest_q, cstAllOWE_uid15_fpExpETest_q)
BEGIN
CASE expRPostExc_uid97_fpExpETest_s IS
WHEN "00" => expRPostExc_uid97_fpExpETest_q <= cstZeroWE_uid11_fpExpETest_q;
WHEN "01" => expRPostExc_uid97_fpExpETest_q <= ld_expR_uid75_fpExpETest_b_to_expRPostExc_uid97_fpExpETest_d_q;
WHEN "10" => expRPostExc_uid97_fpExpETest_q <= cstAllOWE_uid15_fpExpETest_q;
WHEN "11" => expRPostExc_uid97_fpExpETest_q <= cstAllOWE_uid15_fpExpETest_q;
WHEN OTHERS => expRPostExc_uid97_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid90_fpExpETest(CONSTANT,89)
oneFracRPostExc2_uid90_fpExpETest_q <= "0000000000000000000000000000000000000000000000000001";
--peOR_uid67_fpExpETest(BITSELECT,66)@39
peOR_uid67_fpExpETest_in <= s5_uid278_exp10PolyEval_b(57 downto 0);
peOR_uid67_fpExpETest_b <= peOR_uid67_fpExpETest_in(57 downto 5);
--fracR_uid71_fpExpETest(BITSELECT,70)@39
fracR_uid71_fpExpETest_in <= peOR_uid67_fpExpETest_b(51 downto 0);
fracR_uid71_fpExpETest_b <= fracR_uid71_fpExpETest_in(51 downto 0);
--ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_inputreg(DELAY,1005)
ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracR_uid71_fpExpETest_b, xout => ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d(DELAY,507)@39
ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_inputreg_q, xout => ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid93_fpExpETest(MUX,92)@42
fracRPostExc_uid93_fpExpETest_s <= excREnc_uid89_fpExpETest_q;
fracRPostExc_uid93_fpExpETest: PROCESS (fracRPostExc_uid93_fpExpETest_s, en, cstAllZWF_uid16_fpExpETest_q, ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_q, cstAllZWF_uid16_fpExpETest_q, oneFracRPostExc2_uid90_fpExpETest_q)
BEGIN
CASE fracRPostExc_uid93_fpExpETest_s IS
WHEN "00" => fracRPostExc_uid93_fpExpETest_q <= cstAllZWF_uid16_fpExpETest_q;
WHEN "01" => fracRPostExc_uid93_fpExpETest_q <= ld_fracR_uid71_fpExpETest_b_to_fracRPostExc_uid93_fpExpETest_d_q;
WHEN "10" => fracRPostExc_uid93_fpExpETest_q <= cstAllZWF_uid16_fpExpETest_q;
WHEN "11" => fracRPostExc_uid93_fpExpETest_q <= oneFracRPostExc2_uid90_fpExpETest_q;
WHEN OTHERS => fracRPostExc_uid93_fpExpETest_q <= (others => '0');
END CASE;
END PROCESS;
--RExpE_uid98_fpExpETest(BITJOIN,97)@42
RExpE_uid98_fpExpETest_q <= GND_q & expRPostExc_uid97_fpExpETest_q & fracRPostExc_uid93_fpExpETest_q;
--xOut(GPOUT,4)@42
q <= RExpE_uid98_fpExpETest_q;
end normal;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_sin.vhd | 10 | 14482 | -- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_SIN.VHD ***
--*** ***
--*** Function: Single Precision SIN Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take cos(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 7 ***
--*** (1 more than cos) ***
--***************************************************
ENTITY fp_sin IS
GENERIC (
device : integer := 0;
width : positive := 30;
depth : positive := 18;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_sin;
ARCHITECTURE rtl of fp_sin IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal input_number : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal input_number_delay : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (9 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal signoutff : STD_LOGIC;
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC;
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** SIN(X) = X when exponent < 115 ***
input_number <= signin & exponentin & mantissain;
-- level 1 in, level range_depth+cordic_depth+7 out
cdin: fp_del
GENERIC MAP (width=>32,pipes=>range_depth+cordic_depth+6)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>input_number,
cc=>input_number_delay);
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign <= circle(36); -- sin negative in quadrants 3&4
quadrantselect <= circle(35); -- sin (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take cos rather than sin
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
END LOOP;
FOR k IN 1 TO range_depth+cordic_depth+5 LOOP
selectoutputff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff(1) <= quadrantsign XOR signinff(range_depth);
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff(k) <= signcalcff(k-1);
END LOOP;
exponentinff <= exponentin; -- level 1
selectoutputff(1) <= exponentcheck(9); -- level 2 to range_depth+cordic_depth+6
FOR k IN 2 TO range_depth+cordic_depth+5 LOOP
selectoutputff(k) <= selectoutputff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + NOT(quadrant(34)); -- level range_depth+1
-- level range depth+1 to range_depth+4
select_sincosff(1) <= quadrant(34);
FOR k IN 2 TO 4 LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- if exponent < 115, sin = input
exponentcheck <= ('0' & exponentinff) - ('0' & x"73");
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sincosbit=>select_sincosff(4),
sincos=>fixed_sincos);
gfxa: IF (width < 36) GENERATE
fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1);
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sincosnode <= fixed_sincos;
END GENERATE;
clz: fp_clz36
PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode);
sft: fp_lsft36
PORT MAP (inbus=>fixed_sincosff,shift=>countff,
outbus=>mantissanormnode);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode <= "10000000" - ("00" & countff);
overflownode(1) <= mantissanormnode(12);
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sincosff(k) <= '0';
END LOOP;
countff <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
signoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5
countff <= countnode; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12);
exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24);
-- level range_depth+cordic_depth+7
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= (mantissanormff(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(k) AND selectoutputff(range_depth+cordic_depth+5));
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= (exponentnormff(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(k+23) AND selectoutputff(range_depth+cordic_depth+5));
END LOOP;
signoutff <= (signcalcff(cordic_depth+6) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(32) AND selectoutputff(range_depth+cordic_depth+5));
END IF;
END IF;
END PROCESS;
mantissaout <= mantissaoutff;
exponentout <= exponentoutff;
signout <= signoutff;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_lnrnd.vhd | 10 | 6337 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNRND.VHD ***
--*** ***
--*** Function: FP LOG Output Block - Rounded ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_lnrnd;
ARCHITECTURE rtl OF fp_lnrnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal zeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal infinityff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
signff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
infinityff(1) <= infinityin;
infinityff(2) <= infinityff(1);
zeroff(1) <= zeroin;
zeroff(2) <= zeroff(1);
signff(1) <= signln;
signff(2) <= signff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaln(manwidth+1 DOWNTO 2) + (zerovec & mantissaln(1));
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentln;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaln(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaln(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when true
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(zeroff(1)) OR infinityff(1);
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroff(1));
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanff(1) OR infinityff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= infinityff(2);
zeroout <= zeroff(2);
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_mul5418s.vhd | 10 | 4973 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL5418S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** 54x18=54, 3 18x18 architecture, ***
--*** Stratix II/III, 3 or 4 pipeline, ***
--*** synthesizable ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 15/01/08 - outputs up to 72 bits now ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul5418s IS
GENERIC (
widthcc : positive := 36;
pipes : positive := 3 --3/4
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (18 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul5418s;
ARCHITECTURE rtl OF fp_mul5418s IS
signal zerovec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout, multwoout, multhrout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal aavec, bbvec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal lowff, lowdelff : STD_LOGIC_VECTOR (18 DOWNTO 1);
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_mul2s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 18 GENERATE
zerovec(k) <= '0';
END GENERATE;
mulone: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(18 DOWNTO 1),databb=>databb(18 DOWNTO 1),
result=>muloneout);
multwo: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(36 DOWNTO 19),databb=>databb(18 DOWNTO 1),
result=>multwoout);
multhr: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(54 DOWNTO 37),databb=>databb(18 DOWNTO 1),
result=>multhrout);
aavec <= multhrout & muloneout(36 DOWNTO 19);
bbvec <= zerovec(18 DOWNTO 1) & multwoout;
adder: dp_fxadd
GENERIC MAP (width=>54,pipes=>pipes-2,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aavec,bb=>bbvec,carryin=>'0',
cc=>resultnode(72 DOWNTO 19));
gda: IF (pipes = 3) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 18 LOOP
lowff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowff <= muloneout(18 DOWNTO 1);
END IF;
END IF;
END PROCESS;
resultnode(18 DOWNTO 1) <= lowff;
END GENERATE;
gdb: IF (pipes = 4) GENERATE
pdb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 18 LOOP
lowff(k) <= '0';
lowdelff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowff <= muloneout(18 DOWNTO 1);
lowdelff <= lowff;
END IF;
END IF;
END PROCESS;
resultnode(18 DOWNTO 1) <= lowdelff;
END GENERATE;
result <= resultnode(72 DOWNTO 73-widthcc);
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/SinPiDPStratixVf400_safe_path.vhd | 10 | 437 | -- safe_path for SinPiDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinPiDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinPiDPStratixVf400_safe_path;
PACKAGE body SinPiDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END SinPiDPStratixVf400_safe_path;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/dp_ldexp.vhd | 10 | 4877 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_LDEXP.VHD ***
--*** ***
--*** Function: Single Precision Load Exponent ***
--*** ***
--*** ldexp(x,n) - x*2^n - IEEE in and out ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_ldexp IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_ldexp;
ARCHITECTURE rtl OF dp_ldexp IS
signal signinff : STD_LOGIC;
signal exponentinff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal bbff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal satoutff, zerooutff, nanoutff : STD_LOGIC;
signal satnode, zeronode, nannode : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzeroin, expmaxin : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzeronode, expmaxnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzeroout, expmaxout : STD_LOGIC;
signal manzeroin : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
signoutff <= '0';
FOR k IN 1 TO 11 LOOP
exponentinff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissainff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
bbff(k) <= '0';
END LOOP;
satoutff <= '0';
zerooutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
exponentinff <= exponentin;
mantissainff <= mantissain;
bbff <= bb(13 DOWNTO 1);
signoutff <= signinff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeronode)) OR satnode OR nannode;
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= (mantissainff(k) AND NOT(zeronode) AND NOT(satnode)) OR nannode;
END LOOP;
satoutff <= satnode;
zerooutff <= zeronode;
nanoutff <= nannode;
END IF;
END IF;
END PROCESS;
expnode <= ("00" & exponentinff) + bbff;
expzeroin(1) <= exponentinff(1);
expmaxin(1) <= exponentinff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzeroin(k) <= expzeroin(k-1) OR exponentinff(k);
expmaxin(k) <= expmaxin(k-1) AND exponentinff(k);
END GENERATE;
expzeronode(1) <= expnode(1);
expmaxnode(1) <= expnode(1);
gxb: FOR k IN 2 TO 11 GENERATE
expzeronode(k) <= expzeronode(k-1) OR expnode(k);
expmaxnode(k) <= expmaxnode(k-1) AND expnode(k);
END GENERATE;
expzeroout <= NOT(expzeroin(11)) OR (NOT(expzeronode(11)) AND NOT(expnode(12))) OR (expnode(13));
expmaxout <= expmaxin(11) OR (expmaxnode(11) AND NOT(expnode(12))) OR (expnode(12) AND NOT(expnode(13)));
manzeroin(1) <= mantissainff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzeroin(k) <= manzeroin(k-1) OR mantissainff(k);
END GENERATE;
manzero <= NOT(manzeroin(52));
mannonzero <= manzeroin(52);
satnode <= (expmaxin(11) AND NOT(manzeroin(52))) OR expmaxout;
zeronode <= NOT(expzeroin(11)) OR expzeroout;
nannode <= expmaxin(11) AND manzeroin(52);
signout <= signoutff;
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
satout <= satoutff;
zeroout <= zerooutff;
nanout <= nanoutff;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/hcc_mulufp54.vhd | 10 | 5016 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULUFP54.VHD ***
--*** ***
--*** Function: Double precision multiplier ***
--*** core (unsigned mantissa) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulufp54 IS
GENERIC (synthesize : integer := 1); -- 0 = behavioral, 1 = instantiated
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bbman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
bbexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
ccman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (13 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_mulufp54;
ARCHITECTURE rtl OF hcc_mulufp54 IS
constant normtype : integer := 0;
type expfftype IS ARRAY (5 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal mulout : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexpff, bbexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expff : expfftype;
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (5 DOWNTO 1);
component hcc_mul54usb
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_mul54uss
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
-- 54 bit mantissa, signed normalized input
-- [S ][1 ][M...M]
-- [54][53][52..1]
-- multiplier outputs (result < 2)
-- [S....S][1 ][M*M...][X...X]
-- [72..70][69][68..17][16..1]
-- multiplier outputs (result >= 2)
-- [S....S][1 ][M*M...][X...X]
-- [72..71][70][69..18][17..1]
-- assume that result > 2
-- output [71..8] for 64 bit mantissa out
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aaexpff <= "0000000000000";
bbexpff <= "0000000000000";
FOR k IN 1 TO 5 LOOP
expff(k)(13 DOWNTO 1) <= "0000000000000";
END LOOP;
aasatff <= '0';
aazipff <= '0';
bbsatff <= '0';
bbzipff <= '0';
ccsatff <= "00000";
cczipff <= "00000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasatff <= aasat;
aazipff <= aazip;
bbsatff <= bbsat;
bbzipff <= bbzip;
ccsatff(1) <= aasatff OR bbsatff;
FOR k IN 2 TO 5 LOOP
ccsatff(k) <= ccsatff(k-1);
END LOOP;
cczipff(1) <= aazipff OR bbzipff;
FOR k IN 2 TO 5 LOOP
cczipff(k) <= cczipff(k-1);
END LOOP;
aaexpff <= aaexp;
bbexpff <= bbexp;
expff(1)(13 DOWNTO 1) <= aaexpff + bbexpff - "0001111111111";
FOR k IN 1 TO 13 LOOP
expff(2)(k) <= (expff(1)(k) OR ccsatff(1)) AND NOT(cczipff(1));
END LOOP;
FOR k IN 3 TO 5 LOOP
expff(k)(13 DOWNTO 1) <= expff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gsa: IF (synthesize = 0) GENERATE
bmult: hcc_mul54usb
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aaman,bb=>bbman,
cc=>mulout);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
smult: hcc_mul54uss
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
--***************
--*** OUTPUTS ***
--***************
ccman <= mulout;
ccexp <= expff(5)(13 DOWNTO 1);
ccsat <= ccsatff(5);
cczip <= cczipff(5);
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/hcc_mulfp2x.vhd | 10 | 24298 |
LIBRARY ieee;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP2X.VHD ***
--*** ***
--*** Function: Double precision multiplier ***
--*** (unsigned mantissa) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 28/01/08 - see below ***
--*** ***
--*** ***
--***************************************************
-- 28/01/08 - correct manoverflow for ieee output, effects of mantissa shift
-- for both ieee and mult output, test output widths, also reversed exp and man
-- order in ieee output
-- 31/08/08 - behavioral and synth mults both now return "001X" (> 2) OR "0001X" (<2)
-- change xoutput to 1 bit less right shift (behavioral mult changed)
ENTITY hcc_mulfp2x IS
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_mulfp2x;
ARCHITECTURE rtl OF hcc_mulfp2x IS
type ccxexpdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type cceexpdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- multiplier core interface
signal mulinaaman, mulinbbman : STD_LOGIC_VECTOR(54 DOWNTO 1);
signal mulinaaexp, mulinbbexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal mulinaasat, mulinaazip : STD_LOGIC;
signal mulinbbsat, mulinbbzip : STD_LOGIC;
signal mulinaasign, mulinbbsign : STD_LOGIC;
signal mulinaasignff, mulinbbsignff : STD_LOGIC;
signal mulsignff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal ccmannode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccexpnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccsatnode, cczipnode : STD_LOGIC;
-- output section (x out)
signal ccmanshiftnode, signedccxmannode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccxroundnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccxroundff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal ccxexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccxsatff, ccxzipff : STD_LOGIC;
signal ccxexpdelff : ccxexpdelfftype;
signal ccxsatdelff, ccxzipdelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
-- output section (ieeeout)
signal shiftroundbit : STD_LOGIC;
signal cceroundnode : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal cceroundcarry : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal ccemannode : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal ccemanoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal cceexpoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal ccesignbitff : STD_LOGIC;
signal cceroundff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal cceexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccesatff, ccezipff : STD_LOGIC;
signal ccesignff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal cceexpdelff : cceexpdelfftype;
signal ccesatdelff, ccezipdelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal ccesigndelff : STD_LOGIC_VECTOR (3 DOWNTO 1);
signal cceexpbase, cceexpplus : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccesatbase, ccezipbase : STD_LOGIC;
signal cceexpmax, cceexpzero : STD_LOGIC;
signal manoutzero, expoutzero, expoutmax : STD_LOGIC;
signal manoverflow : STD_LOGIC;
-- output section (multout)
signal shiftmanbit : STD_LOGIC;
signal manshiftnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal manshiftff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal ccexpdelff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccsatdelff, cczipdelff : STD_LOGIC;
signal muloutsignff : STD_LOGIC;
-- debug
signal aaexp, bbexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal ccexp : STD_LOGIC_VECTOR (11 + 2*multoutput + 2*xoutput DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR (54+10*xoutput DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_mulufp54
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bbman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
bbexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
ccman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (13 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--**************************************************
--*** ***
--*** Input Section - Normalization, if required ***
--*** ***
--**************************************************
--********************************************************
--*** NOTE THAT IN ALL CASES SIGN BIT IS PACKED IN MSB ***
--*** OF UNSIGNED MULTIPLIER ***
--********************************************************
--*** ieee754 input when multiplier input is from cast ***
--*** cast now creates different ***
--*** formats for multiplier, divider, and alu ***
--*** multiplier format [S][1][mantissa....] ***
--********************************************************
--********************************************************
--*** if input from another double multiplier (special ***
--*** output mode normalizes to 54 bit mantissa and ***
--*** 13 bit exponent ***
--*** multiplier format [S][1][mantissa....] ***
--********************************************************
--********************************************************
--*** if input from internal format, must be normed ***
--*** by normfp2x first, creates [S][1][mantissa...] ***
--********************************************************
mulinaaman <= '0' & aa(66 DOWNTO 14);
mulinaaexp <= aa(13 DOWNTO 1);
mulinbbman <= '0' & bb(66 DOWNTO 14);
mulinbbexp <= bb(13 DOWNTO 1);
mulinaasat <= aasat;
mulinaazip <= aazip;
mulinbbsat <= bbsat;
mulinbbzip <= bbzip;
-- signbits packed in MSB of mantissas
mulinaasign <= aa(67);
mulinbbsign <= bb(67);
--**************************************************
--*** ***
--*** Multiplier Section ***
--*** ***
--**************************************************
mult: hcc_mulufp54
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mulinaaman,aaexp=>mulinaaexp,aasat=>mulinaasat,aazip=>mulinaazip,
bbman=>mulinbbman,bbexp=>mulinbbexp,bbsat=>mulinbbsat,bbzip=>mulinbbzip,
ccman=>ccmannode,ccexp=>ccexpnode,ccsat=>ccsatnode,cczip=>cczipnode);
psd: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
mulinaasignff <= '0';
mulinbbsignff <= '0';
FOR k IN 1 TO 5 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mulinaasignff <= mulinaasign;
mulinbbsignff <= mulinbbsign;
mulsignff(1) <= mulinaasignff XOR mulinbbsignff;
FOR k IN 2 TO 5 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************************************************
--*** ***
--*** Output Section ***
--*** ***
--**************************************************
--********************************************************
--*** internal format output, convert back to signed ***
--*** no need for fine normalization ***
--********************************************************
goxa: IF (xoutput = 1) GENERATE
-- result will be "001X" (>2) or "0001X" (<2)
-- Y is SSSSS1 (<2) - therefore right shift 2 bits
-- 31/08/08 - behavioral mult changed to be same as synth one
ccmanshiftnode <= "00" & ccmannode(64 DOWNTO 3);
goxb: FOR k IN 1 TO 64 GENERATE
signedccxmannode(k) <= ccmanshiftnode(k) XOR mulsignff(5);
END GENERATE;
goxc: IF (roundconvert = 0 AND outputpipe = 0) GENERATE
--*** OUTPUTS ***
cc(77 DOWNTO 14) <= signedccxmannode;
cc(13 DOWNTO 1) <= ccexpnode;
ccsat <= ccsatnode;
cczip <= cczipnode;
END GENERATE;
goxd: IF ((roundconvert = 0 AND outputpipe = 1) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
goxe: IF (roundconvert = 0) GENERATE
ccxroundnode <= signedccxmannode;
END GENERATE;
goxf: IF (roundconvert = 1) GENERATE
ccxroundnode <= signedccxmannode + (zerovec(63 DOWNTO 1) & mulsignff(5));
END GENERATE;
poxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
ccxroundff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
ccxexpff(k) <= '0';
END LOOP;
ccxsatff <= '0';
ccxzipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccxroundff <= ccxroundnode;
ccxexpff <= ccexpnode;
ccxsatff <= ccsatnode;
ccxzipff <= cczipnode;
END IF;
END IF;
END PROCESS;
--*** OUTPUTS ***
cc(77 DOWNTO 14) <= ccxroundff;
cc(13 DOWNTO 1) <= ccxexpff(13 DOWNTO 1);
ccsat <= ccxsatff;
cczip <= ccxzipff;
END GENERATE;
goxg: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
poxb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
ccxexpdelff(1)(k) <= '0';
ccxexpdelff(2)(k) <= '0';
END LOOP;
ccxsatdelff <= "00";
ccxzipdelff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccxexpdelff(1)(13 DOWNTO 1) <= ccexpnode;
ccxexpdelff(2)(13 DOWNTO 1) <= ccxexpdelff(1)(13 DOWNTO 1);
ccxsatdelff(1) <= ccsatnode;
ccxsatdelff(2) <= ccxsatdelff(1);
ccxzipdelff(1) <= cczipnode;
ccxzipdelff(2) <= ccxzipdelff(1);
END IF;
END IF;
END PROCESS;
goxh: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>signedccxmannode,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(5),
cc=>ccxroundnode);
END GENERATE;
goxi: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>signedccxmannode,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(5),
cc=>ccxroundnode);
END GENERATE;
--*** OUTPUTS ***
cc(77 DOWNTO 14) <= ccxroundnode;
cc(13 DOWNTO 1) <= ccxexpdelff(2)(13 DOWNTO 1);
ccsat <= ccxsatdelff(2);
cczip <= ccxzipdelff(2);
END GENERATE;
END GENERATE;
--********************************************************
--*** if output directly out of datapath, convert here ***
--*** input to multiplier always "01XXX" format, so ***
--*** just 1 bit normalization required ***
--********************************************************
goea: IF (ieeeoutput = 1) GENERATE -- ieee754 out of datapath, do conversion
-- output either "0001XXXX.." (<2) or "001XXXX.." (>=2), need to make output
-- 01XXXX
shiftroundbit <= NOT(ccmannode(62));
goeb: FOR k IN 1 TO 55 GENERATE -- format "01"[52..1]R
cceroundnode(k) <= (ccmannode(k+7) AND shiftroundbit) OR
(ccmannode(k+8) AND NOT(shiftroundbit));
END GENERATE;
goec: IF (roundconvert = 0) GENERATE
ccemannode <= cceroundnode(53 DOWNTO 2);
poia: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= '0';
END LOOP;
ccesignbitff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= ccemannode(k) AND NOT(manoutzero);
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= (cceexpplus(k) OR expoutmax) AND NOT(expoutzero);
END LOOP;
ccesignbitff <= mulsignff(5);
END IF;
END IF;
END PROCESS;
cceexpplus <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftroundbit)); -- change 28/01/08
ccesatbase <= ccsatnode;
ccezipbase <= cczipnode;
manoverflow <= '0'; -- change 28/01/08
--*** OUTPUTS ***
cc(64) <= ccesignbitff;
-- change 28/01/08
cc(63 DOWNTO 53) <= cceexpoutff;
cc(52 DOWNTO 1) <= ccemanoutff;
END GENERATE;
goed: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
cceroundcarry <= zerovec(53 DOWNTO 1) & cceroundnode(1);
poeb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
cceroundff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
cceexpff(k) <= '0';
END LOOP;
ccesatff <= '0';
ccezipff <= '0';
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= '0';
END LOOP;
ccesignff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
cceroundff <= cceroundnode(55 DOWNTO 2) + cceroundcarry;
-- change 28/01/08
cceexpff(13 DOWNTO 1) <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftroundbit));
ccesatff <= ccsatnode;
ccezipff <= cczipnode;
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= cceroundff(k) AND NOT(manoutzero);
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= (cceexpplus(k) OR expoutmax) AND NOT(expoutzero);
END LOOP;
ccesignff(1) <= mulsignff(5);
ccesignff(2) <= ccesignff(1);
END IF;
END IF;
END PROCESS;
manoverflow <= cceroundff(54);
cceexpbase <= cceexpff(13 DOWNTO 1);
ccesatbase <= ccesatff;
ccezipbase <= ccezipff;
cceexpplus <= cceexpbase + ("000000000000" & cceroundff(54));
--*** OUTPUTS ***
cc(64) <= ccesignff(2);
-- change 28/01/08
cc(63 DOWNTO 53) <= cceexpoutff;
cc(52 DOWNTO 1) <= ccemanoutff;
END GENERATE;
goef: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
cceroundcarry <= zerovec(53 DOWNTO 1) & cceroundnode(1);
goeg: IF (synthesize = 0) GENERATE
addone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cceroundnode(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),
carryin=>cceroundnode(1),
cc=>cceroundnode);
END GENERATE;
goeh: IF (synthesize = 1) GENERATE
addtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>cceroundnode(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),
carryin=>cceroundnode(1),
cc=>cceroundnode);
END GENERATE;
poea: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
cceexpdelff(1)(k) <= '0';
cceexpdelff(2)(k) <= '0';
END LOOP;
ccesatdelff <= "00";
ccezipdelff <= "00";
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= '0';
END LOOP;
ccesigndelff <= "000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- change 28/01/08
cceexpdelff(1)(13 DOWNTO 1) <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftroundbit));
cceexpdelff(2)(13 DOWNTO 1) <= cceexpdelff(1)(13 DOWNTO 1);
ccesatdelff(1) <= ccsatnode;
ccesatdelff(2) <= ccesatdelff(1);
ccezipdelff(1) <= cczipnode;
ccezipdelff(2) <= ccezipdelff(1);
FOR k IN 1 TO 52 LOOP
ccemanoutff(k) <= cceroundnode(k) AND NOT(manoutzero);
END LOOP;
FOR k IN 1 TO 11 LOOP
cceexpoutff(k) <= (cceexpplus(k) OR expoutmax) AND NOT(expoutzero);
END LOOP;
ccesigndelff(1) <= mulsignff(5);
ccesigndelff(2) <= ccesigndelff(1);
ccesigndelff(3) <= ccesigndelff(2);
END IF;
END IF;
END PROCESS;
manoverflow <= cceroundnode(54);
cceexpbase <= cceexpdelff(2)(13 DOWNTO 1);
ccesatbase <= ccesatdelff(2);
ccezipbase <= ccezipdelff(2);
cceexpplus <= cceexpbase + ("000000000000" & cceroundnode(54));
--*** OUTPUTS ***
cc(64) <= ccesigndelff(3);
-- change 28/01/08
cc(63 DOWNTO 53) <= cceexpoutff;
cc(52 DOWNTO 1) <= ccemanoutff;
END GENERATE;
cceexpmax <= cceexpplus(11) AND cceexpplus(10) AND cceexpplus(9) AND cceexpplus(8) AND
cceexpplus(7) AND cceexpplus(6) AND cceexpplus(5) AND cceexpplus(4) AND
cceexpplus(3) AND cceexpplus(2) AND cceexpplus(1);
cceexpzero <= NOT(cceexpplus(11) OR cceexpplus(10) OR cceexpplus(9) OR cceexpplus(8) OR
cceexpplus(7) OR cceexpplus(6) OR cceexpplus(5) OR cceexpplus(4) OR
cceexpplus(3) OR cceexpplus(2) OR cceexpplus(1));
-- any special condition turns mantissa zero
manoutzero <= ccesatbase OR ccezipbase OR
cceexpmax OR cceexpzero OR
cceexpplus(13) OR cceexpplus(12) OR
manoverflow;
expoutzero <= ccezipbase OR cceexpzero OR cceexpplus(13);
expoutmax <= cceexpmax OR cceexpplus(12);
-- dummy only
ccsat <= '0';
cczip <= '0';
END GENERATE;
--********************************************************
--*** if output directly into DP mult, convert here ***
--*** input to multiplier always "01XXX" format, so ***
--*** just 1 bit normalization required, no round ***
--********************************************************
goma: IF (multoutput = 1) GENERATE -- to another multiplier
-- output either "0001XXXX.." (<2) or "001XXXX.." (>=2), need to make output
-- 01XXXX
shiftmanbit <= NOT(ccmannode(62));
gomb: FOR k IN 1 TO 54 GENERATE -- format "01"[52..1]
manshiftnode(k) <= (ccmannode(k+8) AND shiftmanbit) OR
(ccmannode(k+9) AND NOT(shiftmanbit));
END GENERATE;
poma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
manshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
ccexpdelff(k) <= '0';
END LOOP;
ccsatdelff <= '0';
cczipdelff <= '0';
muloutsignff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
manshiftff <= manshiftnode;
-- change 28/01/08
ccexpdelff(13 DOWNTO 1) <= ccexpnode + (zerovec(12 DOWNTO 1) & NOT(shiftmanbit));
ccsatdelff <= ccsatnode;
cczipdelff <= cczipnode;
muloutsignff <= mulsignff(5);
END IF;
END IF;
END PROCESS;
cc(67) <= muloutsignff;
cc(66 DOWNTO 14) <= manshiftff(53 DOWNTO 1);
cc(13 DOWNTO 1) <= ccexpdelff(13 DOWNTO 1);
ccsat <= ccsatdelff;
cczip <= cczipdelff;
END GENERATE;
--*** DEBUG SECTION ***
aaexp <= aa(13 DOWNTO 1);
bbexp <= bb(13 DOWNTO 1);
aaman <= aa(67 DOWNTO 14);
bbman <= bb(67 DOWNTO 14);
gdba: IF (xoutput = 1) GENERATE
gdbb: IF (roundconvert = 0 AND outputpipe = 0) GENERATE
ccman <= signedccxmannode;
ccexp <= ccexpnode;
END GENERATE;
gdbc: IF ((roundconvert = 0 AND outputpipe = 1) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
ccman <= ccxroundff;
ccexp <= ccxexpff(13 DOWNTO 1);
END GENERATE;
gdbd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
ccman <= ccxroundnode;
ccexp <= ccxexpdelff(2)(13 DOWNTO 1);
END GENERATE;
END GENERATE;
-- change 28/01/08
gdbe: IF (ieeeoutput = 1) GENERATE
ccexp <= cceexpoutff;
ccman <= "01" & ccemanoutff;
END GENERATE;
-- change 28/01/08
gdbf: IF (multoutput = 1) GENERATE
ccexp <= ccexpdelff(13 DOWNTO 1);
ccman <= '0' & manshiftff(53 DOWNTO 1);
END GENERATE;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/hcc_neg1x.vhd | 10 | 5243 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NEG1X.VHD ***
--*** ***
--*** Function: Negate Variable ***
--*** ***
--*** Input is normalized S,'1',mantissa,exp ***
--*** ***
--*** 14/03/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_neg1x IS
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (smantissa/10)
funcoutput : integer := 0 -- function output (S'1'umantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_neg1x;
ARCHITECTURE rtl OF hcc_neg1x IS
signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC;
-- x output
signal ccxman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccxexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
-- function output
signal ccfuncman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccfuncexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
-- ieee output
signal expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal manoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal expoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expmax, expzero : STD_LOGIC;
signal manoutzero, expoutzero, expoutmax : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
END IF;
END IF;
END PROCESS;
--******************************
--*** internal format output ***
--******************************
goxa: IF (xoutput = 1) GENERATE
goxb: FOR k IN 1 TO mantissa GENERATE
ccxman(k) <= NOT(aaff(k+10));
END GENERATE;
ccxexp(10 DOWNTO 1) <= aaff(10 DOWNTO 1);
cc <= ccxman & ccxexp;
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
--***************************************
--*** internal function format output ***
--***************************************
gofa: IF (funcoutput = 1) GENERATE
ccfuncman(mantissa) <= NOT(aaff(mantissa+10));
ccfuncman(mantissa-1 DOWNTO 1) <= aaff(mantissa+9 DOWNTO 11);
ccfuncexp(10 DOWNTO 1) <= aaff(10 DOWNTO 1);
cc <= ccfuncman & ccfuncexp;
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
--**************************
--*** IEEE format output ***
--**************************
goia: IF (ieeeoutput = 1) GENERATE
expnode <= aaff(10 DOWNTO 1);
pio: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 23 LOOP
manoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 23 LOOP
manoutff(k) <= aaff(k+mantissa-15) AND NOT(manoutzero);
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= (expnode(k) AND NOT(expoutzero)) OR expoutmax;
END LOOP;
END IF;
END PROCESS;
expmax <= expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
expzero <= NOT(expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
manoutzero <= aasatff OR aazipff OR expmax OR expzero OR expnode(10) OR expnode(9);
expoutzero <= aazipff OR expzero OR expnode(10);
expoutmax <= aasatff OR expmax OR (NOT(expnode(10)) AND expnode(9));
-- OUTPUTS
cc <= NOT(aaff(mantissa+10)) & expoutff & manoutff;
ccsat <= '0';
cczip <= '0';
END GENERATE;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_mul3s.vhd | 10 | 5539 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL3S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 18-36 bit inputs, 3 pipes ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul3s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul3s;
ARCHITECTURE SYN OF fp_mul3s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
end component;
BEGIN
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/dp_sqr.vhd | 10 | 8540 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION SQUARE ROOT - TOP LEVEL ***
--*** ***
--*** DP_SQR.VHD ***
--*** ***
--*** Function: IEEE754 DP Square Root ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 57 ***
--*** Based on FPROOT1.VHD (12/06) ***
--***************************************************
ENTITY dp_sqr IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END dp_sqr;
ARCHITECTURE rtl OF dp_sqr IS
constant manwidth : positive := 52;
constant expwidth : positive := 11;
type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1);
signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal roundbit : STD_LOGIC;
signal preadjust : STD_LOGIC;
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinitycondition, nancondition : STD_LOGIC;
component fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+4 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
roundff(k) <= '0';
manff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signinff <= signin;
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO manwidth+4 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= expdiv;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset;
FOR k IN 3 TO manwidth+3 LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3);
END LOOP;
roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth+4 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO manwidth+3 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
nanmanff(1) <= nancondition; -- level 1
nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity
FOR k IN 2 TO manwidth+4 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1
zeroexpff(1) <= expzero; -- level 1
FOR k IN 2 TO manwidth+3 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
-- if exponent is odd, double mantissa and adjust exponent
-- core latency manwidth+2 = 54
-- top latency = core + 1 (input) + 2 (output) = 57
sqr: fp_sqrroot
GENERIC MAP (width=>manwidth+2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
rad=>radicand,
root=>squareroot);
radicand(1) <= '0';
radicand(2) <= maninff(1) AND NOT(preadjust);
gra: FOR k IN 3 TO manwidth+1 GENERATE
radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust);
END GENERATE;
radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust);
radicand(manwidth+3) <= preadjust;
--****************
--*** EXPONENT ***
--****************
-- subtract 1023, divide result/2, if odd - preadjust
-- if zero input, zero exponent and mantissa
expnode <= expinff - offset;
preadjust <= expnode(1);
expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2);
--*************
--*** ROUND ***
--*************
-- only need to round up, round to nearest not possible out of root
roundbit <= squareroot(1);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN (unless -0)
-- 2. -0 in -0 out
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '0' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= expinzero(expwidth); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if not zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= maninzero(manwidth);
infinitycondition <= NOT(manzero) AND expmax;
nancondition <= (signinff AND expzero) OR (expmax AND manzero);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(manwidth+4);
exponentout <= expff(manwidth+4)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(manwidth+4);
invalidout <= nanmanff(manwidth+4);
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_rsft32x5.vhd | 10 | 4329 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT32X5.VHD ***
--*** ***
--*** Function: Single Precision Right Shift ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft32x5 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END fp_rsft32x5;
ARCHITECTURE rtl OF fp_rsft32x5 IS
signal rightone, righttwo, rightthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gra: FOR k IN 1 TO 29 GENERATE
rightone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k+1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k+2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k+3) AND shift(2) AND shift(1));
END GENERATE;
rightone(30) <= (inbus(30) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(31) AND NOT(shift(2)) AND shift(1)) OR
(inbus(32) AND shift(2) AND NOT(shift(1)));
rightone(31) <= (inbus(31) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(32) AND NOT(shift(2)) AND shift(1));
rightone(32) <= inbus(32) AND NOT(shift(2)) AND NOT(shift(1));
grb: FOR k IN 1 TO 20 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3))) OR
(rightone(k+12) AND shift(4) AND shift(3));
END GENERATE;
grc: FOR k IN 21 TO 24 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
grd: FOR k IN 25 TO 28 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gre: FOR k IN 29 TO 32 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
grf: FOR k IN 1 TO 16 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5))) OR
(righttwo(k+16) AND shift(5));
END GENERATE;
grg: FOR k IN 17 TO 32 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5)));
END GENERATE;
outbus <= rightthr;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/fp_rsft32x5.vhd | 10 | 4329 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT32X5.VHD ***
--*** ***
--*** Function: Single Precision Right Shift ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft32x5 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END fp_rsft32x5;
ARCHITECTURE rtl OF fp_rsft32x5 IS
signal rightone, righttwo, rightthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
gra: FOR k IN 1 TO 29 GENERATE
rightone(k) <= (inbus(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(k+1) AND NOT(shift(2)) AND shift(1)) OR
(inbus(k+2) AND shift(2) AND NOT(shift(1))) OR
(inbus(k+3) AND shift(2) AND shift(1));
END GENERATE;
rightone(30) <= (inbus(30) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(31) AND NOT(shift(2)) AND shift(1)) OR
(inbus(32) AND shift(2) AND NOT(shift(1)));
rightone(31) <= (inbus(31) AND NOT(shift(2)) AND NOT(shift(1))) OR
(inbus(32) AND NOT(shift(2)) AND shift(1));
rightone(32) <= inbus(32) AND NOT(shift(2)) AND NOT(shift(1));
grb: FOR k IN 1 TO 20 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3))) OR
(rightone(k+12) AND shift(4) AND shift(3));
END GENERATE;
grc: FOR k IN 21 TO 24 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(rightone(k+8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
grd: FOR k IN 25 TO 28 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(rightone(k+4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gre: FOR k IN 29 TO 32 GENERATE
righttwo(k) <= (rightone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
grf: FOR k IN 1 TO 16 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5))) OR
(righttwo(k+16) AND shift(5));
END GENERATE;
grg: FOR k IN 17 TO 32 GENERATE
rightthr(k) <= (righttwo(k) AND NOT(shift(5)));
END GENERATE;
outbus <= rightthr;
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/hcc_normfp2x.vhd | 10 | 13893 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize double precision ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 05/03/08 - correct expbotffdepth constant ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES : TODOS ***
--***************************************************
--*** NEED OVERFLOW CHECK - if 01.11111XXX11111 rounds up to 10.000..0000
ENTITY hcc_normfp2x IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_normfp2x;
ARCHITECTURE rtl OF hcc_normfp2x IS
constant latency : positive := 3 + normspeed +
(roundconvert*doublespeed) +
(roundnormalize + roundnormalize*doublespeed);
constant exptopffdepth : positive := 2 + roundconvert*doublespeed;
constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08
-- if internal format, need to turn back to signed at this point
constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC_VECTOR (latency DOWNTO 1);
signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1);
signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1);
signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1);
signal sign : STD_LOGIC;
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1); -- currently 1 or 3
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** INPUT REGISTER ***
pna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO latency LOOP
aasatff(k) <= '0';
aazipff(k) <= '0';
END LOOP;
FOR k IN 1 TO latency-1 LOOP
mulsignff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp;
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
aasatff(1) <= aasat;
aazipff(1) <= aazip;
FOR k IN 2 TO latency LOOP
aasatff(k) <= aasatff(k-1);
aazipff(k) <= aazipff(k-1);
END LOOP;
mulsignff(1) <= aaff(77);
FOR k IN 2 TO latency-1 LOOP
mulsignff(k) <= mulsignff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- exponent bottom half
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
-- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets
adjustexp <= "0000000000100";
gna: FOR k IN 1 TO 64 GENERATE
aainvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
aaabsnode <= aainvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aaabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaabsff <= aaabsnode;
END IF;
END IF;
END PROCESS;
aaabs <= aaabsff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aainvnode,bb=>zerovec,carryin=>aaff(77),
cc=>aaabs);
END GENERATE;
END GENERATE;
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe)
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>aaabs,
countout=>countnorm,fracout=>normalaa);
gta: IF (target = 0) GENERATE
pnc: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normalaaff <= normalaa(64 DOWNTO 10);
END IF;
END IF;
END PROCESS;
--*** ROUND NORMALIZED VALUE (IF REQUIRED)***
--*** note: normal output is 64 bits
gne: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff(55 DOWNTO 2);
END GENERATE;
gnf: IF (roundnormalize = 1) GENERATE
gng: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1));
pnd: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnh: IF (doublespeed = 1) GENERATE
gra: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
grb: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
sign <= mulsignff(latency-1);
cc <= sign & mantissa(53 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
gtb: IF (target = 1) GENERATE
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
normalaaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO 59 LOOP
normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint);
END LOOP;
normalaaff(60) <= mulsignff(invertpoint);
normalaaff(61) <= mulsignff(invertpoint);
normalaaff(62) <= mulsignff(invertpoint);
normalaaff(63) <= mulsignff(invertpoint);
normalaaff(64) <= mulsignff(invertpoint);
END IF;
END IF;
END PROCESS;
gni: IF (roundnormalize = 0) GENERATE
mantissa <= normalaaff; -- 1's complement
END GENERATE;
gnj: IF (roundnormalize = 1) GENERATE
gnk: IF (doublespeed = 0) GENERATE
aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1));
pne: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
aamanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aamannode;
END IF;
END IF;
END PROCESS;
mantissa <= aamanff;
END GENERATE;
gnl: IF (doublespeed = 1) GENERATE
grc: IF (synthesize = 0) GENERATE
rndone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
grd: IF (synthesize = 1) GENERATE
rndtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1),
cc=>mantissa);
END GENERATE;
END GENERATE;
END GENERATE;
cc <= mantissa(64 DOWNTO 1) & exponent;
ccsat <= aasatff(latency);
cczip <= aazipff(latency);
END GENERATE;
end rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/hcc_castdtox.vhd | 10 | 4863 |
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castdtox IS
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castdtox;
ARCHITECTURE rtl OF hcc_castdtox IS
signal ccprenode : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal ccnode : STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytox IS
GENERIC (
target : integer := 0; -- 1 (signed 64 bit), 0 (unsigned "S1"+52bit)
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
-- if x target is internal (0), output of dtoy is internal (1)
-- if x target is multiplier(1), output of dtoy is internal (1)
-- if x target is divider(2), output of dtoy is divider (0)
-- if x target is internal (0), output of dtoy is internal (1)
gda: IF (target = 0) GENERATE
castinone: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
-- if x target is multiplier(1), output of dtoy is internal (1)
-- leftshift y (SSSSS1XXX) to signed multiplier format (S1XXX)
gdb: IF (target = 1) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccprenode,ccsat=>satnode,cczip=>zipnode);
ccnode <= ccprenode(73 DOWNTO 5) & "0000";
END GENERATE;
gdc: IF (target = 2) GENERATE
castintwo: hcc_castdtoy
GENERIC MAP (target=>0,roundconvert=>roundconvert,doublespeed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>ccnode,ccsat=>satnode,cczip=>zipnode);
END GENERATE;
castout: hcc_castytox
GENERIC MAP (target=>target,roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>ccnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip);
END rtl;
| mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/fp_mul2s.vhd | 10 | 5503 |
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL2S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 18-36 bit inputs, 2 pipes ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul2s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul2s;
ARCHITECTURE SYN OF fp_mul2s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
| mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/dec_shifter.vhd | 1 | 9221 | `protect begin_protected
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5088)
`protect data_block
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`protect end_protected
| mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cic_compiler_v4_0/hdl/delay_bit.vhd | 1 | 9480 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5280)
`protect data_block
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| mit |
spzSource/MPFSM.RegFile.Sort | MPFSM_RegFile_Sort/MPFSM_RegFile_Sort_Design/src/Controller.vhd | 1 | 8076 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use commands.all;
--
-- Holds interaction among ROM, RAM and datapath.
--
entity Controller is
port(
clk : in std_logic;
rst : in std_logic;
start : in std_logic;
stop : out std_logic;
rom_enabled : out std_logic;
rom_address : out std_logic_vector(7 downto 0);
rom_data_output : in std_logic_vector(27 downto 0);
ram_read_write : out std_logic;
ram_write_data_port : out std_logic_vector(7 downto 0);
ram_write_address : out std_logic_vector(7 downto 0);
ram_read_data_port_1 : in std_logic_vector(7 downto 0);
ram_read_data_port_2 : in std_logic_vector(7 downto 0);
ram_read_address_1 : out std_logic_vector(7 downto 0);
ram_read_address_2 : out std_logic_vector(7 downto 0);
datapath_enabled : out std_logic;
datapath_operation_code : out std_logic_vector(3 downto 0);
datapath_operand_1 : out std_logic_vector(7 downto 0);
datapath_operand_2 : out std_logic_vector(7 downto 0);
datapath_result : in std_logic_vector(7 downto 0);
datapath_zero_flag : in std_logic;
datapath_significant_bit_flag : in std_logic
);
end entity Controller;
architecture Controller_Behavioural of Controller is
type states is (
IDLE,
FETCH,
DECODE,
READ,
WRITE,
ADD,
SUB,
HALT,
JUMP_IF_ZERO,
JUMP_IF_NOT_SIGN_BIT_SET,
LOAD_FROM_INDEX_TO,
LOAD_FROM_INDEX_TO_READ_ADDR,
LOAD_ACCEPT_WRITE,
LOAD_TO_INDEX_FROM,
LOAD_TO_INDEX_FROM_READ_ADDR
);
signal next_state : states;
signal current_state : states;
signal instruction : std_logic_vector(27 downto 0);
signal instruction_counter : std_logic_vector(7 downto 0);
signal operation : std_logic_vector(3 downto 0);
signal operand_address_1 : std_logic_vector(7 downto 0);
signal operand_address_2 : std_logic_vector(7 downto 0);
signal result_address : std_logic_vector(7 downto 0);
signal data_1 : std_logic_vector(7 downto 0);
signal data_2 : std_logic_vector(7 downto 0);
signal data_w : std_logic_vector(7 downto 0);
constant DEFAULT_COUNTER_VALUE : std_logic_vector(7 downto 0) := (instruction_counter'range => '0');
constant DEFAULT_INSTRUCTION_VALUE : std_logic_vector(27 downto 0) := (instruction'range => '0');
constant DEFAULT_OPERATION_VALUE : std_logic_vector(3 downto 0) := (operation'range => '0');
constant DEFAULT_ADDRESS_VALUE : std_logic_vector(7 downto 0) := (operand_address_1'range => '0');
begin
FSM : process(clk, rst, next_state)
begin
if (rst = '1') then
current_state <= IDLE;
elsif rising_edge(clk) then
current_state <= next_state;
end if;
end process;
FSM_COMB : process(current_state, start, operation)
begin
case current_state is
when IDLE =>
if (start = '1') then
next_state <= FETCH;
else
next_state <= IDLE;
end if;
when FETCH => next_state <= DECODE;
when DECODE =>
if (operation = HALT_OP) then
next_state <= HALT;
elsif (operation = JZ_OP) then
next_state <= JUMP_IF_ZERO;
elsif (operation = JNSB_OP) then
next_state <= JUMP_IF_NOT_SIGN_BIT_SET;
else
next_state <= READ;
end if;
when READ =>
if (operation = ADD_OP) then
next_state <= ADD;
elsif (operation = SUB_OP) then
next_state <= SUB;
elsif (operation = LOAD_FROM_INEDEX_TO_ADDR_OP) then
next_state <= LOAD_FROM_INDEX_TO;
elsif (operation = LOAD_FROM_ADDR_TO_INDEX_OP) then
next_state <= LOAD_TO_INDEX_FROM;
else
next_state <= IDLE;
end if;
when LOAD_FROM_INDEX_TO =>
next_state <= LOAD_FROM_INDEX_TO_READ_ADDR;
when LOAD_TO_INDEX_FROM =>
next_state <= LOAD_TO_INDEX_FROM_READ_ADDR;
when LOAD_FROM_INDEX_TO_READ_ADDR | LOAD_TO_INDEX_FROM_READ_ADDR =>
next_state <= LOAD_ACCEPT_WRITE;
when ADD | SUB | LOAD_ACCEPT_WRITE =>
next_state <= WRITE;
when WRITE | JUMP_IF_ZERO | JUMP_IF_NOT_SIGN_BIT_SET =>
next_state <= FETCH;
when HALT =>
next_state <= HALT;
when others =>
next_state <= IDLE;
end case;
end process;
--
-- multiplexer to handle stop signal;
--
STOP_PROCESS : process(current_state)
begin
if (current_state = HALT) then
stop <= '1';
else
stop <= '0';
end if;
end process;
--
-- synchronous instruction counter
--
INSTR_COUNTER : process(clk, rst, current_state)
begin
if (rst = '1') then
instruction_counter <= DEFAULT_COUNTER_VALUE;
elsif falling_edge(clk) then
if (current_state = DECODE) then
instruction_counter <= instruction_counter + 1;
elsif (current_state = JUMP_IF_ZERO and datapath_zero_flag = '1') then
instruction_counter <= operand_address_1;
elsif (current_state = JUMP_IF_NOT_SIGN_BIT_SET and datapath_significant_bit_flag = '0') then
instruction_counter <= operand_address_1;
end if;
end if;
end process;
rom_address <= instruction_counter;
ROM_READ_SET : process(next_state, current_state)
begin
if (next_state = FETCH or current_state = FETCH) then
rom_enabled <= '1';
else
rom_enabled <= '0';
end if;
end process;
--
-- reads instructions from the ROM
--
ROM_READ : process(rst, current_state, rom_data_output)
begin
if (rst = '1') then
instruction <= DEFAULT_INSTRUCTION_VALUE;
elsif (current_state = FETCH) then
instruction <= rom_data_output;
end if;
end process;
--
-- determines the states of registers (address and instruction),
-- based on current state of FSM
--
REGS_CONTROL : process(rst, next_state, instruction)
begin
if (rst = '1') then
operation <= DEFAULT_OPERATION_VALUE;
operand_address_1 <= DEFAULT_ADDRESS_VALUE;
operand_address_2 <= DEFAULT_ADDRESS_VALUE;
result_address <= DEFAULT_ADDRESS_VALUE;
elsif (next_state = DECODE) then
operation <= instruction(27 downto 24);
operand_address_1 <= instruction(23 downto 16);
operand_address_2 <= instruction(15 downto 8);
result_address <= instruction(7 downto 0);
elsif (next_state = LOAD_FROM_INDEX_TO) then
operand_address_1 <= data_1;
elsif (next_state = LOAD_TO_INDEX_FROM) then
operand_address_2 <= data_2;
elsif (next_state = LOAD_TO_INDEX_FROM_READ_ADDR) then
result_address <= operand_address_2;
end if;
end process;
RAM_ADDR_SET : process(operand_address_1, operand_address_2, result_address)
begin
if (current_state /= JUMP_IF_NOT_SIGN_BIT_SET and current_state /= JUMP_IF_ZERO) then
ram_read_address_1 <= operand_address_1;
ram_read_address_2 <= operand_address_2;
ram_write_address <= result_address;
end if;
end process;
RAM_MODE_SET : process(current_state)
begin
if (current_state = WRITE) then
ram_read_write <= '0';
else
ram_read_write <= '1';
end if;
end process;
RAM_DATA_OUT : process(current_state)
begin
if (current_state = READ) then
data_1 <= ram_read_data_port_1;
data_2 <= ram_read_data_port_2;
elsif (current_state = LOAD_FROM_INDEX_TO_READ_ADDR) then
data_1 <= ram_read_data_port_1;
end if;
end process;
ram_write_data_port <= datapath_result;
datapath_operand_1 <= data_1;
datapath_operand_2 <= data_2;
datapath_operation_code <= operation;
DATAPATH_SET : process(current_state)
begin
if (current_state = ADD or current_state = SUB or current_state = LOAD_ACCEPT_WRITE) then
datapath_enabled <= '1';
else
datapath_enabled <= '0';
end if;
end process;
end architecture Controller_Behavioural;
| mit |
NicoLedwith/Dr.AluOpysel | RAT_MCU/vga_clk_div.vhd | 1 | 805 | --
-- Declares a clock divider to synchronize the VGA scanlines
--
-- Original author: unknown
--
-- Peter Heatwole, Aaron Barton
-- CPE233, Winter 2012, CalPoly
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_clk_div is
port(clk : in std_logic;
clkout : out std_logic);
end vga_clk_div;
architecture Behavioral of vga_clk_div is
signal tmp_clkf : std_logic;
begin
my_div_fast: process (clk,tmp_clkf)
variable div_cnt : integer := 0;
begin
if (rising_edge(clk)) then
if (div_cnt = 1) then
tmp_clkf <= not tmp_clkf;
div_cnt := 0;
else
div_cnt := div_cnt + 1;
end if;
end if;
clkout <= tmp_clkf;
end process my_div_fast;
end Behavioral;
| mit |
NicoLedwith/Dr.AluOpysel | RAT_MCU/Wrapper.vhd | 1 | 5606 | -------------------------------------------------------------------------------
-- Company: RAT Technologies
-- Engineer: Various RAT rats
--
-- Create Date: 1/31/2012
-- Design Name:
-- Module Name: RAT_wrapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Wrapper for RAT MCU. This model provides a template to
-- interface the RAT MCU to the Nexys2 development board.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RAT_wrapper is
Port ( LEDS : out STD_LOGIC_VECTOR (7 downto 0);
SEGMENTS : out STD_LOGIC_VECTOR (7 downto 0);
DISP_EN : out STD_LOGIC_VECTOR (3 downto 0);
SWITCHES : in STD_LOGIC_VECTOR (7 downto 0);
BUTTONS : in STD_LOGIC_VECTOR (3 downto 0);
RESET : in STD_LOGIC;
CLK : in STD_LOGIC);
end RAT_wrapper;
architecture Behavioral of RAT_wrapper is
-------------------------------------------------------------------------------
-- INPUT PORT IDS -------------------------------------------------------------
CONSTANT SWITCHES_ID : STD_LOGIC_VECTOR (7 downto 0) := X"20";
CONSTANT BUTTONS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"24";
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- OUTPUT PORT IDS ------------------------------------------------------------
CONSTANT LEDS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"40";
CONSTANT SEGMENTS_ID : STD_LOGIC_VECTOR (7 downto 0) := X"82";
CONSTANT DISP_EN_ID : STD_LOGIC_VECTOR (7 downto 0) := X"83";
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Declare RAT_MCU ------------------------------------------------------------
component RAT_MCU
Port ( IN_PORT : in STD_LOGIC_VECTOR (7 downto 0);
OUT_PORT : out STD_LOGIC_VECTOR (7 downto 0);
PORT_ID : out STD_LOGIC_VECTOR (7 downto 0);
IO_STRB : out STD_LOGIC;
RESET : in STD_LOGIC;
INT : in STD_LOGIC;
CLK : in STD_LOGIC);
end component RAT_MCU;
-------------------------------------------------------------------------------
-- Signals for connecting RAT_MCU to RAT_wrapper -------------------------------
signal s_input_port : std_logic_vector (7 downto 0);
signal s_output_port : std_logic_vector (7 downto 0);
signal s_port_id : std_logic_vector (7 downto 0);
signal s_load : std_logic;
--signal s_interrupt : std_logic; -- not yet used
-- Register definitions for output devices ------------------------------------
signal r_LEDS : std_logic_vector (7 downto 0) := (others => '0');
signal r_SEGMENTS : std_logic_vector (7 downto 0) := (others => '0');
signal r_DISP_EN : std_logic_vector (3 downto 0) := (others => '0');
-------------------------------------------------------------------------------
begin
-- Instantiate RAT_MCU --------------------------------------------------------
MCU: RAT_MCU
port map( IN_PORT => s_input_port,
OUT_PORT => s_output_port,
PORT_ID => s_port_id,
RESET => RESET,
IO_STRB => s_load,
INT => BUTTONS(3),
CLK => CLK);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- MUX for selecting what input to read
-------------------------------------------------------------------------------
inputs: process(s_port_id, SWITCHES, BUTTONS)
begin
if (s_port_id = SWITCHES_ID) then
s_input_port <= SWITCHES;
elsif (s_port_id = BUTTONS_ID) then
s_input_port <= "00000" & BUTTONS(2 downto 0);
else
s_input_port <= x"00";
end if;
end process inputs;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Decoder for updating output registers
-- Register updates depend on rising clock edge and asserted load signal
-------------------------------------------------------------------------------
outputs: process(CLK, s_load, s_port_id)
begin
if (rising_edge(CLK)) then
if (s_load = '1') then
if (s_port_id = LEDS_ID) then
r_LEDS <= s_output_port;
elsif (s_port_id = SEGMENTS_ID) then
r_SEGMENTS <= s_output_port;
elsif (s_port_id = DISP_EN_ID) then
r_DISP_EN <= s_output_port(3 downto 0);
end if;
end if;
end if;
end process outputs;
-------------------------------------------------------------------------------
-- Register Interface Assignments ---------------------------------------------
LEDS <= r_LEDS;
SEGMENTS <= r_SEGMENTS;
DISP_EN <= r_DISP_EN;
-------------------------------------------------------------------------------
end Behavioral;
| mit |
zurkiyeh/zurkiyeh.github.io | simulation/qsim/work/controller_vlg_sample_tst/_primary.vhd | 1 | 656 | library verilog;
use verilog.vl_types.all;
entity controller_vlg_sample_tst is
port(
clk : in vl_logic;
coin_Detected : in vl_logic;
comp_equal_in : in vl_logic;
comp_greater_in : in vl_logic;
comp_smaller_in : in vl_logic;
reset : in vl_logic;
soda_choice : in vl_logic;
soda_price_0 : in vl_logic_vector(7 downto 0);
soda_price_1 : in vl_logic_vector(7 downto 0);
value_cents : in vl_logic_vector(7 downto 0);
sampler_tx : out vl_logic
);
end controller_vlg_sample_tst;
| mit |
kjellhar/axi_mmc | src/vhdl/mmc_crc7.vhd | 1 | 1758 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/01/2014 10:27:20 AM
-- Design Name:
-- Module Name: mmc_crc7 - rtl
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mmc_crc7 is
Port ( clk : in std_logic;
clk_en : in std_logic;
reset : in std_logic;
enable : in std_logic;
serial_in : in std_logic;
crc7_out : out std_logic_vector (6 downto 0)
);
end mmc_crc7;
architecture rtl of mmc_crc7 is
signal crc_reg : std_logic_vector (6 downto 0) := (others => '0');
begin
crc7_out <= crc_reg;
process
begin
wait until rising_edge(clk);
if reset='1' then
crc_reg <= (others => '0');
elsif enable='1' and clk_en='1' then
crc_reg(0) <= crc_reg(6) xor serial_in;
crc_reg(1) <= crc_reg(0);
crc_reg(2) <= crc_reg(1);
crc_reg(3) <= crc_reg(2) xor crc_reg(6) xor serial_in;
crc_reg(4) <= crc_reg(3);
crc_reg(5) <= crc_reg(4);
crc_reg(6) <= crc_reg(5);
end if;
end process;
end rtl;
| mit |
spzSource/MPFSM.RegFile.Sort | MPFSM_RegFile_Sort/MPFSM_RegFile_Sort_Design/src/Datapath.vhd | 1 | 2286 | library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use commands.all;
entity Datapath is
port(
enabled : in std_logic;
operation_code : in std_logic_vector(3 downto 0);
operand_1 : in std_logic_vector(7 downto 0);
operand_2 : in std_logic_vector(7 downto 0);
result : out std_logic_vector(7 downto 0);
zero_flag : out std_logic;
significant_bit_flag : out std_logic
);
end entity Datapath;
architecture Datapath_Behavioural of Datapath is
signal op_result : std_logic_vector(7 downto 0);
signal add_result : std_logic_vector(7 downto 0);
signal sub_result : std_logic_vector(7 downto 0);
signal mov_result : std_logic_vector(7 downto 0);
signal result_zero_flag : std_logic;
signal result_significant_bit_flag : std_logic;
begin
--
-- represents 8-bit adder
--
add_result <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(operand_1) + CONV_INTEGER(operand_2), 8);
--
-- represents 8-bit subtraction
--
sub_result <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(operand_1) - CONV_INTEGER(operand_2), 8);
mov_result <= operand_1;
--
-- synchronous register-accumulator
--
ALU_REG : process(enabled, operation_code, operand_1, operand_2, add_result, sub_result, mov_result)
begin
if (rising_edge(enabled)) then
case operation_code is
when ADD_OP => op_result <= add_result;
when SUB_OP => op_result <= sub_result;
when LOAD_FROM_INEDEX_TO_ADDR_OP | LOAD_FROM_ADDR_TO_INDEX_OP => op_result <= mov_result;
when others => null;
end case;
end if;
end process;
FLAGS_PROCESS : process(op_result)
begin
if op_result = (op_result'range => '0') then
result_zero_flag <= '1';
else
result_zero_flag <= '0';
end if;
if op_result(7) = '1' then
result_significant_bit_flag <= '1';
else
result_significant_bit_flag <= '0';
end if;
end process;
result <= op_result;
zero_flag <= result_zero_flag;
significant_bit_flag <= result_significant_bit_flag;
end architecture Datapath_Behavioural;
| mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/half_band_FIR/fir_compiler_v7_1/hdl/halfband_decimation.vhd | 2 | 339334 | `protect begin_protected
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`protect end_protected
| mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/fir_compiler_v7_1/hdl/fir_compiler_v7_1_viv_comp.vhd | 2 | 13565 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
| mit |
NicoLedwith/Dr.AluOpysel | RAT_MCU/Scratch_ram.vhd | 1 | 1202 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity SCR is
Port ( DATA : inout STD_LOGIC_VECTOR (9 downto 0);
ADDR : in STD_LOGIC_VECTOR (7 downto 0);
OE : in STD_LOGIC;
WE : in STD_LOGIC;
CLK : in STD_LOGIC);
end SCR;
architecture SCR of SCR is
TYPE memory is array (0 to 255) of std_logic_vector(9 downto 0);
-----------------------------------------------------------(1)
SIGNAL BD_RAM : memory := (others => (others =>'0') );
begin
my_bi_dir: process(CLK,OE,WE,DATA,ADDR,BD_RAM)
begin
--------------------------------------------------------(2)
if (OE = '1') then
DATA <= BD_RAM(conv_integer(ADDR));
--------------------------------------------------------(3)
else
-----------------------------------------------------(4)
DATA <= (others => 'Z');
-----------------------------------------------------(5)
if (WE = '1') then
if (rising_edge(CLK)) then
BD_RAM(conv_integer(ADDR)) <= DATA;
end if;
end if;
end if;
end process my_bi_dir;
end SCR;
| mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/lp_FIR/axi_utils_v2_0/hdl/axi_utils_v2_0_pkg.vhd | 3 | 8183 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4320)
`protect data_block
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`protect end_protected
| mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/half_band_FIR/fir_compiler_v7_1/hdl/cnfg_and_reload.vhd | 2 | 111911 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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dW+CK7XLAo6WR9FSTFQGQNZydvVSSvtV19jSMXcIP3i/xOxshD0wRkkDVZX1FfrnUc4=
`protect end_protected
| mit |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl | 1 | 1224 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
-- Date : Tue Sep 16 21:34:47 2014
-- Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
-- Design : clk_wiz_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_wiz_0 is
Port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC
);
end clk_wiz_0;
architecture stub of clk_wiz_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_in1,clk_out1,reset,locked";
begin
end;
| mit |
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