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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/common/input_blk.vhd | 19 | 28006 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18992)
`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/builtin/builtin_top.vhd | 19 | 47568 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_auto_pc_3/blk_mem_gen_v8_1/blk_mem_gen_v8_1.vhd | 27 | 19382 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12608)
`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/blk_mem_gen_v8_1/blk_mem_gen_v8_1.vhd | 27 | 19382 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_block
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| mit |
djmatt/VHDL-Lib | VHDL/FIR_Filter/sparse_fir_filter.vhd | 1 | 4158 | --------------------------------------------------------------------------------------------------
-- Sparse FIR Filter
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package sparse_fir_filter_pkg is
--FIR filter component declaration
component sparse_fir_filter is
generic( h : coefficient_array);
port( clk : in std_logic;
rst : in std_logic;
x : in sig;
y : out fir_sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
use work.sparse_fir_tap_pkg.all;
use work.fir_tap_pkg.all;
entity sparse_fir_filter is
generic( h : coefficient_array);
port( clk : in std_logic;
rst : in std_logic;
x : in sig;
y : out fir_sig);
end sparse_fir_filter;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of sparse_fir_filter is
signal x_chain : sig_array(h'range) := (others => (others => '0'));
signal running_sum : fir_sig_array(h'range) := (others => (others => '0'));
begin
filter_loop : for tap in h'low to h'high generate
begin
if_sparse_tap_gen : if h(tap) = ZERO_COEF generate
sparse_head_tap_gen : if tap = h'low generate
sparse_head_tap : sparse_fir_tap
port map(clk => clk,
rst => rst,
sig_in => x,
sig_out => x_chain(tap),
sum_in => (others => '0'),
sum_out => running_sum(tap));
end generate; --if head tap
sparse_tail_taps_gen : if tap /= h'low generate
sparse_tail_tap : sparse_fir_tap
port map(clk => clk,
rst => rst,
sig_in => x_chain(tap-1),
sig_out => x_chain(tap),
sum_in => running_sum(tap-1),
sum_out => running_sum(tap));
end generate; --if tail taps
end generate;
if_normal_tap_gen : if h(tap) /= ZERO_COEF generate
head_tap_gen : if tap = h'low generate
head_tap : fir_tap
port map(clk => clk,
rst => rst,
coef => h(tap),
sig_in => x,
sig_out => x_chain(tap),
sum_in => (others => '0'),
sum_out => running_sum(tap));
end generate; --if head tap
tail_taps_gen : if tap /= h'low generate
tail_tap : fir_tap
port map(clk => clk,
rst => rst,
coef => h(tap),
sig_in => x_chain(tap-1),
sig_out => x_chain(tap),
sum_in => running_sum(tap-1),
sum_out => running_sum(tap));
end generate; --if tail taps
end generate;
end generate;
--output end of the running sum
y <= running_sum(h'high);
end behave;
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/common/wr_pf_as.vhd | 19 | 27402 | `protect begin_protected
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_xbar_1/fifo_generator_v11_0/common/wr_pf_as.vhd | 19 | 27402 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18544)
`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/blk_mem_gen_v8_1/blk_mem_gen_v8_1_synth.vhd | 27 | 68532 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 48992)
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/ramfifo/rd_dc_fwft_ext_as.vhd | 19 | 12811 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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T1kWm6bsuw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7744)
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_xbar_1/fifo_generator_v11_0/ramfifo/rd_dc_fwft_ext_as.vhd | 19 | 12811 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7744)
`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/builtin/bin_cntr.vhd | 19 | 8597 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4624)
`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_xbar_1/fifo_generator_v11_0/builtin/bin_cntr.vhd | 19 | 8597 | `protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_auto_pc_3/fifo_generator_v11_0/builtin/bin_cntr.vhd | 19 | 8597 | `protect begin_protected
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`protect encrypt_agent = "XILINX"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4624)
`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/fifo_generator_top.vhd | 19 | 34705 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23952)
`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/ramfifo/async_fifo.vhd | 19 | 33343 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22944)
`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/builtin/builtin_extdepth_v6.vhd | 19 | 50137 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 35376)
`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/ramfifo/compare.vhd | 19 | 11879 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/ld_arith_reg2.vhd | 15 | 17134 | -------------------------------------------------------------------------------
-- $Id: ld_arith_reg2.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg2.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-- ld_arith_reg2 is derived from ld_arith_reg. There are a few
-- changes:
-- - The control signal for load is active-low, LOAD_n.
-- - Boolean generic C_LOAD_OVERRIDES reverses the default that
-- OP overrides LOAD_n when both are asserted on the
-- same cycle.
-- - The default width is 32.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg2.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 09/01/03 -- First version, derived from ld_arith_reg
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg2 is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 32;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0;
------------------------------------------------------------------------
C_LOAD_OVERRIDES : boolean := false
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD_n)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD_n : in std_logic; -- Active-low enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD_n
-- unless C_LOAD_OVERRIDES = true)
);
end ld_arith_reg2;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg2 is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg2, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <=
'0' when C_ADD_SUB_NOT else
LOAD_n when not C_ADD_SUB_NOT and C_LOAD_OVERRIDES else
OP; -- when not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Adder case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_ADD_OO: if C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Adder case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_ADD_LO: if C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xor arith_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, OP overrides LOAD_n
------------------------------------------------------------------------
Q_I_GEN_SUB_OO: if not C_ADD_SUB_NOT and not C_LOAD_OVERRIDES generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case, LOAD_n overrides OP
------------------------------------------------------------------------
Q_I_GEN_SUB_LO: if not C_ADD_SUB_NOT and C_LOAD_OVERRIDES generate
q_i_ns(j) <= load_bit when LOAD_n = '0' else q_i(j) xnor arith_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_OO_GEN : if not C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
end generate;
MULT_AND_LO_GEN : if C_LOAD_OVERRIDES generate
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => LOAD_n,
I0 => Q_i(j)
);
end generate;
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= not LOAD_n or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
| mit |
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| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/counter.vhd | 15 | 9030 | -------------------------------------------------------------------------------
-- Counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter.vhd
--
-- Description: Implements a parameterizable N-bit counter
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- 1 - LUT per bit plus 3 LUTS for extra features
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter.vhd
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- KC 2002-01-23 First Version
-- LCW 2004-10-08 Updated for NCSim
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity Counter is
generic(
C_NUM_BITS : Integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity Counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of Counter is
signal alu_cy : std_logic_vector(C_NUM_BITS downto 0);
signal iCount_Out : std_logic_vector(C_NUM_BITS - 1 downto 0);
signal count_clock_en : std_logic;
signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(0) <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
count_clock_en <= Count_Enable or Count_Load;
I_ADDSUB_GEN : for I in 0 to (C_NUM_BITS - 1) generate
begin
Counter_Bit_I : entity proc_common_v4_0.counter_bit
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Count_In => iCount_Out(i), -- [in]
Load_In => Load_In(i), -- [in]
Count_Load => Count_Load, -- [in]
Count_Down => Count_Down, -- [in]
Carry_In => alu_cy(I), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iCount_Out(I), -- [out]
Carry_Out => alu_cy(I+1) -- [out]
);
end generate I_ADDSUB_GEN;
carry_active_high <= alu_cy(C_NUM_BITS) xor Count_Down;
CARRY_OUT_I: FDRE
port map (
Q => Carry_Out, -- [out]
C => Clk, -- [in]
CE => count_clock_en, -- [in]
D => carry_active_high, -- [in]
R => Rst -- [in]
);
Count_Out <= iCount_Out;
end architecture imp;
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/muxf_struct_f.vhd | 15 | 15871 | -------------------------------------------------------------------------------
-- $Id: muxf_struct_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: muxf_struct_f.vhd
--
-- Description: Given a vector of input bits, Iv (not necessarily a
-- power of two). and a select value, Sel, this block
-- will build the multiplexing function
--
-- O <= Iv(Sel)
--
-- using the MUXF (MUXF5, MUXF6, etc.) primitives of
-- the target FPGA family, C_FAMILY, if possible and,
-- otherwise, using inferred multiplexers.
--
-- Since MUXF primitives are targeted, it is proper
-- that the Iv signals are driven by LUTs.
--
-- A help entity, muxf_struct, which is instantiated
-- recursively, is used to facilitate the implementation.
-- (So, compiling this file will add two entities,
-- muxf_struct and muxf_struct_f, to the target library.)
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- muxf_struct_f.vhd
-- muxf_struct (entity and architecture in this file)
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
--
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
--------------------------------------------------------------------------------
-- This is a helper entity. The entity declaration for muxf_struct_f is
-- further, below.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
use proc_common_v4_0.family_support.all; -- supported, primitives_type
library unisim;
entity muxf_struct is
generic (
C_START_LEVEL : natural;
C_NUM_INPUTS : positive;
C_NI_PO2E : positive; -- Num Inputs, Power-of-2 Envelope
C_FAMILY : string
);
port (
LO : out std_logic; -- Normally only one of
O : out std_logic; -- LO or O would be used.
Iv : in std_logic_vector(0 to C_NUM_INPUTS-1);
Sel: in std_logic_vector(0 to clog2(C_NI_PO2E)-1)
);
end entity muxf_struct;
library proc_common_v4_0;
library unisim;
use unisim.all; -- Makes unisim entities available for default binding.
--------------------------------------------------------------------------------
-- Line-length guideline purposely not followed in some places to expose parallel code structures.
--------------------------------------------------------------------------------
architecture imp of muxf_struct is
--
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
--
constant SIZE : natural := Iv'length;
constant PO2E : natural := C_NI_PO2E;
constant THIS_LEVEL : natural := C_START_LEVEL + clog2(PO2E);
constant K_FAMILY : families_type := str2fam(C_FAMILY);
constant S5 : boolean := supported(K_FAMILY, u_MUXF5_D) and THIS_LEVEL = 5;
constant S6 : boolean := supported(K_FAMILY, u_MUXF6_D) and THIS_LEVEL = 6;
constant S7 : boolean := supported(K_FAMILY, u_MUXF7_D) and THIS_LEVEL = 7;
constant S8 : boolean := supported(K_FAMILY, u_MUXF8_D) and THIS_LEVEL = 8;
constant INFERRED : boolean := not(S5 or S6 or S7 or S8);
--
signal s, i0, i1 : std_logic; -- If there is no i1 at a particular mux level,
-- it is left undriven and s is tied to '0'.
component MUXF5_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF6_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF7_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
component MUXF8_D
port
(
LO : out std_ulogic;
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Below, some generates and component instantiations are one per line
-- to show similarities and differences.
----------------------------------------------------------------------------
-- Base instance, just one or two inputs, no recursion.
----------------------------------------------------------------------------
E2_GEN : if PO2E=2 and SIZE=2 generate s <= Sel(0); i0 <= Iv(0); i1 <= Iv(1); end generate;
E1_GEN : if PO2E=2 and SIZE=1 generate s <= '0'; i0 <= Iv(0); end generate;-- No driver for i1
----------------------------------------------------------------------------
-- Use recursion to get lower-level mux structures to feed the mux at
-- this level.
----------------------------------------------------------------------------
GT2_GEN : if PO2E > 2 generate
constant NE : natural := PO2E/2; -- Next envelope.
constant BOTH : boolean := (SIZE > NE); -- Needs recursive call for
-- both the left and right sides; otherwise just a left-side
-- recursive call is needed (with C_NI_PO2E reduced by half) and Iv
-- passed down unchanged.
constant LSIZE : natural := bo2na(BOTH) * (2**(clog2(SIZE))/2)
+ bo2na(not BOTH) * SIZE;
-- 1st option above: LSIZE is next smaller power of 2
-- 2nd option above: SIZE is passed down unchanged
begin
LEFT_GEN : IF true generate
I_I0 : entity work.muxf_struct
generic map (C_START_LEVEL => C_START_LEVEL,
C_NUM_INPUTS => LSIZE,
C_NI_PO2E => NE,
C_FAMILY => C_FAMILY
)
port map (LO => i0,
O => open,
Iv => Iv(0 to LSIZE-1),
Sel => Sel(1 to Sel'right)
)
;
end generate;
RIGHT_GEN : IF BOTH generate
I_I1 : entity work.muxf_struct
generic map (C_START_LEVEL => C_START_LEVEL,
C_NUM_INPUTS => SIZE-LSIZE,
C_NI_PO2E => NE,
C_FAMILY => C_FAMILY
)
port map (LO => i1,
O => open,
Iv => Iv(LSIZE to SIZE-1),
Sel => Sel(1 to Sel'right)
)
;
s <= Sel(0);
end generate;
LEFT_ONLY_GEN : IF not BOTH generate
s <= '0';
end generate;
end generate;
-- Instantiate the mux at this level.
--
-- Structurals
S5_GEN : if S5 generate I_F5 : component MUXF5_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
S6_GEN : if S6 generate I_F6 : component MUXF6_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
S7_GEN : if S7 generate I_F7 : component MUXF7_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
S8_GEN : if S8 generate I_F8 : component MUXF8_D port map ( LO => LO, O => O, I0 => i0, I1 => i1, S => s); end generate;
-- Inferred
INFERRED_GEN : if INFERRED generate
signal h : std_logic;
begin
h <= i0 when s = '0' else i1 ;
LO <= h;
O <= h;
END generate;
end architecture imp;
---)
---(
--------------------------------------------------------------------------------
-- Generic descriptions
--------------------------------------------------------------------------------
-- C_START_LEVEL : natural - The size of the LUTs feeding into MUXFN network.
-- For example, for six-input LUTs,
-- C__START_LEVEL = 6 and the first level of muxes
-- are MUXF7.
-- C_NUM_INPUTS : positive - The number of inputs to be muxed.
-- C_FAMILY : string - The target FPGA family.
--------------------------------------------------------------------------------
-- Port descriptions
--------------------------------------------------------------------------------
-- O : out std_logic - Mux ouput
-- Iv : in std_logic_vector(0 to C_NUM_INPUTS-1) - Mux inputs
-- Sel: in std_logic_vector(0 to log2(C_NUM_INPUTS) - 1) - Select lines.
-- - The Iv values must be ordered such that the correct
-- - one is selected according to O <= Iv(Sel).
--------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
--
entity muxf_struct_f is
generic (
C_START_LEVEL : natural;
C_NUM_INPUTS : positive;
C_FAMILY : string
);
port (
O : out std_logic;
Iv : in std_logic_vector(0 to C_NUM_INPUTS-1);
Sel: in std_logic_vector(0 to clog2(C_NUM_INPUTS) - 1)
);
end muxf_struct_f;
architecture imp of muxf_struct_f is
begin
MUXF_STRUCT_I : entity proc_common_v4_0.muxf_struct
generic map (
C_START_LEVEL => C_START_LEVEL,
C_NUM_INPUTS => C_NUM_INPUTS,
C_NI_PO2E => 2**clog2(C_NUM_INPUTS),
C_FAMILY => C_FAMILY
)
port map (
LO => open,
O => O,
Iv => Iv,
Sel => Sel
);
end imp;
---)
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_xbar_1/blk_mem_gen_v8_1/blk_mem_gen_ecc_decoder.vhd | 27 | 24873 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16672)
`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/blk_mem_gen_v8_1/blk_mem_gen_ecc_decoder.vhd | 27 | 24873 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/builtin/delay.vhd | 19 | 10088 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/pf_counter_bit.vhd | 15 | 10926 | -------------------------------------------------------------------------------
-- $Id: pf_counter_bit.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-- DET 2002-02-24
-- - Changed to call out proc_common_v1_00_b library.
-- - Changed the use of MUXCY_L to MUXCY.
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed to call out proc_common v2_00_a library.
-- ^^^^^^
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
Use proc_common_v4_0.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_bit is
port (
Clk : in std_logic;
Rst : In std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic
);
end pf_counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_bit is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
component inferred_lut4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component inferred_lut4;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
--- xst wrk around I_ALU_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"36C6"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => count_AddSub,
--- xst wrk around I0 => Count_In,
--- xst wrk around I1 => Count_Down,
--- xst wrk around I2 => Count_Load,
--- xst wrk around I3 => Load_In);
I_ALU_LUT : inferred_lut4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub,
I0 => Count_In,
I1 => Count_Down,
I2 => Count_Load,
I3 => Load_In);
MUXCY_I : MUXCY
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
O => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg,
C => Clk,
CE => Clock_Enable,
D => count_Result,
R => Rst
);
Result <= count_Result_Reg;
end implementation;
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/pf_counter_bit.vhd | 15 | 10926 | -------------------------------------------------------------------------------
-- $Id: pf_counter_bit.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_bit.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input signal and connected it to the FDRE
-- reset input.
--
-- DET 2002-02-24
-- - Changed to call out proc_common_v1_00_b library.
-- - Changed the use of MUXCY_L to MUXCY.
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed to call out proc_common v2_00_a library.
-- ^^^^^^
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
Use proc_common_v4_0.inferred_lut4;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_bit is
port (
Clk : in std_logic;
Rst : In std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic
);
end pf_counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_bit is
--- xst wrk around component LUT4 is
--- xst wrk around generic(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon : boolean;
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT : bit_vector := X"0000"
--- xst wrk around );
--- xst wrk around port (
--- xst wrk around O : out std_logic;
--- xst wrk around I0 : in std_logic;
--- xst wrk around I1 : in std_logic;
--- xst wrk around I2 : in std_logic;
--- xst wrk around I3 : in std_logic);
--- xst wrk around end component LUT4;
component inferred_lut4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end component inferred_lut4;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
--- xst wrk around I_ALU_LUT : LUT4
--- xst wrk around generic map(
--- xst wrk around -- synthesis translate_off
--- xst wrk around Xon => false,
--- xst wrk around -- synthesis translate_on
--- xst wrk around INIT => X"36C6"
--- xst wrk around )
--- xst wrk around port map (
--- xst wrk around O => count_AddSub,
--- xst wrk around I0 => Count_In,
--- xst wrk around I1 => Count_Down,
--- xst wrk around I2 => Count_Load,
--- xst wrk around I3 => Load_In);
I_ALU_LUT : inferred_lut4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub,
I0 => Count_In,
I1 => Count_Down,
I2 => Count_Load,
I3 => Load_In);
MUXCY_I : MUXCY
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
O => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg,
C => Clk,
CE => Clock_Enable,
D => count_Result,
R => Rst
);
Result <= count_Result_Reg;
end implementation;
| mit |
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| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd | 7 | 7208 | -------------------------------------------------------------------------------
-- $Id: upcnt_n.vhd,v 1.1.2.1 2010/03/25 15:33:04 sanjayk Exp $
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/soft_reset.vhd | 15 | 13928 | -------------------------------------------------------------------------------
-- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/proc_common_pkg.vhd | 15 | 18735 | -------------------------------------------------------------------------------
-- $Id: proc_common_pkg.vhd,v 1.1.4.46 2010/10/28 01:14:32 ostlerf Exp $
-------------------------------------------------------------------------------
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_common_pkg.vhd
-- Version: v1.21b
-- Description: This file contains the constants and functions used in the
-- processor common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 09/12/01 -- Created from opb_arb_pkg.vhd
--
-- ALS 09/21/01
-- ^^^^^^
-- Added pwr function. Replaced log2 function with one that works for XST.
-- ~~~~~~
--
-- ALS 12/07/01
-- ^^^^^^
-- Added Addr_bits function.
-- ~~~~~~
-- ALS 01/31/02
-- ^^^^^^
-- Added max2 function.
-- ~~~~~~
-- FLO 02/22/02
-- ^^^^^^
-- Extended input argument range of log2 function to 2^30. Also, added
-- a check that the argument does not exceed this value; a failure
-- assertion violation is generated if it does not.
-- ~~~~~~
-- FLO 08/31/06
-- ^^^^^^
-- Removed type TARGET_FAMILY_TYPE and functions Get_Reg_File_Area and
-- Get_RLOC_Name. These objects are not used. Further, the functions
-- produced misleading warnings (CR419886, CR419898).
-- ~~~~~~
-- FLO 05/25/07
-- ^^^^^^
-- -Reimplemented function pad_power2 to correct error when the input
-- argument is 1. (fixes CR 303469)
-- -Added function clog2(x), which returns the integer ceiling of the
-- base 2 logarithm of x. This function can be used in place of log2
-- when wishing to avoid the XST warning, "VHDL Assertion Statement
-- with non constant condition is ignored".
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-- DET 5/8/2009 v4_0 for EDK L.SP2
-- ~~~~~~
-- - Per CR520627
-- - Added synthesis translate_off/on constructs to the log2 function
-- around the assertion statement. This removes a repetative XST Warning
-- in SRP files about a non-constant assertion check.
-- ^^^^^^
-- FL0 20/27/2010
-- ^^^^^^
-- Removed 42 TBD comment, again. (CR 568493)
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package proc_common_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end proc_common_pkg;
package body proc_common_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body proc_common_pkg;
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_xbar_1/fifo_generator_v11_0/common/output_blk.vhd | 19 | 27142 | `protect begin_protected
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/ramfifo/dc_ss.vhd | 19 | 8726 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4720)
`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/ld_arith_reg.vhd | 15 | 15091 | -------------------------------------------------------------------------------
-- $Id: ld_arith_reg.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
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-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 08/01 -- First version
--
-- FO 11/14/01 -- Cosmetic improvements
--
-- FO 02/22/02 -- Switched from MUXCY_L primitive to MUXCY.
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end ld_arith_reg;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <= '0' when C_ADD_SUB_NOT else OP;
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
-- Adder case
------------------------------------------------------------------------
Q_I_GEN_ADD: if C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case
------------------------------------------------------------------------
Q_I_GEN_SUB: if not C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= LOAD or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
| mit |
djmatt/VHDL-Lib | VHDL/testbench/tb_clockgen.vhd | 1 | 2082 | --------------------------------------------------------------------------------------------------
-- Clock generator for test-benches
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package tb_clockgen_pkg is
component tb_clockgen is
generic( PERIOD : time := 30ns;
DUTY_CYCLE : real := 0.50);
port( clk : out std_logic);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Clock generator for test-benches/simulations. Do not use for synthesis designs. When used
-- simultaneously with other clock-generators should result in phase-aligned clocks.
entity tb_clockgen is
generic( --Duration of one clock cycle in seconds. Cycle starts at low logic.
PERIOD : time := 30ns;
--Percentage of the cycle spent at high logic. Valid Values between 0 and 1.
DUTY_CYCLE : real := 0.50);
port( --The generated clock signal
clk : out std_logic);
end tb_clockgen;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------------------------
architecture behave of tb_clockgen is
signal clock : std_logic;
begin
clk <= clock;
tictoc: process
begin
clock <= '1';
wait for (PERIOD - (PERIOD * DUTY_CYCLE));
clock <= '0';
wait for (PERIOD * DUTY_CYCLE);
end process;
end behave; | mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/ramfifo/wr_logic.vhd | 19 | 37687 | `protect begin_protected
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/or_muxcy.vhd | 15 | 10538 | -------------------------------------------------------------------------------
-- $Id: or_muxcy.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy.vhd
--
-- Description: This file is used to OR together consecutive bits within
-- sections of a bus.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 04/06/01 -- First version
--
-- ALS 05/18/01
-- ^^^^^^
-- Added use of carry chain muxes if number of bits is > 4
-- ~~~~~~
-- BLT 05/23/01
-- ^^^^^^
-- Removed pad_4 function, replaced with arithmetic expression
-- ~~~~~~
-- BLT 05/24/01
-- ^^^^^^
-- Removed Sig input, removed C_START_BIT and C_BUS_SIZE
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Unisim library contains Xilinx primitives
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BITS -- number of bits to OR in bus section
--
-- Definition of Ports:
-- input In_Bus -- bus containing bits to be ORd
-- output Or_out -- OR result
--
-------------------------------------------------------------------------------
entity or_muxcy is
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy;
architecture implementation of or_muxcy is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Pad the number of bits to OR to the next multiple of 4
constant NUM_BITS_PAD : integer := ((C_NUM_BITS-1)/4+1)*4;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- define output of OR chain
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Carry Chain muxes are used to implement OR of 4 bits or more
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
begin
-- If the number of bits to OR is 4 or less, a simple LUT can be used
LESSTHAN4_GEN: if C_NUM_BITS < 5 generate
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to C_NUM_BITS-1) := (others => '0');
begin
BIT_LOOP: for i in 0 to C_NUM_BITS-1 generate
FIRST: if i = 0 generate
or_tmp(i) <= In_bus(0);
end generate FIRST;
REST: if i /= 0 generate
or_tmp(i) <= or_tmp(i-1) or In_bus(i);
end generate REST;
end generate BIT_LOOP;
Or_out <= or_tmp(C_NUM_BITS-1);
end generate LESSTHAN4_GEN;
-- If the number of bits to OR is 4 or more, then use LUTs and
-- carry chain. Pad the number of bits to the nearest multiple of 4
MORETHAN4_GEN: if C_NUM_BITS >= 5 generate
-- define output of LUTs
signal lut_out : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
-- define padded input bus
signal in_bus_pad : std_logic_vector(0 to NUM_BITS_PAD-1) := (others => '0');
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
begin
-- pad input bus
in_bus_pad(0 to C_NUM_BITS-1) <= In_bus(0 to C_NUM_BITS-1);
OR_GENERATE: for i in 0 to NUM_BITS_PAD/4-1 generate
lut_out(i) <= not( in_bus_pad(i*4) or
in_bus_pad(i*4+1) or
in_bus_pad(i*4+2) or
in_bus_pad(i*4+3) );
FIRST: if i = 0 generate
FIRSTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => '0' , --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate FIRST;
REST: if i /= 0 generate
RESTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => or_tmp(i-1), --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate REST;
end generate OR_GENERATE;
Or_out <= or_tmp(NUM_BITS_PAD/4-1);
end generate MORETHAN4_GEN;
end implementation;
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/or_muxcy.vhd | 15 | 10538 | -------------------------------------------------------------------------------
-- $Id: or_muxcy.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy.vhd
--
-- Description: This file is used to OR together consecutive bits within
-- sections of a bus.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 04/06/01 -- First version
--
-- ALS 05/18/01
-- ^^^^^^
-- Added use of carry chain muxes if number of bits is > 4
-- ~~~~~~
-- BLT 05/23/01
-- ^^^^^^
-- Removed pad_4 function, replaced with arithmetic expression
-- ~~~~~~
-- BLT 05/24/01
-- ^^^^^^
-- Removed Sig input, removed C_START_BIT and C_BUS_SIZE
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Unisim library contains Xilinx primitives
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_BITS -- number of bits to OR in bus section
--
-- Definition of Ports:
-- input In_Bus -- bus containing bits to be ORd
-- output Or_out -- OR result
--
-------------------------------------------------------------------------------
entity or_muxcy is
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy;
architecture implementation of or_muxcy is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Pad the number of bits to OR to the next multiple of 4
constant NUM_BITS_PAD : integer := ((C_NUM_BITS-1)/4+1)*4;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- define output of OR chain
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- Carry Chain muxes are used to implement OR of 4 bits or more
component MUXCY
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component;
begin
-- If the number of bits to OR is 4 or less, a simple LUT can be used
LESSTHAN4_GEN: if C_NUM_BITS < 5 generate
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to C_NUM_BITS-1) := (others => '0');
begin
BIT_LOOP: for i in 0 to C_NUM_BITS-1 generate
FIRST: if i = 0 generate
or_tmp(i) <= In_bus(0);
end generate FIRST;
REST: if i /= 0 generate
or_tmp(i) <= or_tmp(i-1) or In_bus(i);
end generate REST;
end generate BIT_LOOP;
Or_out <= or_tmp(C_NUM_BITS-1);
end generate LESSTHAN4_GEN;
-- If the number of bits to OR is 4 or more, then use LUTs and
-- carry chain. Pad the number of bits to the nearest multiple of 4
MORETHAN4_GEN: if C_NUM_BITS >= 5 generate
-- define output of LUTs
signal lut_out : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
-- define padded input bus
signal in_bus_pad : std_logic_vector(0 to NUM_BITS_PAD-1) := (others => '0');
-- define output of OR chain
signal or_tmp : std_logic_vector(0 to NUM_BITS_PAD/4-1) := (others => '0');
begin
-- pad input bus
in_bus_pad(0 to C_NUM_BITS-1) <= In_bus(0 to C_NUM_BITS-1);
OR_GENERATE: for i in 0 to NUM_BITS_PAD/4-1 generate
lut_out(i) <= not( in_bus_pad(i*4) or
in_bus_pad(i*4+1) or
in_bus_pad(i*4+2) or
in_bus_pad(i*4+3) );
FIRST: if i = 0 generate
FIRSTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => '0' , --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate FIRST;
REST: if i /= 0 generate
RESTMUX_I: MUXCY
port map (
O => or_tmp(i), --[out]
CI => or_tmp(i-1), --[in]
DI => '1' , --[in]
S => lut_out(i) --[in]
);
end generate REST;
end generate OR_GENERATE;
Or_out <= or_tmp(NUM_BITS_PAD/4-1);
end generate MORETHAN4_GEN;
end implementation;
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/dynshreg_f.vhd | 15 | 15946 | -------------------------------------------------------------------------------
-- $Id: dynshreg_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
--
-- ~~~~~~
-- FLO 06/07/15
-- ^^^^^^
-- -XST was observed in some cases to produce a suboptimal implementation when
-- the depth, C_DEPTH, is a power of two and less than the native depth
-- of the SRL. Now a structural implementation is used for these cases.
-- (The particular case where a problem was found was for C_DEPTH=4 and
-- C_FAMILY="virtex5". In this case, rather than use an SRL, XST
-- made an implementation out of discrete FFs and LUTs.)
-- -Added Description.
-- ~~~~~~
-- FLO 07/12/12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.clog2;
entity dynshreg_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_f;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture behavioral of dynshreg_f is
constant K_FAMILY : families_type := str2fam(C_FAMILY);
--
constant W32 : boolean := supported(K_FAMILY, u_SRLC32E) and
(C_DEPTH > 16 or not supported(K_FAMILY, u_SRL16E));
constant W16 : boolean := supported(K_FAMILY, u_SRLC16E) and not W32;
-- XST faster if these two constants are declared here
-- instead of in STRUCTURAL_A_GEN. (I.25)
--
function power_of_2(n: positive) return boolean is
variable i: positive := 1;
begin
while n > i loop i := i*2; end loop;
return n = i;
end power_of_2;
--
constant USE_INFERRED : boolean := ( power_of_2(C_DEPTH)
and ( (W16 and C_DEPTH >= 16)
or (W32 and C_DEPTH >= 32)
)
)
or (not W32 and not W16);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
constant USE_STRUCTURAL_A : boolean := not USE_INFERRED;
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component SRLC16E
generic
(
INIT : bit_vector := X"0000"
);
port
(
Q : out STD_ULOGIC;
Q15 : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
component SRLC32E
generic
(
INIT : bit_vector := X"00000000"
);
port
(
Q : out STD_ULOGIC;
Q31 : out STD_ULOGIC;
A : in STD_LOGIC_VECTOR (4 downto 0);
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
D : in STD_ULOGIC
);
end component;
begin
---(
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A = true generate
type bo2na_type is array(boolean) of natural;
constant bo2na : bo2na_type := (false => 0, true => 1);
constant BPSRL : natural := bo2na(W16)*16 + bo2na(W32)*32; -- Bits per SRL
constant BTASRL : natural := clog2(BPSRL); -- Bits To Address SRL
constant NUM_SRLS_DEEP : natural := (C_DEPTH + BPSRL-1)/BPSRL;
constant ADDR_BITS : integer := Addr'length;
signal dynshreg_addr : std_logic_vector(ADDR_BITS-1 downto 0);
signal cascade_sigs : std_logic_vector(0 to C_DWIDTH*(NUM_SRLS_DEEP+1) - 1);
-- The data signals at the inputs and daisy-chain outputs of SRLs.
-- The last signal of each cascade is not used.
--
signal q_sigs : std_logic_vector(0 to C_DWIDTH*NUM_SRLS_DEEP - 1);
-- The data signals at the addressble outputs of SRLs.
---)(
begin
DIN_TO_CASCADE_GEN : for i in 0 to C_DWIDTH-1 generate
cascade_sigs(i*(NUM_SRLS_DEEP+1)) <= Din(i);
end generate;
dynshreg_addr(ADDR_BITS-1 downto 0) <= Addr(0 to ADDR_BITS-1);
BIT_OF_WIDTH_GEN : for i in 0 to C_DWIDTH-1 generate
CASCADES_GEN : for j in 0 to NUM_SRLS_DEEP-1 generate
signal srl_addr: std_logic_vector(4 downto 0);
begin
-- Here we form the address for the SRL elements. This is just
-- the corresponding low-order bits of dynshreg_addr but we
-- also handle the case where we have to zero-pad to the left
-- a dynshreg_addr that is smaller than the SRL address port.
SRL_ADDR_LO_GEN : for i in 0 to min(ADDR_BITS-1,4) generate
srl_addr(i) <= dynshreg_addr(i);
end generate;
SRL_ADDR_HI_GEN : for i in min(ADDR_BITS-1,4)+1 to 4 generate
srl_addr(i) <= '0';
end generate;
W16_GEN : if W16 generate
SRLC16E_I : component SRLC16E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q15 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A0 => srl_addr(0),
A1 => srl_addr(1),
A2 => srl_addr(2),
A3 => srl_addr(3),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
W32_GEN : if W32 generate
begin
SRLC32E_I : component SRLC32E
port map
(
Q => q_sigs(j + i*NUM_SRLS_DEEP),
Q31 => cascade_sigs(j+1 + i*(NUM_SRLS_DEEP+1)),
A => srl_addr(4 downto 0),
CE => Clken,
Clk => Clk,
D => cascade_sigs(j + i*(NUM_SRLS_DEEP+1))
)
;
end generate;
end generate CASCADES_GEN;
end generate BIT_OF_WIDTH_GEN;
----------------------------------------------------------------------------
-- Generate a MUXFn structure to select the proper SRL
-- as the output of each shift register.
----------------------------------------------------------------------------
SINGLE_SRL_GEN : if NUM_SRLS_DEEP = 1 generate
Dout <= q_sigs;
end generate;
--
MULTI_SRL_GEN : if NUM_SRLS_DEEP > 1 generate
PER_BIT_GEN : for i in 0 to C_DWIDTH-1 generate
begin
MUXF_STRUCT_I0 : entity proc_common_v4_0.muxf_struct_f
generic map (
C_START_LEVEL => native_lut_size(fam => K_FAMILY,
no_lut_return_val => 10000),
-- Artificially high value for C_START_LEVEL when no LUT is
-- supported will cause muxf_struct_f to default to inferred
-- multiplexers.
C_NUM_INPUTS => NUM_SRLS_DEEP,
C_FAMILY => C_FAMILY
)
port map (
O => Dout(i),
Iv => q_sigs(i * (NUM_SRLS_DEEP) to
(i+1) * (NUM_SRLS_DEEP) - 1),
Sel => dynshreg_addr(ADDR_BITS-1 downto BTASRL)
--Bits To Addr SRL
)
;
end generate;
end generate;
end generate STRUCTURAL_A_GEN;
---)
---(
INFERRED_GEN : if USE_INFERRED = true generate
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
signal data: dataType;
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
---)
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_xbar_1/fifo_generator_v11_0/ramfifo/rd_logic.vhd | 19 | 48192 | `protect begin_protected
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/ramfifo/fifo_generator_ramfifo.vhd | 19 | 78408 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 56304)
`protect data_block
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| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/direct_path_cntr.vhd | 15 | 12275 |
--ENTITY_TAG
-------------------------------------------------------------------------------
-- $Id: direct_path_cntr.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- direct_path_cntr.vhd - entity/arch
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
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-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: direct_path_cntr.vhd
--
-- Description: This is an up counter with a combinatorial direct pass-
-- through mode. The passed-through value also serves as
-- the initial "loaded" value when the counter switches to
-- count mode. In pass-though mode, Dout <= Din.
--
-- The mode is controlled by two signals, Load_n and Cnt_en.
-- The counter is in direct pass-through mode any time Load_n
-- is true (low) and up to the first cycle where Cnt_en is
-- true after Load_n goes false. When Load_n is false,
-- Dout increments by one each time Cnt_en is true at
-- the positive edge of Clk.
--
-- The implementation has a one-LUT delay (via the XORCY)
-- in direct pass-through mode and the same delay plus
-- carry-chain propogation in count mode.
-------------------------------------------------------------------------------
-- Structure: direct_path_cntr.vhd
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 05/30/2003 -- First version
--
-- <initials> <date>
-- ^^^^^^
-- Description of changes. If multiple lines are needed to fully describe
-- the changes made to the design, these lines should align with each other.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity direct_path_cntr is
generic (
C_WIDTH : natural := 8
);
port (
Clk : in std_logic;
Din : in std_logic_vector(0 to C_WIDTH-1);
Dout : out std_logic_vector(0 to C_WIDTH-1);
Load_n : in std_logic;
Cnt_en : in std_logic
);
end direct_path_cntr;
library unisim;
use unisim.all;
architecture imp of direct_path_cntr is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
component FDE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic
);
end component FDE;
signal q_i,
lut_out,
q_i_ns : std_logic_vector(0 to C_WIDTH-1);
signal cry : std_logic_vector(0 to C_WIDTH);
signal sel_cntr : std_logic;
begin
----------------------------------------------------------------------------
-- Load_n takes effect combinatorially, causing Dout to be directly driven
-- from Din when Load_n is asserted. When Load_n is not asserted, then the
-- first clocking of asserted Cnt_en switches modes so that Dout is driven
-- by the register value plus one. The value of Dout is clocked into the
-- register with each Cnt_en, thus realizing the counting behavior.
-- The combinatorial override of Load_n takes place in the LUT and covers
-- the cycle that it takes for the mode to recover (since the mode FF has a
-- synchronous reset). Use of an asynchronous reset is rejected as an
-- option to avoid the requirement that Load_n be generated glitch free.
----------------------------------------------------------------------------
I_MODE_SELECTION : process(Clk)
begin
if Clk'event and Clk='1' then
if Load_n = '0' then
sel_cntr <= '0';
elsif Cnt_en = '1' then
sel_cntr <= '1';
end if;
end if;
end process;
Dout <= q_i_ns;
cry(C_WIDTH) <= '0';
PERBIT_GEN: for j in C_WIDTH-1 downto 0 generate
signal gen_cry: std_logic;
begin
gen_cry <= '1' when j = C_WIDTH-1 else '0'; -- cntrl increments
-- at LSB
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
LSB_LUT_GEN: if j = C_WIDTH-1 generate
begin
lut_out(j) <= not q_i(j) when (sel_cntr and Load_n)='1' else Din(j);
end generate;
--
NON_LSB_LUT_GEN: if j /= C_WIDTH-1 generate
begin
lut_out(j) <= q_i(j) when (sel_cntr and Load_n)='1' else Din(j);
end generate;
------------------------------------------------------------------------
-- Propagate the carry out.
------------------------------------------------------------------------
LSB_MUXCY_GEN: if j = C_WIDTH-1 generate
signal sel_cntr_and_Load_n : std_logic;
begin
I_MULT_AND : MULT_AND
port map (
LO => sel_cntr_and_Load_n,
I1 => sel_cntr,
I0 => Load_n
);
MUXCY_i1: MUXCY
port map (
DI => sel_cntr_and_Load_n,
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
--
NON_LSB_MUXCY_GEN: if j /= C_WIDTH-1 generate
begin
MUXCY_i1: MUXCY
port map (
DI => '0',
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
------------------------------------------------------------------------
-- Apply the effect of carry in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => lut_out(j),
CI => cry(j+1),
O => q_i_ns(j)
);
FDRE_i1: FDE
port map (
Q => q_i(j),
C => Clk,
CE => Cnt_en,
D => q_i_ns(j)
);
end generate;
end imp;
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/common/wr_pf_ss.vhd | 19 | 30385 | `protect begin_protected
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/rd_bin_cntr.vhd | 19 | 13156 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8000)
`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_xbar_1/fifo_generator_v11_0/ramfifo/rd_bin_cntr.vhd | 19 | 13156 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8000)
`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/builtin/builtin_extdepth_low_latency.vhd | 19 | 43742 | `protect begin_protected
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| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/mux_onehot.vhd | 15 | 14596 | -------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
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-- ** Use with non-Xilinx devices or technologies is expressly **
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-- ** covered by a separate agreement. **
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-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
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-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/fifo_generator_v11_0_defaults.vhd | 19 | 30145 | `protect begin_protected
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_auto_pc_3/fifo_generator_v11_0/fifo_generator_v11_0_defaults.vhd | 19 | 30145 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576)
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/ramfifo/wr_status_flags_sshft.vhd | 19 | 23122 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15376)
`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/ramfifo/wr_status_flags_ss.vhd | 19 | 23791 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
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`protect end_protected
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/ramfifo/wr_status_flags_ss.vhd | 19 | 23791 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/or_muxcy_f.vhd | 15 | 12722 | -------------------------------------------------------------------------------
-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy_f
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy_f.vhd
--
-- Description:
-- (Note: It is recommended to use this module sparingly.
-- XST synthesis inferral of reduction-OR functionality
-- has progressed to where a carry-chain implementation
-- will be selected if it has advantages. At the same
-- time, if a rigid carry chain structure is not imposed,
-- XST has more degrees of freedom for optimization.
--
-- This module can be used to get an inferred implementation
-- by specifying C_FAMILY = "nofamily", which is the default
-- value of this Generic. It is equally possible to use
-- a reduction-or function (see or_reduce, below, for an
-- example) instead of this module.
--
-- If however the designer wants without compromise
-- a structural carry-chain implementation, then this
-- module can be used with C_FAMILY set to the target
-- Xilinx FPGA family.
--
-- End of Note.
-- )
--
--
-- Or_out <= or_reduce(In_bus)
--
-- i.e., OR together the bits in In_bus and assign to Or_out.
--
-- The implementation uses a single LUT if possible.
-- Otherwise, if C_FAMILY supports the carry chain concept,
-- it uses a minimal number of LUTs on a carry chain.
-- The native LUT size of C_FAMILY is taken into account.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 07/06/06 -- First version - derived from or_with_enable_f
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
entity or_muxcy_f is
generic (
C_NUM_BITS : integer;
C_FAMILY : string := "nofamily"
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy_f;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-- Makes visible the function 'supported' and related types,
-- including enumeration literals for the unisim primitives (e.g.
-- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.).
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
--
architecture implementation of or_muxcy_f is
----------------------------------------------------------------------------
-- Here is determined the largest LUT width supported by the target family.
-- If no LUT is supported, the width is set to a very large number, which,
-- as things are structured, will cause an inferred implementation
-- to be used.
----------------------------------------------------------------------------
constant lut_size : integer
:= native_lut_size(fam_as_string => C_FAMILY,
no_lut_return_val => integer'high);
----------------------------------------------------------------------------
-- Here is determined which structural or inferred implementation to use.
----------------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and
In_bus'length > lut_size;
-- Structural implementation not needed if the number
-- bits to be ORed will fit into a single LUT.
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
----------------------------------------------------------------------------
-- Reduction OR function.
----------------------------------------------------------------------------
function or_reduce (v : std_logic_vector) return std_logic is
variable r : std_logic := '0';
begin
for i in v'range loop
r := r or v(i);
end loop;
return r;
end;
----------------------------------------------------------------------------
-- Min function.
----------------------------------------------------------------------------
function min (a, b: natural) return natural is
begin
if (a>b) then return b; else return a; end if;
end;
----------------------------------------------------------------------------
-- Signal to recast In_bus into a local array whose index bounds and
-- direction are known.
----------------------------------------------------------------------------
signal OB : std_logic_vector(0 to In_bus'length-1);
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
OB <= In_bus;
----------------------------------------------------------------------------
-- Inferred implementation.
----------------------------------------------------------------------------
INFERRED_GEN : if USE_INFERRED generate
begin
Or_out <= or_reduce(OB);
end generate INFERRED_GEN;
----------------------------------------------------------------------------
-- Structural implementation.
----------------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size);
signal cy : std_logic_vector(0 to NUM_LUTS);
begin
--
cy(0) <= '0';
--
GEN : for i in 0 to NUM_LUTS-1 generate
signal lut : std_logic;
begin
lut <= not or_reduce(OB(i*lut_size to
min((i+1)*lut_size-1, OB'right))); -- The min
-- function catches the case where one LUT
-- is partial (i.e., not all inputs are used).
--
I_MUXCY : component MUXCY
port map (O =>cy(NUM_LUTS - i),
CI=>cy(NUM_LUTS - 1 - i),
DI=>'1',
S =>lut);
-- Note on cy handling: As done here, the partial LUT, if any,
-- is placed at the start of the cy chain.
end generate;
--
Or_out <= cy(NUM_LUTS);
--
end generate STRUCTURAL_A_GEN;
end implementation;
| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/dc_ss_fwft.vhd | 19 | 9156 | `protect begin_protected
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| mit |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/srl_fifo2.vhd | 15 | 14428 | -------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
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-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
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-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
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-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo2.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo2.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.all;
entity srl_fifo2 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo2;
architecture imp of srl_fifo2 is
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic;
-- I1 : in std_logic;
-- I2 : in std_logic;
-- I3 : in std_logic);
-- end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
| mit |
dries007/Basys3 | VGA_text/VGA_text.srcs/sources_1/ip/FrameBuffer/synth/FrameBuffer.vhd | 1 | 15058 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
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-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY FrameBuffer IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END FrameBuffer;
ARCHITECTURE FrameBuffer_arch OF FrameBuffer IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FrameBuffer_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF FrameBuffer_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF FrameBuffer_arch : ARCHITECTURE IS "FrameBuffer,blk_mem_gen_v8_3_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF FrameBuffer_arch: ARCHITECTURE IS "FrameBuffer,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=FrameBuffer.mif,C_INIT_FILE=FrameBuffer.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=10240,C_READ_DEPTH_A=10240,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=10240,C_READ_DEPTH_B=10240,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.61856 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "FrameBuffer.mif",
C_INIT_FILE => "FrameBuffer.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 10240,
C_READ_DEPTH_A => 10240,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 10240,
C_READ_DEPTH_B => 10240,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.61856 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END FrameBuffer_arch;
| mit |
dries007/Basys3 | FPGA-Z/FPGA-Z.ip_user_files/ip/Mem/Mem_stub.vhdl | 2 | 1381 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Thu May 5 01:21:43 2016
-- Host : Dries007-Arch running 64-bit unknown
-- Command : write_vhdl -force -mode synth_stub
-- /home/dries/Projects/Basys3/FPGA-Z/FPGA-Z.srcs/sources_1/ip/Mem/Mem_stub.vhdl
-- Design : Mem
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Mem is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end Mem;
architecture stub of Mem is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[16:0],dina[7:0],douta[7:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_1,Vivado 2015.4";
begin
end;
| mit |
dries007/Basys3 | VGA_text/VGA_text.srcs/sources_1/ip/ClockDivider/ClockDivider_sim_netlist.vhdl | 1 | 8108 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Sat Jun 4 16:53:15 2016
-- Host : Dries007-Arch running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/ClockDivider/ClockDivider_sim_netlist.vhdl
-- Design : ClockDivider
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ClockDivider_ClockDivider_clk_wiz is
port (
clk : in STD_LOGIC;
clk_vga : out STD_LOGIC;
clk_cpu : out STD_LOGIC;
clk_2cpu : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ClockDivider_ClockDivider_clk_wiz : entity is "ClockDivider_clk_wiz";
end ClockDivider_ClockDivider_clk_wiz;
architecture STRUCTURE of ClockDivider_ClockDivider_clk_wiz is
signal clk_2cpu_ClockDivider : STD_LOGIC;
signal clk_ClockDivider : STD_LOGIC;
signal clk_cpu_ClockDivider : STD_LOGIC;
signal clk_vga_ClockDivider : STD_LOGIC;
signal clkfbout_ClockDivider : STD_LOGIC;
signal clkfbout_buf_ClockDivider : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout3_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_ClockDivider,
O => clkfbout_buf_ClockDivider
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk,
O => clk_ClockDivider
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_vga_ClockDivider,
O => clk_vga
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_cpu_ClockDivider,
O => clk_cpu
);
clkout3_buf: unisim.vcomponents.BUFG
port map (
I => clk_2cpu_ClockDivider,
O => clk_2cpu
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 54.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 10.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 120,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 60,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_ClockDivider,
CLKFBOUT => clkfbout_ClockDivider,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_ClockDivider,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_vga_ClockDivider,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk_cpu_ClockDivider,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => clk_2cpu_ClockDivider,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ClockDivider is
port (
clk : in STD_LOGIC;
clk_vga : out STD_LOGIC;
clk_cpu : out STD_LOGIC;
clk_2cpu : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ClockDivider : entity is true;
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of ClockDivider : entity is "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=3,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end ClockDivider;
architecture STRUCTURE of ClockDivider is
begin
inst: entity work.ClockDivider_ClockDivider_clk_wiz
port map (
clk => clk,
clk_2cpu => clk_2cpu,
clk_cpu => clk_cpu,
clk_vga => clk_vga
);
end STRUCTURE;
| mit |
dries007/Basys3 | VGA/VGA.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_v8_0_9/hdl/dist_mem_gen_v8_0.vhd | 3 | 17706 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect end_protected
| mit |
dries007/Basys3 | FPGA-Z/FPGA-Z.srcs/sources_1/new/Font.vhd | 1 | 59948 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_unsigned.all;
use ieee.math_real.all;
package Font is
function draw_char(X : integer range 0 to 8; Y : integer range 0 to 16; char : integer range 0 to 128) return boolean;
end Font;
package body Font is
function draw_char(X : integer range 0 to 8; Y : integer range 0 to 16; char : integer range 0 to 128) return boolean is
type rom_type is array (0 to 2**11-1) of std_logic_vector(7 downto 0);
constant ROM: rom_type:=(
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x01 ?
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x02 ?
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x03 ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x04 ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00001000", -- 4 *
"00011100", -- 5 ***
"00111110", -- 6 *****
"01111111", -- 7 *******
"00111110", -- 8 *****
"00011100", -- 9 ***
"00001000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x05 ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x06 ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x07 �
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x08 ?
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x09 ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0a ?
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111", -- f ********
-- code x0b ?
"00000000", -- 0
"00000000", -- 1
"01111000", -- 2 ****
"01110000", -- 3 ***
"01011000", -- 4 ** *
"01001100", -- 5 ** *
"00011110", -- 6 ****
"00110011", -- 7 ** **
"00110011", -- 8 ** **
"00110011", -- 9 ** **
"00110011", -- a ** **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0c ?
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0d ?
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"11001100", -- 3 ** **
"11111100", -- 4 ******
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001110", -- 9 ***
"00001111", -- a ****
"00000111", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0e ?
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"11111110", -- 4 *******
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11100110", -- 9 ** ***
"11100111", -- a *** ***
"01100111", -- b *** **
"00000011", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x0f ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x10 ?
"00000000", -- 0
"00000001", -- 1 *
"00000011", -- 2 **
"00000111", -- 3 ***
"00001111", -- 4 ****
"00011111", -- 5 *****
"01111111", -- 6 *******
"00011111", -- 7 *****
"00001111", -- 8 ****
"00000111", -- 9 ***
"00000011", -- a **
"00000001", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x11 ?
"00000000", -- 0
"01000000", -- 1 *
"01100000", -- 2 **
"01110000", -- 3 ***
"01111000", -- 4 ****
"01111100", -- 5 *****
"01111111", -- 6 *******
"01111100", -- 7 *****
"01111000", -- 8 ****
"01110000", -- 9 ***
"01100000", -- a **
"01000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x12 ?
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x13 ?
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x14 �
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"11011110", -- 6 **** **
"11011000", -- 7 ** **
"11011000", -- 8 ** **
"11011000", -- 9 ** **
"11011000", -- a ** **
"11011000", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x15 �
"00000000", -- 0
"00111110", -- 1 *****
"01100011", -- 2 ** **
"00000110", -- 3 **
"00011100", -- 4 ***
"00110110", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"00110110", -- 8 ** **
"00011100", -- 9 ***
"00110000", -- a **
"01100011", -- b ** **
"00111110", -- c *****
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x16 ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"01111111", -- 8 *******
"01111111", -- 9 *******
"01111111", -- a *******
"01111111", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x17 ?
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00001100", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x18 ?
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x19 ?
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1a ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00110000", -- 6 **
"01111111", -- 7 *******
"00110000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1b ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00001100", -- 5 **
"00000110", -- 6 **
"01111111", -- 7 *******
"00000110", -- 8 **
"00001100", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1c ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000011", -- 6 **
"00000011", -- 7 **
"00000011", -- 8 **
"01111111", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1d ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1e ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00001000", -- 4 *
"00011100", -- 5 ***
"00011100", -- 6 ***
"00111110", -- 7 *****
"00111110", -- 8 *****
"01111111", -- 9 *******
"01111111", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x1f ?
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01111111", -- 4 *******
"01111111", -- 5 *******
"00111110", -- 6 *****
"00111110", -- 7 *****
"00011100", -- 8 ***
"00011100", -- 9 ***
"00001000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x20 ' '
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x21 !
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x22 "
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x23 #
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00110110", -- 3 ** **
"00110110", -- 4 ** **
"01111111", -- 5 *******
"00110110", -- 6 ** **
"00110110", -- 7 ** **
"00110110", -- 8 ** **
"01111111", -- 9 *******
"00110110", -- a ** **
"00110110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x24 $
"00011000", -- 0 **
"00011000", -- 1 **
"00111110", -- 2 *****
"01100011", -- 3 ** **
"01000011", -- 4 ** *
"00000011", -- 5 **
"00111110", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100001", -- 9 * **
"01100011", -- a ** **
"00111110", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000", -- f
-- code x25 %
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01000011", -- 4 ** *
"01100011", -- 5 ** **
"00110000", -- 6 **
"00011000", -- 7 **
"00001100", -- 8 **
"00000110", -- 9 **
"01100011", -- a ** **
"01100001", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x26 &
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00110110", -- 3 ** **
"00110110", -- 4 ** **
"00011100", -- 5 ***
"01101110", -- 6 *** **
"00111011", -- 7 ** ***
"00110011", -- 8 ** **
"00110011", -- 9 ** **
"00110011", -- a ** **
"01101110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x27 '
"00000000", -- 0
"00001100", -- 1 **
"00001100", -- 2 **
"00001100", -- 3 **
"00000110", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x28 (
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x29 )
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2a *
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2b +
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2c ,
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00001100", -- c **
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2d -
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2e .
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x2f /
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01000000", -- 4 *
"01100000", -- 5 **
"00110000", -- 6 **
"00011000", -- 7 **
"00001100", -- 8 **
"00000110", -- 9 **
"00000011", -- a **
"00000001", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x30
"00000000", -- 0
"00000000", -- 1
"00111110", -- 2 *****
"01100011", -- 3 ** **
"01100011", -- 4 ** **
"01110011", -- 5 ** ***
"01111011", -- 6 ** ****
"01101111", -- 7 **** **
"01100111", -- 8 *** **
"01100011", -- 9 ** **
"01100011", -- a ** **
"00111110", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x31
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00011100", -- 3
"00011110", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000", -- f
-- code x32
"00000000", -- 0
"00000000", -- 1
"00111110", -- 2 *****
"01100011", -- 3 ** **
"01100000", -- 4 **
"00110000", -- 5 **
"00011000", -- 6 **
"00001100", -- 7 **
"00000110", -- 8 **
"00000011", -- 9 **
"01100011", -- a ** **
"01111111", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x33
"00000000", -- 0
"00000000", -- 1
"00111110", -- 2 *****
"01100011", -- 3 ** **
"01100000", -- 4 **
"01100000", -- 5 **
"00111100", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100011", -- a ** **
"00111110", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x34
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00111000", -- 3 ***
"00111100", -- 4 ****
"00110110", -- 5 ** **
"00110011", -- 6 ** **
"01111111", -- 7 *******
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x35
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"00000011", -- 3 **
"00000011", -- 4 **
"00000011", -- 5 **
"00111111", -- 6 ******
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100011", -- a ** **
"00111110", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x36
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00000110", -- 3 **
"00000011", -- 4 **
"00000011", -- 5 **
"00111111", -- 6 ******
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100011", -- 9 ** **
"01100011", -- a ** **
"00111110", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x37
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01100000", -- 4 **
"01100000", -- 5 **
"00110000", -- 6 **
"00011000", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x38
"00000000", -- 0
"00000000", -- 1
"00111110", -- 2 *****
"01100011", -- 3 ** **
"01100011", -- 4 ** **
"01100011", -- 5 ** **
"00111110", -- 6 *****
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100011", -- 9 ** **
"01100011", -- a ** **
"00111110", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x39
"00000000", -- 0
"00000000", -- 1
"00111110", -- 2 *****
"01100011", -- 3 ** **
"01100011", -- 4 ** **
"01100011", -- 5 ** **
"01111110", -- 6 ******
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"00110000", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3a :
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3b ;
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3c <
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3d =
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3e >
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x3f ?
"00000000", -- 0
"00000000", -- 1
"00111110", -- 2 *****
"01100011", -- 3 ** **
"01100011", -- 4 ** **
"00110000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x40 @
"00000000", -- 0
"00000000", -- 1
"00111110", -- 2 *****
"01100011", -- 3 ** **
"01100011", -- 4 ** **
"01100011", -- 5 ** **
"01111011", -- 6 ** ****
"01111011", -- 7 ** ****
"01111011", -- 8 ** ****
"00111011", -- 9 ** ***
"00000011", -- a **
"00111110", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x41
"00000000", -- 0
"00000000", -- 1
"00001000", -- 2 *
"00011100", -- 3 ***
"00110110", -- 4 ** **
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01111111", -- 7 *******
"01100011", -- 8 ** **
"01100011", -- 9 ** **
"01100011", -- a ** **
"01100011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x42
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"00111110", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"00111111", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x43
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01000011", -- 4 ** *
"00000011", -- 5 **
"00000011", -- 6 **
"00000011", -- 7 **
"00000011", -- 8 **
"01000011", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x44
"00000000", -- 0
"00000000", -- 1
"00011111", -- 2 *****
"00110110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"00110110", -- a ** **
"00011111", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x45
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100110", -- 3 ** **
"01000110", -- 4 ** *
"00010110", -- 5 ** *
"00011110", -- 6 ****
"00010110", -- 7 ** *
"00000110", -- 8 **
"01000110", -- 9 ** *
"01100110", -- a ** **
"01111111", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x46
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100110", -- 3 ** **
"01000110", -- 4 ** *
"00010110", -- 5 ** *
"00011110", -- 6 ****
"00010110", -- 7 ** *
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00001111", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x47
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01000011", -- 4 ** *
"00000011", -- 5 **
"00000011", -- 6 **
"01111011", -- 7 ** ****
"01100011", -- 8 ** **
"01100011", -- 9 ** **
"01100110", -- a ** **
"01011100", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x48
"00000000", -- 0
"00000000", -- 1
"01100011", -- 2 ** **
"01100011", -- 3 ** **
"01100011", -- 4 ** **
"01100011", -- 5 ** **
"01111111", -- 6 *******
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100011", -- 9 ** **
"01100011", -- a ** **
"01100011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x49
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4a
"00000000", -- 0
"00000000", -- 1
"01111000", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110011", -- 8 ** **
"00110011", -- 9 ** **
"00110011", -- a ** **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4b
"00000000", -- 0
"00000000", -- 1
"01100111", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"00110110", -- 5 ** **
"00011110", -- 6 ****
"00011110", -- 7 ****
"00110110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100111", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4c
"00000000", -- 0
"00000000", -- 1
"00001111", -- 2 ****
"00000110", -- 3 **
"00000110", -- 4 **
"00000110", -- 5 **
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"01000110", -- 9 ** *
"01100110", -- a ** **
"01111111", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4d
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4e
"00000000", -- 0
"00000000", -- 1
"01100011", -- 2 ** **
"01100111", -- 3 *** **
"01101111", -- 4 **** **
"01111111", -- 5 *******
"01111011", -- 6 ** ****
"01110011", -- 7 ** ***
"01100011", -- 8 ** **
"01100011", -- 9 ** **
"01100011", -- a ** **
"01100011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x4f
"00000000", -- 0
"00000000", -- 1
"00111110", -- 2 *****
"01100011", -- 3 ** **
"01100011", -- 4 ** **
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100011", -- 9 ** **
"01100011", -- a ** **
"00111110", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x50
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"00111110", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00001111", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x510
"00000000", -- 0
"00000000", -- 1
"00111110", -- 2 *****
"01100011", -- 3 ** **
"01100011", -- 4 ** **
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01101011", -- 9 ** * **
"01111011", -- a ** ****
"00111110", -- b *****
"00110000", -- c **
"01110000", -- d ***
"00000000", -- e
"00000000", -- f
-- code x52
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"00111110", -- 6 *****
"00110110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100111", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x53
"00000000", -- 0
"00000000", -- 1
"00111110", -- 2 *****
"01100011", -- 3 ** **
"01100011", -- 4 ** **
"00000110", -- 5 **
"00011100", -- 6 ***
"00110000", -- 7 **
"01100000", -- 8 **
"01100011", -- 9 ** **
"01100011", -- a ** **
"00111110", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x54
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x55
"00000000", -- 0
"00000000", -- 1
"01100011", -- 2 ** **
"01100011", -- 3 ** **
"01100011", -- 4 ** **
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100011", -- 9 ** **
"01100011", -- a ** **
"00111110", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x56
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x57
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x58
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x59
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5a
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"01100001", -- 4 * **
"00110000", -- 5 **
"00011000", -- 6 **
"00001100", -- 7 **
"00000110", -- 8 **
"10000011", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5b
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000001", -- 3 *
"00000011", -- 4 **
"00000111", -- 5 ***
"00001110", -- 6 ***
"00011100", -- 7 ***
"00111000", -- 8 ***
"01110000", -- 9 ***
"01100000", -- a **
"01000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5d
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5e
"00001000", -- 0 *
"00011100", -- 1 ***
"00110110", -- 2 ** **
"01100011", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x5f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000", -- f
-- code x60
"00001100", -- 0 **
"00001100", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x61
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011110", -- 5 ****
"00110000", -- 6 **
"00111110", -- 7 *****
"00110011", -- 8 ** **
"00110011", -- 9 ** **
"00110011", -- a ** **
"01101110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x62
"00000000", -- 0
"00000000", -- 1
"00000111", -- 2 ***
"00000110", -- 3 **
"00000110", -- 4 **
"00011110", -- 5 ****
"00110110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"00111110", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x63
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111110", -- 5 *****
"01100011", -- 6 ** **
"00000011", -- 7 **
"00000011", -- 8 **
"00000011", -- 9 **
"01100011", -- a ** **
"00111110", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x64
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00110000", -- 3 **
"00110000", -- 4 **
"00111100", -- 5 ****
"00110110", -- 6 ** **
"00110011", -- 7 ** **
"00110011", -- 8 ** **
"00110011", -- 9 ** **
"00110011", -- a ** **
"01101110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x65
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111110", -- 5 *****
"01100011", -- 6 ** **
"01111111", -- 7 *******
"00000011", -- 8 **
"00000011", -- 9 **
"01100011", -- a ** **
"00111110", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x66
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00110110", -- 3 ** **
"00100110", -- 4 ** *
"00000110", -- 5 **
"00001111", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00001111", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x67
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01101110", -- 5 *** **
"00110011", -- 6 ** **
"00110011", -- 7 ** **
"00110011", -- 8 ** **
"00110011", -- 9 ** **
"00110011", -- a ** **
"00111110", -- b *****
"00110000", -- c **
"00110011", -- d ** **
"00011110", -- e ****
"00000000", -- f
-- code x68
"00000000", -- 0
"00000000", -- 1
"00000111", -- 2 ***
"00000110", -- 3 **
"00000110", -- 4 **
"00110110", -- 5 ** **
"01101110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100111", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x69
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00011100", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6a
"00000000", -- 0
"00000000", -- 1
"01100000", -- 2 **
"01100000", -- 3 **
"00000000", -- 4
"01110000", -- 5 ***
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"01100000", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000", -- f
-- code x6b
"00000000", -- 0
"00000000", -- 1
"00000111", -- 2 ***
"00000110", -- 3 **
"00000110", -- 4 **
"01100110", -- 5 ** **
"00110110", -- 6 ** **
"00011110", -- 7 ****
"00011110", -- 8 ****
"00110110", -- 9 ** **
"01100110", -- a ** **
"01100111", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6c
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100111", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111011", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x6f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111110", -- 5 *****
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100011", -- 9 ** **
"01100011", -- a ** **
"00111110", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x70
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111011", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"00111110", -- b *****
"00000110", -- c **
"00000110", -- d **
"00001111", -- e ****
"00000000", -- f
-- code x71
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01101110", -- 5 *** **
"00110011", -- 6 ** **
"00110011", -- 7 ** **
"00110011", -- 8 ** **
"00110011", -- 9 ** **
"00110011", -- a ** **
"00111110", -- b *****
"00110000", -- c **
"00110000", -- d **
"01111000", -- e ****
"00000000", -- f
-- code x72
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111011", -- 5 ** ***
"01101110", -- 6 *** **
"01100110", -- 7 ** **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00001111", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x73
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111110", -- 5 *****
"01100011", -- 6 ** **
"00000110", -- 7 **
"00011100", -- 8 ***
"00110000", -- 9 **
"01100011", -- a ** **
"00111110", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x74
"00000000", -- 0
"00000000", -- 1
"00001000", -- 2 *
"00001100", -- 3 **
"00001100", -- 4 **
"00111111", -- 5 ******
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"01101100", -- a ** **
"00111000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x75
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110011", -- 5 ** **
"00110011", -- 6 ** **
"00110011", -- 7 ** **
"00110011", -- 8 ** **
"00110011", -- 9 ** **
"00110011", -- a ** **
"01101110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x76
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x77
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x78
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x79
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100011", -- 9 ** **
"01100011", -- a ** **
"01111110", -- b ******
"01100000", -- c **
"00110000", -- d **
"00011111", -- e *****
"00000000", -- f
-- code x7a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111111", -- 5 *******
"00110011", -- 6 ** **
"00011000", -- 7 **
"00001100", -- 8 **
"00000110", -- 9 **
"01100011", -- a ** **
"01111111", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7b {
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7c |
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7d }
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7e ~
"00000000", -- 0
"00000000", -- 1
"01101110", -- 2 *** **
"00111011", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000", -- f
-- code x7f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00001000", -- 4 *
"00011100", -- 5 ***
"00110110", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100011", -- 9 ** **
"01111111", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000" -- f
);
begin
return ROM((char * 16) + Y)(X) = '1';
end draw_char;
end Font;
| mit |
dries007/Basys3 | VGA/VGA.srcs/sources_1/ip/v_ram/v_ram_sim_netlist.vhdl | 1 | 624873 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
-- Date : Tue Mar 01 14:57:36 2016
-- Host : Dries007Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim d:/Xilinx/Projects/VGA/VGA.srcs/sources_1/ip/v_ram/v_ram_sim_netlist.vhdl
-- Design : v_ram
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_mux__parameterized0\ is
port (
\^doutb\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
DOBDO : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 4 downto 0 );
clkb : in STD_LOGIC;
DOUTB : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
DOPBDOP : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_21\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_22\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_23\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_24\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_25\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_26\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_27\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_28\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_29\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_30\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_31\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_32\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_33\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_34\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_35\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_36\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux";
end \v_ram_blk_mem_gen_mux__parameterized0\;
architecture STRUCTURE of \v_ram_blk_mem_gen_mux__parameterized0\ is
signal \doutb[0]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[10]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[10]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[10]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[10]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[10]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[10]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[10]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[11]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[11]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[11]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[11]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[11]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[11]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[1]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[2]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[3]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[4]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[4]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[4]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[4]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[4]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[5]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[5]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[5]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[5]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[5]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[6]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[6]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[6]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[6]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[6]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[7]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[7]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[7]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[7]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[7]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[8]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[8]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[8]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[8]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[8]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[8]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[8]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \doutb[9]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \doutb[9]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \doutb[9]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \doutb[9]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \doutb[9]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \doutb[9]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \doutb[9]_INST_0_i_7_n_0\ : STD_LOGIC;
signal sel_pipe : STD_LOGIC_VECTOR ( 4 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
\doutb[0]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => DOUTB(0),
I1 => \doutb[0]_INST_0_i_1_n_0\,
O => \^doutb\(0),
S => sel_pipe_d1(4)
);
\doutb[0]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(2),
I1 => DOBDO(0),
I2 => sel_pipe_d1(3),
O => \doutb[0]_INST_0_i_1_n_0\
);
\doutb[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[10]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[10]_INST_0_i_2_n_0\,
I5 => \doutb[10]_INST_0_i_3_n_0\,
O => \^doutb\(10)
);
\doutb[10]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(7),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(7),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(7),
O => \doutb[10]_INST_0_i_1_n_0\
);
\doutb[10]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[10]_INST_0_i_4_n_0\,
I1 => \doutb[10]_INST_0_i_5_n_0\,
O => \doutb[10]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[10]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[10]_INST_0_i_6_n_0\,
I1 => \doutb[10]_INST_0_i_7_n_0\,
O => \doutb[10]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[10]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(7),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(7),
O => \doutb[10]_INST_0_i_4_n_0\
);
\doutb[10]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(7),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(7),
O => \doutb[10]_INST_0_i_5_n_0\
);
\doutb[10]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(7),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(7),
O => \doutb[10]_INST_0_i_6_n_0\
);
\doutb[10]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(7),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(7),
O => \doutb[10]_INST_0_i_7_n_0\
);
\doutb[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[11]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[11]_INST_0_i_2_n_0\,
I5 => \doutb[11]_INST_0_i_3_n_0\,
O => \^doutb\(11)
);
\doutb[11]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_34\(0),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_35\(0),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_36\(0),
O => \doutb[11]_INST_0_i_1_n_0\
);
\doutb[11]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[11]_INST_0_i_4_n_0\,
I1 => \doutb[11]_INST_0_i_5_n_0\,
O => \doutb[11]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[11]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[11]_INST_0_i_6_n_0\,
I1 => \doutb[11]_INST_0_i_7_n_0\,
O => \doutb[11]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[11]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_26\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_27\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_28\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_29\(0),
O => \doutb[11]_INST_0_i_4_n_0\
);
\doutb[11]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_30\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_31\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_32\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_33\(0),
O => \doutb[11]_INST_0_i_5_n_0\
);
\doutb[11]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => DOPBDOP(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_21\(0),
O => \doutb[11]_INST_0_i_6_n_0\
);
\doutb[11]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_22\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_23\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_24\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_25\(0),
O => \doutb[11]_INST_0_i_7_n_0\
);
\doutb[1]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\(0),
I1 => \doutb[1]_INST_0_i_1_n_0\,
O => \^doutb\(1),
S => sel_pipe_d1(4)
);
\doutb[1]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0),
I2 => sel_pipe_d1(3),
O => \doutb[1]_INST_0_i_1_n_0\
);
\doutb[2]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0\(0),
I1 => \doutb[2]_INST_0_i_1_n_0\,
O => \^doutb\(2),
S => sel_pipe_d1(4)
);
\doutb[2]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1),
I2 => sel_pipe_d1(3),
O => \doutb[2]_INST_0_i_1_n_0\
);
\doutb[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[3]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[3]_INST_0_i_2_n_0\,
I5 => \doutb[3]_INST_0_i_3_n_0\,
O => \^doutb\(3)
);
\doutb[3]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(0),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(0),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(0),
O => \doutb[3]_INST_0_i_1_n_0\
);
\doutb[3]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[3]_INST_0_i_4_n_0\,
I1 => \doutb[3]_INST_0_i_5_n_0\,
O => \doutb[3]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[3]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[3]_INST_0_i_6_n_0\,
I1 => \doutb[3]_INST_0_i_7_n_0\,
O => \doutb[3]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[3]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(0),
O => \doutb[3]_INST_0_i_4_n_0\
);
\doutb[3]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(0),
O => \doutb[3]_INST_0_i_5_n_0\
);
\doutb[3]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(0),
O => \doutb[3]_INST_0_i_6_n_0\
);
\doutb[3]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(0),
O => \doutb[3]_INST_0_i_7_n_0\
);
\doutb[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[4]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[4]_INST_0_i_2_n_0\,
I5 => \doutb[4]_INST_0_i_3_n_0\,
O => \^doutb\(4)
);
\doutb[4]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(1),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(1),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(1),
O => \doutb[4]_INST_0_i_1_n_0\
);
\doutb[4]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[4]_INST_0_i_4_n_0\,
I1 => \doutb[4]_INST_0_i_5_n_0\,
O => \doutb[4]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[4]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[4]_INST_0_i_6_n_0\,
I1 => \doutb[4]_INST_0_i_7_n_0\,
O => \doutb[4]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[4]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(1),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(1),
O => \doutb[4]_INST_0_i_4_n_0\
);
\doutb[4]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(1),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(1),
O => \doutb[4]_INST_0_i_5_n_0\
);
\doutb[4]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(1),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(1),
O => \doutb[4]_INST_0_i_6_n_0\
);
\doutb[4]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(1),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(1),
O => \doutb[4]_INST_0_i_7_n_0\
);
\doutb[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[5]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[5]_INST_0_i_2_n_0\,
I5 => \doutb[5]_INST_0_i_3_n_0\,
O => \^doutb\(5)
);
\doutb[5]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(2),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(2),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(2),
O => \doutb[5]_INST_0_i_1_n_0\
);
\doutb[5]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[5]_INST_0_i_4_n_0\,
I1 => \doutb[5]_INST_0_i_5_n_0\,
O => \doutb[5]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[5]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[5]_INST_0_i_6_n_0\,
I1 => \doutb[5]_INST_0_i_7_n_0\,
O => \doutb[5]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[5]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(2),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(2),
O => \doutb[5]_INST_0_i_4_n_0\
);
\doutb[5]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(2),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(2),
O => \doutb[5]_INST_0_i_5_n_0\
);
\doutb[5]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(2),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(2),
O => \doutb[5]_INST_0_i_6_n_0\
);
\doutb[5]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(2),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(2),
O => \doutb[5]_INST_0_i_7_n_0\
);
\doutb[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[6]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[6]_INST_0_i_2_n_0\,
I5 => \doutb[6]_INST_0_i_3_n_0\,
O => \^doutb\(6)
);
\doutb[6]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(3),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(3),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(3),
O => \doutb[6]_INST_0_i_1_n_0\
);
\doutb[6]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[6]_INST_0_i_4_n_0\,
I1 => \doutb[6]_INST_0_i_5_n_0\,
O => \doutb[6]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[6]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[6]_INST_0_i_6_n_0\,
I1 => \doutb[6]_INST_0_i_7_n_0\,
O => \doutb[6]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[6]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(3),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(3),
O => \doutb[6]_INST_0_i_4_n_0\
);
\doutb[6]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(3),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(3),
O => \doutb[6]_INST_0_i_5_n_0\
);
\doutb[6]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(3),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3),
O => \doutb[6]_INST_0_i_6_n_0\
);
\doutb[6]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(3),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(3),
O => \doutb[6]_INST_0_i_7_n_0\
);
\doutb[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[7]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[7]_INST_0_i_2_n_0\,
I5 => \doutb[7]_INST_0_i_3_n_0\,
O => \^doutb\(7)
);
\doutb[7]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(4),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(4),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(4),
O => \doutb[7]_INST_0_i_1_n_0\
);
\doutb[7]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[7]_INST_0_i_4_n_0\,
I1 => \doutb[7]_INST_0_i_5_n_0\,
O => \doutb[7]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[7]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[7]_INST_0_i_6_n_0\,
I1 => \doutb[7]_INST_0_i_7_n_0\,
O => \doutb[7]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[7]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(4),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(4),
O => \doutb[7]_INST_0_i_4_n_0\
);
\doutb[7]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(4),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(4),
O => \doutb[7]_INST_0_i_5_n_0\
);
\doutb[7]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(4),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(4),
O => \doutb[7]_INST_0_i_6_n_0\
);
\doutb[7]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(4),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(4),
O => \doutb[7]_INST_0_i_7_n_0\
);
\doutb[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[8]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[8]_INST_0_i_2_n_0\,
I5 => \doutb[8]_INST_0_i_3_n_0\,
O => \^doutb\(8)
);
\doutb[8]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(5),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(5),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(5),
O => \doutb[8]_INST_0_i_1_n_0\
);
\doutb[8]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[8]_INST_0_i_4_n_0\,
I1 => \doutb[8]_INST_0_i_5_n_0\,
O => \doutb[8]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[8]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[8]_INST_0_i_6_n_0\,
I1 => \doutb[8]_INST_0_i_7_n_0\,
O => \doutb[8]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[8]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(5),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(5),
O => \doutb[8]_INST_0_i_4_n_0\
);
\doutb[8]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(5),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(5),
O => \doutb[8]_INST_0_i_5_n_0\
);
\doutb[8]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(5),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(5),
O => \doutb[8]_INST_0_i_6_n_0\
);
\doutb[8]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(5),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(5),
O => \doutb[8]_INST_0_i_7_n_0\
);
\doutb[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"10FF105510AA1000"
)
port map (
I0 => sel_pipe_d1(3),
I1 => sel_pipe_d1(2),
I2 => \doutb[9]_INST_0_i_1_n_0\,
I3 => sel_pipe_d1(4),
I4 => \doutb[9]_INST_0_i_2_n_0\,
I5 => \doutb[9]_INST_0_i_3_n_0\,
O => \^doutb\(9)
);
\doutb[9]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"30BB3088"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(6),
I1 => sel_pipe_d1(1),
I2 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(6),
I3 => sel_pipe_d1(0),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(6),
O => \doutb[9]_INST_0_i_1_n_0\
);
\doutb[9]_INST_0_i_2\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[9]_INST_0_i_4_n_0\,
I1 => \doutb[9]_INST_0_i_5_n_0\,
O => \doutb[9]_INST_0_i_2_n_0\,
S => sel_pipe_d1(2)
);
\doutb[9]_INST_0_i_3\: unisim.vcomponents.MUXF7
port map (
I0 => \doutb[9]_INST_0_i_6_n_0\,
I1 => \doutb[9]_INST_0_i_7_n_0\,
O => \doutb[9]_INST_0_i_3_n_0\,
S => sel_pipe_d1(2)
);
\doutb[9]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(6),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(6),
O => \doutb[9]_INST_0_i_4_n_0\
);
\doutb[9]_INST_0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(6),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(6),
O => \doutb[9]_INST_0_i_5_n_0\
);
\doutb[9]_INST_0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(6),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(6),
O => \doutb[9]_INST_0_i_6_n_0\
);
\doutb[9]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(6),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(6),
O => \doutb[9]_INST_0_i_7_n_0\
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(2),
Q => sel_pipe_d1(2),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(3),
Q => sel_pipe_d1(3),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => sel_pipe(4),
Q => sel_pipe_d1(4),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(1),
Q => sel_pipe(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(2),
Q => sel_pipe(2),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(3),
Q => sel_pipe(3),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clkb,
CE => '1',
D => addrb(4),
Q => sel_pipe(4),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity v_ram_blk_mem_gen_prim_wrapper_init is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ENA : in STD_LOGIC;
ENB : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of v_ram_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end v_ram_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of v_ram_blk_mem_gen_prim_wrapper_init is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "INDEPENDENT";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ram_ena : in STD_LOGIC;
ram_enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => addrb(13 downto 0),
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0),
DOBDO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 1),
DOBDO(0) => DOBDO(0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ram_ena,
ENBWREN => ram_enb,
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"11",
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
ENA : out STD_LOGIC;
ENB : out STD_LOGIC;
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \^ena\ : STD_LOGIC;
signal \^enb\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "INDEPENDENT";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
ENA <= \^ena\;
ENB <= \^enb\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena\,
ENBWREN => \^enb\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ena\,
ENBWREN => \^enb\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"4"
)
port map (
I0 => addra(16),
I1 => wea(0),
O => \^ena\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => addrb(16),
O => \^enb\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized10\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized10\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized10\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized10\ is
signal ena_array : STD_LOGIC_VECTOR ( 6 to 6 );
signal enb_array : STD_LOGIC_VECTOR ( 6 to 6 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(6),
ENBWREN => enb_array(6),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => addra(14),
I1 => wea(0),
I2 => addra(15),
I3 => addra(12),
I4 => addra(16),
I5 => addra(13),
O => ena_array(6)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(12),
I3 => addrb(13),
I4 => addrb(14),
O => enb_array(6)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized11\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized11\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized11\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized11\ is
signal ena_array : STD_LOGIC_VECTOR ( 7 to 7 );
signal enb_array : STD_LOGIC_VECTOR ( 7 to 7 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(7),
ENBWREN => enb_array(7),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => addra(12),
I1 => addra(13),
I2 => addra(16),
I3 => addra(15),
I4 => wea(0),
I5 => addra(14),
O => ena_array(7)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__6\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(14),
I3 => addrb(12),
I4 => addrb(13),
O => enb_array(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized12\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized12\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized12\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized12\ is
signal ena_array : STD_LOGIC_VECTOR ( 8 to 8 );
signal enb_array : STD_LOGIC_VECTOR ( 8 to 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(8),
ENBWREN => enb_array(8),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__7\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => addra(15),
I1 => wea(0),
I2 => addra(12),
I3 => addra(13),
I4 => addra(16),
I5 => addra(14),
O => ena_array(8)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__7\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addrb(16),
I1 => addrb(14),
I2 => addrb(15),
I3 => addrb(12),
I4 => addrb(13),
O => enb_array(8)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized13\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized13\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized13\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized13\ is
signal ena_array : STD_LOGIC_VECTOR ( 9 to 9 );
signal enb_array : STD_LOGIC_VECTOR ( 9 to 9 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(9),
ENBWREN => enb_array(9),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__8\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(13),
I3 => addra(14),
I4 => addra(16),
I5 => addra(15),
O => ena_array(9)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__8\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(16),
I1 => addrb(14),
I2 => addrb(13),
I3 => addrb(12),
I4 => addrb(15),
O => enb_array(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized14\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized14\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized14\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized14\ is
signal ena_array : STD_LOGIC_VECTOR ( 10 to 10 );
signal enb_array : STD_LOGIC_VECTOR ( 10 to 10 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(10),
ENBWREN => enb_array(10),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__9\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => addra(15),
I1 => wea(0),
I2 => addra(12),
I3 => addra(14),
I4 => addra(16),
I5 => addra(13),
O => ena_array(10)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__9\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(16),
I1 => addrb(14),
I2 => addrb(12),
I3 => addrb(13),
I4 => addrb(15),
O => enb_array(10)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized15\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized15\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized15\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized15\ is
signal ena_array : STD_LOGIC_VECTOR ( 11 to 11 );
signal enb_array : STD_LOGIC_VECTOR ( 11 to 11 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(11),
ENBWREN => enb_array(11),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__10\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => addra(12),
I1 => addra(13),
I2 => addra(16),
I3 => addra(14),
I4 => wea(0),
I5 => addra(15),
O => ena_array(11)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__10\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => addrb(16),
I1 => addrb(14),
I2 => addrb(15),
I3 => addrb(12),
I4 => addrb(13),
O => enb_array(11)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized16\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized16\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized16\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized16\ is
signal ena_array : STD_LOGIC_VECTOR ( 12 to 12 );
signal enb_array : STD_LOGIC_VECTOR ( 12 to 12 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(12),
ENBWREN => enb_array(12),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__11\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => addra(15),
I1 => wea(0),
I2 => addra(12),
I3 => addra(13),
I4 => addra(16),
I5 => addra(14),
O => ena_array(12)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__11\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(16),
I1 => addrb(13),
I2 => addrb(12),
I3 => addrb(14),
I4 => addrb(15),
O => enb_array(12)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized17\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized17\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized17\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized17\ is
signal ena_array : STD_LOGIC_VECTOR ( 13 to 13 );
signal enb_array : STD_LOGIC_VECTOR ( 13 to 13 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(13),
ENBWREN => enb_array(13),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__12\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => addra(12),
I1 => addra(15),
I2 => addra(16),
I3 => addra(13),
I4 => wea(0),
I5 => addra(14),
O => ena_array(13)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__12\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => addrb(16),
I1 => addrb(13),
I2 => addrb(15),
I3 => addrb(12),
I4 => addrb(14),
O => enb_array(13)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized18\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized18\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized18\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized18\ is
signal ena_array : STD_LOGIC_VECTOR ( 14 to 14 );
signal enb_array : STD_LOGIC_VECTOR ( 14 to 14 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(14),
ENBWREN => enb_array(14),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__13\: unisim.vcomponents.LUT6
generic map(
INIT => X"0008000000000000"
)
port map (
I0 => addra(15),
I1 => addra(13),
I2 => addra(16),
I3 => addra(12),
I4 => wea(0),
I5 => addra(14),
O => ena_array(14)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__13\: unisim.vcomponents.LUT5
generic map(
INIT => X"10000000"
)
port map (
I0 => addrb(16),
I1 => addrb(12),
I2 => addrb(15),
I3 => addrb(13),
I4 => addrb(14),
O => enb_array(14)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized19\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized19\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized19\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized19\ is
signal ena_array : STD_LOGIC_VECTOR ( 15 to 15 );
signal enb_array : STD_LOGIC_VECTOR ( 15 to 15 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(15),
ENBWREN => enb_array(15),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__14\: unisim.vcomponents.LUT6
generic map(
INIT => X"0800000000000000"
)
port map (
I0 => wea(0),
I1 => addra(12),
I2 => addra(16),
I3 => addra(13),
I4 => addra(15),
I5 => addra(14),
O => ena_array(15)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__14\: unisim.vcomponents.LUT5
generic map(
INIT => X"40000000"
)
port map (
I0 => addrb(16),
I1 => addrb(15),
I2 => addrb(14),
I3 => addrb(12),
I4 => addrb(13),
O => enb_array(15)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
\doutb[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
ram_ena : out STD_LOGIC;
ram_enb : out STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \^ram_ena\ : STD_LOGIC;
signal \^ram_enb\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
ram_ena <= \^ram_ena\;
ram_enb <= \^ram_enb\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => wea(0),
I1 => addra(16),
I2 => addra(15),
I3 => addra(14),
O => \^ram_ena\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => addrb(15),
I1 => addrb(14),
I2 => addrb(16),
O => \^ram_enb\
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => \doutb[2]\(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => \^ram_ena\,
ENBWREN => \^ram_enb\,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized20\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized20\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized20\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized20\ is
signal ena_array : STD_LOGIC_VECTOR ( 16 to 16 );
signal enb_array : STD_LOGIC_VECTOR ( 16 to 16 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(16),
ENBWREN => enb_array(16),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__15\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => wea(0),
I1 => addra(16),
I2 => addra(15),
I3 => addra(12),
I4 => addra(13),
I5 => addra(14),
O => ena_array(16)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__15\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addrb(15),
I1 => addrb(14),
I2 => addrb(16),
I3 => addrb(12),
I4 => addrb(13),
O => enb_array(16)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized21\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized21\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized21\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized21\ is
signal ena_array : STD_LOGIC_VECTOR ( 17 to 17 );
signal enb_array : STD_LOGIC_VECTOR ( 17 to 17 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(17),
ENBWREN => enb_array(17),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => addra(12),
I1 => addra(16),
I2 => addra(15),
I3 => addra(13),
I4 => addra(14),
I5 => wea(0),
O => ena_array(17)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__16\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(15),
I1 => addrb(14),
I2 => addrb(13),
I3 => addrb(12),
I4 => addrb(16),
O => enb_array(17)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized22\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized22\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized22\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized22\ is
signal ena_array : STD_LOGIC_VECTOR ( 18 to 18 );
signal enb_array : STD_LOGIC_VECTOR ( 18 to 18 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(18),
ENBWREN => enb_array(18),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => wea(0),
I1 => addra(16),
I2 => addra(15),
I3 => addra(12),
I4 => addra(14),
I5 => addra(13),
O => ena_array(18)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__17\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(15),
I1 => addrb(14),
I2 => addrb(12),
I3 => addrb(13),
I4 => addrb(16),
O => enb_array(18)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ENA : in STD_LOGIC;
ENB : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal CASCADEINA : STD_LOGIC;
signal CASCADEINB : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\ : label is "PRIMITIVE";
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "INDEPENDENT";
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "LOWER",
RAM_EXTENSION_B => "LOWER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => CASCADEINA,
CASCADEOUTB => CASCADEINB,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "UPPER",
RAM_EXTENSION_B => "UPPER",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(15 downto 0) => addra(15 downto 0),
ADDRBWRADDR(15 downto 0) => addrb(15 downto 0),
CASCADEINA => CASCADEINA,
CASCADEINB => CASCADEINB,
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DBITERR_UNCONNECTED\,
DIADI(31 downto 1) => B"0000000000000000000000000000000",
DIADI(0) => dina(0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOBDO_UNCONNECTED\(31 downto 1),
DOBDO(0) => DOUTB(0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ENA,
ENBWREN => ENB,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal ena_array : STD_LOGIC_VECTOR ( 0 to 0 );
signal enb_array : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => enb_array(0),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => wea(0),
I1 => addra(16),
I2 => addra(13),
I3 => addra(12),
I4 => addra(15),
I5 => addra(14),
O => ena_array(0)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(12),
I3 => addrb(13),
I4 => addrb(14),
O => enb_array(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized5\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized5\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized5\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized5\ is
signal ena_array : STD_LOGIC_VECTOR ( 1 to 1 );
signal enb_array : STD_LOGIC_VECTOR ( 1 to 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(1),
ENBWREN => enb_array(1),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(15),
I3 => addra(13),
I4 => addra(16),
I5 => addra(14),
O => ena_array(1)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(12),
I3 => addrb(13),
I4 => addrb(14),
O => enb_array(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized6\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized6\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized6\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized6\ is
signal ena_array : STD_LOGIC_VECTOR ( 2 to 2 );
signal enb_array : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(2),
ENBWREN => enb_array(2),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => addra(13),
I1 => wea(0),
I2 => addra(15),
I3 => addra(12),
I4 => addra(16),
I5 => addra(14),
O => ena_array(2)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(13),
I3 => addrb(12),
I4 => addrb(14),
O => enb_array(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized7\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPBDOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized7\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized7\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized7\ is
signal ena_array : STD_LOGIC_VECTOR ( 3 to 3 );
signal enb_array : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => DOPBDOP(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(3),
ENBWREN => enb_array(3),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(15),
I3 => addra(14),
I4 => addra(16),
I5 => addra(13),
O => ena_array(3)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(14),
I3 => addrb(12),
I4 => addrb(13),
O => enb_array(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized8\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized8\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized8\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized8\ is
signal ena_array : STD_LOGIC_VECTOR ( 4 to 4 );
signal enb_array : STD_LOGIC_VECTOR ( 4 to 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(4),
ENBWREN => enb_array(4),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => addra(14),
I1 => wea(0),
I2 => addra(15),
I3 => addra(13),
I4 => addra(16),
I5 => addra(12),
O => ena_array(4)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000010"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(14),
I3 => addrb(12),
I4 => addrb(13),
O => enb_array(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_wrapper_init__parameterized9\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized9\ : entity is "blk_mem_gen_prim_wrapper_init";
end \v_ram_blk_mem_gen_prim_wrapper_init__parameterized9\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_wrapper_init__parameterized9\ is
signal ena_array : STD_LOGIC_VECTOR ( 5 to 5 );
signal enb_array : STD_LOGIC_VECTOR ( 5 to 5 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 3) => addrb(11 downto 0),
ADDRBWRADDR(2 downto 0) => B"111",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0),
DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8),
DOBDO(7 downto 0) => \doutb[10]\(7 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1),
DOPBDOP(0) => \doutb[11]\(0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(5),
ENBWREN => enb_array(5),
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => addra(12),
I1 => wea(0),
I2 => addra(15),
I3 => addra(13),
I4 => addra(16),
I5 => addra(14),
O => ena_array(5)
);
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => addrb(15),
I1 => addrb(16),
I2 => addrb(13),
I3 => addrb(12),
I4 => addrb(14),
O => enb_array(5)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity v_ram_blk_mem_gen_prim_width is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ENA : in STD_LOGIC;
ENB : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of v_ram_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end v_ram_blk_mem_gen_prim_width;
architecture STRUCTURE of v_ram_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.v_ram_blk_mem_gen_prim_wrapper_init
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized0\ is
port (
DOBDO : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ram_ena : in STD_LOGIC;
ram_enb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
DOBDO(0) => DOBDO(0),
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
ram_ena => ram_ena,
ram_enb => ram_enb
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized1\ is
port (
ENA : out STD_LOGIC;
ENB : out STD_LOGIC;
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized10\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized10\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized10\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized10\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized10\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized11\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized11\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized11\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized11\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized11\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized12\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized12\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized12\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized12\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized12\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized13\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized13\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized13\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized13\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized13\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized14\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized14\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized14\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized14\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized14\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized15\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized15\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized15\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized15\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized15\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized16\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized16\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized16\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized16\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized16\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized17\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized17\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized17\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized17\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized17\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized18\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized18\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized18\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized18\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized18\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized19\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized19\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized19\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized19\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized19\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized2\ is
port (
\doutb[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
ram_ena : out STD_LOGIC;
ram_enb : out STD_LOGIC;
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
\doutb[2]\(1 downto 0) => \doutb[2]\(1 downto 0),
ram_ena => ram_ena,
ram_enb => ram_enb,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized20\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized20\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized20\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized20\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized20\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized21\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized21\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized21\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized21\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized21\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized22\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized22\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized22\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized22\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized22\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized3\ is
port (
DOUTB : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ENA : in STD_LOGIC;
ENB : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
DOUTB(0) => DOUTB(0),
ENA => ENA,
ENB => ENB,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized4\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized5\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized5\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized6\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized6\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized7\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
DOPBDOP : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized7\
port map (
DOPBDOP(0) => DOPBDOP(0),
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized8\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized8\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \v_ram_blk_mem_gen_prim_width__parameterized9\ is
port (
\doutb[10]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\doutb[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \v_ram_blk_mem_gen_prim_width__parameterized9\ : entity is "blk_mem_gen_prim_width";
end \v_ram_blk_mem_gen_prim_width__parameterized9\;
architecture STRUCTURE of \v_ram_blk_mem_gen_prim_width__parameterized9\ is
begin
\prim_init.ram\: entity work.\v_ram_blk_mem_gen_prim_wrapper_init__parameterized9\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(8 downto 0),
\doutb[10]\(7 downto 0) => \doutb[10]\(7 downto 0),
\doutb[11]\(0) => \doutb[11]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity v_ram_blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of v_ram_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end v_ram_blk_mem_gen_generic_cstr;
architecture STRUCTURE of v_ram_blk_mem_gen_generic_cstr is
signal ram_doutb : STD_LOGIC;
signal ram_ena : STD_LOGIC;
signal ram_enb : STD_LOGIC;
signal \ramloop[10].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[10].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[11].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[12].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[13].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[14].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[15].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[16].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[17].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[18].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[19].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[20].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[21].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[22].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[23].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_8\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_8\ : STD_LOGIC;
begin
\has_mux_b.B\: entity work.\v_ram_blk_mem_gen_mux__parameterized0\
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T\(0) => \ramloop[2].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_T_0\(0) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1) => \ramloop[3].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0) => \ramloop[3].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[8].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[8].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[8].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[8].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[8].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[8].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[8].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[8].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[7].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[7].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[7].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[7].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[7].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[7].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[7].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[7].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(7) => \ramloop[14].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(6) => \ramloop[14].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(5) => \ramloop[14].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(4) => \ramloop[14].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(3) => \ramloop[14].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(2) => \ramloop[14].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(1) => \ramloop[14].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_10\(0) => \ramloop[14].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(7) => \ramloop[13].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(6) => \ramloop[13].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(5) => \ramloop[13].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(4) => \ramloop[13].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(3) => \ramloop[13].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(2) => \ramloop[13].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(1) => \ramloop[13].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_11\(0) => \ramloop[13].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(7) => \ramloop[20].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(6) => \ramloop[20].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(5) => \ramloop[20].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(4) => \ramloop[20].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(3) => \ramloop[20].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(2) => \ramloop[20].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(1) => \ramloop[20].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_12\(0) => \ramloop[20].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(7) => \ramloop[19].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(6) => \ramloop[19].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(5) => \ramloop[19].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(4) => \ramloop[19].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(3) => \ramloop[19].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(2) => \ramloop[19].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(1) => \ramloop[19].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_13\(0) => \ramloop[19].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(7) => \ramloop[18].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(6) => \ramloop[18].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(5) => \ramloop[18].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(4) => \ramloop[18].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(3) => \ramloop[18].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(2) => \ramloop[18].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(1) => \ramloop[18].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_14\(0) => \ramloop[18].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(7) => \ramloop[17].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(6) => \ramloop[17].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(5) => \ramloop[17].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(4) => \ramloop[17].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(3) => \ramloop[17].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(2) => \ramloop[17].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(1) => \ramloop[17].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_15\(0) => \ramloop[17].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(7) => \ramloop[23].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(6) => \ramloop[23].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(5) => \ramloop[23].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(4) => \ramloop[23].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(3) => \ramloop[23].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(2) => \ramloop[23].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(1) => \ramloop[23].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_16\(0) => \ramloop[23].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(7) => \ramloop[22].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(6) => \ramloop[22].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(5) => \ramloop[22].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(4) => \ramloop[22].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(3) => \ramloop[22].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(2) => \ramloop[22].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(1) => \ramloop[22].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_17\(0) => \ramloop[22].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(7) => \ramloop[21].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(6) => \ramloop[21].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(5) => \ramloop[21].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(4) => \ramloop[21].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(3) => \ramloop[21].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(2) => \ramloop[21].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(1) => \ramloop[21].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_18\(0) => \ramloop[21].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_19\(0) => \ramloop[7].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(7) => \ramloop[6].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(6) => \ramloop[6].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(5) => \ramloop[6].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(4) => \ramloop[6].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(3) => \ramloop[6].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(2) => \ramloop[6].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(1) => \ramloop[6].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[6].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_20\(0) => \ramloop[6].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_21\(0) => \ramloop[5].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_22\(0) => \ramloop[12].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_23\(0) => \ramloop[11].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_24\(0) => \ramloop[10].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_25\(0) => \ramloop[9].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_26\(0) => \ramloop[16].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_27\(0) => \ramloop[15].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_28\(0) => \ramloop[14].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_29\(0) => \ramloop[13].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(7) => \ramloop[5].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(6) => \ramloop[5].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(5) => \ramloop[5].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(4) => \ramloop[5].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(3) => \ramloop[5].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(2) => \ramloop[5].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(1) => \ramloop[5].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_3\(0) => \ramloop[5].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_30\(0) => \ramloop[20].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_31\(0) => \ramloop[19].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_32\(0) => \ramloop[18].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_33\(0) => \ramloop[17].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_34\(0) => \ramloop[23].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_35\(0) => \ramloop[22].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_36\(0) => \ramloop[21].ram.r_n_8\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(7) => \ramloop[12].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(6) => \ramloop[12].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(5) => \ramloop[12].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(4) => \ramloop[12].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(3) => \ramloop[12].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(2) => \ramloop[12].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(1) => \ramloop[12].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_4\(0) => \ramloop[12].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(7) => \ramloop[11].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(6) => \ramloop[11].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(5) => \ramloop[11].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(4) => \ramloop[11].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(3) => \ramloop[11].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(2) => \ramloop[11].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(1) => \ramloop[11].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_5\(0) => \ramloop[11].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(7) => \ramloop[10].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(6) => \ramloop[10].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(5) => \ramloop[10].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(4) => \ramloop[10].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(3) => \ramloop[10].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(2) => \ramloop[10].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(1) => \ramloop[10].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_6\(0) => \ramloop[10].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(7) => \ramloop[9].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(6) => \ramloop[9].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(5) => \ramloop[9].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(4) => \ramloop[9].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(3) => \ramloop[9].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(2) => \ramloop[9].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(1) => \ramloop[9].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_7\(0) => \ramloop[9].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(7) => \ramloop[16].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(6) => \ramloop[16].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(5) => \ramloop[16].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(4) => \ramloop[16].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(3) => \ramloop[16].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(2) => \ramloop[16].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(1) => \ramloop[16].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_8\(0) => \ramloop[16].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(7) => \ramloop[15].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(6) => \ramloop[15].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(5) => \ramloop[15].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(4) => \ramloop[15].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(3) => \ramloop[15].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(2) => \ramloop[15].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(1) => \ramloop[15].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_9\(0) => \ramloop[15].ram.r_n_7\,
DOBDO(0) => \ramloop[1].ram.r_n_0\,
DOPBDOP(0) => \ramloop[8].ram.r_n_8\,
DOUTB(0) => ram_doutb,
addrb(4 downto 0) => addrb(16 downto 12),
clkb => clkb,
\^doutb\(11 downto 0) => doutb(11 downto 0)
);
\ramloop[0].ram.r\: entity work.v_ram_blk_mem_gen_prim_width
port map (
DOUTB(0) => ram_doutb,
ENA => \ramloop[2].ram.r_n_0\,
ENB => \ramloop[2].ram.r_n_1\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0)
);
\ramloop[10].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized9\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[10].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[10].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[10].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[10].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[10].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[10].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[10].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[10].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[10].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[11].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized10\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[11].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[11].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[11].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[11].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[11].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[11].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[11].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[11].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[11].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[12].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized11\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[12].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[12].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[12].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[12].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[12].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[12].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[12].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[12].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[12].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[13].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized12\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[13].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[13].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[13].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[13].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[13].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[13].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[13].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[13].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[13].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[14].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized13\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[14].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[14].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[14].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[14].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[14].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[14].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[14].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[14].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[14].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[15].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized14\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[15].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[15].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[15].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[15].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[15].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[15].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[15].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[15].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[15].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[16].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized15\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[16].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[16].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[16].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[16].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[16].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[16].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[16].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[16].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[16].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[17].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized16\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[17].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[17].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[17].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[17].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[17].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[17].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[17].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[17].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[17].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[18].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized17\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[18].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[18].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[18].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[18].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[18].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[18].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[18].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[18].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[18].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[19].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized18\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[19].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[19].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[19].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[19].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[19].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[19].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[19].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[19].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[19].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized0\
port map (
DOBDO(0) => \ramloop[1].ram.r_n_0\,
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(0),
ram_ena => ram_ena,
ram_enb => ram_enb
);
\ramloop[20].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized19\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[20].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[20].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[20].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[20].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[20].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[20].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[20].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[20].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[20].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[21].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized20\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[21].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[21].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[21].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[21].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[21].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[21].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[21].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[21].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[21].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[22].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized21\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[22].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[22].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[22].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[22].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[22].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[22].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[22].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[22].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[22].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[23].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized22\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[23].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[23].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[23].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[23].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[23].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[23].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[23].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[23].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[23].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized1\
port map (
DOUTB(0) => \ramloop[2].ram.r_n_2\,
ENA => \ramloop[2].ram.r_n_0\,
ENB => \ramloop[2].ram.r_n_1\,
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(1),
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized2\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(2 downto 1),
\doutb[2]\(1) => \ramloop[3].ram.r_n_0\,
\doutb[2]\(0) => \ramloop[3].ram.r_n_1\,
ram_ena => ram_ena,
ram_enb => ram_enb,
wea(0) => wea(0)
);
\ramloop[4].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized3\
port map (
DOUTB(0) => \ramloop[4].ram.r_n_0\,
ENA => \ramloop[2].ram.r_n_0\,
ENB => \ramloop[2].ram.r_n_1\,
addra(15 downto 0) => addra(15 downto 0),
addrb(15 downto 0) => addrb(15 downto 0),
clka => clka,
clkb => clkb,
dina(0) => dina(2)
);
\ramloop[5].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized4\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[5].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[5].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[5].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[5].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[5].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[5].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[5].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[5].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[5].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[6].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized5\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[6].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[6].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[6].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[6].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[6].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[6].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[6].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[6].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[6].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[7].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized6\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[7].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[7].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[7].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[7].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[7].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[7].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[7].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[7].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[7].ram.r_n_8\,
wea(0) => wea(0)
);
\ramloop[8].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized7\
port map (
DOPBDOP(0) => \ramloop[8].ram.r_n_8\,
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[8].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[8].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[8].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[8].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[8].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[8].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[8].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[8].ram.r_n_7\,
wea(0) => wea(0)
);
\ramloop[9].ram.r\: entity work.\v_ram_blk_mem_gen_prim_width__parameterized8\
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(8 downto 0) => dina(11 downto 3),
\doutb[10]\(7) => \ramloop[9].ram.r_n_0\,
\doutb[10]\(6) => \ramloop[9].ram.r_n_1\,
\doutb[10]\(5) => \ramloop[9].ram.r_n_2\,
\doutb[10]\(4) => \ramloop[9].ram.r_n_3\,
\doutb[10]\(3) => \ramloop[9].ram.r_n_4\,
\doutb[10]\(2) => \ramloop[9].ram.r_n_5\,
\doutb[10]\(1) => \ramloop[9].ram.r_n_6\,
\doutb[10]\(0) => \ramloop[9].ram.r_n_7\,
\doutb[11]\(0) => \ramloop[9].ram.r_n_8\,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity v_ram_blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of v_ram_blk_mem_gen_top : entity is "blk_mem_gen_top";
end v_ram_blk_mem_gen_top;
architecture STRUCTURE of v_ram_blk_mem_gen_top is
begin
\valid.cstr\: entity work.v_ram_blk_mem_gen_generic_cstr
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(11 downto 0) => dina(11 downto 0),
doutb(11 downto 0) => doutb(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity v_ram_blk_mem_gen_v8_3_1_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of v_ram_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth";
end v_ram_blk_mem_gen_v8_3_1_synth;
architecture STRUCTURE of v_ram_blk_mem_gen_v8_3_1_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.v_ram_blk_mem_gen_top
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(11 downto 0) => dina(11 downto 0),
doutb(11 downto 0) => doutb(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity v_ram_blk_mem_gen_v8_3_1 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 16 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 16 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of v_ram_blk_mem_gen_v8_3_1 : entity is 17;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of v_ram_blk_mem_gen_v8_3_1 : entity is 17;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of v_ram_blk_mem_gen_v8_3_1 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of v_ram_blk_mem_gen_v8_3_1 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of v_ram_blk_mem_gen_v8_3_1 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of v_ram_blk_mem_gen_v8_3_1 : entity is "26";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of v_ram_blk_mem_gen_v8_3_1 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of v_ram_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of v_ram_blk_mem_gen_v8_3_1 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of v_ram_blk_mem_gen_v8_3_1 : entity is "Estimated Power for IP : 16.2184 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of v_ram_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of v_ram_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of v_ram_blk_mem_gen_v8_3_1 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of v_ram_blk_mem_gen_v8_3_1 : entity is "v_ram.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of v_ram_blk_mem_gen_v8_3_1 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of v_ram_blk_mem_gen_v8_3_1 : entity is 76800;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of v_ram_blk_mem_gen_v8_3_1 : entity is 76800;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of v_ram_blk_mem_gen_v8_3_1 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of v_ram_blk_mem_gen_v8_3_1 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of v_ram_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of v_ram_blk_mem_gen_v8_3_1 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of v_ram_blk_mem_gen_v8_3_1 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of v_ram_blk_mem_gen_v8_3_1 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of v_ram_blk_mem_gen_v8_3_1 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of v_ram_blk_mem_gen_v8_3_1 : entity is 76800;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of v_ram_blk_mem_gen_v8_3_1 : entity is 76800;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of v_ram_blk_mem_gen_v8_3_1 : entity is "NO_CHANGE";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of v_ram_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of v_ram_blk_mem_gen_v8_3_1 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of v_ram_blk_mem_gen_v8_3_1 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of v_ram_blk_mem_gen_v8_3_1 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of v_ram_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of v_ram_blk_mem_gen_v8_3_1 : entity is "yes";
end v_ram_blk_mem_gen_v8_3_1;
architecture STRUCTURE of v_ram_blk_mem_gen_v8_3_1 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
douta(11) <= \<const0>\;
douta(10) <= \<const0>\;
douta(9) <= \<const0>\;
douta(8) <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
rdaddrecc(16) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(16) <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.v_ram_blk_mem_gen_v8_3_1_synth
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dina(11 downto 0) => dina(11 downto 0),
doutb(11 downto 0) => doutb(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity v_ram is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 16 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 16 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of v_ram : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of v_ram : entity is "v_ram,blk_mem_gen_v8_3_1,{}";
attribute core_generation_info : string;
attribute core_generation_info of v_ram : entity is "v_ram,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=v_ram.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=12,C_READ_WIDTH_A=12,C_WRITE_DEPTH_A=76800,C_READ_DEPTH_A=76800,C_ADDRA_WIDTH=17,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=12,C_READ_WIDTH_B=12,C_WRITE_DEPTH_B=76800,C_READ_DEPTH_B=76800,C_ADDRB_WIDTH=17,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=26,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 16.2184 mW}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of v_ram : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of v_ram : entity is "blk_mem_gen_v8_3_1,Vivado 2015.4";
end v_ram;
architecture STRUCTURE of v_ram is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 16 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 17;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 17;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "26";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 16.2184 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "v_ram.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 76800;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 76800;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 76800;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 76800;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "NO_CHANGE";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.v_ram_blk_mem_gen_v8_3_1
port map (
addra(16 downto 0) => addra(16 downto 0),
addrb(16 downto 0) => addrb(16 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => NLW_U0_douta_UNCONNECTED(11 downto 0),
doutb(11 downto 0) => doutb(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(16 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(16 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(16 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(16 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
| mit |
dries007/Basys3 | VGA/VGA.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_sim_netlist.vhdl | 1 | 7597 | -- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
-- Date : Fri Mar 04 11:10:30 2016
-- Host : Dries007Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- d:/Xilinx/Projects/VGA/VGA.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_sim_netlist.vhdl
-- Design : clk_wiz_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_1_clk_wiz_1_clk_wiz is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_wiz_1_clk_wiz_1_clk_wiz : entity is "clk_wiz_1_clk_wiz";
end clk_wiz_1_clk_wiz_1_clk_wiz;
architecture STRUCTURE of clk_wiz_1_clk_wiz_1_clk_wiz is
signal clk_in1_clk_wiz_1 : STD_LOGIC;
signal clk_out1_clk_wiz_1 : STD_LOGIC;
signal clkfbout_buf_clk_wiz_1 : STD_LOGIC;
signal clkfbout_clk_wiz_1 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_wiz_1,
O => clkfbout_buf_clk_wiz_1
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_clk_wiz_1
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_clk_wiz_1,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 32.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 128.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_wiz_1,
CLKFBOUT => clkfbout_clk_wiz_1,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_clk_wiz_1,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_clk_wiz_1,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_1 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_wiz_1 : entity is true;
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of clk_wiz_1 : entity is "clk_wiz_1,clk_wiz_v5_2_1,{component_name=clk_wiz_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_wiz_1;
architecture STRUCTURE of clk_wiz_1 is
begin
inst: entity work.clk_wiz_1_clk_wiz_1_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1
);
end STRUCTURE;
| mit |
dries007/Basys3 | VGA_text/VGA_text.srcs/sources_1/imports/new/Prng.vhd | 1 | 901 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Seeded PRNG (linear feedback shift register)
-- Thanks wikipedia for the consept and explaination
entity Prng is
Generic
(
BITS : integer := 32
);
Port
(
seed : in std_logic_vector (BITS-1 downto 0);
seed_en : in std_logic;
clk : in std_logic;
rnd : out std_logic_vector (BITS-1 downto 0)
);
end Prng;
architecture Behavioral of Prng is
begin
process (clk)
variable tmp_a : std_logic_vector(BITS-1 downto 0) := ('1', '0', '1', others => '0');
variable tmp_b : std_logic := '0';
begin
if rising_edge(clk) then
if seed_en = '1' then
tmp_a := seed;
else
tmp_b := tmp_a(BITS-1) xor tmp_a(BITS-2);
tmp_a := tmp_a(BITS-2 downto 0) & tmp_b;
rnd <= tmp_a;
end if;
end if;
end process;
end Behavioral;
| mit |
dries007/Basys3 | VGA_text/VGA_text.ip_user_files/ipstatic/axi_uartlite_v2_0_10/hdl/src/vhdl/dynshreg_i_f.vhd | 1 | 12369 | -- dynshreg_i_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: dynshreg_i_f.vhd
--
-- Description: This module implements a dynamic shift register with clock
-- enable. (Think, for example, of the function of the SRL16E.)
-- The width and depth of the shift register are selectable
-- via generics C_WIDTH and C_DEPTH, respectively. The C_FAMILY
-- allows the implementation to be tailored to the target
-- FPGA family. An inferred implementation is used if C_FAMILY
-- is "nofamily" (the default) or if synthesis will not produce
-- an optimal implementation. Otherwise, a structural
-- implementation will be generated.
--
-- There is no restriction on the values of C_WIDTH and
-- C_DEPTH and, in particular, the C_DEPTH does not have
-- to be a power of two.
--
-- This version allows the client to specify the initial value
-- of the contents of the shift register, as applied
-- during configuration.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
---(
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.TO_INTEGER;
--
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--------------------------------------------------------------------------------
-- Explanations of generics and ports regarding aspects that may not be obvious.
--
-- C_DWIDTH
--------
-- Theoretically, C_DWIDTH may be set to zero and this could be a more
-- natural or preferrable way of excluding a dynamic shift register
-- in a client than using a VHDL Generate statement. However, this usage is not
-- tested, and the user should expect that some VHDL tools will be deficient
-- with respect to handling this properly.
--
-- C_INIT_VALUE
---------------
-- C_INIT_VALUE can be used to specify the initial values of the elements
-- in the dynamic shift register, i.e. the values to be present after config-
-- uration. C_INIT_VALUE need not be the same size as the dynamic shift
-- register, i.e. C_DWIDTH*C_DEPTH. When smaller, C_INIT_VALUE
-- is replicated as many times as needed (possibly fractionally the last time)
-- to form a full initial value that is the size of the shift register.
-- So, if C_INIT_VALUE is left at its default value--an array of size one
-- whose value is '0'--the shift register will initialize with all bits at
-- all addresses set to '0'. This will also be the case if C_INIT_VALUE is a
-- null (size zero) array.
-- When determined according to the rules outlined above, the full
-- initial value is a std_logic_vector value from (0 to C_DWIDTH*C_DEPTH-1). It
-- is allocated to the addresses of the dynamic shift register in this
-- manner: The first C_DWIDTH values (i.e. 0 to C_CWIDTH-1) assigned to
-- the corresponding indices at address 0, the second C_DWIDTH values
-- assigned to address 1, and so forth.
-- Please note that the shift register is not resettable after configuration.
--
-- Addr
----
-- Addr addresses the elements of the dynamic shift register. Addr=0 causes
-- the most recently shifted-in element to appear at Dout, Addr=1
-- the second most recently shifted in element, etc. If C_DEPTH is not
-- a power of two, then not all of the values of Addr correspond to an
-- element in the shift register. When such an address is applied, the value
-- of Dout is undefined until a valid address is established.
--------------------------------------------------------------------------------
entity dynshreg_i_f is
generic (
C_DEPTH : positive := 32;
C_DWIDTH : natural := 1;
C_INIT_VALUE : bit_vector := "0";
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Clken : in std_logic;
Addr : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Din : in std_logic_vector(0 to C_DWIDTH-1);
Dout : out std_logic_vector(0 to C_DWIDTH-1)
);
end dynshreg_i_f;
architecture behavioral of dynshreg_i_f is
constant USE_INFERRED : boolean := true;
type bv2sl_type is array(bit) of std_logic;
constant bv2sl : bv2sl_type := ('0' => '0', '1' => '1');
function min(a, b: natural) return natural is
begin
if a<b then return a; else return b; end if;
end min;
--
------------------------------------------------------------------------------
-- Function used to establish the full initial value. (See the comments for
-- C_INIT_VALUE, above.)
------------------------------------------------------------------------------
function full_initial_value(w : natural; d : positive; v : bit_vector
) return bit_vector is
variable r : bit_vector(0 to w*d-1);
variable i, j : natural;
-- i - the index where filling of r continues
-- j - the amount to fill on the cur. iteration of the while loop
begin
if w = 0 then null; -- Handle the case where the shift reg width is zero
elsif v'length = 0 then r := (others => '0');
else
i := 0;
while i /= r'length loop
j := min(v'length, r'length-i);
r(i to i+j-1) := v(0 to j-1);
i := i+j;
end loop;
end if;
return r;
end full_initial_value;
constant FULL_INIT_VAL : bit_vector(0 to C_DWIDTH*C_DEPTH -1)
:= full_initial_value(C_DWIDTH, C_DEPTH, C_INIT_VALUE);
-- As of I.32, XST is not infering optimal dynamic shift registers for
-- depths not a power of two (by not taking advantage of don't care
-- at output when address not within the range of the depth)
-- or a power of two less than the native SRL depth (by building shift
-- register out of discrete FFs and LUTs instead of SRLs).
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
begin
INFERRED_GEN : if USE_INFERRED = true generate
--
type dataType is array (0 to C_DEPTH-1) of std_logic_vector(0 to C_DWIDTH-1);
--
function fill_data(w: natural; d: positive; v: bit_vector
) return dataType is
variable r : dataType;
begin
for i in 0 to d-1 loop
for j in 0 to w-1 loop
r(i)(j) := bv2sl(v(i*w+j));
end loop;
end loop;
return r;
end fill_data;
signal data: dataType := fill_data(C_DWIDTH, C_DEPTH, FULL_INIT_VAL);
--
begin
process(Clk)
begin
if Clk'event and Clk = '1' then
if Clken = '1' then
data <= Din & data(0 to C_DEPTH-2);
end if;
end if;
end process;
Dout <= data(TO_INTEGER(UNSIGNED(Addr)))
when (TO_INTEGER(UNSIGNED(Addr)) < C_DEPTH)
else
(others => '-');
end generate INFERRED_GEN;
---)
end behavioral;
| mit |
dries007/Basys3 | VGA_text/VGA_text.ip_user_files/ipstatic/blk_mem_gen_v8_3_1/simulation/blk_mem_gen_v8_3.vhd | 13 | 222214 | -------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
| mit |
dries007/Basys3 | FPGA-Z/FPGA-Z.srcs/sources_1/ip/FrameBuffer/blk_mem_gen_v8_3_1/simulation/blk_mem_gen_v8_3.vhd | 13 | 222214 | -------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v8_3_1.vhd
--
-- Description:
-- This file is the VHDL behvarial model for the
-- Block Memory Generator Core.
--
-------------------------------------------------------------------------------
-- Author: Xilinx
--
-- History: January 11, 2006: Initial revision
-- June 11, 2007 : Added independent register stages for
-- Port A and Port B (IP1_Jm/v2.5)
-- August 28, 2007 : Added mux pipeline stages feature (IP2_Jm/v2.6)
-- April 07, 2009 : Added support for Spartan-6 and Virtex-6
-- features, including the following:
-- (i) error injection, detection and/or correction
-- (ii) reset priority
-- (iii) special reset behavior
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
ENTITY blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END ENTITY blk_mem_axi_regs_fwd_v8_3;
ARCHITECTURE axi_regs_fwd_arch OF blk_mem_axi_regs_fwd_v8_3 IS
SIGNAL STORAGE_DATA : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL S_READY_I : STD_LOGIC := '0';
SIGNAL M_VALID_I : STD_LOGIC := '0';
SIGNAL ARESET_D : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');-- Reset delay register
BEGIN
--assign local signal to its output signal
S_READY <= S_READY_I;
M_VALID <= M_VALID_I;
PROCESS(ACLK)
BEGIN
IF(ACLK'event AND ACLK = '1') THEN
ARESET_D <= ARESET_D(0) & ARESET;
END IF;
END PROCESS;
--Save payload data whenever we have a transaction on the slave side
PROCESS(ACLK, ARESET)
BEGIN
IF (ARESET = '1') THEN
STORAGE_DATA <= (OTHERS => '0');
ELSIF(ACLK'event AND ACLK = '1') THEN
IF(S_VALID = '1' AND S_READY_I = '1') THEN
STORAGE_DATA <= S_PAYLOAD_DATA;
END IF;
END IF;
END PROCESS;
M_PAYLOAD_DATA <= STORAGE_DATA;
-- M_Valid set to high when we have a completed transfer on slave side
-- Is removed on a M_READY except if we have a new transfer on the slave side
PROCESS(ACLK,ARESET)
BEGIN
IF (ARESET_D /= "00") THEN
M_VALID_I <= '0';
ELSIF(ACLK'event AND ACLK = '1') THEN
IF (S_VALID = '1') THEN
--Always set M_VALID_I when slave side is valid
M_VALID_I <= '1';
ELSIF (M_READY = '1') THEN
--Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= '0';
END IF;
END IF;
END PROCESS;
--Slave Ready is either when Master side drives M_READY or we have space in our storage data
S_READY_I <= (M_READY OR (NOT M_VALID_I)) AND NOT(OR_REDUCE(ARESET_D));
END axi_regs_fwd_arch;
-------------------------------------------------------------------------------
-- Description:
-- This is the behavioral model of write_wrapper for the
-- Block Memory Generator Core.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_axi_write_wrapper_beh IS
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END blk_mem_axi_write_wrapper_beh;
ARCHITECTURE axi_write_wrap_arch OF blk_mem_axi_write_wrapper_beh IS
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_AXI_WDATA_WIDTH=8,0,
if_then_else((C_AXI_WDATA_WIDTH=16),1,
if_then_else((C_AXI_WDATA_WIDTH=32),2,
if_then_else((C_AXI_WDATA_WIDTH=64),3,
if_then_else((C_AXI_WDATA_WIDTH=128),4,
if_then_else((C_AXI_WDATA_WIDTH=256),5,0))))));
SIGNAL bvalid_c : std_logic := '0';
SIGNAL bready_timeout_c : std_logic := '0';
SIGNAL bvalid_rd_cnt_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_r : std_logic := '0';
SIGNAL bvalid_count_r : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL awaddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
C_AXI_AWADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL bvalid_wr_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL bvalid_rd_cnt_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL w_last_c : std_logic := '0';
SIGNAL addr_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL aw_ready_r : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL awlen_cntr_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '1');
SIGNAL awlen_int : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL awburst_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes : integer := 0;
SIGNAL wrap_boundary : integer := 0;
SIGNAL wrap_base_addr : integer := 0;
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
-- Array to store BIDs
TYPE id_array IS ARRAY (3 DOWNTO 0) OF std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
SIGNAL axi_bid_array : id_array := (others => (others => '0'));
COMPONENT write_netlist
GENERIC(
C_AXI_TYPE : integer
);
PORT(
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
S_AXI_AWVALID : IN std_logic;
aw_ready_r : OUT std_logic;
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN std_logic;
S_AXI_WR_EN : OUT std_logic;
w_last_c : IN std_logic;
bready_timeout_c : IN std_logic;
addr_en_c : OUT std_logic;
incr_addr_c : OUT std_logic;
bvalid_c : OUT std_logic
);
END COMPONENT write_netlist;
BEGIN
---------------------------------------
--AXI WRITE FSM COMPONENT INSTANTIATION
---------------------------------------
axi_wr_fsm : write_netlist
GENERIC MAP (
C_AXI_TYPE => C_AXI_TYPE
)
PORT MAP (
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
S_AXI_AWVALID => S_AXI_AWVALID,
aw_ready_r => aw_ready_r,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BVALID => OPEN,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_WR_EN => S_AXI_WR_EN,
w_last_c => w_last_c,
bready_timeout_c => bready_timeout_c,
addr_en_c => addr_en_c,
incr_addr_c => incr_addr_c,
bvalid_c => bvalid_c
);
--Wrap Address boundary calculation
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWSIZE,"000"));
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(awlen_int)+1);
wrap_base_addr <= (conv_integer(awaddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary <= wrap_base_addr+total_bytes;
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awaddr_reg <= (OTHERS => '0');
num_of_bytes_r <= 0;
awburst_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awaddr_reg <= S_AXI_AWADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_AWBURST,"01");
ELSIF (incr_addr_c = '1') THEN
IF (awburst_int = "10") THEN
IF(conv_integer(awaddr_reg) = (wrap_boundary-num_of_bytes_r)) THEN
awaddr_reg <= conv_std_logic_vector(wrap_base_addr,C_AXI_AWADDR_WIDTH);
ELSE
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
ELSIF (awburst_int = "01" OR awburst_int = "11") THEN
awaddr_reg <= awaddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
S_AXI_AWADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),
awaddr_reg(C_AXI_AWADDR_WIDTH-1 DOWNTO C_RANGE),awaddr_reg);
---------------------------------------------------------------------------
-- AXI wlast generation
---------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
awlen_cntr_r <= (OTHERS => '1');
awlen_int <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (addr_en_c = '1') THEN
awlen_int <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
awlen_cntr_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_AWLEN) AFTER FLOP_DELAY;
ELSIF (dec_alen_c = '1') THEN
awlen_cntr_r <= awlen_cntr_r - ONE AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
w_last_c <= '1' WHEN (awlen_cntr_r = "00000000" AND S_AXI_WVALID = '1') ELSE '0';
dec_alen_c <= (incr_addr_c OR w_last_c);
---------------------------------------------------------------------------
-- Generation of bvalid counter for outstanding transactions
---------------------------------------------------------------------------
P_b_valid_os_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_count_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- bvalid_count_r generation
IF (bvalid_c = '1' AND bvalid_r = '1' AND S_AXI_BREADY = '1') THEN
bvalid_count_r <= bvalid_count_r AFTER FLOP_DELAY;
ELSIF (bvalid_c = '1') THEN
bvalid_count_r <= bvalid_count_r + "01" AFTER FLOP_DELAY;
ELSIF (bvalid_r = '1' AND S_AXI_BREADY = '1' AND bvalid_count_r /= "0") THEN
bvalid_count_r <= bvalid_count_r - "01" AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_os_r ;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is used
---------------------------------------------------------------------------
gaxi_bvalid_id_r:IF (C_HAS_AXI_ID = 1) GENERATE
SIGNAL bvalid_d1_c : std_logic := '0';
BEGIN
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
bvalid_d1_c <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
--external bvalid signal generation
IF (bvalid_d1_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_id_r;
---------------------------------------------------------------------------
-- Generation of bvalid when BID is not used
---------------------------------------------------------------------------
gaxi_bvalid_noid_r:IF (C_HAS_AXI_ID = 0) GENERATE
P_b_valid_r: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
bvalid_r <= '0';
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
--external bvalid signal generation
IF (bvalid_c = '1') THEN
bvalid_r <= '1' AFTER FLOP_DELAY;
ELSIF (conv_integer(bvalid_count_r) <= 1 AND S_AXI_BREADY = '1') THEN
bvalid_r <= '0' AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_b_valid_r ;
END GENERATE gaxi_bvalid_noid_r;
---------------------------------------------------------------------------
-- Generation of Bready timeout
---------------------------------------------------------------------------
P_brdy_tout_c: PROCESS (bvalid_count_r)
BEGIN
-- bready_timeout_c generation
IF(conv_integer(bvalid_count_r) = C_AXI_OS_WR-1) THEN
bready_timeout_c <= '1';
ELSE
bready_timeout_c <= '0';
END IF;
END PROCESS P_brdy_tout_c;
---------------------------------------------------------------------------
-- Generation of BID
---------------------------------------------------------------------------
gaxi_bid_gen:IF (C_HAS_AXI_ID = 1) GENERATE
P_bid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
bvalid_wr_cnt_r <= (OTHERS => '0');
bvalid_rd_cnt_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
-- STORE AWID IN AN ARRAY
IF(bvalid_c = '1') THEN
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + "01";
END IF;
-- GENERATE BID FROM AWID ARRAY
bvalid_rd_cnt_r <= bvalid_rd_cnt_c AFTER FLOP_DELAY;
S_AXI_BID <= axi_bid_array(conv_integer(bvalid_rd_cnt_c));
END IF;
END PROCESS P_bid_gen;
bvalid_rd_cnt_c <= bvalid_rd_cnt_r + "01" WHEN (bvalid_r = '1' AND S_AXI_BREADY = '1') ELSE bvalid_rd_cnt_r;
---------------------------------------------------------------------------
-- Storing AWID for generation of BID
---------------------------------------------------------------------------
P_awid_reg:PROCESS (S_ACLK)
BEGIN
IF (S_ACLK'event AND S_ACLK='1') THEN
IF(aw_ready_r = '1' AND S_AXI_AWVALID = '1') THEN
axi_bid_array(conv_integer(bvalid_wr_cnt_r)) <= S_AXI_AWID;
END IF;
END IF;
END PROCESS P_awid_reg;
END GENERATE gaxi_bid_gen;
S_AXI_BVALID <= bvalid_r;
S_AXI_AWREADY <= aw_ready_r;
END axi_write_wrap_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity write_netlist is
GENERIC(
C_AXI_TYPE : integer
);
port (
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_AWVALID : in STD_LOGIC := '0';
S_AXI_WVALID : in STD_LOGIC := '0';
S_AXI_BREADY : in STD_LOGIC := '0';
w_last_c : in STD_LOGIC := '0';
bready_timeout_c : in STD_LOGIC := '0';
aw_ready_r : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_WR_EN : out STD_LOGIC;
addr_en_c : out STD_LOGIC;
incr_addr_c : out STD_LOGIC;
bvalid_c : out STD_LOGIC
);
end write_netlist;
architecture STRUCTURE of write_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
BEGIN
---------------------------------------------------------------------------
-- AXI LITE
---------------------------------------------------------------------------
gbeh_axi_lite_sm: IF (C_AXI_TYPE = 0 ) GENERATE
signal w_ready_r_7 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSignal_bvalid_c : STD_LOGIC;
signal NlwRenamedSignal_incr_addr_c : STD_LOGIC;
signal present_state_FSM_FFd3_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal present_state_FSM_FFd1_15 : STD_LOGIC;
signal present_state_FSM_FFd4_16 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd4_In1_21 : STD_LOGIC;
signal Mmux_aw_ready_c : STD_LOGIC_VECTOR ( 0 downto 0 );
begin
S_AXI_WREADY <= w_ready_r_7;
S_AXI_BVALID <= NlwRenamedSignal_incr_addr_c;
S_AXI_WR_EN <= NlwRenamedSignal_bvalid_c;
incr_addr_c <= NlwRenamedSignal_incr_addr_c;
bvalid_c <= NlwRenamedSignal_bvalid_c;
NlwRenamedSignal_incr_addr_c <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_7
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_16
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_13
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_15
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000055554440"
)
port map (
I0 => S_AXI_WVALID,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => '0',
O => present_state_FSM_FFd3_In
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"0000000088880800"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
I2 => bready_timeout_c,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => present_state_FSM_FFd2_In
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAA2000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_WVALID,
I4 => present_state_FSM_FFd4_16,
I5 => '0',
O => addr_en_c
);
Mmux_w_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"F5F07570F5F05500"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => w_ready_c
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd3_13,
I3 => present_state_FSM_FFd2_14,
I4 => present_state_FSM_FFd1_15,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_14,
I2 => present_state_FSM_FFd3_13,
I3 => '0',
I4 => '0',
I5 => '0',
O => NlwRenamedSignal_bvalid_c
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"2F0F27072F0F2200"
)
port map (
I0 => S_AXI_WVALID,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_13,
I4 => present_state_FSM_FFd4_16,
I5 => present_state_FSM_FFd2_14,
O => present_state_FSM_FFd4_In1_21
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_In1_21,
I3 => '0',
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_aw_ready_c_0_1 : STATE_LOGIC
generic map(
INIT => X"7535753575305500"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => S_AXI_WVALID,
I3 => present_state_FSM_FFd4_16,
I4 => present_state_FSM_FFd3_13,
I5 => present_state_FSM_FFd2_14,
O => Mmux_aw_ready_c(0)
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"00000000000000F8"
)
port map (
I0 => present_state_FSM_FFd1_15,
I1 => S_AXI_BREADY,
I2 => Mmux_aw_ready_c(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => aw_ready_c
);
END GENERATE gbeh_axi_lite_sm;
---------------------------------------------------------------------------
-- AXI FULL
---------------------------------------------------------------------------
gbeh_axi_full_sm: IF (C_AXI_TYPE = 1 ) GENERATE
signal w_ready_r_8 : STD_LOGIC;
signal w_ready_c : STD_LOGIC;
signal aw_ready_c : STD_LOGIC;
signal NlwRenamedSig_OI_bvalid_c : STD_LOGIC;
signal present_state_FSM_FFd1_16 : STD_LOGIC;
signal present_state_FSM_FFd4_17 : STD_LOGIC;
signal present_state_FSM_FFd3_18 : STD_LOGIC;
signal present_state_FSM_FFd2_19 : STD_LOGIC;
signal present_state_FSM_FFd4_In : STD_LOGIC;
signal present_state_FSM_FFd3_In : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal present_state_FSM_FFd2_In1_24 : STD_LOGIC;
signal present_state_FSM_FFd4_In1_25 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal N4 : STD_LOGIC;
begin
S_AXI_WREADY <= w_ready_r_8;
bvalid_c <= NlwRenamedSig_OI_bvalid_c;
S_AXI_BVALID <= '0';
aw_ready_r_2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => aw_ready_c,
Q => aw_ready_r
);
w_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => w_ready_c,
Q => w_ready_r_8
);
present_state_FSM_FFd4 : beh_ff_pre
generic map(
INIT => '1'
)
port map (
C => S_ACLK,
D => present_state_FSM_FFd4_In,
PRE => S_ARESETN,
Q => present_state_FSM_FFd4_17
);
present_state_FSM_FFd3 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd3_In,
Q => present_state_FSM_FFd3_18
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_19
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_16
);
present_state_FSM_FFd3_In1 : STATE_LOGIC
generic map(
INIT => X"0000000000005540"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd4_17,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd3_In
);
Mmux_aw_ready_c_0_2 : STATE_LOGIC
generic map(
INIT => X"BF3FBB33AF0FAA00"
)
port map (
I0 => S_AXI_BREADY,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd1_16,
I4 => present_state_FSM_FFd4_17,
I5 => NlwRenamedSig_OI_bvalid_c,
O => aw_ready_c
);
Mmux_addr_en_c_0_1 : STATE_LOGIC
generic map(
INIT => X"AAAAAAAA20000000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => bready_timeout_c,
I2 => present_state_FSM_FFd2_19,
I3 => S_AXI_WVALID,
I4 => w_last_c,
I5 => present_state_FSM_FFd4_17,
O => addr_en_c
);
Mmux_S_AXI_WR_EN_0_1 : STATE_LOGIC
generic map(
INIT => X"00000000000000A8"
)
port map (
I0 => S_AXI_WVALID,
I1 => present_state_FSM_FFd2_19,
I2 => present_state_FSM_FFd3_18,
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_WR_EN
);
Mmux_incr_addr_c_0_1 : STATE_LOGIC
generic map(
INIT => X"0000000000002220"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => incr_addr_c
);
Mmux_aw_ready_c_0_11 : STATE_LOGIC
generic map(
INIT => X"0000000000008880"
)
port map (
I0 => S_AXI_WVALID,
I1 => w_last_c,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => NlwRenamedSig_OI_bvalid_c
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"000000000000D5C0"
)
port map (
I0 => w_last_c,
I1 => S_AXI_AWVALID,
I2 => present_state_FSM_FFd4_17,
I3 => present_state_FSM_FFd3_18,
I4 => '0',
I5 => '0',
O => present_state_FSM_FFd2_In1_24
);
present_state_FSM_FFd2_In2 : STATE_LOGIC
generic map(
INIT => X"FFFFAAAA08AAAAAA"
)
port map (
I0 => present_state_FSM_FFd2_19,
I1 => S_AXI_AWVALID,
I2 => bready_timeout_c,
I3 => w_last_c,
I4 => S_AXI_WVALID,
I5 => present_state_FSM_FFd2_In1_24,
O => present_state_FSM_FFd2_In
);
present_state_FSM_FFd4_In1 : STATE_LOGIC
generic map(
INIT => X"00C0004000C00000"
)
port map (
I0 => S_AXI_AWVALID,
I1 => w_last_c,
I2 => S_AXI_WVALID,
I3 => bready_timeout_c,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => present_state_FSM_FFd4_In1_25
);
present_state_FSM_FFd4_In2 : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88F8"
)
port map (
I0 => present_state_FSM_FFd1_16,
I1 => S_AXI_BREADY,
I2 => present_state_FSM_FFd4_17,
I3 => S_AXI_AWVALID,
I4 => present_state_FSM_FFd4_In1_25,
I5 => '0',
O => present_state_FSM_FFd4_In
);
Mmux_w_ready_c_0_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => w_last_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_w_ready_c_0_Q : STATE_LOGIC
generic map(
INIT => X"FABAFABAFAAAF000"
)
port map (
I0 => N2,
I1 => bready_timeout_c,
I2 => S_AXI_AWVALID,
I3 => present_state_FSM_FFd4_17,
I4 => present_state_FSM_FFd3_18,
I5 => present_state_FSM_FFd2_19,
O => w_ready_c
);
Mmux_aw_ready_c_0_11_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => bready_timeout_c,
I1 => S_AXI_WVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
present_state_FSM_FFd1_In1 : STATE_LOGIC
generic map(
INIT => X"88808880FFFF8880"
)
port map (
I0 => w_last_c,
I1 => N4,
I2 => present_state_FSM_FFd2_19,
I3 => present_state_FSM_FFd3_18,
I4 => present_state_FSM_FFd1_16,
I5 => S_AXI_BREADY,
O => present_state_FSM_FFd1_In
);
END GENERATE gbeh_axi_full_sm;
end STRUCTURE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--AXI Behavioral Model entities
ENTITY blk_mem_axi_read_wrapper_beh is
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
port (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END blk_mem_axi_read_wrapper_beh;
architecture blk_mem_axi_read_wrapper_beh_arch of blk_mem_axi_read_wrapper_beh is
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
CONSTANT FLOP_DELAY : TIME := 100 PS;
CONSTANT ONE : std_logic_vector(7 DOWNTO 0) := ("00000001");
CONSTANT C_RANGE : INTEGER := if_then_else(C_WRITE_WIDTH_A=8,0,
if_then_else((C_WRITE_WIDTH_A=16),1,
if_then_else((C_WRITE_WIDTH_A=32),2,
if_then_else((C_WRITE_WIDTH_A=64),3,
if_then_else((C_WRITE_WIDTH_A=128),4,
if_then_else((C_WRITE_WIDTH_A=256),5,0))))));
SIGNAL ar_id_r : std_logic_vector (C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
SIGNAL addr_en_c : std_logic := '0';
SIGNAL rd_en_c : std_logic := '0';
SIGNAL incr_addr_c : std_logic := '0';
SIGNAL single_trans_c : std_logic := '0';
SIGNAL dec_alen_c : std_logic := '0';
SIGNAL mux_sel_c : std_logic := '0';
SIGNAL r_last_c : std_logic := '0';
SIGNAL r_last_int_c : std_logic := '0';
SIGNAL arlen_int_r : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL arlen_cntr : std_logic_vector(7 DOWNTO 0) := ONE;
SIGNAL arburst_int_c : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL arburst_int_r : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL araddr_reg : std_logic_vector(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),C_AXI_ARADDR_WIDTH,C_ADDRA_WIDTH)-1 DOWNTO 0);
SIGNAL num_of_bytes_c : integer := 0;
SIGNAL total_bytes : integer := 0;
SIGNAL num_of_bytes_r : integer := 0;
SIGNAL wrap_base_addr_r : integer := 0;
SIGNAL wrap_boundary_r : integer := 0;
SIGNAL arlen_int_c : std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL total_bytes_c : integer := 0;
SIGNAL wrap_base_addr_c : integer := 0;
SIGNAL wrap_boundary_c : integer := 0;
SIGNAL araddr_out : std_logic_vector(C_ADDRB_WIDTH-1 downto 0) := (OTHERS => '0');
COMPONENT read_netlist
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_INCR_ADDR : OUT std_logic := '0';
S_AXI_ADDR_EN : OUT std_logic := '0';
S_AXI_SINGLE_TRANS : OUT std_logic := '0';
S_AXI_MUX_SEL : OUT std_logic := '0';
S_AXI_R_LAST : OUT std_logic := '0';
S_AXI_R_LAST_INT : IN std_logic := '0';
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT read_netlist;
BEGIN
dec_alen_c <= incr_addr_c OR r_last_int_c;
axi_read_fsm : read_netlist
GENERIC MAP(
C_AXI_TYPE => 1,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
S_AXI_INCR_ADDR => incr_addr_c,
S_AXI_ADDR_EN => addr_en_c,
S_AXI_SINGLE_TRANS => single_trans_c,
S_AXI_MUX_SEL => mux_sel_c,
S_AXI_R_LAST => r_last_c,
S_AXI_R_LAST_INT => r_last_int_c,
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => S_ARESETN,
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => S_AXI_RLAST,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_RD_EN => rd_en_c
);
total_bytes <= conv_integer(num_of_bytes_r)*(conv_integer(arlen_int_r)+1);
wrap_base_addr_r <= (conv_integer(araddr_reg)/if_then_else(total_bytes=0,1,total_bytes))*(total_bytes);
wrap_boundary_r <= wrap_base_addr_r+total_bytes;
---- combinatorial from interface
num_of_bytes_c <= 2**conv_integer(if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARSIZE,"000"));
arlen_int_c <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
total_bytes_c <= conv_integer(num_of_bytes_c)*(conv_integer(arlen_int_c)+1);
wrap_base_addr_c <= (conv_integer(S_AXI_ARADDR)/if_then_else(total_bytes_c=0,1,total_bytes_c))*(total_bytes_c);
wrap_boundary_c <= wrap_base_addr_c+total_bytes_c;
arburst_int_c <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARBURST,"01");
---------------------------------------------------------------------------
-- BMG address generation
---------------------------------------------------------------------------
P_addr_reg: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN = '1') THEN
araddr_reg <= (OTHERS => '0');
arburst_int_r <= (OTHERS => '0');
num_of_bytes_r <= 0;
ELSIF (S_ACLK'event AND S_ACLK = '1') THEN
IF (incr_addr_c = '1' AND addr_en_c = '1' AND single_trans_c = '0') THEN
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
IF (arburst_int_c = "10") THEN
IF(conv_integer(S_AXI_ARADDR) = (wrap_boundary_c-num_of_bytes_c)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_c,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (arburst_int_c = "01" OR arburst_int_c = "11") THEN
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
END IF;
ELSIF (addr_en_c = '1') THEN
araddr_reg <= S_AXI_ARADDR AFTER FLOP_DELAY;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
ELSIF (incr_addr_c = '1') THEN
IF (arburst_int_r = "10") THEN
IF(conv_integer(araddr_reg) = (wrap_boundary_r-num_of_bytes_r)) THEN
araddr_reg <= conv_std_logic_vector(wrap_base_addr_r,C_AXI_ARADDR_WIDTH);
ELSE
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
ELSIF (arburst_int_r = "01" OR arburst_int_r = "11") THEN
araddr_reg <= araddr_reg + num_of_bytes_r;
END IF;
END IF;
END IF;
END PROCESS P_addr_reg;
araddr_out <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),araddr_reg(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),araddr_reg);
--------------------------------------------------------------------------
-- Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
--------------------------------------------------------------------------
P_addr_cnt: PROCESS (S_ACLK, S_ARESETN)
BEGIN
IF S_ARESETN = '1' THEN
arlen_cntr <= ONE;
arlen_int_r <= (OTHERS => '0');
ELSIF S_ACLK'event AND S_ACLK = '1' THEN
IF (addr_en_c = '1' AND dec_alen_c = '1' AND single_trans_c = '0') THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= S_AXI_ARLEN - ONE AFTER FLOP_DELAY;
ELSIF addr_en_c = '1' THEN
arlen_int_r <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
arlen_cntr <= if_then_else(C_AXI_TYPE = 0,"00000000",S_AXI_ARLEN);
ELSIF dec_alen_c = '1' THEN
arlen_cntr <= arlen_cntr - ONE AFTER FLOP_DELAY;
ELSE
arlen_cntr <= arlen_cntr AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS P_addr_cnt;
r_last_int_c <= '1' WHEN (arlen_cntr = "00000000" AND S_AXI_RREADY = '1') ELSE '0' ;
--------------------------------------------------------------------------
-- AXI FULL FSM
-- Mux Selection of ARADDR
-- ARADDR is driven out from the read fsm based on the mux_sel_c
-- Based on mux_sel either ARADDR is given out or the latched ARADDR is
-- given out to BRAM
--------------------------------------------------------------------------
P_araddr_mux: PROCESS (mux_sel_c,S_AXI_ARADDR,araddr_out)
BEGIN
IF (mux_sel_c = '0') THEN
S_AXI_ARADDR_OUT <= if_then_else((C_AXI_TYPE = 1 AND C_AXI_SLAVE_TYPE = 0),S_AXI_ARADDR(C_AXI_ARADDR_WIDTH-1 DOWNTO C_RANGE),S_AXI_ARADDR);
ELSE
S_AXI_ARADDR_OUT <= araddr_out;
END IF;
END PROCESS P_araddr_mux;
--------------------------------------------------------------------------
-- Assign output signals - AXI FULL FSM
--------------------------------------------------------------------------
S_AXI_RD_EN <= rd_en_c;
grid: IF (C_HAS_AXI_ID = 1) GENERATE
P_rid_gen: PROCESS (S_ACLK,S_ARESETN)
BEGIN
IF (S_ARESETN='1') THEN
S_AXI_RID <= (OTHERS => '0');
ar_id_r <= (OTHERS => '0');
ELSIF (S_ACLK'event AND S_ACLK='1') THEN
IF (addr_en_c = '1' AND rd_en_c = '1') THEN
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
ELSIF (addr_en_c = '1' AND rd_en_c = '0') THEN
ar_id_r <= S_AXI_ARID;
ELSIF (rd_en_c = '1') THEN
S_AXI_RID <= ar_id_r;
END IF;
END IF;
END PROCESS P_rid_gen;
END GENERATE grid;
END blk_mem_axi_read_wrapper_beh_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity read_netlist is
GENERIC (
-- AXI Interface related parameters start here
C_AXI_TYPE : integer := 1;
C_ADDRB_WIDTH : integer := 12
);
port (
S_AXI_R_LAST_INT : in STD_LOGIC := '0';
S_ACLK : in STD_LOGIC := '0';
S_ARESETN : in STD_LOGIC := '0';
S_AXI_ARVALID : in STD_LOGIC := '0';
S_AXI_RREADY : in STD_LOGIC := '0';
S_AXI_INCR_ADDR : out STD_LOGIC;
S_AXI_ADDR_EN : out STD_LOGIC;
S_AXI_SINGLE_TRANS : out STD_LOGIC;
S_AXI_MUX_SEL : out STD_LOGIC;
S_AXI_R_LAST : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RLAST : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_RD_EN : out STD_LOGIC;
S_AXI_ARLEN : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end read_netlist;
architecture STRUCTURE of read_netlist is
component beh_muxf7
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end component;
COMPONENT beh_ff_pre
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end COMPONENT beh_ff_pre;
COMPONENT beh_ff_ce
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_ce;
COMPONENT beh_ff_clr
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end COMPONENT beh_ff_clr;
COMPONENT STATE_LOGIC
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
I4 : in std_logic;
I5 : in std_logic
);
end COMPONENT STATE_LOGIC;
signal present_state_FSM_FFd1_13 : STD_LOGIC;
signal present_state_FSM_FFd2_14 : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_r_15 : STD_LOGIC;
signal gaxi_full_sm_ar_ready_r_16 : STD_LOGIC;
signal gaxi_full_sm_r_last_r_17 : STD_LOGIC;
signal NlwRenamedSig_OI_gaxi_full_sm_r_valid_r : STD_LOGIC;
signal gaxi_full_sm_r_valid_c : STD_LOGIC;
signal S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o : STD_LOGIC;
signal gaxi_full_sm_ar_ready_c : STD_LOGIC;
signal gaxi_full_sm_outstanding_read_c : STD_LOGIC;
signal NlwRenamedSig_OI_S_AXI_R_LAST : STD_LOGIC;
signal S_AXI_ARLEN_7_GND_8_o_equal_1_o : STD_LOGIC;
signal present_state_FSM_FFd2_In : STD_LOGIC;
signal present_state_FSM_FFd1_In : STD_LOGIC;
signal Mmux_S_AXI_R_LAST13 : STD_LOGIC;
signal N01 : STD_LOGIC;
signal N2 : STD_LOGIC;
signal Mmux_gaxi_full_sm_ar_ready_c11 : STD_LOGIC;
signal N4 : STD_LOGIC;
signal N8 : STD_LOGIC;
signal N9 : STD_LOGIC;
signal N10 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N12 : STD_LOGIC;
signal N13 : STD_LOGIC;
begin
S_AXI_R_LAST <= NlwRenamedSig_OI_S_AXI_R_LAST;
S_AXI_ARREADY <= gaxi_full_sm_ar_ready_r_16;
S_AXI_RLAST <= gaxi_full_sm_r_last_r_17;
S_AXI_RVALID <= NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
gaxi_full_sm_outstanding_read_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_outstanding_read_c,
Q => gaxi_full_sm_outstanding_read_r_15
);
gaxi_full_sm_r_valid_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => gaxi_full_sm_r_valid_c,
Q => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r
);
gaxi_full_sm_ar_ready_r : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => gaxi_full_sm_ar_ready_c,
Q => gaxi_full_sm_ar_ready_r_16
);
gaxi_full_sm_r_last_r : beh_ff_ce
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CE => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
CLR => S_ARESETN,
D => NlwRenamedSig_OI_S_AXI_R_LAST,
Q => gaxi_full_sm_r_last_r_17
);
present_state_FSM_FFd2 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd2_In,
Q => present_state_FSM_FFd2_14
);
present_state_FSM_FFd1 : beh_ff_clr
generic map(
INIT => '0'
)
port map (
C => S_ACLK,
CLR => S_ARESETN,
D => present_state_FSM_FFd1_In,
Q => present_state_FSM_FFd1_13
);
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 : STATE_LOGIC
generic map(
INIT => X"000000000000000B"
)
port map (
I0 => S_AXI_RREADY,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o
);
Mmux_S_AXI_SINGLE_TRANS11 : STATE_LOGIC
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_SINGLE_TRANS
);
Mmux_S_AXI_ADDR_EN11 : STATE_LOGIC
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => S_AXI_ADDR_EN
);
present_state_FSM_FFd2_In1 : STATE_LOGIC
generic map(
INIT => X"ECEE2022EEEE2022"
)
port map (
I0 => S_AXI_ARVALID,
I1 => present_state_FSM_FFd1_13,
I2 => S_AXI_RREADY,
I3 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I4 => present_state_FSM_FFd2_14,
I5 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
O => present_state_FSM_FFd2_In
);
Mmux_S_AXI_R_LAST131 : STATE_LOGIC
generic map(
INIT => X"0000000044440444"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_RREADY,
I5 => '0',
O => Mmux_S_AXI_R_LAST13
);
Mmux_S_AXI_INCR_ADDR11 : STATE_LOGIC
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => S_AXI_R_LAST_INT,
I1 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => Mmux_S_AXI_R_LAST13,
O => S_AXI_INCR_ADDR
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000FE"
)
port map (
I0 => S_AXI_ARLEN(2),
I1 => S_AXI_ARLEN(1),
I2 => S_AXI_ARLEN(0),
I3 => '0',
I4 => '0',
I5 => '0',
O => N01
);
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q : STATE_LOGIC
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => S_AXI_ARLEN(7),
I1 => S_AXI_ARLEN(6),
I2 => S_AXI_ARLEN(5),
I3 => S_AXI_ARLEN(4),
I4 => S_AXI_ARLEN(3),
I5 => N01,
O => S_AXI_ARLEN_7_GND_8_o_equal_1_o
);
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 : STATE_LOGIC
generic map(
INIT => X"0000000000000007"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I2 => '0',
I3 => '0',
I4 => '0',
I5 => '0',
O => N2
);
Mmux_gaxi_full_sm_outstanding_read_c1 : STATE_LOGIC
generic map(
INIT => X"0020000002200200"
)
port map (
I0 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd1_13,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => N2,
O => gaxi_full_sm_outstanding_read_c
);
Mmux_gaxi_full_sm_ar_ready_c12 : STATE_LOGIC
generic map(
INIT => X"0000000000004555"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => '0',
I5 => '0',
O => Mmux_gaxi_full_sm_ar_ready_c11
);
Mmux_S_AXI_R_LAST11_SW0 : STATE_LOGIC
generic map(
INIT => X"00000000000000EF"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I3 => '0',
I4 => '0',
I5 => '0',
O => N4
);
Mmux_S_AXI_R_LAST11 : STATE_LOGIC
generic map(
INIT => X"FCAAFC0A00AA000A"
)
port map (
I0 => S_AXI_ARVALID,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => present_state_FSM_FFd2_14,
I3 => present_state_FSM_FFd1_13,
I4 => N4,
I5 => S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o,
O => gaxi_full_sm_r_valid_c
);
S_AXI_MUX_SEL1 : STATE_LOGIC
generic map(
INIT => X"00000000AAAAAA08"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => present_state_FSM_FFd2_14,
I4 => gaxi_full_sm_outstanding_read_r_15,
I5 => '0',
O => S_AXI_MUX_SEL
);
Mmux_S_AXI_RD_EN11 : STATE_LOGIC
generic map(
INIT => X"F3F3F755A2A2A200"
)
port map (
I0 => present_state_FSM_FFd1_13,
I1 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I2 => S_AXI_RREADY,
I3 => gaxi_full_sm_outstanding_read_r_15,
I4 => present_state_FSM_FFd2_14,
I5 => S_AXI_ARVALID,
O => S_AXI_RD_EN
);
present_state_FSM_FFd1_In3 : beh_muxf7
port map (
I0 => N8,
I1 => N9,
S => present_state_FSM_FFd1_13,
O => present_state_FSM_FFd1_In
);
present_state_FSM_FFd1_In3_F : STATE_LOGIC
generic map(
INIT => X"000000005410F4F0"
)
port map (
I0 => S_AXI_RREADY,
I1 => present_state_FSM_FFd2_14,
I2 => S_AXI_ARVALID,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I5 => '0',
O => N8
);
present_state_FSM_FFd1_In3_G : STATE_LOGIC
generic map(
INIT => X"0000000072FF7272"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N9
);
Mmux_gaxi_full_sm_ar_ready_c14 : beh_muxf7
port map (
I0 => N10,
I1 => N11,
S => present_state_FSM_FFd1_13,
O => gaxi_full_sm_ar_ready_c
);
Mmux_gaxi_full_sm_ar_ready_c14_F : STATE_LOGIC
generic map(
INIT => X"00000000FFFF88A8"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_RREADY,
I2 => present_state_FSM_FFd2_14,
I3 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I4 => Mmux_gaxi_full_sm_ar_ready_c11,
I5 => '0',
O => N10
);
Mmux_gaxi_full_sm_ar_ready_c14_G : STATE_LOGIC
generic map(
INIT => X"000000008D008D8D"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => S_AXI_R_LAST_INT,
I2 => gaxi_full_sm_outstanding_read_r_15,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N11
);
Mmux_S_AXI_R_LAST1 : beh_muxf7
port map (
I0 => N12,
I1 => N13,
S => present_state_FSM_FFd1_13,
O => NlwRenamedSig_OI_S_AXI_R_LAST
);
Mmux_S_AXI_R_LAST1_F : STATE_LOGIC
generic map(
INIT => X"0000000088088888"
)
port map (
I0 => S_AXI_ARLEN_7_GND_8_o_equal_1_o,
I1 => S_AXI_ARVALID,
I2 => present_state_FSM_FFd2_14,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N12
);
Mmux_S_AXI_R_LAST1_G : STATE_LOGIC
generic map(
INIT => X"00000000E400E4E4"
)
port map (
I0 => present_state_FSM_FFd2_14,
I1 => gaxi_full_sm_outstanding_read_r_15,
I2 => S_AXI_R_LAST_INT,
I3 => S_AXI_RREADY,
I4 => NlwRenamedSig_OI_gaxi_full_sm_r_valid_r,
I5 => '0',
O => N13
);
end STRUCTURE;
-------------------------------------------------------------------------------
-- Output Register Stage Entity
--
-- This module builds the output register stages of the memory. This module is
-- instantiated in the main memory module (blk_mem_gen_v8_3_1) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_output_stage IS
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_output_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6" and "virtex6l".
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
-- C_HAS_RST : Determines the presence of the RST port
-- C_RSTRAM : Determines if special reset behavior is used
-- C_RST_PRIORITY : Determines the priority between CE and SR
-- C_INIT_VAL : Initialization value
-- C_HAS_EN : Determines the presence of the EN port
-- C_HAS_REGCE : Determines the presence of the REGCE port
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
-- of the RAM primitive
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- NUM_STAGES : Determines the number of output stages
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE output_stage_behavioral OF blk_mem_gen_v8_3_1_output_stage IS
--*******************************************************
-- Functions used in the output stage ARCHITECTURE
--*******************************************************
-- Calculate num_reg_stages
FUNCTION get_num_reg_stages(NUM_STAGES: INTEGER) RETURN INTEGER IS
VARIABLE num_reg_stages : INTEGER := 0;
BEGIN
IF (NUM_STAGES = 0) THEN
num_reg_stages := 0;
ELSE
num_reg_stages := NUM_STAGES - 1;
END IF;
RETURN num_reg_stages;
END get_num_reg_stages;
-- Check if the INTEGER is zero or non-zero
FUNCTION int_to_bit(input: INTEGER) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = 0) THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END int_to_bit;
-- Constants
CONSTANT HAS_EN : STD_LOGIC := int_to_bit(C_HAS_EN);
CONSTANT HAS_REGCE : STD_LOGIC := int_to_bit(C_HAS_REGCE);
CONSTANT HAS_RST : STD_LOGIC := int_to_bit(C_HAS_RST);
CONSTANT REG_STAGES : INTEGER := get_num_reg_stages(NUM_STAGES);
-- Pipeline array
TYPE reg_data_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
TYPE reg_ecc_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC;
TYPE reg_eccaddr_array IS ARRAY (REG_STAGES-1 DOWNTO 0) OF STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
CONSTANT REG_INIT : reg_data_array := (OTHERS => init_val);
SIGNAL out_regs : reg_data_array := REG_INIT;
SIGNAL sbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL dbiterr_regs : reg_ecc_array := (OTHERS => '0');
SIGNAL rdaddrecc_regs: reg_eccaddr_array := (OTHERS => (OTHERS => '0'));
-- Internal signals
SIGNAL en_i : STD_LOGIC;
SIGNAL regce_i : STD_LOGIC;
SIGNAL rst_i : STD_LOGIC;
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := init_val;
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL DIN : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL RDADDRECC_IN : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0') ;
SIGNAL SBITERR_IN : STD_LOGIC := '0';
SIGNAL DBITERR_IN : STD_LOGIC := '0';
BEGIN
--***********************************************************************
-- Assign internal signals. This effectively wires off optional inputs.
--***********************************************************************
-- Internal enable for output registers is tied to user EN or '1' depending
-- on parameters
en_i <= EN OR (NOT HAS_EN);
-- Internal register enable for output registers is tied to user REGCE, EN
-- or '1' depending on parameters
regce_i <= (HAS_REGCE AND REGCE)
OR ((NOT HAS_REGCE) AND en_i);
-- Internal SRR is tied to user RST or '0' depending on parameters
rst_i <= RST AND HAS_RST;
--***************************************************************************
-- NUM_STAGES = 0 (No output registers. RAM only)
--***************************************************************************
zero_stages: IF (NUM_STAGES = 0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE zero_stages;
NO_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 0) GENERATE
DIN <= DIN_I;
RDADDRECC_IN <= RDADDRECC_IN_I;
SBITERR_IN <= SBITERR_IN_I;
DBITERR_IN <= DBITERR_IN_I;
END GENERATE NO_ECC_PIPE_REG;
WITH_ECC_PIPE_REG: IF (C_EN_ECC_PIPE = 1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(ECCPIPECE = '1') THEN
DIN <= DIN_I AFTER FLOP_DELAY;
RDADDRECC_IN <= RDADDRECC_IN_I AFTER FLOP_DELAY;
SBITERR_IN <= SBITERR_IN_I AFTER FLOP_DELAY;
DBITERR_IN <= DBITERR_IN_I AFTER FLOP_DELAY;
END IF;
END IF;
END PROCESS;
END GENERATE WITH_ECC_PIPE_REG;
--***************************************************************************
-- NUM_STAGES = 1
-- (Mem Output Reg only or Mux Output Reg only)
--***************************************************************************
-- Possible valid combinations:
-- Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
-- +-----------------------------------------+
-- | C_RSTRAM_* | Reset Behavior |
-- +----------------+------------------------+
-- | 0 | Normal Behavior |
-- +----------------+------------------------+
-- | 1 | Special Behavior |
-- +----------------+------------------------+
--
-- Normal = REGCE gates reset, as in the case of all Virtex families and all
-- spartan families with the exception of S3ADSP and S6.
-- Special = EN gates reset, as in the case of S3ADSP and S6.
one_stage_norm: IF (NUM_STAGES = 1 AND
(C_RSTRAM=0 OR (C_RSTRAM=1 AND (C_XDEVICEFAMILY/="spartan3adsp" AND C_XDEVICEFAMILY/="aspartan3adsp")) OR
C_HAS_MEM_OUTPUT_REGS=0 OR C_HAS_RST=0)) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_i WHEN (C_USE_ECC=1 OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i = '1' AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
END IF;--CLK
END PROCESS;
END GENERATE one_stage_norm;
-- Special Reset Behavior for S6 and S3ADSP
one_stage_splbhv: IF (NUM_STAGES=1 AND C_RSTRAM=1 AND (C_XDEVICEFAMILY ="spartan3adsp" OR C_XDEVICEFAMILY ="aspartan3adsp"))
GENERATE
DOUT <= dout_i;
SBITERR <= '0';
DBITERR <= '0';
RDADDRECC <= (OTHERS => '0');
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF (rst_i='1' AND en_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
ELSIF (regce_i='1' AND rst_i/='1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE one_stage_splbhv;
--****************************************************************************
-- NUM_STAGES > 1
-- Mem Output Reg + Mux Output Reg
-- or
-- Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
-- or
-- Mux Pipeline Stages (>0) + Mux Output Reg
--****************************************************************************
multi_stage: IF (NUM_STAGES > 1) GENERATE
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
PROCESS (CLK,rst_i,regce_i)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF(C_RST_PRIORITY = "CE") THEN --REGCE has priority and controls reset
IF (rst_i='1'AND regce_i='1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
ELSE --RSTA has priority and is independent of REGCE
IF (rst_i = '1') THEN
dout_i <= init_val AFTER FLOP_DELAY;
sbiterr_i <= '0' AFTER FLOP_DELAY;
dbiterr_i <= '0' AFTER FLOP_DELAY;
rdaddrecc_i <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSIF (regce_i='1') THEN
dout_i <= out_regs(REG_STAGES-1) AFTER FLOP_DELAY;
sbiterr_i <= sbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
dbiterr_i <= dbiterr_regs(REG_STAGES-1) AFTER FLOP_DELAY;
rdaddrecc_i <= rdaddrecc_regs(REG_STAGES-1) AFTER FLOP_DELAY;
END IF;
END IF;--Priority conditions
IF (en_i='1') THEN
-- Shift the data through the output stages
FOR i IN 1 TO REG_STAGES-1 LOOP
out_regs(i) <= out_regs(i-1) AFTER FLOP_DELAY;
sbiterr_regs(i) <= sbiterr_regs(i-1) AFTER FLOP_DELAY;
dbiterr_regs(i) <= dbiterr_regs(i-1) AFTER FLOP_DELAY;
rdaddrecc_regs(i) <= rdaddrecc_regs(i-1) AFTER FLOP_DELAY;
END LOOP;
out_regs(0) <= DIN;
sbiterr_regs(0) <= SBITERR_IN;
dbiterr_regs(0) <= DBITERR_IN;
rdaddrecc_regs(0) <= RDADDRECC_IN;
END IF;
END IF;--CLK
END PROCESS;
END GENERATE multi_stage;
END output_stage_behavioral;
-------------------------------------------------------------------------------
-- SoftECC Output Register Stage Entity
-- This module builds the softecc output register stages. This module is
-- instantiated in the memory module (blk_mem_gen_v8_3_1_mem_module) which is
-- declared/implemented further down in this file.
-------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) ;
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) ;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_DATA_WIDTH : Memory write/read width
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- of the RAM primitive
-- FLOP_DELAY : Constant delay for register assignments
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLK : Clock to synchronize all read and write operations
-- RST : Reset input to reset memory outputs to a user-defined
-- reset state
-- EN : Enable all read and write operations
-- REGCE : Register Clock Enable to control each pipeline output
-- register stages
-- DIN : Data input to the Output stage.
-- DOUT : Final Data output
-- SBITERR_IN : SBITERR input signal to the Output stage.
-- SBITERR : Final SBITERR Output signal.
-- DBITERR_IN : DBITERR input signal to the Output stage.
-- DBITERR : Final DBITERR Output signal.
-- RDADDRECC_IN : RDADDRECC input signal to the Output stage.
-- RDADDRECC : Final RDADDRECC Output signal.
---------------------------------------------------------------------------
ARCHITECTURE softecc_output_reg_stage_behavioral OF blk_mem_gen_v8_3_1_softecc_output_reg_stage IS
-- Internal signals
SIGNAL dout_i : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i: STD_LOGIC := '0';
SIGNAL dbiterr_i: STD_LOGIC := '0';
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
--***************************************************************************
-- NO OUTPUT STAGES
--***************************************************************************
no_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=0) GENERATE
DOUT <= DIN;
SBITERR <= SBITERR_IN;
DBITERR <= DBITERR_IN;
RDADDRECC <= RDADDRECC_IN;
END GENERATE no_output_stage;
--****************************************************************************
-- WITH OUTPUT STAGE
--****************************************************************************
has_output_stage: IF (C_HAS_SOFTECC_OUTPUT_REGS_B=1) GENERATE
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
dout_i <= DIN AFTER FLOP_DELAY;
sbiterr_i <= SBITERR_IN AFTER FLOP_DELAY;
dbiterr_i <= DBITERR_IN AFTER FLOP_DELAY;
rdaddrecc_i <= RDADDRECC_IN AFTER FLOP_DELAY;
END IF;
END PROCESS;
DOUT <= dout_i;
SBITERR <= sbiterr_i;
DBITERR <= dbiterr_i;
RDADDRECC <= rdaddrecc_i;
END GENERATE has_output_stage;
END softecc_output_reg_stage_behavioral;
--******************************************************************************
-- Main Memory module
--
-- This module is the behavioral model which implements the RAM
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
ENTITY blk_mem_gen_v8_3_1_mem_module IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END blk_mem_gen_v8_3_1_mem_module;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE mem_module_behavioral OF blk_mem_gen_v8_3_1_mem_module IS
--****************************************
-- min/max constant functions
--****************************************
-- get_max
----------
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
FUNCTION get_max(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a > b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
-- get_min
----------
FUNCTION get_min(a: INTEGER; b: INTEGER) RETURN INTEGER IS
BEGIN
IF (a < b) THEN
RETURN a;
ELSE
RETURN b;
END IF;
END FUNCTION;
--***************************************************************
-- convert write_mode from STRING type for use in case statement
--***************************************************************
FUNCTION write_mode_to_vector(mode: STRING) RETURN STD_LOGIC_VECTOR IS
BEGIN
IF (mode = "NO_CHANGE") THEN
RETURN "10";
ELSIF (mode = "READ_FIRST") THEN
RETURN "01";
ELSE
RETURN "00"; -- WRITE_FIRST
END IF;
END FUNCTION;
--***************************************************************
-- convert hex STRING to STD_LOGIC_VECTOR
--***************************************************************
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
--***************************************************************
-- locally derived constants to determine memory shape
--***************************************************************
CONSTANT MIN_WIDTH_A : INTEGER := get_min(C_WRITE_WIDTH_A, C_READ_WIDTH_A);
CONSTANT MIN_WIDTH_B : INTEGER := get_min(C_WRITE_WIDTH_B,C_READ_WIDTH_B);
CONSTANT MIN_WIDTH : INTEGER := get_min(MIN_WIDTH_A, MIN_WIDTH_B);
CONSTANT MAX_DEPTH_A : INTEGER := get_max(C_WRITE_DEPTH_A, C_READ_DEPTH_A);
CONSTANT MAX_DEPTH_B : INTEGER := get_max(C_WRITE_DEPTH_B, C_READ_DEPTH_B);
CONSTANT MAX_DEPTH : INTEGER := get_max(MAX_DEPTH_A, MAX_DEPTH_B);
TYPE int_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF std_logic_vector(C_WRITE_WIDTH_A-1 DOWNTO 0);
TYPE mem_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC_VECTOR(MIN_WIDTH-1 DOWNTO 0);
TYPE ecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
TYPE softecc_err_array IS ARRAY (MAX_DEPTH-1 DOWNTO 0) OF STD_LOGIC;
--***************************************************************
-- memory initialization function
--***************************************************************
IMPURE FUNCTION init_memory(DEFAULT_DATA :
STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
write_width_a : INTEGER;
depth : INTEGER;
width : INTEGER)
RETURN mem_array IS
VARIABLE init_return : mem_array := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(write_width_a-1 DOWNTO 0);
VARIABLE int_mem_vector : int_array:= (OTHERS => (OTHERS => '0'));
VARIABLE file_buffer : LINE;
VARIABLE i : INTEGER := 0;
VARIABLE j : INTEGER;
VARIABLE k : INTEGER;
VARIABLE ignore_line : BOOLEAN := false;
VARIABLE good_data : BOOLEAN := false;
VARIABLE char_tmp : CHARACTER;
VARIABLE index : INTEGER;
variable init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable data : std_logic_vector(255 downto 0) := (others => '0');
variable inside_init_addr_slv : std_logic_vector(31 downto 0) := (others => '0');
variable k_slv : std_logic_vector(31 downto 0) := (others => '0');
variable i_slv : std_logic_vector(31 downto 0) := (others => '0');
VARIABLE disp_line : line := null;
variable open_status : file_open_status;
variable input_initf_tmp : mem_array ;
variable input_initf : mem_array := (others => (others => '0'));
file int_infile : text;
variable data_line, data_line_tmp, out_data_line : line;
variable slv_width : integer;
VARIABLE d_l : LINE;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
index := 0;
FOR i IN 0 TO depth-1 LOOP
FOR j IN 0 TO width-1 LOOP
init_return(i)(j) := DEFAULT_DATA(index);
index := (index + 1) MOD C_WRITE_WIDTH_A;
END LOOP;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, file_buffer);
read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO write_width_a-1 LOOP
IF (j MOD width = 0 AND j /= 0) THEN
i := i + 1;
END IF;
init_return(i)(j MOD width) := bit_to_sl(mem_vector(j));
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
--Display output message indicating that the behavioral model is done
--initializing
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator data initialization complete." SEVERITY NOTE;
if (C_USE_BRAM_BLOCK = 1) then
--Display output message indicating that the behavioral model is being
--initialized
-- Read in the .mem file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_INIT_FILE /= "NONE") then
file_open(open_status, int_infile, C_INIT_FILE, read_mode);
while not endfile(int_infile) loop
readline(int_infile, data_line);
while (data_line /= null and data_line'length > 0) loop
if (data_line(data_line'low to data_line'low + 1) = "//") then
deallocate(data_line);
elsif ((data_line(data_line'low to data_line'low + 1) = "/*") and (data_line(data_line'high-1 to data_line'high) = "*/")) then
deallocate(data_line);
elsif (data_line(data_line'low to data_line'low + 1) = "/*") then
deallocate(data_line);
ignore_line := true;
elsif (ignore_line = true and data_line(data_line'high-1 to data_line'high) = "*/") then
deallocate(data_line);
ignore_line := false;
elsif (ignore_line = false and data_line(data_line'low) = '@') then
read(data_line, char_tmp);
hread(data_line, init_addr_slv, good_data);
i := SLV_TO_INT(init_addr_slv);
elsif (ignore_line = false) then
hread(data_line, input_initf_tmp(i), good_data);
init_return(i)(write_width_a - 1 downto 0) := input_initf_tmp(i)(write_width_a - 1 downto 0);
if (good_data = true) then
i := i + 1;
end if;
else
deallocate(data_line);
end if;
end loop;
end loop;
file_close(int_infile);
END IF;
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- memory type constants
--***************************************************************
CONSTANT MEM_TYPE_SP_RAM : INTEGER := 0;
CONSTANT MEM_TYPE_SDP_RAM : INTEGER := 1;
CONSTANT MEM_TYPE_TDP_RAM : INTEGER := 2;
CONSTANT MEM_TYPE_SP_ROM : INTEGER := 3;
CONSTANT MEM_TYPE_DP_ROM : INTEGER := 4;
--***************************************************************
-- memory configuration constant functions
--***************************************************************
--get_single_port
-----------------
FUNCTION get_single_port(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_RAM OR mem_type=MEM_TYPE_SP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_single_port;
--get_is_rom
--------------
FUNCTION get_is_rom(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SP_ROM OR mem_type=MEM_TYPE_DP_ROM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_is_rom;
--get_has_a_write
------------------
FUNCTION get_has_a_write(IS_ROM : INTEGER) RETURN INTEGER IS
BEGIN
IF (IS_ROM=0) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_a_write;
--get_has_b_write
------------------
FUNCTION get_has_b_write(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_TDP_RAM) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_write;
--get_has_a_read
------------------
FUNCTION get_has_a_read(mem_type : INTEGER) RETURN INTEGER IS
BEGIN
IF (mem_type=MEM_TYPE_SDP_RAM) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_a_read;
--get_has_b_read
------------------
FUNCTION get_has_b_read(SINGLE_PORT : INTEGER) RETURN INTEGER IS
BEGIN
IF (SINGLE_PORT=1) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END get_has_b_read;
--get_has_b_port
------------------
FUNCTION get_has_b_port(HAS_B_READ : INTEGER;
HAS_B_WRITE : INTEGER)
RETURN INTEGER IS
BEGIN
IF (HAS_B_READ=1 OR HAS_B_WRITE=1) THEN
RETURN 1;
ELSE
RETURN 0;
END IF;
END get_has_b_port;
--get_num_output_stages
-----------------------
FUNCTION get_num_output_stages(has_mem_output_regs : INTEGER;
has_mux_output_regs : INTEGER;
mux_pipeline_stages : INTEGER)
RETURN INTEGER IS
VARIABLE actual_mux_pipeline_stages : INTEGER;
BEGIN
-- Mux pipeline stages can be non-zero only when there is a mux
-- output register.
IF (has_mux_output_regs=1) THEN
actual_mux_pipeline_stages := mux_pipeline_stages;
ELSE
actual_mux_pipeline_stages := 0;
END IF;
RETURN has_mem_output_regs+actual_mux_pipeline_stages+has_mux_output_regs;
END get_num_output_stages;
--***************************************************************************
-- Component declaration of the VARIABLE depth output register stage
--***************************************************************************
COMPONENT blk_mem_gen_v8_3_1_output_stage
GENERIC (
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RST : INTEGER := 0;
C_RSTRAM : INTEGER := 0;
C_RST_PRIORITY : STRING := "CE";
init_val : STD_LOGIC_VECTOR;
C_HAS_EN : INTEGER := 0;
C_HAS_REGCE : INTEGER := 0;
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_MEM_OUTPUT_REGS : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
NUM_STAGES : INTEGER := 1;
C_EN_ECC_PIPE : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
REGCE : IN STD_LOGIC;
EN : IN STD_LOGIC;
DIN_I : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN_I : IN STD_LOGIC;
DBITERR_IN_I : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN_I : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
ECCPIPECE : IN STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_output_stage;
COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC (
C_DATA_WIDTH : INTEGER := 32;
C_ADDRB_WIDTH : INTEGER := 10;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
FLOP_DELAY : TIME := 100 ps
);
PORT (
CLK : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
SBITERR_IN : IN STD_LOGIC;
DBITERR_IN : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC_IN : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_softecc_output_reg_stage;
--******************************************************
-- locally derived constants to assist memory access
--******************************************************
CONSTANT WRITE_WIDTH_RATIO_A : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_A : INTEGER := C_READ_WIDTH_A/MIN_WIDTH;
CONSTANT WRITE_WIDTH_RATIO_B : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH;
CONSTANT READ_WIDTH_RATIO_B : INTEGER := C_READ_WIDTH_B/MIN_WIDTH;
--******************************************************
-- To modify the LSBs of the 'wider' data to the actual
-- address value
--******************************************************
CONSTANT WRITE_ADDR_A_DIV : INTEGER := C_WRITE_WIDTH_A/MIN_WIDTH_A;
CONSTANT READ_ADDR_A_DIV : INTEGER := C_READ_WIDTH_A/MIN_WIDTH_A;
CONSTANT WRITE_ADDR_B_DIV : INTEGER := C_WRITE_WIDTH_B/MIN_WIDTH_B;
CONSTANT READ_ADDR_B_DIV : INTEGER := C_READ_WIDTH_B/MIN_WIDTH_B;
--******************************************************
-- FUNCTION : log2roundup
--******************************************************
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
--******************************************************
-- Other constants and signals
--******************************************************
CONSTANT COLL_DELAY : TIME := 100 ps;
-- default data vector
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_DEFAULT_DATA,
C_WRITE_WIDTH_A);
CONSTANT CHKBIT_WIDTH : INTEGER := if_then_else(C_WRITE_WIDTH_A>57,8,if_then_else(C_WRITE_WIDTH_A>26,7,if_then_else(C_WRITE_WIDTH_A>11,6,if_then_else(C_WRITE_WIDTH_A>4,5,if_then_else(C_WRITE_WIDTH_A<5,4,0)))));
-- the init memory SIGNAL
SIGNAL memory_i : mem_array;
SIGNAL doublebit_error_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0);
SIGNAL current_contents_i : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
-- write mode constants
CONSTANT WRITE_MODE_A : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_A);
CONSTANT WRITE_MODE_B : STD_LOGIC_VECTOR(1 DOWNTO 0) :=
write_mode_to_vector(C_WRITE_MODE_B);
CONSTANT WRITE_MODES : STD_LOGIC_VECTOR(3 DOWNTO 0) :=
WRITE_MODE_A & WRITE_MODE_B;
-- reset values
CONSTANT INITA_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITA_VAL,
C_READ_WIDTH_A);
CONSTANT INITB_VAL : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0)
:= hex_to_std_logic_vector(C_INITB_VAL,
C_READ_WIDTH_B);
-- memory output 'latches'
SIGNAL memory_out_a : STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0) :=
INITA_VAL;
SIGNAL memory_out_b : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) :=
INITB_VAL;
SIGNAL sbiterr_in : STD_LOGIC := '0';
SIGNAL sbiterr_sdp : STD_LOGIC := '0';
SIGNAL dbiterr_in : STD_LOGIC := '0';
SIGNAL dbiterr_sdp : STD_LOGIC := '0';
SIGNAL rdaddrecc_in : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_sdp : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL doutb_i : STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL sbiterr_i : STD_LOGIC := '0';
SIGNAL dbiterr_i : STD_LOGIC := '0';
-- memory configuration constants
-----------------------------------------------
CONSTANT SINGLE_PORT : INTEGER := get_single_port(C_MEM_TYPE);
CONSTANT IS_ROM : INTEGER := get_is_rom(C_MEM_TYPE);
CONSTANT HAS_A_WRITE : INTEGER := get_has_a_write(IS_ROM);
CONSTANT HAS_B_WRITE : INTEGER := get_has_b_write(C_MEM_TYPE);
CONSTANT HAS_A_READ : INTEGER := get_has_a_read(C_MEM_TYPE);
CONSTANT HAS_B_READ : INTEGER := get_has_b_read(SINGLE_PORT);
CONSTANT HAS_B_PORT : INTEGER := get_has_b_port(HAS_B_READ, HAS_B_WRITE);
CONSTANT NUM_OUTPUT_STAGES_A : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_A, C_HAS_MUX_OUTPUT_REGS_A,
C_MUX_PIPELINE_STAGES);
CONSTANT NUM_OUTPUT_STAGES_B : INTEGER :=
get_num_output_stages(C_HAS_MEM_OUTPUT_REGS_B, C_HAS_MUX_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES);
CONSTANT WEA0 : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT WEB0 : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- DEBUG CONTROL
-- DEBUG=0 : Debug output OFF
-- DEBUG=1 : Some debug info printed
-----------------------------------------------------------------------------
CONSTANT DEBUG : INTEGER := 0;
-- internal signals
-----------------------------------------------
SIGNAL ena_i : STD_LOGIC;
SIGNAL enb_i : STD_LOGIC;
SIGNAL reseta_i : STD_LOGIC;
SIGNAL resetb_i : STD_LOGIC;
SIGNAL wea_i : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL web_i : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL rea_i : STD_LOGIC;
SIGNAL reb_i : STD_LOGIC;
SIGNAL message_complete : BOOLEAN := false;
SIGNAL rsta_outp_stage : STD_LOGIC := '0';
SIGNAL rstb_outp_stage : STD_LOGIC := '0';
--*********************************************************
--FUNCTION : Collision check
--*********************************************************
FUNCTION collision_check (addr_a :
STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
iswrite_a : BOOLEAN;
addr_b :
STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
iswrite_b : BOOLEAN)
RETURN BOOLEAN IS
VARIABLE c_aw_bw : INTEGER;
VARIABLE c_aw_br : INTEGER;
VARIABLE c_ar_bw : INTEGER;
VARIABLE write_addr_a_width : INTEGER;
VARIABLE read_addr_a_width : INTEGER;
VARIABLE write_addr_b_width : INTEGER;
VARIABLE read_addr_b_width : INTEGER;
BEGIN
c_aw_bw := 0;
c_aw_br := 0;
c_ar_bw := 0;
-- Determine the effective address widths FOR each of the 4 ports
write_addr_a_width := C_ADDRA_WIDTH-log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width := C_ADDRA_WIDTH-log2roundup(READ_ADDR_A_DIV);
write_addr_b_width := C_ADDRB_WIDTH-log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width := C_ADDRB_WIDTH-log2roundup(READ_ADDR_B_DIV);
--Look FOR a write-write collision. In order FOR a write-write
--collision to exist, both ports must have a write transaction.
IF (iswrite_a AND iswrite_b) THEN
IF (write_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_bw := 1;
ELSE
c_aw_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_a and iswrite_b
--If the B port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_a) THEN
IF (write_addr_a_width > read_addr_b_width) THEN
--read_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_b_width
--Once both are scaled to read_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_b_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
ELSE
--write_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing write_addr_a and read_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_a_width
--Once both are scaled to write_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_a_width))) THEN
c_aw_br := 1;
ELSE
c_aw_br := 0;
END IF;
END IF; --width
END IF; --iswrite_a
--If the A port is reading (which means it is enabled - so could be
-- a TX_WRITE or TX_READ), then check FOR a write-read collision).
--This could happen whether or not a write-write collision exists due
-- to asymmetric write/read ports.
IF (iswrite_b) THEN
IF (read_addr_a_width > write_addr_b_width) THEN
--write_addr_b_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to write_addr_b_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to write_addr_b_width
--Once both are scaled to write_addr_b_width, compare.
IF ((conv_integer(addr_a)/2**(C_ADDRA_WIDTH-write_addr_b_width)) =
(conv_integer(addr_b)/2**(C_ADDRB_WIDTH-write_addr_b_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
ELSE
--read_addr_a_width is smaller, so scale both addresses to that
-- width FOR comparing read_addr_a and write_addr_b
--addr_a starts as C_ADDRA_WIDTH,
-- scale it down to read_addr_a_width
--addr_b starts as C_ADDRB_WIDTH,
-- scale it down to read_addr_a_width
--Once both are scaled to read_addr_a_width, compare.
IF ((conv_integer(addr_b)/2**(C_ADDRB_WIDTH-read_addr_a_width)) =
(conv_integer(addr_a)/2**(C_ADDRA_WIDTH-read_addr_a_width))) THEN
c_ar_bw := 1;
ELSE
c_ar_bw := 0;
END IF;
END IF; --width
END IF; --iswrite_b
RETURN (c_aw_bw=1 OR c_aw_br=1 OR c_ar_bw=1);
END FUNCTION collision_check;
BEGIN -- Architecture
-----------------------------------------------------------------------------
-- SOFTECC and ECC SBITERR/DBITERR Outputs
-- The ECC Behavior is modeled by the behavioral models only for Virtex-6.
-- The SOFTECC Behavior is modeled by the behavioral models for Spartan-6.
-- For Virtex-5, these outputs will be tied to 0.
-----------------------------------------------------------------------------
SBITERR <= sbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
DBITERR <= dbiterr_sdp WHEN ((C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE '0';
RDADDRECC <= rdaddrecc_sdp WHEN (((C_FAMILY="virtex7") AND C_MEM_TYPE = 1 AND C_USE_ECC = 1) OR C_USE_SOFTECC = 1) ELSE (OTHERS => '0');
-----------------------------------------------
-- This effectively wires off optional inputs
-----------------------------------------------
ena_i <= ENA WHEN (C_HAS_ENA=1) ELSE '1';
enb_i <= ENB WHEN (C_HAS_ENB=1 AND HAS_B_PORT=1) ELSE '1';
-- We are doing an "AND" operation of WEA and ENA and passing to Enbale pin of BRAM when built-in ECC is enabled,
-- what this means is that the write operation happens only when both WEA and ENA are high.
wea_i <= WEA WHEN (HAS_A_WRITE=1 AND ena_i='1') ELSE WEA0;
-- wea_i <= (OTHERS => '1') WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=1 AND ENA = '1') ELSE -- Use_ENA_pin
-- WEA WHEN (HAS_A_WRITE=1 AND C_MEM_TYPE = 1 AND C_USE_ECC = 1 AND C_HAS_ENA=0) ELSE -- Always_enabled
-- WEA WHEN (HAS_A_WRITE=1 AND ena_i='1' AND C_USE_ECC = 0) ELSE
-- WEA0;
web_i <= WEB WHEN (HAS_B_WRITE=1 AND enb_i='1') ELSE WEB0;
rea_i <= ena_i WHEN (HAS_A_READ=1) ELSE '0';
reb_i <= enb_i WHEN (HAS_B_READ=1) ELSE '0';
-- these signals reset the memory latches
-- For the special reset behaviors in some of the families, the C_RSTRAM
-- attribute of the corresponding port is used to indicate if the latch is
-- reset or not.
reseta_i <= RSTA WHEN
((C_HAS_RSTA=1 AND NUM_OUTPUT_STAGES_A=0) OR
(C_HAS_RSTA=1 AND C_RSTRAM_A=1))
ELSE '0';
resetb_i <= RSTB WHEN
((C_HAS_RSTB=1 AND NUM_OUTPUT_STAGES_B=0) OR
(C_HAS_RSTB=1 AND C_RSTRAM_B=1) )
ELSE '0';
--***************************************************************************
-- This is the main PROCESS which includes the memory VARIABLE and the read
-- and write procedures. It also schedules read and write operations
--***************************************************************************
PROCESS (CLKA, CLKB,rea_i,reb_i,reseta_i,resetb_i)
-- Initialize the init memory array
------------------------------------
VARIABLE memory : mem_array := init_memory(DEFAULT_DATA,
C_WRITE_WIDTH_A,
MAX_DEPTH,
MIN_WIDTH);
-- Initialize the mem memory array
------------------------------------
VARIABLE softecc_sbiterr_arr : softecc_err_array;
VARIABLE softecc_dbiterr_arr : softecc_err_array;
VARIABLE sbiterr_arr : ecc_err_array;
VARIABLE dbiterr_arr : ecc_err_array;
CONSTANT doublebit_lsb : STD_LOGIC_VECTOR (1 DOWNTO 0):="11";
CONSTANT doublebit_msb : STD_LOGIC_VECTOR (C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 DOWNTO 0):= (OTHERS => '0');
VARIABLE doublebit_error : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 DOWNTO 0) := doublebit_msb & doublebit_lsb ;
VARIABLE current_contents_var : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
--***********************************
-- procedures to access the memory
--***********************************
-- write_a
----------
PROCEDURE write_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
inj_sbiterr : IN STD_LOGIC;
inj_dbiterr : IN STD_LOGIC) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
VARIABLE message : LINE;
VARIABLE errbit_current_contents : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
-- Block Memory Generator non-cycle-accurate message
ASSERT (message_complete) REPORT "Block Memory Generator module is using a behavioral model FOR simulation which will not precisely model memory collision behavior."
SEVERITY NOTE;
message_complete <= true;
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_A_DIV);
IF (address_i >= C_WRITE_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range FOR A Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEA = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_A + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEA_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Insert double bit errors:
IF (C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
current_contents(0) := NOT(current_contents(0));
current_contents(1) := NOT(current_contents(1));
--current_contents(0) := NOT(current_contents(30));
--current_contents(1) := NOT(current_contents(62));
END IF;
END IF;
-- Insert double bit errors:
IF (C_USE_SOFTECC=1) THEN
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1 downto 2) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-3 downto 0);
doublebit_error(0) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-1);
doublebit_error(1) := doublebit_error(C_WRITE_WIDTH_A+CHKBIT_WIDTH-2);
current_contents := current_contents XOR doublebit_error(C_WRITE_WIDTH_A-1 DOWNTO 0);
END IF;
END IF;
IF(DEBUG=1) THEN
current_contents_var := current_contents; --for debugging current
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_A-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_A + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
-- Store address at which error is injected:
IF ((C_FAMILY = "virtex7") AND C_USE_ECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
sbiterr_arr(address_i) := '1';
ELSE
sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
dbiterr_arr(address_i) := '1';
ELSE
dbiterr_arr(address_i) := '0';
END IF;
END IF;
-- Store address at which softecc error is injected:
IF (C_USE_SOFTECC = 1) THEN
IF ((C_HAS_INJECTERR = 1 AND inj_sbiterr = '1') OR (C_HAS_INJECTERR = 3 AND inj_sbiterr = '1' AND inj_dbiterr /= '1')) THEN
softecc_sbiterr_arr(address_i) := '1';
ELSE
softecc_sbiterr_arr(address_i) := '0';
END IF;
IF ((C_HAS_INJECTERR = 2 OR C_HAS_INJECTERR = 3) AND inj_dbiterr = '1') THEN
softecc_dbiterr_arr(address_i) := '1';
ELSE
softecc_dbiterr_arr(address_i) := '0';
END IF;
END IF;
END IF;
END PROCEDURE;
-- write_b
----------
PROCEDURE write_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
byte_en : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)) IS
VARIABLE current_contents : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
-- Shift the address by the ratio
address_i := (conv_integer(addr)/WRITE_ADDR_B_DIV);
IF (address_i >= C_WRITE_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE = 0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Write"
SEVERITY WARNING;
END IF;
-- valid address
ELSE
-- Combine w/ byte writes
IF (C_USE_BYTE_WEB = 1) THEN
-- Get the current memory contents
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i)
:= memory(address_i*WRITE_WIDTH_RATIO_B + i);
END LOOP;
-- Apply incoming bytes
FOR i IN 0 TO C_WEB_WIDTH-1 LOOP
IF (byte_en(i) = '1') THEN
current_contents(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i)
:= data(C_BYTE_SIZE*(i+1)-1 DOWNTO C_BYTE_SIZE*i);
END IF;
END LOOP;
-- No byte-writes, overwrite the whole word
ELSE
current_contents := data;
END IF;
-- Write data to memory
FOR i IN 0 TO WRITE_WIDTH_RATIO_B-1 LOOP
memory(address_i*WRITE_WIDTH_RATIO_B + i) :=
current_contents(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i);
END LOOP;
END IF;
END PROCEDURE;
-- read_a
----------
PROCEDURE read_a
(addr : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_A_DIV);
IF (address_i >= C_READ_DEPTH_A) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for A Read"
SEVERITY WARNING;
END IF;
memory_out_a <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_A-1 LOOP
memory_out_a(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_A + i) AFTER FLOP_DELAY;
END LOOP;
END IF;
END IF;
END PROCEDURE;
-- read_b
----------
PROCEDURE read_b
(addr : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
reset : IN STD_LOGIC) IS
VARIABLE address_i : INTEGER;
VARIABLE i : INTEGER;
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
ELSE
-- Shift the address by the ratio
address_i := (conv_integer(addr)/READ_ADDR_B_DIV);
IF (address_i >= C_READ_DEPTH_B) THEN
IF (C_DISABLE_WARN_BHV_RANGE=0) THEN
ASSERT FALSE
REPORT C_CORENAME & " WARNING: Address " &
INTEGER'IMAGE(conv_integer(addr)) & " is outside range for B Read"
SEVERITY WARNING;
END IF;
memory_out_b <= (OTHERS => 'X') AFTER FLOP_DELAY;
sbiterr_in <= 'X' AFTER FLOP_DELAY;
dbiterr_in <= 'X' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => 'X') AFTER FLOP_DELAY;
-- valid address
ELSE
-- Increment through the 'partial' words in the memory
FOR i IN 0 TO READ_WIDTH_RATIO_B-1 LOOP
memory_out_b(MIN_WIDTH*(i+1)-1 DOWNTO MIN_WIDTH*i) <=
memory(address_i*READ_WIDTH_RATIO_B + i) AFTER FLOP_DELAY;
END LOOP;
--assert sbiterr and dbiterr signals
IF ((C_FAMILY="virtex7") AND C_USE_ECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
--assert softecc sbiterr and dbiterr signals
ELSIF (C_USE_SOFTECC = 1) THEN
rdaddrecc_in <= addr AFTER FLOP_DELAY;
IF (softecc_sbiterr_arr(address_i) = '1') THEN
sbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
IF (softecc_dbiterr_arr(address_i) = '1') THEN
dbiterr_in <= '1' AFTER FLOP_DELAY;
ELSE
dbiterr_in <= '0' AFTER FLOP_DELAY;
END IF;
ELSE
sbiterr_in <= '0' AFTER FLOP_DELAY;
dbiterr_in <= '0' AFTER FLOP_DELAY;
rdaddrecc_in <= (OTHERS => '0') AFTER FLOP_DELAY;
END IF;
END IF;
END IF;
END PROCEDURE;
-- reset_a
----------
PROCEDURE reset_a
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_a <= INITA_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
-- reset_b
----------
PROCEDURE reset_b
(reset : IN STD_LOGIC) IS
BEGIN
IF (reset = '1') THEN
memory_out_b <= INITB_VAL AFTER FLOP_DELAY;
END IF;
END PROCEDURE;
BEGIN -- begin the main PROCESS
--***************************************************************************
-- These are the main blocks which schedule read and write operations
-- Note that the reset priority feature at the latch stage is only supported
-- for Spartan-6. For other families, the default priority at the latch stage
-- is "CE"
--***************************************************************************
-- Synchronous clocks: schedule port operations with respect to both
-- write operating modes
IF (C_COMMON_CLK=1) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODES IS
WHEN "0000" => -- write_first write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "0100" => -- read_first write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "0001" => -- write_first read_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0101" => --read_first read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0010" => -- write_first no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "0110" => -- read_first no_change
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1000" => -- no_change write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "1001" => -- no_change read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "1010" => -- no_change no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Synchronous clocks
-- Asynchronous clocks: port operation is independent
IF (C_COMMON_CLK=0) THEN
IF (CLKA='1' AND CLKA'EVENT) THEN
CASE WRITE_MODE_A IS
WHEN "00" => -- write_first
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN "01" => -- read_first
--Read A
IF (rea_i='1') THEN
read_a(ADDRA, reseta_i);
END IF;
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
WHEN "10" => -- no_change
--Write A
IF (wea_i/=WEA0) THEN
write_a(ADDRA, wea_i, DINA,INJECTSBITERR,INJECTDBITERR);
END IF;
--Read A
IF (rea_i='1' AND (wea_i=WEA0 OR reseta_i='1')) THEN
read_a(ADDRA, reseta_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
IF (CLKB='1' AND CLKB'EVENT) THEN
CASE WRITE_MODE_B IS
WHEN "00" => -- write_first
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN "01" => -- read_first
--Read B
IF (reb_i='1') THEN
read_b(ADDRB, resetb_i);
END IF;
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
WHEN "10" => -- no_change
--Write B
IF (web_i/=WEB0) THEN
write_b(ADDRB, web_i, DINB);
END IF;
--Read B
IF (reb_i='1' AND (web_i=WEB0 OR resetb_i='1')) THEN
read_b(ADDRB, resetb_i);
END IF;
WHEN OTHERS =>
ASSERT FALSE REPORT "Invalid Operating Mode" SEVERITY ERROR;
END CASE;
END IF;
END IF; -- Asynchronous clocks
-- Assign the memory VARIABLE to the user_visible memory_i SIGNAL
IF(DEBUG=1) THEN
memory_i <= memory;
doublebit_error_i <= doublebit_error;
current_contents_i <= current_contents_var;
END IF;
END PROCESS;
--********************************************************************
-- Instantiate the VARIABLE depth output stage
--********************************************************************
-- Port A
rsta_outp_stage <= RSTA and not sleep;
rstb_outp_stage <= RSTB and not sleep;
reg_a : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTA,
C_RSTRAM => C_RSTRAM_A,
C_RST_PRIORITY => C_RST_PRIORITY_A,
init_val => INITA_VAL,
C_HAS_EN => C_HAS_ENA,
C_HAS_REGCE => C_HAS_REGCEA,
C_DATA_WIDTH => C_READ_WIDTH_A,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_A,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_A,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKA,
RST => rsta_outp_stage, --RSTA,
EN => ENA,
REGCE => REGCEA,
DIN_I => memory_out_a,
DOUT => DOUTA,
SBITERR_IN_I => '0',
DBITERR_IN_I => '0',
SBITERR => OPEN,
DBITERR => OPEN,
RDADDRECC_IN_I => (OTHERS => '0'),
ECCPIPECE => '0',
RDADDRECC => OPEN
);
-- Port B
reg_b : blk_mem_gen_v8_3_1_output_stage
GENERIC MAP(
C_FAMILY => C_FAMILY,
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_RST_TYPE => "SYNC",
C_HAS_RST => C_HAS_RSTB,
C_RSTRAM => C_RSTRAM_B,
C_RST_PRIORITY => C_RST_PRIORITY_B,
init_val => INITB_VAL,
C_HAS_EN => C_HAS_ENB,
C_HAS_REGCE => C_HAS_REGCEB,
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
NUM_STAGES => NUM_OUTPUT_STAGES_B,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP (
CLK => CLKB,
RST => rstb_outp_stage,--RSTB,
EN => ENB,
REGCE => REGCEB,
DIN_I => memory_out_b,
DOUT => doutb_i,
SBITERR_IN_I => sbiterr_in,
DBITERR_IN_I => dbiterr_in,
SBITERR => sbiterr_i,
DBITERR => dbiterr_i,
RDADDRECC_IN_I => rdaddrecc_in,
ECCPIPECE => ECCPIPECE,
RDADDRECC => rdaddrecc_i
);
--********************************************************************
-- Instantiate the input / Output Register stages
--********************************************************************
output_reg_stage: blk_mem_gen_v8_3_1_softecc_output_reg_stage
GENERIC MAP(
C_DATA_WIDTH => C_READ_WIDTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_USE_SOFTECC => C_USE_SOFTECC,
FLOP_DELAY => FLOP_DELAY
)
PORT MAP(
CLK => CLKB,
DIN => doutb_i,
DOUT => DOUTB,
SBITERR_IN => sbiterr_i,
DBITERR_IN => dbiterr_i,
SBITERR => sbiterr_sdp,
DBITERR => dbiterr_sdp,
RDADDRECC_IN => rdaddrecc_i,
RDADDRECC => rdaddrecc_sdp
);
--*********************************
-- Synchronous collision checks
--*********************************
sync_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=1) GENERATE
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
-- collision detect
VARIABLE is_collision : BOOLEAN;
VARIABLE message : LINE;
BEGIN
IF (CLKA='1' AND CLKA'EVENT) THEN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision := false;
END IF;
-- If the write port is in READ_FIRST mode, there is no collision
IF (C_WRITE_MODE_A="READ_FIRST" AND wea_i/=WEA0 AND web_i=WEB0) THEN
is_collision := false;
END IF;
IF (C_WRITE_MODE_B="READ_FIRST" AND web_i/=WEB0 AND wea_i=WEA0) THEN
is_collision := false;
END IF;
-- Only flag if one of the accesses is a write
IF (is_collision AND (wea_i/=WEA0 OR web_i/=WEB0)) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END IF;
END PROCESS;
END GENERATE;
--*********************************
-- Asynchronous collision checks
--*********************************
async_coll: IF (C_DISABLE_WARN_BHV_COLL=0 AND C_COMMON_CLK=0) GENERATE
SIGNAL addra_delay : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL wea_delay : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0);
SIGNAL ena_delay : STD_LOGIC;
SIGNAL addrb_delay : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
SIGNAL web_delay : STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0);
SIGNAL enb_delay : STD_LOGIC;
BEGIN
-- Delay A and B addresses in order to mimic setup/hold times
PROCESS (ADDRA, wea_i, ena_i, ADDRB, web_i, enb_i)
BEGIN
addra_delay <= ADDRA AFTER COLL_DELAY;
wea_delay <= wea_i AFTER COLL_DELAY;
ena_delay <= ena_i AFTER COLL_DELAY;
addrb_delay <= ADDRB AFTER COLL_DELAY;
web_delay <= web_i AFTER COLL_DELAY;
enb_delay <= enb_i AFTER COLL_DELAY;
END PROCESS;
-- Do the checks w/rt A
PROCESS (CLKA)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_a : BOOLEAN;
VARIABLE is_collision_delay_a : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_a := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_a := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(ADDRA)/='X') THEN
is_collision_delay_a := collision_check(ADDRA,
wea_i/=WEA0,
addrb_delay,
web_delay/=WEB0);
ELSE
is_collision_delay_a := false;
END IF;
-- Only flag if B access is a write
IF (is_collision_a AND web_i/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_a AND web_delay/=WEB0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
IF (wea_i/=WEA0) THEN
write(message, STRING'("A write address: "));
ELSE
write(message, STRING'("A read address: "));
END IF;
write(message, ADDRA);
write(message, STRING'(", B write address: "));
write(message, addrb_delay);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
-- Do the checks w/rt B
PROCESS (CLKB)
use IEEE.STD_LOGIC_TEXTIO.ALL;
VARIABLE is_collision_b : BOOLEAN;
VARIABLE is_collision_delay_b : BOOLEAN;
VARIABLE message : LINE;
BEGIN
-- Possible collision if both are enabled and the addresses match
-- Not checking the collision condition when there is an 'x' on the Addr bus
IF (ena_i='1' AND enb_i='1' AND OR_REDUCE(ADDRA) /= 'X') THEN
is_collision_b := collision_check(ADDRA,
wea_i/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_b := false;
END IF;
IF (ena_i='1' AND enb_delay='1' AND OR_REDUCE(addra_delay) /= 'X') THEN
is_collision_delay_b := collision_check(addra_delay,
wea_delay/=WEA0,
ADDRB,
web_i/=WEB0);
ELSE
is_collision_delay_b := false;
END IF;
-- Only flag if A access is a write
-- Modified condition checking (is_collision_b AND WEA0_i=/WEA0) to fix CR526228
IF (is_collision_b AND wea_i/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, ADDRA);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
ELSIF (is_collision_delay_b AND wea_delay/=WEA0) THEN
write(message, C_CORENAME);
write(message, STRING'(" WARNING: collision detected: "));
write(message, STRING'("A write address: "));
write(message, addra_delay);
IF (web_i/=WEB0) THEN
write(message, STRING'(", B write address: "));
ELSE
write(message, STRING'(", B read address: "));
END IF;
write(message, ADDRB);
write(message, LF);
ASSERT false REPORT message.ALL SEVERITY WARNING;
deallocate(message);
END IF;
END PROCESS;
END GENERATE;
END mem_module_behavioral;
--******************************************************************************
-- Top module that wraps SoftECC Input register stage and the main memory module
--
-- This module is the top-level of behavioral model
--******************************************************************************
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY blk_mem_gen_v8_3_1 IS
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_CTRL_ECC_ALGO : STRING := "NONE";
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
--C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_SLEEP_PIN : INTEGER := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
PORT (
clka : IN STD_LOGIC := '0';
rsta : IN STD_LOGIC := '0';
ena : IN STD_LOGIC := '1';
regcea : IN STD_LOGIC := '1';
wea : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
clkb : IN STD_LOGIC := '0';
rstb : IN STD_LOGIC := '0';
enb : IN STD_LOGIC := '1';
regceb : IN STD_LOGIC := '1';
web : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
addrb : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
dinb : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
doutb : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
injectsbiterr : IN STD_LOGIC := '0';
injectdbiterr : IN STD_LOGIC := '0';
sbiterr : OUT STD_LOGIC := '0';
dbiterr : OUT STD_LOGIC := '0';
rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
eccpipece : in std_logic := '0';
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic := '0';
rstb_busy : out std_logic := '0';
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
s_aclk : IN STD_LOGIC := '0';
s_aresetn : IN STD_LOGIC := '0';
-- axi full/lite slave Write (write side)
s_axi_awid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_awvalid : IN STD_LOGIC := '0';
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wstrb : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_wlast : IN STD_LOGIC := '0';
s_axi_wvalid : IN STD_LOGIC := '0';
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC := '0';
-- axi full/lite slave Read (Write side)
s_axi_arid : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
s_axi_arlen : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
s_axi_arvalid : IN STD_LOGIC := '0';
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
s_axi_rdata : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC := '0';
-- axi full/lite sideband Signals
s_axi_injectsbiterr : IN STD_LOGIC := '0';
s_axi_injectdbiterr : IN STD_LOGIC := '0';
s_axi_sbiterr : OUT STD_LOGIC := '0';
s_axi_dbiterr : OUT STD_LOGIC := '0';
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END blk_mem_gen_v8_3_1;
--******************************
-- Port and Generic Definitions
--******************************
---------------------------------------------------------------------------
-- Generic Definitions
---------------------------------------------------------------------------
-- C_CORENAME : Instance name of the Block Memory Generator core
-- C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
-- options are available - "spartan3", "spartan6",
-- "virtex4", "virtex5", "virtex6l" and "virtex6".
-- C_MEM_TYPE : Designates memory type.
-- It can be
-- 0 - Single Port Memory
-- 1 - Simple Dual Port Memory
-- 2 - True Dual Port Memory
-- 3 - Single Port Read Only Memory
-- 4 - Dual Port Read Only Memory
-- C_BYTE_SIZE : Size of a byte (8 or 9 bits)
-- C_ALGORITHM : Designates the algorithm method used
-- for constructing the memory.
-- It can be Fixed_Primitives, Minimum_Area or
-- Low_Power
-- C_PRIM_TYPE : Designates the user selected primitive used to
-- construct the memory.
--
-- C_LOAD_INIT_FILE : Designates the use of an initialization file to
-- initialize memory contents.
-- C_INIT_FILE_NAME : Memory initialization file name.
-- C_USE_DEFAULT_DATA : Designates whether to fill remaining
-- initialization space with default data
-- C_DEFAULT_DATA : Default value of all memory locations
-- not initialized by the memory
-- initialization file.
-- C_RST_TYPE : Type of reset - Synchronous or Asynchronous
--
-- C_HAS_RSTA : Determines the presence of the RSTA port
-- C_RST_PRIORITY_A : Determines the priority between CE and SR for
-- Port A.
-- C_RSTRAM_A : Determines if special reset behavior is used for
-- Port A
-- C_INITA_VAL : The initialization value for Port A
-- C_HAS_ENA : Determines the presence of the ENA port
-- C_HAS_REGCEA : Determines the presence of the REGCEA port
-- C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
-- C_WEA_WIDTH : The width of the WEA port
-- C_WRITE_MODE_A : Configurable write mode for Port A. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_A : Memory write width for Port A.
-- C_READ_WIDTH_A : Memory read width for Port A.
-- C_WRITE_DEPTH_A : Memory write depth for Port A.
-- C_READ_DEPTH_A : Memory read depth for Port A.
-- C_ADDRA_WIDTH : Width of the ADDRA input port
-- C_HAS_RSTB : Determines the presence of the RSTB port
-- C_RST_PRIORITY_B : Determines the priority between CE and SR for
-- Port B.
-- C_RSTRAM_B : Determines if special reset behavior is used for
-- Port B
-- C_INITB_VAL : The initialization value for Port B
-- C_HAS_ENB : Determines the presence of the ENB port
-- C_HAS_REGCEB : Determines the presence of the REGCEB port
-- C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
-- C_WEB_WIDTH : The width of the WEB port
-- C_WRITE_MODE_B : Configurable write mode for Port B. It can be
-- WRITE_FIRST, READ_FIRST or NO_CHANGE.
-- C_WRITE_WIDTH_B : Memory write width for Port B.
-- C_READ_WIDTH_B : Memory read width for Port B.
-- C_WRITE_DEPTH_B : Memory write depth for Port B.
-- C_READ_DEPTH_B : Memory read depth for Port B.
-- C_ADDRB_WIDTH : Width of the ADDRB input port
-- C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the RAM primitive for Port A.
-- C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the RAM primitive for Port B.
-- C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
-- of the MUX for Port A.
-- C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
-- of the MUX for Port B.
-- C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
-- between the muxes.
-- C_USE_SOFTECC : Determines if the Soft ECC feature is used or
-- not. Only applicable Spartan-6
-- C_USE_ECC : Determines if the ECC feature is used or
-- not. Only applicable for V5 and V6
-- C_HAS_INJECTERR : Determines if the error injection pins
-- are present or not. If the ECC feature
-- is not used, this value is defaulted to
-- 0, else the following are the allowed
-- values:
-- 0 : No INJECTSBITERR or INJECTDBITERR pins
-- 1 : Only INJECTSBITERR pin exists
-- 2 : Only INJECTDBITERR pin exists
-- 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
-- C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
-- warnings. It can be "ALL", "NONE",
-- "Warnings_Only" or "Generate_X_Only".
-- C_COMMON_CLK : Determins if the core has a single CLK input.
-- C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
-- C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
-- warnings
---------------------------------------------------------------------------
-- Port Definitions
---------------------------------------------------------------------------
-- CLKA : Clock to synchronize all read and write operations of Port A.
-- RSTA : Reset input to reset memory outputs to a user-defined
-- reset state for Port A.
-- ENA : Enable all read and write operations of Port A.
-- REGCEA : Register Clock Enable to control each pipeline output
-- register stages for Port A.
-- WEA : Write Enable to enable all write operations of Port A.
-- ADDRA : Address of Port A.
-- DINA : Data input of Port A.
-- DOUTA : Data output of Port A.
-- CLKB : Clock to synchronize all read and write operations of Port B.
-- RSTB : Reset input to reset memory outputs to a user-defined
-- reset state for Port B.
-- ENB : Enable all read and write operations of Port B.
-- REGCEB : Register Clock Enable to control each pipeline output
-- register stages for Port B.
-- WEB : Write Enable to enable all write operations of Port B.
-- ADDRB : Address of Port B.
-- DINB : Data input of Port B.
-- DOUTB : Data output of Port B.
-- INJECTSBITERR : Single Bit ECC Error Injection Pin.
-- INJECTDBITERR : Double Bit ECC Error Injection Pin.
-- SBITERR : Output signal indicating that a Single Bit ECC Error has been
-- detected and corrected.
-- DBITERR : Output signal indicating that a Double Bit ECC Error has been
-- detected.
-- RDADDRECC : Read Address Output signal indicating address at which an
-- ECC error has occurred.
---------------------------------------------------------------------------
ARCHITECTURE behavioral OF blk_mem_gen_v8_3_1 IS
COMPONENT blk_mem_gen_v8_3_1_mem_module
GENERIC (
C_CORENAME : STRING := "blk_mem_gen_v8_3_1";
C_FAMILY : STRING := "virtex7";
C_XDEVICEFAMILY : STRING := "virtex7";
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
FLOP_DELAY : TIME := 100 ps;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_EN_ECC_PIPE : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
ECCPIPECE : IN STD_LOGIC;
SLEEP : IN STD_LOGIC;
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1_mem_module;
COMPONENT blk_mem_axi_regs_fwd_v8_3 IS
GENERIC(
C_DATA_WIDTH : INTEGER := 8
);
PORT (
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
S_VALID : IN STD_LOGIC;
S_READY : OUT STD_LOGIC;
S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0);
M_VALID : OUT STD_LOGIC;
M_READY : IN STD_LOGIC;
M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0)
);
END COMPONENT blk_mem_axi_regs_fwd_v8_3;
COMPONENT blk_mem_axi_read_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 0;
C_AXI_SLAVE_TYPE : integer := 0;
C_MEMORY_TYPE : integer := 0;
C_WRITE_WIDTH_A : integer := 4;
C_WRITE_DEPTH_A : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_PIPELINE_STAGES : integer := 0;
C_AXI_ARADDR_WIDTH : integer := 12;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_ADDRB_WIDTH : integer := 12
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Read (Read side)
S_AXI_ARADDR : IN std_logic_vector(C_AXI_ARADDR_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_ARLEN : IN std_logic_vector(7 downto 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN std_logic := '0';
S_AXI_ARREADY : OUT std_logic;
S_AXI_RLAST : OUT std_logic;
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic := '0';
S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (OTHERS => '0');
-- AXI Full/Lite Read Address Signals to BRAM
S_AXI_ARADDR_OUT : OUT std_logic_vector(C_ADDRB_WIDTH-1 downto 0);
S_AXI_RD_EN : OUT std_logic
);
END COMPONENT blk_mem_axi_read_wrapper_beh;
COMPONENT blk_mem_axi_write_wrapper_beh
GENERIC (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE : integer := 0; -- 0: AXI Lite; 1: AXI Full;
C_AXI_SLAVE_TYPE : integer := 0; -- 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
C_MEMORY_TYPE : integer := 0; -- 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
C_WRITE_DEPTH_A : integer := 0;
C_AXI_AWADDR_WIDTH : integer := 32;
C_ADDRA_WIDTH : integer := 12;
C_AXI_WDATA_WIDTH : integer := 32;
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
-- AXI OUTSTANDING WRITES
C_AXI_OS_WR : integer := 2
);
PORT (
-- AXI Global Signals
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN std_logic_vector(C_AXI_AWADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN std_logic := '0';
S_AXI_AWREADY : OUT std_logic := '0';
S_AXI_WVALID : IN std_logic := '0';
S_AXI_WREADY : OUT std_logic := '0';
S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BVALID : OUT std_logic := '0';
S_AXI_BREADY : IN std_logic := '0';
-- Signals for BMG interface
S_AXI_AWADDR_OUT : OUT std_logic_vector(C_ADDRA_WIDTH-1 DOWNTO 0);
S_AXI_WR_EN : OUT std_logic:= '0'
);
END COMPONENT blk_mem_axi_write_wrapper_beh;
CONSTANT FLOP_DELAY : TIME := 100 ps;
SIGNAL rsta_in : STD_LOGIC := '1';
SIGNAL ena_in : STD_LOGIC := '1';
SIGNAL regcea_in : STD_LOGIC := '1';
SIGNAL wea_in : STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL addra_in : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0);
SIGNAL dina_in : STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0):= (OTHERS => '0');
SIGNAL injectsbiterr_in : STD_LOGIC := '0';
SIGNAL injectdbiterr_in : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- FUNCTION: toLowerCaseChar
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
-----------------------------------------------------------------------------
FUNCTION toLowerCaseChar(
char : character )
RETURN character IS
BEGIN
-- If char is not an upper case letter then return char
IF char<'A' OR char>'Z' THEN
RETURN char;
END IF;
-- Otherwise map char to its corresponding lower case character and
-- RETURN that
CASE char IS
WHEN 'A' => RETURN 'a';
WHEN 'B' => RETURN 'b';
WHEN 'C' => RETURN 'c';
WHEN 'D' => RETURN 'd';
WHEN 'E' => RETURN 'e';
WHEN 'F' => RETURN 'f';
WHEN 'G' => RETURN 'g';
WHEN 'H' => RETURN 'h';
WHEN 'I' => RETURN 'i';
WHEN 'J' => RETURN 'j';
WHEN 'K' => RETURN 'k';
WHEN 'L' => RETURN 'l';
WHEN 'M' => RETURN 'm';
WHEN 'N' => RETURN 'n';
WHEN 'O' => RETURN 'o';
WHEN 'P' => RETURN 'p';
WHEN 'Q' => RETURN 'q';
WHEN 'R' => RETURN 'r';
WHEN 'S' => RETURN 's';
WHEN 'T' => RETURN 't';
WHEN 'U' => RETURN 'u';
WHEN 'V' => RETURN 'v';
WHEN 'W' => RETURN 'w';
WHEN 'X' => RETURN 'x';
WHEN 'Y' => RETURN 'y';
WHEN 'Z' => RETURN 'z';
WHEN OTHERS => RETURN char;
END CASE;
END toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
FUNCTION equalIgnoreCase(
str1 : STRING;
str2 : STRING )
RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str2'left TO str1'right LOOP
IF NOT (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equalIgnoreCase;
-----------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
----------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STRING;
false_case : STRING)
RETURN STRING IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC_VECTOR;
false_case : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT condition THEN
RETURN false_case;
ELSE
RETURN true_case;
END IF;
END if_then_else;
----------------------------------------------------------------------------
-- FUNCTION : log2roundup
----------------------------------------------------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
CONSTANT lower_limit : INTEGER := 1;
CONSTANT upper_limit : INTEGER := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-----------------------------------------------------------------------------
-- FUNCTION : log2int
-----------------------------------------------------------------------------
FUNCTION log2int (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := data_value;
BEGIN
WHILE (cnt >1) LOOP
width := width + 1;
cnt := cnt/2;
END LOOP;
RETURN width;
END log2int;
-----------------------------------------------------------------------------
-- FUNCTION : divroundup
-- Returns the ceiling value of the division
-- Data_value - the quantity to be divided, dividend
-- Divisor - the value to divide the data_value by
-----------------------------------------------------------------------------
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
SIGNAL s_axi_awaddr_out_c : STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_araddr_out_c : STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_wr_en_c : STD_LOGIC := '0';
SIGNAL s_axi_rd_en_c : STD_LOGIC := '0';
SIGNAL s_aresetn_a_c : STD_LOGIC := '0';
--**************************************************************************
-- AXI PARAMETERS
CONSTANT AXI_FULL_MEMORY_SLAVE : integer := if_then_else((C_AXI_SLAVE_TYPE = 0 AND C_AXI_TYPE = 1),1,0);
CONSTANT C_AXI_ADDR_WIDTH_MSB : integer := C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
CONSTANT C_AXI_ADDR_WIDTH : integer := C_AXI_ADDR_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT LOWER_BOUND_VAL : integer := if_then_else((log2roundup(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT C_AXI_ADDR_WIDTH_LSB : integer := if_then_else((AXI_FULL_MEMORY_SLAVE = 1),0,LOWER_BOUND_VAL);
CONSTANT C_AXI_OS_WR : integer := 2;
-- SAFETY LOGIC related Signals
SIGNAL RSTA_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_A : STD_LOGIC := '0';
SIGNAL RSTB_SHFT_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL POR_B : STD_LOGIC := '0';
SIGNAL ENA_dly : STD_LOGIC := '0';
SIGNAL ENA_dly_D : STD_LOGIC := '0';
SIGNAL ENB_dly : STD_LOGIC := '0';
SIGNAL ENB_dly_D : STD_LOGIC := '0';
SIGNAL RSTA_I_SAFE : STD_LOGIC := '0';
SIGNAL RSTB_I_SAFE : STD_LOGIC := '0';
SIGNAL ENA_I_SAFE : STD_LOGIC := '0';
SIGNAL ENB_I_SAFE : STD_LOGIC := '0';
SIGNAL ram_rstram_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_a_busy : STD_LOGIC := '0';
SIGNAL ram_rstram_b_busy : STD_LOGIC := '0';
SIGNAL ram_rstreg_b_busy : STD_LOGIC := '0';
SIGNAL ENA_dly_reg : STD_LOGIC := '0';
SIGNAL ENB_dly_reg : STD_LOGIC := '0';
SIGNAL ENA_dly_reg_D : STD_LOGIC := '0';
SIGNAL ENB_dly_reg_D : STD_LOGIC := '0';
--**************************************************************************
BEGIN -- Architecture
--*************************************************************************
-- NO INPUT STAGE
--*************************************************************************
no_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=0) GENERATE
rsta_in <= RSTA;
ena_in <= ENA;
regcea_in <= REGCEA;
wea_in <= WEA;
addra_in <= ADDRA;
dina_in <= DINA;
injectsbiterr_in <= INJECTSBITERR;
injectdbiterr_in <= INJECTDBITERR;
END GENERATE no_input_stage;
--**************************************************************************
-- WITH INPUT STAGE
--**************************************************************************
has_input_stage: IF (C_HAS_SOFTECC_INPUT_REGS_A=1) GENERATE
PROCESS (CLKA)
BEGIN
IF (CLKA'EVENT AND CLKA = '1') THEN
rsta_in <= RSTA AFTER FLOP_DELAY;
ena_in <= ENA AFTER FLOP_DELAY;
regcea_in <= REGCEA AFTER FLOP_DELAY;
wea_in <= WEA AFTER FLOP_DELAY;
addra_in <= ADDRA AFTER FLOP_DELAY;
dina_in <= DINA AFTER FLOP_DELAY;
injectsbiterr_in <= INJECTSBITERR AFTER FLOP_DELAY;
injectdbiterr_in <= INJECTDBITERR AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE has_input_stage;
--**************************************************************************
-- NO SAFETY LOGIC
--**************************************************************************
NO_SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 0) GENERATE
ENA_I_SAFE <= ena_in;
ENB_I_SAFE <= ENB;
RSTA_I_SAFE <= rsta_in;
RSTB_I_SAFE <= RSTB;
END GENERATE NO_SAFETY_CKT_GEN;
--**************************************************************************
-- SAFETY LOGIC
--**************************************************************************
SAFETY_CKT_GEN: IF(C_EN_SAFETY_CKT = 1) GENERATE
-- RESET SAFETY LOGIC Generation
-- POR Generation
------------------------------------------------------------------------------
-- Power-ON Reset Generation
------------------------------------------------------------------------------
RST_SHFT_LOGIC_A : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
RSTA_SHFT_REG(4 DOWNTO 0) <= RSTA_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_A;
POR_RSTA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE(CLKA) THEN
POR_A <= RSTA_SHFT_REG(4) xor RSTA_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTA_GEN;
RST_SHFT_LOGIC_B : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
RSTB_SHFT_REG(4 DOWNTO 0) <= RSTB_SHFT_REG(3 DOWNTO 0) & '1' AFTER FLOP_DELAY;
END IF;
END PROCESS RST_SHFT_LOGIC_B;
POR_RSTB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE(CLKB) THEN
POR_B <= RSTB_SHFT_REG(4) xor RSTB_SHFT_REG(0) AFTER FLOP_DELAY;
END IF;
END PROCESS POR_RSTB_GEN;
-----------------------------------------------------------------------------
-- Fix for the AR42571
-----------------------------------------------------------------------------
-- Reset Generation
-----------------------------------------------------------------------------
RSTA_I_SAFE <= rsta_in OR POR_A;
SPRAM_RST: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_I_SAFE <= '0';
END GENERATE SPRAM_RST;
nSPRAM_RST: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_I_SAFE <= RSTB OR POR_B;
END GENERATE nSPRAM_RST;
-----------------------------------------------------------------------------
-- RSTA/B_BUSY Generation
-----------------------------------------------------------------------------
RSTA_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
ram_rstram_a_busy <= rsta_in OR ENA_dly OR ENA_dly_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstram_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_NO_REG;
RSTA_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
ram_rstreg_a_busy <= rsta_in OR ENA_dly OR ENA_dly_reg_D;
PROC_RSTA_BUSY_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
RSTA_BUSY <= ram_rstreg_a_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTA_BUSY_WITH_REG;
SPRAM_RST_BUSY: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
RSTB_BUSY <= '0';
END GENERATE SPRAM_RST_BUSY;
nSPRAM_RST_BUSY: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
RSTB_BUSY_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
ram_rstram_b_busy <= RSTB OR ENB_dly OR ENB_dly_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstram_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_NO_REG;
RSTB_BUSY_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
ram_rstreg_b_busy <= RSTB OR ENB_dly OR ENB_dly_reg_D;
PROC_RSTB_BUSY_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
RSTB_BUSY <= ram_rstreg_b_busy AFTER FLOP_DELAY;
END IF;
END PROCESS;
END GENERATE RSTB_BUSY_WITH_REG;
END GENERATE nSPRAM_RST_BUSY;
-----------------------------------------------------------------------------
-- ENA/ENB Generation
-----------------------------------------------------------------------------
ENA_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=0 OR (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=1)) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly <= rsta_in AFTER FLOP_DELAY;
ENA_dly_D <= ENA_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_D OR ena_in;
END GENERATE ENA_NO_REG;
ENA_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_A=1 AND C_RSTRAM_A=0) GENERATE
BEGIN
PROC_ENA_GEN : PROCESS(CLKA)
BEGIN
IF RISING_EDGE (CLKA) THEN
ENA_dly_reg <= rsta_in AFTER FLOP_DELAY;
ENA_dly_reg_D <= ENA_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENA_I_SAFE <= ENA_dly_reg_D OR ena_in;
END GENERATE ENA_WITH_REG;
SPRAM_ENB: IF ((C_MEM_TYPE = 0) OR (C_MEM_TYPE = 3)) GENERATE
BEGIN
ENB_I_SAFE <= '0';
END GENERATE SPRAM_ENB;
nSPRAM_ENB: IF ((C_MEM_TYPE /= 0) AND (C_MEM_TYPE /= 3)) GENERATE
BEGIN
ENB_NO_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=0 OR (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=1)) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly <= RSTB AFTER FLOP_DELAY;
ENB_dly_D <= ENB_dly AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_D OR ENB;
END GENERATE ENB_NO_REG;
ENB_WITH_REG: IF (C_HAS_MEM_OUTPUT_REGS_B=1 AND C_RSTRAM_B=0) GENERATE
BEGIN
PROC_ENB_GEN : PROCESS(CLKB)
BEGIN
IF RISING_EDGE (CLKB) THEN
ENB_dly_reg <= RSTB AFTER FLOP_DELAY;
ENB_dly_reg_D <= ENB_dly_reg AFTER FLOP_DELAY;
END IF;
END PROCESS;
ENB_I_SAFE <= ENB_dly_reg_D OR ENB;
END GENERATE ENB_WITH_REG;
END GENERATE nSPRAM_ENB;
END GENERATE SAFETY_CKT_GEN;
--**************************************************************************
-- NATIVE MEMORY MODULE INSTANCE
--**************************************************************************
native_mem_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 0) GENERATE
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXUPLUS"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEXU"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,--rsta_in,
ENA => ENA_I_SAFE,--ena_in,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in,
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => RDADDRECC
);
END GENERATE native_mem_module;
--**************************************************************************
-- NATIVE MEMORY MAPPED MODULE INSTANCE
--**************************************************************************
native_mem_map_module: IF (C_INTERFACE_TYPE = 0 AND C_ENABLE_32BIT_ADDRESS = 1) GENERATE
--**************************************************************************
-- NATIVE MEMORY MAPPED PARAMETERS
CONSTANT C_ADDRA_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_A);
CONSTANT C_ADDRB_WIDTH_ACTUAL : integer := log2roundup(C_WRITE_DEPTH_B);
CONSTANT C_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
CONSTANT C_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
CONSTANT C_MEM_MAP_ADDRA_WIDTH_MSB : integer := C_ADDRA_WIDTH_MSB;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_MSB : integer := C_ADDRB_WIDTH_MSB;
-- Data Width Number of LSB address bits to be discarded
-- 1 to 16 1
-- 17 to 32 2
-- 33 to 64 3
-- 65 to 128 4
-- 129 to 256 5
-- 257 to 512 6
-- 513 to 1024 7
-- The following two constants determine this.
CONSTANT MEM_MAP_LOWER_BOUND_VAL_A : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_A,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_A,8)));
CONSTANT MEM_MAP_LOWER_BOUND_VAL_B : integer := if_then_else((log2int(divroundup(C_WRITE_WIDTH_B,8))) = 0, 0, log2int(divroundup(C_WRITE_WIDTH_B,8)));
CONSTANT C_MEM_MAP_ADDRA_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_A;
CONSTANT C_MEM_MAP_ADDRB_WIDTH_LSB : integer := MEM_MAP_LOWER_BOUND_VAL_B;
SIGNAL rdaddrecc_i : STD_LOGIC_VECTOR(C_ADDRB_WIDTH_ACTUAL-1 DOWNTO 0) := (OTHERS => '0');
--**************************************************************************
BEGIN
RDADDRECC(C_ADDRB_WIDTH-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_MSB) <= (OTHERS => '0');
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB) <= rdaddrecc_i;
RDADDRECC(C_MEM_MAP_ADDRB_WIDTH_LSB-1 DOWNTO 0) <= (OTHERS => '0');
mem_map_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => C_USE_BYTE_WEA,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH_ACTUAL,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => C_HAS_ENB,
C_HAS_REGCEB => C_HAS_REGCEB,
C_USE_BYTE_WEB => C_USE_BYTE_WEB,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH_ACTUAL,
C_HAS_MEM_OUTPUT_REGS_A => C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => C_HAS_MUX_OUTPUT_REGS_A,
C_HAS_MUX_OUTPUT_REGS_B => C_HAS_MUX_OUTPUT_REGS_B,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => C_EN_ECC_PIPE,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
CLKA => CLKA,
RSTA => RSTA_I_SAFE,
ENA => ENA_I_SAFE,
REGCEA => regcea_in,
WEA => wea_in,
ADDRA => addra_in(C_MEM_MAP_ADDRA_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRA_WIDTH_LSB),
DINA => dina_in,
DOUTA => DOUTA,
CLKB => CLKB,
RSTB => RSTB_I_SAFE,
ENB => ENB_I_SAFE,
REGCEB => REGCEB,
WEB => WEB,
ADDRB => ADDRB(C_MEM_MAP_ADDRB_WIDTH_MSB-1 DOWNTO C_MEM_MAP_ADDRB_WIDTH_LSB),
DINB => DINB,
DOUTB => DOUTB,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => ECCPIPECE,
SLEEP => SLEEP,
RDADDRECC => rdaddrecc_i
);
END GENERATE native_mem_map_module;
--****************************************************************************
-- AXI MEMORY MODULE INSTANCE
--****************************************************************************
axi_mem_module: IF (C_INTERFACE_TYPE = 1) GENERATE
SIGNAL s_axi_rid_c : STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rdata_c : STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rresp_c : STD_LOGIC_VECTOR(2-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL s_axi_rlast_c : STD_LOGIC := '0';
SIGNAL s_axi_rvalid_c : STD_LOGIC := '0';
SIGNAL s_axi_rready_c : STD_LOGIC := '0';
SIGNAL regceb_c : STD_LOGIC := '0';
BEGIN
s_aresetn_a_c <= NOT S_ARESETN;
S_AXI_BRESP <= (OTHERS => '0');
s_axi_rresp_c <= (OTHERS => '0');
no_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 0 AND C_HAS_MUX_OUTPUT_REGS_B = 0 ) GENERATE
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RLAST <= s_axi_rlast_c;
S_AXI_RVALID <= s_axi_rvalid_c;
S_AXI_RID <= s_axi_rid_c;
S_AXI_RRESP <= s_axi_rresp_c;
s_axi_rready_c <= S_AXI_RREADY;
END GENERATE no_regs;
has_regs_fwd: IF (C_HAS_MUX_OUTPUT_REGS_B = 1 OR C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
CONSTANT C_AXI_PAYLOAD : INTEGER := if_then_else((C_HAS_MUX_OUTPUT_REGS_B = 1),C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3,C_AXI_ID_WIDTH+3);
SIGNAL s_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL m_axi_payload_c : STD_LOGIC_VECTOR(C_AXI_PAYLOAD-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
has_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
regceb_c <= s_axi_rvalid_c AND s_axi_rready_c;
END GENERATE has_regceb;
no_regceb: IF (C_HAS_MEM_OUTPUT_REGS_B = 0) GENERATE
regceb_c <= REGCEB;
END GENERATE no_regceb;
only_core_op_regs: IF (C_HAS_MUX_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rdata_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RDATA <= m_axi_payload_c(C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_core_op_regs;
only_emb_op_regs: IF (C_HAS_MEM_OUTPUT_REGS_B = 1) GENERATE
s_axi_payload_c <= s_axi_rid_c & s_axi_rresp_c & s_axi_rlast_c;
S_AXI_RDATA <= s_axi_rdata_c;
S_AXI_RID <= m_axi_payload_c(C_AXI_PAYLOAD-1 DOWNTO C_AXI_PAYLOAD-C_AXI_ID_WIDTH);
S_AXI_RRESP <= m_axi_payload_c(2 DOWNTO 1);
S_AXI_RLAST <= m_axi_payload_c(0);
END GENERATE only_emb_op_regs;
axi_regs_inst : blk_mem_axi_regs_fwd_v8_3
GENERIC MAP(
C_DATA_WIDTH => C_AXI_PAYLOAD
)
PORT MAP (
ACLK => S_ACLK,
ARESET => s_aresetn_a_c,
S_VALID => s_axi_rvalid_c,
S_READY => s_axi_rready_c,
S_PAYLOAD_DATA => s_axi_payload_c,
M_VALID => S_AXI_RVALID,
M_READY => S_AXI_RREADY,
M_PAYLOAD_DATA => m_axi_payload_c
);
END GENERATE has_regs_fwd;
axi_wr_fsm : blk_mem_axi_write_wrapper_beh
GENERIC MAP(
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_AXI_AWADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_WDATA_WIDTH => C_WRITE_WIDTH_A,
C_AXI_OS_WR => C_AXI_OS_WR
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_ACLK,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Slave Write Interface
S_AXI_AWADDR => S_AXI_AWADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_AWLEN => S_AXI_AWLEN,
S_AXI_AWID => S_AXI_AWID,
S_AXI_AWSIZE => S_AXI_AWSIZE,
S_AXI_AWBURST => S_AXI_AWBURST,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BID => S_AXI_BID,
-- Signals for BRAM interface
S_AXI_AWADDR_OUT =>s_axi_awaddr_out_c,
S_AXI_WR_EN =>s_axi_wr_en_c
);
mem_module: blk_mem_gen_v8_3_1_mem_module
GENERIC MAP(
C_CORENAME => C_CORENAME,
C_FAMILY => if_then_else(equalIgnoreCase(C_FAMILY,"VIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QVIRTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"KINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QKINTEX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QARTIX7L"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AARTIX7"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"ZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"AZYNQ"),"virtex7",if_then_else(equalIgnoreCase(C_FAMILY,"QZYNQ"),"virtex7",C_FAMILY))))))))))))))),
C_XDEVICEFAMILY => C_XDEVICEFAMILY,
C_USE_BRAM_BLOCK => C_USE_BRAM_BLOCK,
C_ENABLE_32BIT_ADDRESS => C_ENABLE_32BIT_ADDRESS,
C_MEM_TYPE => C_MEM_TYPE,
C_BYTE_SIZE => C_BYTE_SIZE,
C_ALGORITHM => C_ALGORITHM,
C_PRIM_TYPE => C_PRIM_TYPE,
C_LOAD_INIT_FILE => C_LOAD_INIT_FILE,
C_INIT_FILE_NAME => C_INIT_FILE_NAME,
C_INIT_FILE => C_INIT_FILE,
C_USE_DEFAULT_DATA => C_USE_DEFAULT_DATA,
C_DEFAULT_DATA => C_DEFAULT_DATA,
C_RST_TYPE => "SYNC",
C_HAS_RSTA => C_HAS_RSTA,
C_RST_PRIORITY_A => C_RST_PRIORITY_A,
C_RSTRAM_A => C_RSTRAM_A,
C_INITA_VAL => C_INITA_VAL,
C_HAS_ENA => 1, -- For AXI, Read Enable is always C_HAS_ENA,
C_HAS_REGCEA => C_HAS_REGCEA,
C_USE_BYTE_WEA => 1, -- For AXI C_USE_BYTE_WEA is always 1,
C_WEA_WIDTH => C_WEA_WIDTH,
C_WRITE_MODE_A => C_WRITE_MODE_A,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_READ_WIDTH_A => C_READ_WIDTH_A,
C_WRITE_DEPTH_A => C_WRITE_DEPTH_A,
C_READ_DEPTH_A => C_READ_DEPTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_HAS_RSTB => C_HAS_RSTB,
C_RST_PRIORITY_B => C_RST_PRIORITY_B,
C_RSTRAM_B => C_RSTRAM_B,
C_INITB_VAL => C_INITB_VAL,
C_HAS_ENB => 1, -- For AXI, Read Enable is always C_HAS_ENB,
C_HAS_REGCEB => C_HAS_MEM_OUTPUT_REGS_B,
C_USE_BYTE_WEB => 1, -- For AXI C_USE_BYTE_WEB is always 1,
C_WEB_WIDTH => C_WEB_WIDTH,
C_WRITE_MODE_B => C_WRITE_MODE_B,
C_WRITE_WIDTH_B => C_WRITE_WIDTH_B,
C_READ_WIDTH_B => C_READ_WIDTH_B,
C_WRITE_DEPTH_B => C_WRITE_DEPTH_B,
C_READ_DEPTH_B => C_READ_DEPTH_B,
C_ADDRB_WIDTH => C_ADDRB_WIDTH,
C_HAS_MEM_OUTPUT_REGS_A => 0, --For AXI, Primitive Registers A is not supported C_HAS_MEM_OUTPUT_REGS_A,
C_HAS_MEM_OUTPUT_REGS_B => C_HAS_MEM_OUTPUT_REGS_B,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_HAS_SOFTECC_INPUT_REGS_A => C_HAS_SOFTECC_INPUT_REGS_A,
C_HAS_SOFTECC_OUTPUT_REGS_B => C_HAS_SOFTECC_OUTPUT_REGS_B,
C_MUX_PIPELINE_STAGES => C_MUX_PIPELINE_STAGES,
C_USE_SOFTECC => C_USE_SOFTECC,
C_USE_ECC => C_USE_ECC,
C_HAS_INJECTERR => C_HAS_INJECTERR,
C_SIM_COLLISION_CHECK => C_SIM_COLLISION_CHECK,
C_COMMON_CLK => C_COMMON_CLK,
FLOP_DELAY => FLOP_DELAY,
C_DISABLE_WARN_BHV_COLL => C_DISABLE_WARN_BHV_COLL,
C_EN_ECC_PIPE => 0,
C_DISABLE_WARN_BHV_RANGE => C_DISABLE_WARN_BHV_RANGE
)
PORT MAP(
--Port A:
CLKA => S_AClk,
RSTA => s_aresetn_a_c,
ENA => s_axi_wr_en_c,
REGCEA => regcea_in,
WEA => S_AXI_WSTRB,
ADDRA => s_axi_awaddr_out_c,
DINA => S_AXI_WDATA,
DOUTA => DOUTA,
--Port B:
CLKB => S_AClk,
RSTB => s_aresetn_a_c,
ENB => s_axi_rd_en_c,
REGCEB => regceb_c,
WEB => (OTHERS => '0'),
ADDRB => s_axi_araddr_out_c,
DINB => DINB,
DOUTB => s_axi_rdata_c,
INJECTSBITERR => injectsbiterr_in,
INJECTDBITERR => injectdbiterr_in,
SBITERR => SBITERR,
DBITERR => DBITERR,
ECCPIPECE => '0',
SLEEP => '0',
RDADDRECC => RDADDRECC
);
axi_rd_sm : blk_mem_axi_read_wrapper_beh
GENERIC MAP (
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => C_INTERFACE_TYPE,
C_AXI_TYPE => C_AXI_TYPE,
C_AXI_SLAVE_TYPE => C_AXI_SLAVE_TYPE,
C_MEMORY_TYPE => C_MEM_TYPE,
C_WRITE_WIDTH_A => C_WRITE_WIDTH_A,
C_ADDRA_WIDTH => C_ADDRA_WIDTH,
C_AXI_PIPELINE_STAGES => 1,
C_AXI_ARADDR_WIDTH => if_then_else((AXI_FULL_MEMORY_SLAVE = 1),C_AXI_ADDR_WIDTH,C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
C_HAS_AXI_ID => C_HAS_AXI_ID,
C_AXI_ID_WIDTH => C_AXI_ID_WIDTH,
C_ADDRB_WIDTH => C_ADDRB_WIDTH
)
PORT MAP(
-- AXI Global Signals
S_ACLK => S_AClk,
S_ARESETN => s_aresetn_a_c,
-- AXI Full/Lite Read Side
S_AXI_ARADDR => S_AXI_ARADDR(C_AXI_ADDR_WIDTH_MSB-1 DOWNTO C_AXI_ADDR_WIDTH_LSB),
S_AXI_ARLEN => S_AXI_ARLEN,
S_AXI_ARSIZE => S_AXI_ARSIZE,
S_AXI_ARBURST => S_AXI_ARBURST,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RLAST => s_axi_rlast_c,
S_AXI_RVALID => s_axi_rvalid_c,
S_AXI_RREADY => s_axi_rready_c,
S_AXI_ARID => S_AXI_ARID,
S_AXI_RID => s_axi_rid_c,
-- AXI Full/Lite Read FSM Outputs
S_AXI_ARADDR_OUT => s_axi_araddr_out_c,
S_AXI_RD_EN => s_axi_rd_en_c
);
END GENERATE axi_mem_module;
END behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_clr is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_clr;
architecture beh_ff_clr_arch of beh_ff_clr is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(CLR, C)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_clr_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_ce is
generic(
INIT : std_logic := '0'
);
port(
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic
);
end beh_ff_ce;
architecture beh_ff_ce_arch of beh_ff_ce is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, CLR)
begin
if (CLR = '1') then
q_o <= '0';
elsif (rising_edge(C)) then
if (CE = '1') then
q_o <= D after 100 ps;
end if;
end if;
end process;
end beh_ff_ce_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_ff_pre is
generic(
INIT : std_logic := '1'
);
port(
Q : out std_logic;
C : in std_logic;
D : in std_logic;
PRE : in std_logic
);
end beh_ff_pre;
architecture beh_ff_pre_arch of beh_ff_pre is
signal q_o : std_logic := INIT;
begin
Q <= q_o;
VITALBehavior : process(C, PRE)
begin
if (PRE = '1') then
q_o <= '1';
elsif (C' event and C = '1') then
q_o <= D after 100 ps;
end if;
end process;
end beh_ff_pre_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity beh_muxf7 is
port(
O : out std_ulogic;
I0 : in std_ulogic;
I1 : in std_ulogic;
S : in std_ulogic
);
end beh_muxf7;
architecture beh_muxf7_arch of beh_muxf7 is
begin
VITALBehavior : process (I0, I1, S)
begin
if (S = '0') then
O <= I0;
else
O <= I1;
end if;
end process;
end beh_muxf7_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STATE_LOGIC is
generic(
INIT : std_logic_vector(63 downto 0) := X"0000000000000000"
);
port(
O : out std_logic := '0';
I0 : in std_logic := '0';
I1 : in std_logic := '0';
I2 : in std_logic := '0';
I3 : in std_logic := '0';
I4 : in std_logic := '0';
I5 : in std_logic := '0'
);
end STATE_LOGIC;
architecture STATE_LOGIC_arch of STATE_LOGIC is
constant INIT_reg : std_logic_vector(63 downto 0) := INIT;
begin
LUT_beh:process (I0, I1, I2, I3, I4, I5)
variable I_reg : std_logic_vector(5 downto 0);
begin
I_reg := I5 & I4 & I3 & I2 & I1 & I0;
O <= INIT_reg(conv_integer(I_reg));
end process;
end STATE_LOGIC_arch;
| mit |
dries007/Basys3 | FPGA-Z/FPGA-Z.srcs/sources_1/imports/Downloads/ps2_keyboard.vhd | 2 | 4180 | --------------------------------------------------------------------------------
--
-- filename: ps2_keyboard.vhd
-- dependencies: debounce.vhd
-- design software: quartus ii 32-bit version 12.1 build 177 sj full version
--
-- hdl code is provided "as is." digi-key expressly disclaims any
-- warranty of any kind, whether express or implied, including but not
-- limited to, the implied warranties of merchantability, fitness for a
-- particular purpose, or non-infringement. in no event shall digi-key
-- be liable for any incidental, special, indirect or consequential
-- damages, lost profits or lost data, harm to your equipment, cost of
-- procurement of substitute goods, technology or services, any claims
-- by third parties (including but not limited to any defense thereof),
-- any claims for indemnity or contribution, or other similar costs.
--
-- version history
-- version 1.0 11/25/2013 scott larson
-- initial public release
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ps2_keyboard is
generic
(
clk_freq : integer := 100_000_000 --system clock frequency in hz
);
port(
clk : in std_logic; --system clock
ps2_clk : in std_logic; --clock signal from ps/2 keyboard
ps2_data : in std_logic; --data signal from ps/2 keyboard
ps2_code_new : out std_logic; --flag that new ps/2 code is available on ps2_code bus
ps2_code : out std_logic_vector(7 downto 0)); --code received from ps/2
end ps2_keyboard;
architecture logic of ps2_keyboard is
signal ps2_clk_int : std_logic; --debounced clock signal from ps/2 keyboard
signal ps2_data_int : std_logic; --debounced data signal from ps/2 keyboard
signal ps2_word : std_logic_vector(10 downto 0); --stores the ps2 data word
signal error : std_logic; --validate parity, start, and stop bits
signal count_idle : integer range 0 to clk_freq/18_000; --counter to determine ps/2 is idle
begin
--synchronizer flip-flops
process(clk)
begin
if(clk'event and clk = '1') then --rising edge of system clock
ps2_clk_int <= ps2_clk; --synchronize ps/2 clock signal
ps2_data_int <= ps2_data; --synchronize ps/2 data signal
end if;
end process;
--input ps2 data
process(ps2_clk_int)
begin
if(ps2_clk_int'event and ps2_clk_int = '0') then --falling edge of ps2 clock
ps2_word <= ps2_data_int & ps2_word(10 downto 1); --shift in ps2 data bit
end if;
end process;
--verify that parity, start, and stop bits are all correct
error <= not (not ps2_word(0) and ps2_word(10) and (ps2_word(9) xor ps2_word(8) xor
ps2_word(7) xor ps2_word(6) xor ps2_word(5) xor ps2_word(4) xor ps2_word(3) xor
ps2_word(2) xor ps2_word(1)));
--determine if ps2 port is idle (i.e. last transaction is finished) and output result
process(clk)
begin
if(clk'event and clk = '1') then --rising edge of system clock
if(ps2_clk_int = '0') then --low ps2 clock, ps/2 is active
count_idle <= 0; --reset idle counter
elsif(count_idle /= clk_freq/18_000) then --ps2 clock has been high less than a half clock period (<55us)
count_idle <= count_idle + 1; --continue counting
end if;
if(count_idle = clk_freq/18_000 and error = '0') then --idle threshold reached and no errors detected
ps2_code_new <= '1'; --set flag that new ps/2 code is available
ps2_code <= ps2_word(8 downto 1); --output new ps/2 code
else --ps/2 port active or error detected
ps2_code_new <= '0'; --set flag that ps/2 transaction is in progress
end if;
end if;
end process;
end logic;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution_OH/impl/verilog/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_3_max_dsp_32/hdl/xbip_pipe_v3_0_vh_rfs.vhd | 16 | 30077 | `protect begin_protected
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| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_nco_0_0/ip_design_nco_0_0_stub.vhdl | 1 | 2595 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:27 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_nco_0_0/ip_design_nco_0_0_stub.vhdl
-- Design : ip_design_nco_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ip_design_nco_0_0 is
Port (
s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_AWVALID : in STD_LOGIC;
s_axi_AXILiteS_AWREADY : out STD_LOGIC;
s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_AXILiteS_WVALID : in STD_LOGIC;
s_axi_AXILiteS_WREADY : out STD_LOGIC;
s_axi_AXILiteS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_BVALID : out STD_LOGIC;
s_axi_AXILiteS_BREADY : in STD_LOGIC;
s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_ARVALID : in STD_LOGIC;
s_axi_AXILiteS_ARREADY : out STD_LOGIC;
s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_RVALID : out STD_LOGIC;
s_axi_AXILiteS_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC
);
end ip_design_nco_0_0;
architecture stub of ip_design_nco_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_AXILiteS_AWADDR[5:0],s_axi_AXILiteS_AWVALID,s_axi_AXILiteS_AWREADY,s_axi_AXILiteS_WDATA[31:0],s_axi_AXILiteS_WSTRB[3:0],s_axi_AXILiteS_WVALID,s_axi_AXILiteS_WREADY,s_axi_AXILiteS_BRESP[1:0],s_axi_AXILiteS_BVALID,s_axi_AXILiteS_BREADY,s_axi_AXILiteS_ARADDR[5:0],s_axi_AXILiteS_ARVALID,s_axi_AXILiteS_ARREADY,s_axi_AXILiteS_RDATA[31:0],s_axi_AXILiteS_RRESP[1:0],s_axi_AXILiteS_RVALID,s_axi_AXILiteS_RREADY,ap_clk,ap_rst_n";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "nco,Vivado 2017.3";
begin
end;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_6_max_dsp_32/hdl/xbip_utils_v3_0_vh_rfs.vhd | 16 | 168945 | `protect begin_protected
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| mit |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Accum/src/TestBench/mrom_TB.vhd | 1 | 1406 | library accum;
use accum.OneHotAccum.all;
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity mrom_tb is
end mrom_tb;
architecture TB_ARCHITECTURE of mrom_tb is
-- Component declaration of the tested unit
component mrom
port(
RE : in STD_LOGIC;
ADDR : in mem_addr;
DOUT : out command );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal RE : STD_LOGIC;
signal ADDR : mem_addr;
-- Observed signals - signals mapped to the output ports of tested entity
signal DOUT : command;
-- Add your code here ...
constant WAIT_period: time := 10 ns;
begin
-- Unit Under Test port map
UUT : mrom
port map (
RE => RE,
ADDR => ADDR,
DOUT => DOUT
);
-- Add your stimulus here ...
main: process
begin
re <= '0';
addr <= "00010";
wait for 1 * WAIT_period;
re <= '1';
wait for 1 * WAIT_period;
addr <= "00000";
re <= '1';
wait for 1 * WAIT_period;
re <= '0';
wait for 100 * WAIT_period;
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_mrom of mrom_tb is
for TB_ARCHITECTURE
for UUT : mrom
use entity work.mrom(beh);
end for;
end for;
end TESTBENCH_FOR_mrom;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution_OH/impl/ip/hdl/vhdl/convolve_kernel_fbkb.vhd | 5 | 3080 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 1;
NUM_STAGE : integer := 9;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_7_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_7_full_dsp_32_u : component convolve_kernel_ap_fadd_7_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/111e5b5bdee7fef3/ip_design_axi_gpio_0_0_stub.vhdl | 1 | 2562 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:27 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_axi_gpio_0_0_stub.vhdl
-- Design : ip_design_axi_gpio_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_i[1:0],gpio_io_o[1:0],gpio_io_t[1:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2017.3";
begin
end;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.ip_user_files/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xbar_0/zqynq_lab_1_design_xbar_0_sim_netlist.vhdl | 1 | 856369 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 17:41:04 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xbar_0/zqynq_lab_1_design_xbar_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter is
port (
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_arvalid : out STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast_i0 : out STD_LOGIC;
\m_axi_arqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
ADDRESS_HIT_0 : out STD_LOGIC;
match : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : out STD_LOGIC;
p_39_in : out STD_LOGIC;
p_57_in : out STD_LOGIC;
p_75_in : out STD_LOGIC;
\gen_master_slots[4].r_issuing_cnt_reg[32]\ : out STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_arready_4 : in STD_LOGIC;
p_23_in : in STD_LOGIC;
\read_cs__0\ : in STD_LOGIC;
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
\r_cmd_pop_0__1\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
\r_cmd_pop_1__1\ : in STD_LOGIC;
\r_cmd_pop_3__1\ : in STD_LOGIC;
\r_cmd_pop_2__1\ : in STD_LOGIC;
m_valid_i : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
\s_axi_araddr[24]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter is
signal \^address_hit_0\ : STD_LOGIC;
signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^aa_mi_arvalid\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_3_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC;
signal \^m_axi_arqos[15]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^match\ : STD_LOGIC;
signal s_ready_i2 : STD_LOGIC;
signal st_aa_artarget_hot : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_rid_i[11]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[10]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_4\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[18]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[19]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[19]_i_4\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[26]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_axi_arvalid[3]_INST_0\ : label is "soft_lutpair2";
begin
ADDRESS_HIT_0 <= \^address_hit_0\;
D(2 downto 0) <= \^d\(2 downto 0);
Q(0) <= \^q\(0);
aa_mi_arvalid <= \^aa_mi_arvalid\;
\m_axi_arqos[15]\(68 downto 0) <= \^m_axi_arqos[15]\(68 downto 0);
match <= \^match\;
\gen_axi.s_axi_rid_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^q\(0),
I1 => \^aa_mi_arvalid\,
I2 => mi_arready_4,
I3 => p_23_in,
O => \gen_axi.s_axi_rid_i_reg[11]\(0)
);
\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"55035500"
)
port map (
I0 => \read_cs__0\,
I1 => \^m_axi_arqos[15]\(45),
I2 => \^m_axi_arqos[15]\(44),
I3 => p_23_in,
I4 => \gen_axi.s_axi_rlast_i_i_5_n_0\,
O => s_axi_rlast_i0
);
\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \^m_axi_arqos[15]\(46),
I1 => \^m_axi_arqos[15]\(47),
I2 => \^m_axi_arqos[15]\(48),
I3 => \^m_axi_arqos[15]\(49),
I4 => \^m_axi_arqos[15]\(51),
I5 => \^m_axi_arqos[15]\(50),
O => \gen_axi.s_axi_rlast_i_i_5_n_0\
);
\gen_master_slots[0].r_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \r_cmd_pop_0__1\,
I2 => m_axi_arready(0),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(0),
I5 => r_issuing_cnt(1),
O => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].r_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I1 => r_issuing_cnt(1),
I2 => r_issuing_cnt(2),
O => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(1),
I1 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I2 => r_issuing_cnt(3),
I3 => r_issuing_cnt(2),
O => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(0),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(0),
O => p_93_in
);
\gen_master_slots[0].r_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \r_cmd_pop_0__1\,
I2 => m_axi_arready(0),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(0),
I5 => r_issuing_cnt(1),
O => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I1 => r_issuing_cnt(5),
I2 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(5),
I1 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I2 => r_issuing_cnt(7),
I3 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(1),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(1),
O => p_75_in
);
\gen_master_slots[1].r_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \r_cmd_pop_1__1\,
I2 => m_axi_arready(1),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(1),
I5 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \r_cmd_pop_1__1\,
I2 => m_axi_arready(1),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(1),
I5 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0)
);
\gen_master_slots[2].r_issuing_cnt[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(8),
I1 => \r_cmd_pop_2__1\,
I2 => m_axi_arready(2),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(2),
I5 => r_issuing_cnt(9),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0)
);
\gen_master_slots[2].r_issuing_cnt[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\,
I1 => r_issuing_cnt(9),
I2 => r_issuing_cnt(10),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(9),
I1 => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\,
I2 => r_issuing_cnt(11),
I3 => r_issuing_cnt(10),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(2),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(2),
O => p_57_in
);
\gen_master_slots[2].r_issuing_cnt[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(8),
I1 => \r_cmd_pop_2__1\,
I2 => m_axi_arready(2),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(2),
I5 => r_issuing_cnt(9),
O => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\
);
\gen_master_slots[3].r_issuing_cnt[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(12),
I1 => \r_cmd_pop_3__1\,
I2 => m_axi_arready(3),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(3),
I5 => r_issuing_cnt(13),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0)
);
\gen_master_slots[3].r_issuing_cnt[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\,
I1 => r_issuing_cnt(13),
I2 => r_issuing_cnt(14),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(13),
I1 => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\,
I2 => r_issuing_cnt(15),
I3 => r_issuing_cnt(14),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(3),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(3),
O => p_39_in
);
\gen_master_slots[3].r_issuing_cnt[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(12),
I1 => \r_cmd_pop_3__1\,
I2 => m_axi_arready(3),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(3),
I5 => r_issuing_cnt(13),
O => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\
);
\gen_master_slots[4].r_issuing_cnt[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"807F0080"
)
port map (
I0 => \^q\(0),
I1 => \^aa_mi_arvalid\,
I2 => mi_arready_4,
I3 => \r_cmd_pop_4__1\,
I4 => r_issuing_cnt(16),
O => \gen_master_slots[4].r_issuing_cnt_reg[32]\
);
\gen_no_arbiter.m_mesg_i[11]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_mi_arvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(0),
Q => \^m_axi_arqos[15]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(10),
Q => \^m_axi_arqos[15]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(11),
Q => \^m_axi_arqos[15]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(12),
Q => \^m_axi_arqos[15]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(13),
Q => \^m_axi_arqos[15]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(14),
Q => \^m_axi_arqos[15]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(15),
Q => \^m_axi_arqos[15]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(16),
Q => \^m_axi_arqos[15]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(17),
Q => \^m_axi_arqos[15]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(18),
Q => \^m_axi_arqos[15]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(19),
Q => \^m_axi_arqos[15]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(1),
Q => \^m_axi_arqos[15]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(20),
Q => \^m_axi_arqos[15]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(21),
Q => \^m_axi_arqos[15]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(22),
Q => \^m_axi_arqos[15]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(23),
Q => \^m_axi_arqos[15]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(24),
Q => \^m_axi_arqos[15]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(25),
Q => \^m_axi_arqos[15]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(26),
Q => \^m_axi_arqos[15]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(27),
Q => \^m_axi_arqos[15]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(28),
Q => \^m_axi_arqos[15]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(29),
Q => \^m_axi_arqos[15]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(2),
Q => \^m_axi_arqos[15]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(30),
Q => \^m_axi_arqos[15]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(31),
Q => \^m_axi_arqos[15]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(32),
Q => \^m_axi_arqos[15]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(33),
Q => \^m_axi_arqos[15]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(34),
Q => \^m_axi_arqos[15]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(35),
Q => \^m_axi_arqos[15]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(36),
Q => \^m_axi_arqos[15]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(37),
Q => \^m_axi_arqos[15]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(38),
Q => \^m_axi_arqos[15]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(39),
Q => \^m_axi_arqos[15]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(3),
Q => \^m_axi_arqos[15]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(40),
Q => \^m_axi_arqos[15]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(41),
Q => \^m_axi_arqos[15]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(42),
Q => \^m_axi_arqos[15]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(43),
Q => \^m_axi_arqos[15]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(44),
Q => \^m_axi_arqos[15]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(45),
Q => \^m_axi_arqos[15]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(46),
Q => \^m_axi_arqos[15]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(47),
Q => \^m_axi_arqos[15]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(48),
Q => \^m_axi_arqos[15]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(49),
Q => \^m_axi_arqos[15]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(4),
Q => \^m_axi_arqos[15]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(50),
Q => \^m_axi_arqos[15]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(51),
Q => \^m_axi_arqos[15]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(52),
Q => \^m_axi_arqos[15]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(53),
Q => \^m_axi_arqos[15]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(54),
Q => \^m_axi_arqos[15]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(55),
Q => \^m_axi_arqos[15]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(56),
Q => \^m_axi_arqos[15]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(57),
Q => \^m_axi_arqos[15]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(58),
Q => \^m_axi_arqos[15]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(5),
Q => \^m_axi_arqos[15]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(59),
Q => \^m_axi_arqos[15]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(60),
Q => \^m_axi_arqos[15]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(61),
Q => \^m_axi_arqos[15]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(62),
Q => \^m_axi_arqos[15]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(63),
Q => \^m_axi_arqos[15]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(64),
Q => \^m_axi_arqos[15]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(6),
Q => \^m_axi_arqos[15]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(65),
Q => \^m_axi_arqos[15]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(66),
Q => \^m_axi_arqos[15]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(67),
Q => \^m_axi_arqos[15]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(68),
Q => \^m_axi_arqos[15]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(7),
Q => \^m_axi_arqos[15]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(8),
Q => \^m_axi_arqos[15]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(9),
Q => \^m_axi_arqos[15]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^address_hit_0\,
I1 => \^match\,
O => st_aa_artarget_hot(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_arqos[3]\(29),
I1 => \s_axi_arqos[3]\(28),
I2 => \s_axi_arqos[3]\(31),
I3 => \s_axi_arqos[3]\(30),
I4 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^address_hit_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I1 => \s_axi_arqos[3]\(29),
I2 => \s_axi_arqos[3]\(28),
I3 => \s_axi_arqos[3]\(31),
I4 => \s_axi_arqos[3]\(30),
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(0)
);
\gen_no_arbiter.m_target_hot_i[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => \s_axi_arqos[3]\(34),
I1 => \s_axi_arqos[3]\(35),
I2 => \s_axi_arqos[3]\(33),
I3 => \s_axi_arqos[3]\(32),
I4 => \s_axi_arqos[3]\(37),
I5 => \s_axi_arqos[3]\(36),
O => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\
);
\gen_no_arbiter.m_target_hot_i[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_arqos[3]\(29),
I1 => \s_axi_arqos[3]\(28),
I2 => \s_axi_arqos[3]\(31),
I3 => \s_axi_arqos[3]\(30),
I4 => \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0\,
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(1)
);
\gen_no_arbiter.m_target_hot_i[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => \s_axi_arqos[3]\(35),
I1 => \s_axi_arqos[3]\(34),
I2 => \s_axi_arqos[3]\(32),
I3 => \s_axi_arqos[3]\(33),
I4 => \s_axi_arqos[3]\(36),
I5 => \s_axi_arqos[3]\(37),
O => \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0\,
I1 => \s_axi_arqos[3]\(25),
I2 => \s_axi_arqos[3]\(26),
I3 => \s_axi_arqos[3]\(27),
I4 => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\,
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(2)
);
\gen_no_arbiter.m_target_hot_i[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \s_axi_arqos[3]\(32),
I1 => \s_axi_arqos[3]\(33),
I2 => \s_axi_arqos[3]\(34),
I3 => \s_axi_arqos[3]\(35),
I4 => \s_axi_arqos[3]\(37),
I5 => \s_axi_arqos[3]\(36),
O => \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \s_axi_arqos[3]\(31),
I1 => \s_axi_arqos[3]\(30),
I2 => \s_axi_arqos[3]\(29),
I3 => \s_axi_arqos[3]\(28),
O => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \s_axi_arqos[3]\(40),
I1 => \s_axi_arqos[3]\(41),
I2 => \s_axi_arqos[3]\(38),
I3 => \s_axi_arqos[3]\(39),
I4 => \s_axi_arqos[3]\(43),
I5 => \s_axi_arqos[3]\(42),
O => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\
);
\gen_no_arbiter.m_target_hot_i[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^d\(1),
I1 => \^d\(2),
I2 => \^d\(0),
I3 => \^address_hit_0\,
O => \^match\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_artarget_hot(0),
Q => aa_mi_artarget_hot(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(0),
Q => aa_mi_artarget_hot(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(1),
Q => aa_mi_artarget_hot(2),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(2),
Q => aa_mi_artarget_hot(3),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \s_axi_araddr[24]\(0),
Q => \^q\(0),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"DC"
)
port map (
I0 => \gen_no_arbiter.m_valid_i_i_2_n_0\,
I1 => m_valid_i,
I2 => \^aa_mi_arvalid\,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF88800000000"
)
port map (
I0 => m_axi_arready(2),
I1 => aa_mi_artarget_hot(2),
I2 => m_axi_arready(1),
I3 => aa_mi_artarget_hot(1),
I4 => \gen_no_arbiter.m_valid_i_i_3_n_0\,
I5 => \^aa_mi_arvalid\,
O => \gen_no_arbiter.m_valid_i_i_2_n_0\
);
\gen_no_arbiter.m_valid_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => aa_mi_artarget_hot(0),
I1 => m_axi_arready(0),
I2 => \^q\(0),
I3 => mi_arready_4,
I4 => m_axi_arready(3),
I5 => aa_mi_artarget_hot(3),
O => \gen_no_arbiter.m_valid_i_i_3_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^aa_mi_arvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => E(0),
Q => S_AXI_ARREADY(0),
R => '0'
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(0),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(1),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(1)
);
\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(2),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(2)
);
\m_axi_arvalid[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(3),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 is
port (
ss_aa_awready : out STD_LOGIC;
aa_sa_awvalid : out STD_LOGIC;
\mi_awready_mux__3\ : out STD_LOGIC;
\s_ready_i0__1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
p_84_in : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
p_66_in : out STD_LOGIC;
p_48_in : out STD_LOGIC;
p_101_in : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
write_cs01_out : out STD_LOGIC;
ADDRESS_HIT_0 : out STD_LOGIC;
match : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC;
\sa_wm_awready_mux__3\ : out STD_LOGIC;
\gen_master_slots[4].w_issuing_cnt_reg[32]\ : out STD_LOGIC;
\m_axi_awqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_valid_i : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
mi_awready_4 : in STD_LOGIC;
\s_axi_awqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[24]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0 is
signal \^address_hit_0\ : STD_LOGIC;
signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^aa_sa_awvalid\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC;
signal \m_ready_d[1]_i_4_n_0\ : STD_LOGIC;
signal \^match\ : STD_LOGIC;
signal \^mi_awready_mux__3\ : STD_LOGIC;
signal \^s_ready_i0__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal s_ready_i2 : STD_LOGIC;
signal \^ss_aa_awready\ : STD_LOGIC;
signal st_aa_awtarget_hot : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^write_cs01_out\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_wready_i_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_4\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_4\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_4\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[4]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_axi_awvalid[3]_INST_0\ : label is "soft_lutpair14";
begin
ADDRESS_HIT_0 <= \^address_hit_0\;
D(2 downto 0) <= \^d\(2 downto 0);
Q(4 downto 0) <= \^q\(4 downto 0);
aa_sa_awvalid <= \^aa_sa_awvalid\;
match <= \^match\;
\mi_awready_mux__3\ <= \^mi_awready_mux__3\;
\s_ready_i0__1\(0) <= \^s_ready_i0__1\(0);
ss_aa_awready <= \^ss_aa_awready\;
write_cs01_out <= \^write_cs01_out\;
\gen_axi.s_axi_wready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => mi_awready_4,
I1 => \^q\(4),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => \^write_cs01_out\
);
\gen_master_slots[0].w_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(0),
I1 => \^q\(0),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_101_in
);
\gen_master_slots[1].w_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(1),
I1 => \^q\(1),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_84_in
);
\gen_master_slots[2].w_issuing_cnt[19]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(2),
I1 => \^q\(2),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_66_in
);
\gen_master_slots[3].w_issuing_cnt[27]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(3),
I1 => \^q\(3),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_48_in
);
\gen_master_slots[4].w_issuing_cnt[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"95552AAA"
)
port map (
I0 => \^write_cs01_out\,
I1 => s_axi_bready(0),
I2 => p_46_out,
I3 => \chosen_reg[4]\(0),
I4 => w_issuing_cnt(0),
O => \gen_master_slots[4].w_issuing_cnt_reg[32]\
);
\gen_no_arbiter.m_mesg_i[11]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_sa_awvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(0),
Q => \m_axi_awqos[15]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(10),
Q => \m_axi_awqos[15]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(11),
Q => \m_axi_awqos[15]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(12),
Q => \m_axi_awqos[15]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(13),
Q => \m_axi_awqos[15]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(14),
Q => \m_axi_awqos[15]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(15),
Q => \m_axi_awqos[15]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(16),
Q => \m_axi_awqos[15]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(17),
Q => \m_axi_awqos[15]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(18),
Q => \m_axi_awqos[15]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(19),
Q => \m_axi_awqos[15]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(1),
Q => \m_axi_awqos[15]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(20),
Q => \m_axi_awqos[15]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(21),
Q => \m_axi_awqos[15]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(22),
Q => \m_axi_awqos[15]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(23),
Q => \m_axi_awqos[15]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(24),
Q => \m_axi_awqos[15]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(25),
Q => \m_axi_awqos[15]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(26),
Q => \m_axi_awqos[15]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(27),
Q => \m_axi_awqos[15]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(28),
Q => \m_axi_awqos[15]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(29),
Q => \m_axi_awqos[15]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(2),
Q => \m_axi_awqos[15]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(30),
Q => \m_axi_awqos[15]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(31),
Q => \m_axi_awqos[15]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(32),
Q => \m_axi_awqos[15]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(33),
Q => \m_axi_awqos[15]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(34),
Q => \m_axi_awqos[15]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(35),
Q => \m_axi_awqos[15]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(36),
Q => \m_axi_awqos[15]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(37),
Q => \m_axi_awqos[15]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(38),
Q => \m_axi_awqos[15]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(39),
Q => \m_axi_awqos[15]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(3),
Q => \m_axi_awqos[15]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(40),
Q => \m_axi_awqos[15]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(41),
Q => \m_axi_awqos[15]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(42),
Q => \m_axi_awqos[15]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(43),
Q => \m_axi_awqos[15]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(44),
Q => \m_axi_awqos[15]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(45),
Q => \m_axi_awqos[15]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(46),
Q => \m_axi_awqos[15]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(47),
Q => \m_axi_awqos[15]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(48),
Q => \m_axi_awqos[15]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(49),
Q => \m_axi_awqos[15]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(4),
Q => \m_axi_awqos[15]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(50),
Q => \m_axi_awqos[15]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(51),
Q => \m_axi_awqos[15]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(52),
Q => \m_axi_awqos[15]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(53),
Q => \m_axi_awqos[15]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(54),
Q => \m_axi_awqos[15]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(55),
Q => \m_axi_awqos[15]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(56),
Q => \m_axi_awqos[15]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(57),
Q => \m_axi_awqos[15]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(58),
Q => \m_axi_awqos[15]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(5),
Q => \m_axi_awqos[15]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(59),
Q => \m_axi_awqos[15]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(60),
Q => \m_axi_awqos[15]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(61),
Q => \m_axi_awqos[15]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(62),
Q => \m_axi_awqos[15]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(63),
Q => \m_axi_awqos[15]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(64),
Q => \m_axi_awqos[15]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(6),
Q => \m_axi_awqos[15]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(65),
Q => \m_axi_awqos[15]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(66),
Q => \m_axi_awqos[15]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(67),
Q => \m_axi_awqos[15]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(68),
Q => \m_axi_awqos[15]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(7),
Q => \m_axi_awqos[15]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(8),
Q => \m_axi_awqos[15]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(9),
Q => \m_axi_awqos[15]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^address_hit_0\,
I1 => \^match\,
O => st_aa_awtarget_hot(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_awqos[3]\(29),
I1 => \s_axi_awqos[3]\(28),
I2 => \s_axi_awqos[3]\(31),
I3 => \s_axi_awqos[3]\(30),
I4 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^address_hit_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I1 => \s_axi_awqos[3]\(29),
I2 => \s_axi_awqos[3]\(28),
I3 => \s_axi_awqos[3]\(31),
I4 => \s_axi_awqos[3]\(30),
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(0)
);
\gen_no_arbiter.m_target_hot_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => \s_axi_awqos[3]\(34),
I1 => \s_axi_awqos[3]\(35),
I2 => \s_axi_awqos[3]\(33),
I3 => \s_axi_awqos[3]\(32),
I4 => \s_axi_awqos[3]\(37),
I5 => \s_axi_awqos[3]\(36),
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\
);
\gen_no_arbiter.m_target_hot_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_awqos[3]\(29),
I1 => \s_axi_awqos[3]\(28),
I2 => \s_axi_awqos[3]\(31),
I3 => \s_axi_awqos[3]\(30),
I4 => \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0\,
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(1)
);
\gen_no_arbiter.m_target_hot_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => \s_axi_awqos[3]\(35),
I1 => \s_axi_awqos[3]\(34),
I2 => \s_axi_awqos[3]\(32),
I3 => \s_axi_awqos[3]\(33),
I4 => \s_axi_awqos[3]\(36),
I5 => \s_axi_awqos[3]\(37),
O => \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0\,
I1 => \s_axi_awqos[3]\(25),
I2 => \s_axi_awqos[3]\(26),
I3 => \s_axi_awqos[3]\(27),
I4 => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\,
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(2)
);
\gen_no_arbiter.m_target_hot_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \s_axi_awqos[3]\(32),
I1 => \s_axi_awqos[3]\(33),
I2 => \s_axi_awqos[3]\(34),
I3 => \s_axi_awqos[3]\(35),
I4 => \s_axi_awqos[3]\(37),
I5 => \s_axi_awqos[3]\(36),
O => \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \s_axi_awqos[3]\(31),
I1 => \s_axi_awqos[3]\(30),
I2 => \s_axi_awqos[3]\(29),
I3 => \s_axi_awqos[3]\(28),
O => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \s_axi_awqos[3]\(40),
I1 => \s_axi_awqos[3]\(41),
I2 => \s_axi_awqos[3]\(38),
I3 => \s_axi_awqos[3]\(39),
I4 => \s_axi_awqos[3]\(43),
I5 => \s_axi_awqos[3]\(42),
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\
);
\gen_no_arbiter.m_target_hot_i[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^d\(1),
I1 => \^d\(2),
I2 => \^d\(0),
I3 => \^address_hit_0\,
O => \^match\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_awtarget_hot(0),
Q => \^q\(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(0),
Q => \^q\(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(1),
Q => \^q\(2),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(2),
Q => \^q\(3),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \s_axi_awaddr[24]\(0),
Q => \^q\(4),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF1F00"
)
port map (
I0 => m_ready_d(1),
I1 => \^mi_awready_mux__3\,
I2 => \^s_ready_i0__1\(0),
I3 => \^aa_sa_awvalid\,
I4 => m_valid_i,
O => \gen_no_arbiter.m_valid_i_i_1__0_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1__0_n_0\,
Q => \^aa_sa_awvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i[0]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^ss_aa_awready\,
I1 => s_axi_awvalid(0),
I2 => m_ready_d_0(0),
O => \gen_no_arbiter.s_ready_i_reg[0]_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => E(0),
Q => \^ss_aa_awready\,
R => '0'
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(0),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(1)
);
\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(2),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(2)
);
\m_axi_awvalid[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(3),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(3)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(4),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(2),
I4 => \^q\(3),
O => \sa_wm_awready_mux__3\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \m_ready_d[1]_i_4_n_0\,
I1 => \^q\(1),
I2 => m_axi_awready(1),
I3 => \^q\(2),
I4 => m_axi_awready(2),
O => \^mi_awready_mux__3\
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => m_ready_d(0),
I1 => \^q\(3),
I2 => \^q\(2),
I3 => \^q\(1),
I4 => \^q\(0),
I5 => \^q\(4),
O => \^s_ready_i0__1\(0)
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \^q\(0),
I1 => m_axi_awready(0),
I2 => \^q\(4),
I3 => mi_awready_4,
I4 => m_axi_awready(3),
I5 => \^q\(3),
O => \m_ready_d[1]_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].w_issuing_cnt_reg[24]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
\s_axi_bvalid[0]\ : out STD_LOGIC;
resp_select : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
f_mux4_return : out STD_LOGIC_VECTOR ( 13 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
p_84_in : in STD_LOGIC;
p_66_in : in STD_LOGIC;
p_48_in : in STD_LOGIC;
p_101_in : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
match : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
p_0_out : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
st_mr_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
st_mr_bmesg : in STD_LOGIC_VECTOR ( 7 downto 0 );
p_68_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_24_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_25_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_26_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_36_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_37_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_38_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_39_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6_n_0\ : STD_LOGIC;
signal last_rr_hot : STD_LOGIC;
signal \last_rr_hot[0]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_4__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_5__0_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_5_in6_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in9_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal \^resp_select\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \resp_select__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_bvalid[0]\ : STD_LOGIC;
signal \^s_ready_i_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \w_cmd_pop_0__0\ : STD_LOGIC;
signal \w_cmd_pop_1__0\ : STD_LOGIC;
signal \w_cmd_pop_2__0\ : STD_LOGIC;
signal \w_cmd_pop_3__0\ : STD_LOGIC;
signal \w_cmd_pop_4__0\ : STD_LOGIC;
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[3]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_3\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_3\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[19]_i_3\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_3\ : label is "soft_lutpair156";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_2__0\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_3__0\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \last_rr_hot[1]_i_2__0\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_3__0\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_2__0\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_3__0\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0_i_1\ : label is "soft_lutpair156";
begin
SR(0) <= \^sr\(0);
m_valid_i <= \^m_valid_i\;
resp_select(0) <= \^resp_select\(0);
\s_axi_bvalid[0]\ <= \^s_axi_bvalid[0]\;
s_ready_i_reg(4 downto 0) <= \^s_ready_i_reg\(4 downto 0);
\chosen[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBBBBBBBBB8"
)
port map (
I0 => s_axi_bready(0),
I1 => \^s_axi_bvalid[0]\,
I2 => p_46_out,
I3 => p_128_out,
I4 => p_108_out,
I5 => m_valid_i_reg,
O => need_arbitration
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(0),
Q => \^s_ready_i_reg\(0),
R => \^sr\(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(1),
Q => \^s_ready_i_reg\(1),
R => \^sr\(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(2),
Q => \^s_ready_i_reg\(2),
R => \^sr\(0)
);
\chosen_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(3),
Q => \^s_ready_i_reg\(3),
R => \^sr\(0)
);
\chosen_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(4),
Q => \^s_ready_i_reg\(4),
R => \^sr\(0)
);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(36),
I1 => st_mr_bid(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(24),
I5 => st_mr_bid(12),
O => f_mux4_return(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(46),
I1 => st_mr_bid(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(34),
I5 => st_mr_bid(22),
O => f_mux4_return(10)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_ready_i_reg\(4),
I1 => p_46_out,
O => \^resp_select\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(47),
I1 => st_mr_bid(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(35),
I5 => st_mr_bid(23),
O => f_mux4_return(11)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_68_out,
I1 => \^s_ready_i_reg\(3),
I2 => p_108_out,
I3 => \^s_ready_i_reg\(1),
O => \resp_select__0\(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bmesg(6),
I1 => st_mr_bmesg(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bmesg(4),
I5 => st_mr_bmesg(2),
O => f_mux4_return(12)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bmesg(7),
I1 => st_mr_bmesg(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bmesg(5),
I5 => st_mr_bmesg(3),
O => f_mux4_return(13)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(37),
I1 => st_mr_bid(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(25),
I5 => st_mr_bid(13),
O => f_mux4_return(1)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(38),
I1 => st_mr_bid(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(26),
I5 => st_mr_bid(14),
O => f_mux4_return(2)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(39),
I1 => st_mr_bid(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(27),
I5 => st_mr_bid(15),
O => f_mux4_return(3)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(40),
I1 => st_mr_bid(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(28),
I5 => st_mr_bid(16),
O => f_mux4_return(4)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(41),
I1 => st_mr_bid(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(29),
I5 => st_mr_bid(17),
O => f_mux4_return(5)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(42),
I1 => st_mr_bid(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(30),
I5 => st_mr_bid(18),
O => f_mux4_return(6)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(43),
I1 => st_mr_bid(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(31),
I5 => st_mr_bid(19),
O => f_mux4_return(7)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(44),
I1 => st_mr_bid(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(32),
I5 => st_mr_bid(20),
O => f_mux4_return(8)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(45),
I1 => st_mr_bid(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(33),
I5 => st_mr_bid(21),
O => f_mux4_return(9)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(1),
I1 => w_issuing_cnt(2),
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(3),
I4 => \w_cmd_pop_0__0\,
I5 => p_101_in,
O => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(0),
I1 => p_128_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_0__0\
);
\gen_master_slots[1].w_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(5),
I1 => w_issuing_cnt(6),
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(7),
I4 => \w_cmd_pop_1__0\,
I5 => p_84_in,
O => E(0)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(1),
I1 => p_108_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_1__0\
);
\gen_master_slots[2].w_issuing_cnt[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(9),
I1 => w_issuing_cnt(10),
I2 => w_issuing_cnt(8),
I3 => w_issuing_cnt(11),
I4 => \w_cmd_pop_2__0\,
I5 => p_66_in,
O => \gen_master_slots[2].w_issuing_cnt_reg[16]\(0)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(2),
I1 => p_88_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_2__0\
);
\gen_master_slots[3].w_issuing_cnt[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(13),
I1 => w_issuing_cnt(14),
I2 => w_issuing_cnt(12),
I3 => w_issuing_cnt(15),
I4 => \w_cmd_pop_3__0\,
I5 => p_48_in,
O => \gen_master_slots[3].w_issuing_cnt_reg[24]\(0)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(3),
I1 => p_68_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_3__0\
);
\gen_no_arbiter.m_mesg_i[11]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => \gen_no_arbiter.s_ready_i_reg[0]\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\,
I5 => aa_sa_awvalid,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8888888AAAAAAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_0\,
I1 => \gen_multi_thread.accept_cnt_reg[0]\,
I2 => \^s_axi_bvalid[0]\,
I3 => p_0_out,
I4 => s_axi_bready(0),
I5 => Q(0),
O => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_36_n_0\,
I1 => \s_axi_awaddr[30]\(0),
I2 => ADDRESS_HIT_0,
I3 => \gen_no_arbiter.s_ready_i[0]_i_37_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"ECA0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_38_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_39_n_0\,
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_26_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(4),
I1 => p_46_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_36\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_1__0\,
I1 => w_issuing_cnt(4),
I2 => w_issuing_cnt(7),
I3 => w_issuing_cnt(5),
I4 => w_issuing_cnt(6),
O => \gen_no_arbiter.s_ready_i[0]_i_36_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_37\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_0__0\,
I1 => w_issuing_cnt(0),
I2 => w_issuing_cnt(3),
I3 => w_issuing_cnt(1),
I4 => w_issuing_cnt(2),
O => \gen_no_arbiter.s_ready_i[0]_i_37_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_38\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_2__0\,
I1 => w_issuing_cnt(8),
I2 => w_issuing_cnt(11),
I3 => w_issuing_cnt(9),
I4 => w_issuing_cnt(10),
O => \gen_no_arbiter.s_ready_i[0]_i_38_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_39\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_3__0\,
I1 => w_issuing_cnt(12),
I2 => w_issuing_cnt(15),
I3 => w_issuing_cnt(13),
I4 => w_issuing_cnt(14),
O => \gen_no_arbiter.s_ready_i[0]_i_39_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8AAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\,
I2 => \gen_no_arbiter.s_ready_i[0]_i_26_n_0\,
I3 => \w_cmd_pop_4__0\,
I4 => match,
I5 => w_issuing_cnt(16),
O => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\
);
\last_rr_hot[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_128_out,
I1 => p_68_out,
I2 => p_46_out,
I3 => \last_rr_hot[0]_i_2__0_n_0\,
I4 => \last_rr_hot[0]_i_3__0_n_0\,
I5 => p_6_in,
O => next_rr_hot(0)
);
\last_rr_hot[0]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_5_in6_in,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_108_out,
I3 => p_88_out,
O => \last_rr_hot[0]_i_2__0_n_0\
);
\last_rr_hot[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_46_out,
I1 => p_7_in9_in,
I2 => p_8_in,
O => \last_rr_hot[0]_i_3__0_n_0\
);
\last_rr_hot[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_108_out,
I1 => p_128_out,
I2 => p_46_out,
I3 => \last_rr_hot[1]_i_2__0_n_0\,
I4 => \last_rr_hot[4]_i_4__0_n_0\,
I5 => p_7_in9_in,
O => next_rr_hot(1)
);
\last_rr_hot[1]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_6_in,
I1 => p_5_in6_in,
I2 => p_88_out,
I3 => p_68_out,
O => \last_rr_hot[1]_i_2__0_n_0\
);
\last_rr_hot[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_88_out,
I1 => m_valid_i_reg_0,
I2 => \last_rr_hot[4]_i_5__0_n_0\,
I3 => p_46_out,
I4 => \last_rr_hot[2]_i_3__0_n_0\,
I5 => p_8_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_108_out,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_5_in6_in,
O => \last_rr_hot[2]_i_3__0_n_0\
);
\last_rr_hot[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_68_out,
I1 => p_108_out,
I2 => p_88_out,
I3 => \last_rr_hot[3]_i_2__0_n_0\,
I4 => \last_rr_hot[3]_i_3__0_n_0\,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(3)
);
\last_rr_hot[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_8_in,
I1 => p_7_in9_in,
I2 => p_46_out,
I3 => p_128_out,
O => \last_rr_hot[3]_i_2__0_n_0\
);
\last_rr_hot[3]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_88_out,
I1 => p_5_in6_in,
I2 => p_6_in,
O => \last_rr_hot[3]_i_3__0_n_0\
);
\last_rr_hot[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(3),
I2 => next_rr_hot(2),
I3 => next_rr_hot(1),
I4 => next_rr_hot(0),
I5 => next_rr_hot(4),
O => last_rr_hot
);
\last_rr_hot[4]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_46_out,
I1 => m_valid_i_reg,
I2 => \last_rr_hot[4]_i_4__0_n_0\,
I3 => p_108_out,
I4 => \last_rr_hot[4]_i_5__0_n_0\,
I5 => p_5_in6_in,
O => next_rr_hot(4)
);
\last_rr_hot[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_128_out,
I1 => p_8_in,
I2 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[4]_i_4__0_n_0\
);
\last_rr_hot[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_68_out,
I1 => p_6_in,
I2 => p_7_in9_in,
O => \last_rr_hot[4]_i_5__0_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(0),
Q => \last_rr_hot_reg_n_0_[0]\,
R => \^sr\(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(1),
Q => p_5_in6_in,
R => \^sr\(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(2),
Q => p_6_in,
R => \^sr\(0)
);
\last_rr_hot_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(3),
Q => p_7_in9_in,
R => \^sr\(0)
);
\last_rr_hot_reg[4]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(4),
Q => p_8_in,
S => \^sr\(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \^resp_select\(0),
I1 => p_128_out,
I2 => \^s_ready_i_reg\(0),
I3 => p_108_out,
I4 => \^s_ready_i_reg\(1),
I5 => \resp_select__0\(1),
O => \^s_axi_bvalid[0]\
);
\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_68_out,
I1 => \^s_ready_i_reg\(3),
I2 => p_88_out,
I3 => \^s_ready_i_reg\(2),
O => \resp_select__0\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_8 is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
f_mux4_return : out STD_LOGIC_VECTOR ( 46 downto 0 );
\s_axi_rvalid[0]\ : out STD_LOGIC;
resp_select : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
match : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : in STD_LOGIC;
st_mr_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
st_mr_rmesg : in STD_LOGIC_VECTOR ( 135 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_62_out : in STD_LOGIC;
p_102_out : in STD_LOGIC;
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[34]_4\ : in STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_40_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_8 : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_8;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_8 is
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\ : STD_LOGIC;
signal last_rr_hot : STD_LOGIC;
signal \last_rr_hot[0]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_4_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_5_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_in1_in : STD_LOGIC_VECTOR ( 3 downto 1 );
signal p_5_in6_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in9_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal \^resp_select\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \resp_select__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_rvalid[0]\ : STD_LOGIC;
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[3]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_2\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_3\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \last_rr_hot[1]_i_2\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_3\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_2\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_3\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_4\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_5\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__2\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__3\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0_i_3\ : label is "soft_lutpair123";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
m_valid_i <= \^m_valid_i\;
resp_select(0) <= \^resp_select\(0);
\s_axi_rvalid[0]\ <= \^s_axi_rvalid[0]\;
\chosen[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBBBBBBBBB8"
)
port map (
I0 => s_axi_rready(0),
I1 => \^s_axi_rvalid[0]\,
I2 => p_40_out,
I3 => p_122_out,
I4 => p_102_out,
I5 => m_valid_i_reg,
O => need_arbitration
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(0),
Q => \^q\(0),
R => SR(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(1),
Q => \^q\(1),
R => SR(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(2),
Q => \^q\(2),
R => SR(0)
);
\chosen_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(3),
Q => \^q\(3),
R => SR(0)
);
\chosen_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(4),
Q => \^q\(4),
R => SR(0)
);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(36),
I1 => st_mr_rid(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(24),
I5 => st_mr_rid(12),
O => f_mux4_return(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(46),
I1 => st_mr_rid(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(34),
I5 => st_mr_rid(22),
O => f_mux4_return(10)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(4),
I1 => p_40_out,
O => \^resp_select\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(47),
I1 => st_mr_rid(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(35),
I5 => st_mr_rid(23),
O => f_mux4_return(11)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_62_out,
I1 => \^q\(3),
I2 => p_102_out,
I3 => \^q\(1),
O => \resp_select__0\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_62_out,
I1 => \^q\(3),
I2 => p_82_out,
I3 => \^q\(2),
O => \resp_select__0\(1)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(102),
I1 => st_mr_rmesg(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(68),
I5 => st_mr_rmesg(34),
O => f_mux4_return(12)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(103),
I1 => st_mr_rmesg(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(69),
I5 => st_mr_rmesg(35),
O => f_mux4_return(13)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(104),
I1 => st_mr_rmesg(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(70),
I5 => st_mr_rmesg(36),
O => f_mux4_return(14)
);
\gen_fpga.gen_mux_5_8[16].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(105),
I1 => st_mr_rmesg(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(71),
I5 => st_mr_rmesg(37),
O => f_mux4_return(15)
);
\gen_fpga.gen_mux_5_8[17].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(106),
I1 => st_mr_rmesg(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(72),
I5 => st_mr_rmesg(38),
O => f_mux4_return(16)
);
\gen_fpga.gen_mux_5_8[18].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(107),
I1 => st_mr_rmesg(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(73),
I5 => st_mr_rmesg(39),
O => f_mux4_return(17)
);
\gen_fpga.gen_mux_5_8[19].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(108),
I1 => st_mr_rmesg(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(74),
I5 => st_mr_rmesg(40),
O => f_mux4_return(18)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(37),
I1 => st_mr_rid(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(25),
I5 => st_mr_rid(13),
O => f_mux4_return(1)
);
\gen_fpga.gen_mux_5_8[20].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(109),
I1 => st_mr_rmesg(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(75),
I5 => st_mr_rmesg(41),
O => f_mux4_return(19)
);
\gen_fpga.gen_mux_5_8[21].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(110),
I1 => st_mr_rmesg(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(76),
I5 => st_mr_rmesg(42),
O => f_mux4_return(20)
);
\gen_fpga.gen_mux_5_8[22].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(111),
I1 => st_mr_rmesg(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(77),
I5 => st_mr_rmesg(43),
O => f_mux4_return(21)
);
\gen_fpga.gen_mux_5_8[23].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(112),
I1 => st_mr_rmesg(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(78),
I5 => st_mr_rmesg(44),
O => f_mux4_return(22)
);
\gen_fpga.gen_mux_5_8[24].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(113),
I1 => st_mr_rmesg(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(79),
I5 => st_mr_rmesg(45),
O => f_mux4_return(23)
);
\gen_fpga.gen_mux_5_8[25].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(114),
I1 => st_mr_rmesg(12),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(80),
I5 => st_mr_rmesg(46),
O => f_mux4_return(24)
);
\gen_fpga.gen_mux_5_8[26].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(115),
I1 => st_mr_rmesg(13),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(81),
I5 => st_mr_rmesg(47),
O => f_mux4_return(25)
);
\gen_fpga.gen_mux_5_8[27].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(116),
I1 => st_mr_rmesg(14),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(82),
I5 => st_mr_rmesg(48),
O => f_mux4_return(26)
);
\gen_fpga.gen_mux_5_8[28].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(117),
I1 => st_mr_rmesg(15),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(83),
I5 => st_mr_rmesg(49),
O => f_mux4_return(27)
);
\gen_fpga.gen_mux_5_8[29].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(118),
I1 => st_mr_rmesg(16),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(84),
I5 => st_mr_rmesg(50),
O => f_mux4_return(28)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(38),
I1 => st_mr_rid(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(26),
I5 => st_mr_rid(14),
O => f_mux4_return(2)
);
\gen_fpga.gen_mux_5_8[30].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(119),
I1 => st_mr_rmesg(17),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(85),
I5 => st_mr_rmesg(51),
O => f_mux4_return(29)
);
\gen_fpga.gen_mux_5_8[31].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(120),
I1 => st_mr_rmesg(18),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(86),
I5 => st_mr_rmesg(52),
O => f_mux4_return(30)
);
\gen_fpga.gen_mux_5_8[32].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(121),
I1 => st_mr_rmesg(19),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(87),
I5 => st_mr_rmesg(53),
O => f_mux4_return(31)
);
\gen_fpga.gen_mux_5_8[33].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(122),
I1 => st_mr_rmesg(20),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(88),
I5 => st_mr_rmesg(54),
O => f_mux4_return(32)
);
\gen_fpga.gen_mux_5_8[34].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(123),
I1 => st_mr_rmesg(21),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(89),
I5 => st_mr_rmesg(55),
O => f_mux4_return(33)
);
\gen_fpga.gen_mux_5_8[35].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(124),
I1 => st_mr_rmesg(22),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(90),
I5 => st_mr_rmesg(56),
O => f_mux4_return(34)
);
\gen_fpga.gen_mux_5_8[36].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(125),
I1 => st_mr_rmesg(23),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(91),
I5 => st_mr_rmesg(57),
O => f_mux4_return(35)
);
\gen_fpga.gen_mux_5_8[37].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(126),
I1 => st_mr_rmesg(24),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(92),
I5 => st_mr_rmesg(58),
O => f_mux4_return(36)
);
\gen_fpga.gen_mux_5_8[38].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(127),
I1 => st_mr_rmesg(25),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(93),
I5 => st_mr_rmesg(59),
O => f_mux4_return(37)
);
\gen_fpga.gen_mux_5_8[39].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(128),
I1 => st_mr_rmesg(26),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(94),
I5 => st_mr_rmesg(60),
O => f_mux4_return(38)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(39),
I1 => st_mr_rid(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(27),
I5 => st_mr_rid(15),
O => f_mux4_return(3)
);
\gen_fpga.gen_mux_5_8[40].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(129),
I1 => st_mr_rmesg(27),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(95),
I5 => st_mr_rmesg(61),
O => f_mux4_return(39)
);
\gen_fpga.gen_mux_5_8[41].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(130),
I1 => st_mr_rmesg(28),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(96),
I5 => st_mr_rmesg(62),
O => f_mux4_return(40)
);
\gen_fpga.gen_mux_5_8[42].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(131),
I1 => st_mr_rmesg(29),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(97),
I5 => st_mr_rmesg(63),
O => f_mux4_return(41)
);
\gen_fpga.gen_mux_5_8[43].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(132),
I1 => st_mr_rmesg(30),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(98),
I5 => st_mr_rmesg(64),
O => f_mux4_return(42)
);
\gen_fpga.gen_mux_5_8[44].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(133),
I1 => st_mr_rmesg(31),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(99),
I5 => st_mr_rmesg(65),
O => f_mux4_return(43)
);
\gen_fpga.gen_mux_5_8[45].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(134),
I1 => st_mr_rmesg(32),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(100),
I5 => st_mr_rmesg(66),
O => f_mux4_return(44)
);
\gen_fpga.gen_mux_5_8[46].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(135),
I1 => st_mr_rmesg(33),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(101),
I5 => st_mr_rmesg(67),
O => f_mux4_return(45)
);
\gen_fpga.gen_mux_5_8[47].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => \m_payload_i_reg[34]_0\(0),
I1 => \m_payload_i_reg[34]_1\(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => \m_payload_i_reg[34]_2\(0),
I5 => \m_payload_i_reg[34]_3\(0),
O => f_mux4_return(46)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(40),
I1 => st_mr_rid(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(28),
I5 => st_mr_rid(16),
O => f_mux4_return(4)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(41),
I1 => st_mr_rid(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(29),
I5 => st_mr_rid(17),
O => f_mux4_return(5)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(42),
I1 => st_mr_rid(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(30),
I5 => st_mr_rid(18),
O => f_mux4_return(6)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(43),
I1 => st_mr_rid(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(31),
I5 => st_mr_rid(19),
O => f_mux4_return(7)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(44),
I1 => st_mr_rid(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(32),
I5 => st_mr_rid(20),
O => f_mux4_return(8)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(45),
I1 => st_mr_rid(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(33),
I5 => st_mr_rid(21),
O => f_mux4_return(9)
);
\gen_no_arbiter.s_ready_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => E(0)
);
\gen_no_arbiter.s_ready_i[0]_i_24__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440404044444444"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => s_axi_arvalid(0),
I2 => \gen_multi_thread.accept_cnt_reg[0]\,
I3 => \^s_axi_rvalid[0]\,
I4 => \m_payload_i_reg[34]_4\,
I5 => \gen_multi_thread.accept_cnt_reg[3]\(0),
O => \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\,
I5 => aa_mi_arvalid,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8AAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\,
I1 => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
I2 => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
I3 => \r_cmd_pop_4__1\,
I4 => match,
I5 => r_issuing_cnt(0),
O => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\
);
\last_rr_hot[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_122_out,
I1 => p_62_out,
I2 => p_40_out,
I3 => \last_rr_hot[0]_i_2_n_0\,
I4 => \last_rr_hot[0]_i_3_n_0\,
I5 => p_6_in,
O => next_rr_hot(0)
);
\last_rr_hot[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_5_in6_in,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_102_out,
I3 => p_82_out,
O => \last_rr_hot[0]_i_2_n_0\
);
\last_rr_hot[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_40_out,
I1 => p_7_in9_in,
I2 => p_8_in,
O => \last_rr_hot[0]_i_3_n_0\
);
\last_rr_hot[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_102_out,
I1 => p_40_out,
I2 => p_122_out,
I3 => \last_rr_hot[1]_i_2_n_0\,
I4 => \last_rr_hot[4]_i_4_n_0\,
I5 => p_7_in9_in,
O => next_rr_hot(1)
);
\last_rr_hot[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_6_in,
I1 => p_5_in6_in,
I2 => p_82_out,
I3 => p_62_out,
O => \last_rr_hot[1]_i_2_n_0\
);
\last_rr_hot[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_82_out,
I1 => m_valid_i_reg_0,
I2 => \last_rr_hot[4]_i_5_n_0\,
I3 => p_40_out,
I4 => \last_rr_hot[2]_i_3_n_0\,
I5 => p_8_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_102_out,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_5_in6_in,
O => \last_rr_hot[2]_i_3_n_0\
);
\last_rr_hot[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_62_out,
I1 => p_102_out,
I2 => p_82_out,
I3 => \last_rr_hot[3]_i_2_n_0\,
I4 => \last_rr_hot[3]_i_3_n_0\,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(3)
);
\last_rr_hot[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_8_in,
I1 => p_7_in9_in,
I2 => p_40_out,
I3 => p_122_out,
O => \last_rr_hot[3]_i_2_n_0\
);
\last_rr_hot[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_82_out,
I1 => p_5_in6_in,
I2 => p_6_in,
O => \last_rr_hot[3]_i_3_n_0\
);
\last_rr_hot[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(3),
I2 => next_rr_hot(2),
I3 => next_rr_hot(1),
I4 => next_rr_hot(0),
I5 => next_rr_hot(4),
O => last_rr_hot
);
\last_rr_hot[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_40_out,
I1 => m_valid_i_reg,
I2 => \last_rr_hot[4]_i_4_n_0\,
I3 => p_102_out,
I4 => \last_rr_hot[4]_i_5_n_0\,
I5 => p_5_in6_in,
O => next_rr_hot(4)
);
\last_rr_hot[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_122_out,
I1 => p_8_in,
I2 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[4]_i_4_n_0\
);
\last_rr_hot[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_62_out,
I1 => p_6_in,
I2 => p_7_in9_in,
O => \last_rr_hot[4]_i_5_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(0),
Q => \last_rr_hot_reg_n_0_[0]\,
R => SR(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(1),
Q => p_5_in6_in,
R => SR(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(2),
Q => p_6_in,
R => SR(0)
);
\last_rr_hot_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(3),
Q => p_7_in9_in,
R => SR(0)
);
\last_rr_hot_reg[4]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(4),
Q => p_8_in,
S => SR(0)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(0),
I1 => s_axi_rready(0),
I2 => p_122_out,
O => \m_payload_i_reg[0]\(0)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(1),
I1 => s_axi_rready(0),
I2 => p_102_out,
O => \m_payload_i_reg[0]_0\(0)
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(4),
I1 => s_axi_rready(0),
I2 => p_40_out,
O => \m_payload_i_reg[34]\(0)
);
\m_payload_i[46]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(3),
I1 => s_axi_rready(0),
I2 => p_62_out,
O => \m_payload_i_reg[0]_1\(0)
);
\m_payload_i[46]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(2),
I1 => s_axi_rready(0),
I2 => p_82_out,
O => \m_payload_i_reg[0]_2\(0)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF8"
)
port map (
I0 => \^q\(0),
I1 => p_122_out,
I2 => p_0_in1_in(2),
I3 => p_0_in1_in(1),
I4 => p_0_in1_in(3),
I5 => \^resp_select\(0),
O => \^s_axi_rvalid[0]\
);
\s_axi_rvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(2),
I1 => p_82_out,
O => p_0_in1_in(2)
);
\s_axi_rvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(1),
I1 => p_102_out,
O => p_0_in1_in(1)
);
\s_axi_rvalid[0]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(3),
I1 => p_62_out,
O => p_0_in1_in(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_decerr_slave is
port (
mi_awready_4 : out STD_LOGIC;
p_22_in : out STD_LOGIC;
p_29_in : out STD_LOGIC;
p_23_in : out STD_LOGIC;
p_25_in : out STD_LOGIC;
\read_cs__0\ : out STD_LOGIC;
mi_arready_4 : out STD_LOGIC;
\m_payload_i_reg[13]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_rready_4 : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[51]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
mi_bready_4 : in STD_LOGIC;
\write_cs0__0\ : in STD_LOGIC;
write_cs01_out : in STD_LOGIC;
s_axi_rlast_i0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aresetn_d : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_decerr_slave : entity is "axi_crossbar_v2_1_14_decerr_slave";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_decerr_slave;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_decerr_slave is
signal \gen_axi.read_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt_reg\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bid_i[11]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \^mi_arready_4\ : STD_LOGIC;
signal \^mi_awready_4\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^p_22_in\ : STD_LOGIC;
signal \^p_23_in\ : STD_LOGIC;
signal \^p_25_in\ : STD_LOGIC;
signal \^p_29_in\ : STD_LOGIC;
signal \^read_cs__0\ : STD_LOGIC;
signal write_cs : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[4]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_3\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair16";
begin
mi_arready_4 <= \^mi_arready_4\;
mi_awready_4 <= \^mi_awready_4\;
p_22_in <= \^p_22_in\;
p_23_in <= \^p_23_in\;
p_25_in <= \^p_25_in\;
p_29_in <= \^p_29_in\;
\read_cs__0\ <= \^read_cs__0\;
\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(0),
I1 => \^p_23_in\,
I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(12),
O => p_0_in(0)
);
\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E22E"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(13),
I1 => \^p_23_in\,
I2 => \gen_axi.read_cnt_reg__0\(0),
I3 => \gen_axi.read_cnt_reg\(1),
O => p_0_in(1)
);
\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCAA03AA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(14),
I1 => \gen_axi.read_cnt_reg\(1),
I2 => \gen_axi.read_cnt_reg__0\(0),
I3 => \^p_23_in\,
I4 => \gen_axi.read_cnt_reg\(2),
O => p_0_in(2)
);
\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCAAAA0003AAAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(15),
I1 => \gen_axi.read_cnt_reg__0\(0),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg\(2),
I4 => \^p_23_in\,
I5 => \gen_axi.read_cnt_reg\(3),
O => p_0_in(3)
);
\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCAAAA0003AAAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(16),
I1 => \gen_axi.read_cnt_reg\(2),
I2 => \gen_axi.read_cnt[4]_i_2_n_0\,
I3 => \gen_axi.read_cnt_reg\(3),
I4 => \^p_23_in\,
I5 => \gen_axi.read_cnt_reg\(4),
O => p_0_in(4)
);
\gen_axi.read_cnt[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \gen_axi.read_cnt_reg\(1),
I1 => \gen_axi.read_cnt_reg__0\(0),
O => \gen_axi.read_cnt[4]_i_2_n_0\
);
\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CA3A"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(17),
I1 => \gen_axi.read_cnt[5]_i_2_n_0\,
I2 => \^p_23_in\,
I3 => \gen_axi.read_cnt_reg\(5),
O => p_0_in(5)
);
\gen_axi.read_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg\(3),
I1 => \gen_axi.read_cnt_reg__0\(0),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg\(2),
I4 => \gen_axi.read_cnt_reg\(4),
O => \gen_axi.read_cnt[5]_i_2_n_0\
);
\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CA3A"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(18),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \^p_23_in\,
I3 => \gen_axi.read_cnt_reg\(6),
O => p_0_in(6)
);
\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F40404040404040"
)
port map (
I0 => \^read_cs__0\,
I1 => mi_rready_4,
I2 => \^p_23_in\,
I3 => \^mi_arready_4\,
I4 => aa_mi_arvalid,
I5 => \gen_no_arbiter.m_target_hot_i_reg[4]\(0),
O => \gen_axi.read_cnt[7]_i_1_n_0\
);
\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCAA03AA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(19),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg\(6),
I3 => \^p_23_in\,
I4 => \gen_axi.read_cnt_reg\(7),
O => p_0_in(7)
);
\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(2),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg__0\(0),
I4 => \gen_axi.read_cnt_reg\(3),
I5 => \gen_axi.read_cnt_reg\(5),
O => \gen_axi.read_cnt[7]_i_3_n_0\
);
\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(0),
Q => \gen_axi.read_cnt_reg__0\(0),
R => SR(0)
);
\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(1),
Q => \gen_axi.read_cnt_reg\(1),
R => SR(0)
);
\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(2),
Q => \gen_axi.read_cnt_reg\(2),
R => SR(0)
);
\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(3),
Q => \gen_axi.read_cnt_reg\(3),
R => SR(0)
);
\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(4),
Q => \gen_axi.read_cnt_reg\(4),
R => SR(0)
);
\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(5),
Q => \gen_axi.read_cnt_reg\(5),
R => SR(0)
);
\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(6),
Q => \gen_axi.read_cnt_reg\(6),
R => SR(0)
);
\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(7),
Q => \gen_axi.read_cnt_reg\(7),
R => SR(0)
);
\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F70707070707070"
)
port map (
I0 => \^read_cs__0\,
I1 => mi_rready_4,
I2 => \^p_23_in\,
I3 => \^mi_arready_4\,
I4 => aa_mi_arvalid,
I5 => \gen_no_arbiter.m_target_hot_i_reg[4]\(0),
O => \gen_axi.read_cs[0]_i_1_n_0\
);
\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.read_cs[0]_i_1_n_0\,
Q => \^p_23_in\,
R => SR(0)
);
\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FBBB0000"
)
port map (
I0 => \^mi_arready_4\,
I1 => \^p_23_in\,
I2 => \^read_cs__0\,
I3 => mi_rready_4,
I4 => aresetn_d,
I5 => E(0),
O => \gen_axi.s_axi_arready_i_i_1_n_0\
);
\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_axi.read_cnt[4]_i_2_n_0\,
I1 => \gen_axi.read_cnt_reg\(6),
I2 => \gen_axi.read_cnt_reg\(7),
I3 => \gen_axi.s_axi_arready_i_i_3_n_0\,
I4 => \gen_axi.read_cnt_reg\(2),
I5 => \gen_axi.read_cnt_reg\(3),
O => \^read_cs__0\
);
\gen_axi.s_axi_arready_i_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(5),
O => \gen_axi.s_axi_arready_i_i_3_n_0\
);
\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_arready_i_i_1_n_0\,
Q => \^mi_arready_4\,
R => '0'
);
\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFBB0000F0FF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => Q(0),
I2 => mi_bready_4,
I3 => write_cs(1),
I4 => write_cs(0),
I5 => \^mi_awready_4\,
O => \gen_axi.s_axi_awready_i_i_1_n_0\
);
\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_awready_i_i_1_n_0\,
Q => \^mi_awready_4\,
R => SR(0)
);
\gen_axi.s_axi_bid_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => write_cs(1),
I1 => write_cs(0),
I2 => m_ready_d(0),
I3 => aa_sa_awvalid,
I4 => Q(0),
I5 => \^mi_awready_4\,
O => \gen_axi.s_axi_bid_i[11]_i_1_n_0\
);
\gen_axi.s_axi_bid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(0),
Q => \m_payload_i_reg[13]\(0),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(10),
Q => \m_payload_i_reg[13]\(10),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(11),
Q => \m_payload_i_reg[13]\(11),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(1),
Q => \m_payload_i_reg[13]\(1),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(2),
Q => \m_payload_i_reg[13]\(2),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(3),
Q => \m_payload_i_reg[13]\(3),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(4),
Q => \m_payload_i_reg[13]\(4),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(5),
Q => \m_payload_i_reg[13]\(5),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(6),
Q => \m_payload_i_reg[13]\(6),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(7),
Q => \m_payload_i_reg[13]\(7),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(8),
Q => \m_payload_i_reg[13]\(8),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(9),
Q => \m_payload_i_reg[13]\(9),
R => SR(0)
);
\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFF00C0"
)
port map (
I0 => mi_bready_4,
I1 => write_cs(0),
I2 => \write_cs0__0\,
I3 => write_cs(1),
I4 => \^p_29_in\,
O => \gen_axi.s_axi_bvalid_i_i_1_n_0\
);
\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_i_1_n_0\,
Q => \^p_29_in\,
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(0),
Q => \skid_buffer_reg[46]\(0),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(10),
Q => \skid_buffer_reg[46]\(10),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(11),
Q => \skid_buffer_reg[46]\(11),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(1),
Q => \skid_buffer_reg[46]\(1),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(2),
Q => \skid_buffer_reg[46]\(2),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(3),
Q => \skid_buffer_reg[46]\(3),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(4),
Q => \skid_buffer_reg[46]\(4),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(5),
Q => \skid_buffer_reg[46]\(5),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(6),
Q => \skid_buffer_reg[46]\(6),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(7),
Q => \skid_buffer_reg[46]\(7),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(8),
Q => \skid_buffer_reg[46]\(8),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(9),
Q => \skid_buffer_reg[46]\(9),
R => SR(0)
);
\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFBFFAAAA0800"
)
port map (
I0 => s_axi_rlast_i0,
I1 => \gen_axi.s_axi_rlast_i_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.s_axi_rlast_i_i_4_n_0\,
I4 => E(0),
I5 => \^p_25_in\,
O => \gen_axi.s_axi_rlast_i_i_1_n_0\
);
\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \gen_axi.read_cnt_reg\(2),
I1 => \gen_axi.read_cnt_reg\(3),
O => \gen_axi.s_axi_rlast_i_i_3_n_0\
);
\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(5),
I2 => \gen_axi.read_cnt_reg\(6),
I3 => \gen_axi.read_cnt_reg\(7),
I4 => mi_rready_4,
I5 => \^p_23_in\,
O => \gen_axi.s_axi_rlast_i_i_4_n_0\
);
\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_rlast_i_i_1_n_0\,
Q => \^p_25_in\,
R => SR(0)
);
\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF5F000C"
)
port map (
I0 => \write_cs0__0\,
I1 => write_cs01_out,
I2 => write_cs(0),
I3 => write_cs(1),
I4 => \^p_22_in\,
O => \gen_axi.s_axi_wready_i_i_1_n_0\
);
\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_wready_i_i_1_n_0\,
Q => \^p_22_in\,
R => SR(0)
);
\gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4522"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => write_cs(1),
I2 => \write_cs0__0\,
I3 => write_cs(0),
O => \gen_axi.write_cs[0]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE00FE44"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => write_cs(1),
I2 => \write_cs0__0\,
I3 => write_cs(0),
I4 => mi_bready_4,
O => \gen_axi.write_cs[1]_i_1_n_0\
);
\gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[0]_i_1_n_0\,
Q => write_cs(0),
R => SR(0)
);
\gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[1]_i_1_n_0\,
Q => write_cs(1),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter is
port (
\s_axi_awready[0]\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
ss_wr_awvalid : out STD_LOGIC;
ss_wr_awready : in STD_LOGIC;
ss_aa_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter : entity is "axi_crossbar_v2_1_14_splitter";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_valid_i_i_2__0\ : label is "soft_lutpair190";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair190";
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0008000C0000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => ss_wr_awready,
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000C8C0"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => ss_wr_awready,
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\m_valid_i_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
O => ss_wr_awvalid
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEE0"
)
port map (
I0 => \^m_ready_d\(1),
I1 => ss_wr_awready,
I2 => \^m_ready_d\(0),
I3 => ss_aa_awready,
O => \s_axi_awready[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter_5 is
port (
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_axi.s_axi_awready_i_reg\ : out STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[19]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[3].w_issuing_cnt_reg[27]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].w_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 15 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_108_out : in STD_LOGIC;
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_88_out : in STD_LOGIC;
p_68_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\mi_awready_mux__3\ : in STD_LOGIC;
\s_ready_i0__1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\sa_wm_awready_mux__3\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter_5 : entity is "axi_crossbar_v2_1_14_splitter";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter_5;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter_5 is
signal \^gen_axi.s_axi_awready_i_reg\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\ : STD_LOGIC;
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_awready_i_i_2\ : label is "soft_lutpair194";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[2]_i_1\ : label is "soft_lutpair197";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_2\ : label is "soft_lutpair197";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[10]_i_1\ : label is "soft_lutpair193";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_2\ : label is "soft_lutpair193";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[18]_i_1\ : label is "soft_lutpair195";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[19]_i_2\ : label is "soft_lutpair195";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[26]_i_1\ : label is "soft_lutpair196";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_2\ : label is "soft_lutpair196";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_1\ : label is "soft_lutpair194";
begin
\gen_axi.s_axi_awready_i_reg\ <= \^gen_axi.s_axi_awready_i_reg\;
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\gen_axi.s_axi_awready_i_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_ready_d\(1),
I1 => aa_sa_awvalid,
O => \^gen_axi.s_axi_awready_i_reg\
);
\gen_master_slots[0].w_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(0),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(1),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].w_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I1 => w_issuing_cnt(0),
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(1),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(3),
I4 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(0),
I2 => m_axi_awready(0),
I3 => s_axi_bready(0),
I4 => p_128_out,
I5 => \chosen_reg[3]\(0),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I1 => w_issuing_cnt(4),
I2 => w_issuing_cnt(5),
I3 => w_issuing_cnt(6),
O => D(1)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(5),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(7),
I4 => w_issuing_cnt(6),
O => D(2)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(1),
I2 => m_axi_awready(1),
I3 => s_axi_bready(0),
I4 => p_108_out,
I5 => \chosen_reg[3]\(1),
O => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(4),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(5),
O => D(0)
);
\gen_master_slots[2].w_issuing_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(8),
I1 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I2 => w_issuing_cnt(9),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(0)
);
\gen_master_slots[2].w_issuing_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I1 => w_issuing_cnt(8),
I2 => w_issuing_cnt(9),
I3 => w_issuing_cnt(10),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(1)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(9),
I1 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I2 => w_issuing_cnt(8),
I3 => w_issuing_cnt(11),
I4 => w_issuing_cnt(10),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(2)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(2),
I2 => m_axi_awready(2),
I3 => s_axi_bready(0),
I4 => p_88_out,
I5 => \chosen_reg[3]\(2),
O => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\
);
\gen_master_slots[3].w_issuing_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(12),
I1 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I2 => w_issuing_cnt(13),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(0)
);
\gen_master_slots[3].w_issuing_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I1 => w_issuing_cnt(12),
I2 => w_issuing_cnt(13),
I3 => w_issuing_cnt(14),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(1)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(13),
I1 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I2 => w_issuing_cnt(12),
I3 => w_issuing_cnt(15),
I4 => w_issuing_cnt(14),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(2)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(3),
I2 => m_axi_awready(3),
I3 => s_axi_bready(0),
I4 => p_68_out,
I5 => \chosen_reg[3]\(3),
O => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0008000C0000"
)
port map (
I0 => aa_sa_awvalid,
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => \mi_awready_mux__3\,
I4 => \^m_ready_d\(0),
I5 => \sa_wm_awready_mux__3\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000C8C0"
)
port map (
I0 => aa_sa_awvalid,
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => \mi_awready_mux__3\,
I4 => \s_ready_i0__1\(0),
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
push : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
out0 : in STD_LOGIC_VECTOR ( 0 to 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
signal \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\ : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => D(0),
Q => \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\storage_data1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0EEFFFFF0EE0000"
)
port map (
I0 => \s_axi_awaddr[30]\(1),
I1 => \s_axi_awaddr[30]\(0),
I2 => \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\,
I3 => out0(0),
I4 => load_s1,
I5 => m_select_enc(0),
O => \storage_data1_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ is
port (
\storage_data1_reg[1]\ : out STD_LOGIC;
push : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
out0 : in STD_LOGIC_VECTOR ( 0 to 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ is
signal p_2_out : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => D(0),
Q => p_2_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\storage_data1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0EEFFFFF0EE0000"
)
port map (
I0 => \s_axi_awaddr[30]\(1),
I1 => \s_axi_awaddr[30]\(0),
I2 => p_2_out,
I3 => out0(0),
I4 => load_s1,
I5 => m_select_enc(0),
O => \storage_data1_reg[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ is
port (
push : out STD_LOGIC;
\storage_data1_reg[2]\ : out STD_LOGIC;
\m_aready__1\ : out STD_LOGIC;
\m_aready0__3\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
match : in STD_LOGIC;
out0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
ss_wr_awready : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ is
signal \^m_aready0__3\ : STD_LOGIC;
signal \^m_aready__1\ : STD_LOGIC;
signal p_3_out : STD_LOGIC;
signal \^push\ : STD_LOGIC;
signal \s_axi_wready[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[2].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[2].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\m_aready0__3\ <= \^m_aready0__3\;
\m_aready__1\ <= \^m_aready__1\;
push <= \^push\;
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => \^push\,
CLK => aclk,
D => D(0),
Q => p_3_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0088000000F80000"
)
port map (
I0 => ss_wr_awready,
I1 => out0(0),
I2 => out0(1),
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => \^m_aready__1\,
O => \^push\
);
\m_valid_i_i_1__8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => s_axi_wlast(0),
I1 => m_avalid,
I2 => s_axi_wvalid(0),
I3 => \^m_aready0__3\,
O => \^m_aready__1\
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAFEAAAAAAAEA"
)
port map (
I0 => \s_axi_wready[0]_INST_0_i_2_n_0\,
I1 => m_axi_wready(1),
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
I5 => m_axi_wready(2),
O => \^m_aready0__3\
);
\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0000CA000000CA"
)
port map (
I0 => m_axi_wready(0),
I1 => p_22_in,
I2 => m_select_enc(2),
I3 => m_select_enc(1),
I4 => m_select_enc(0),
I5 => m_axi_wready(3),
O => \s_axi_wready[0]_INST_0_i_2_n_0\
);
\storage_data1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"C5FFC500"
)
port map (
I0 => match,
I1 => p_3_out,
I2 => out0(0),
I3 => load_s1,
I4 => m_select_enc(2),
O => \storage_data1_reg[2]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
\m_payload_i_reg[2]_0\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
mi_bready_4 : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_29_in : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\ : STD_LOGIC;
signal \^m_payload_i_reg[2]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^mi_bready_4\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
begin
\m_payload_i_reg[2]_0\ <= \^m_payload_i_reg[2]_0\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
mi_bready_4 <= \^mi_bready_4\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]\,
Q => \^s_ready_i_reg_0\,
R => '0'
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => p_29_in,
I1 => \^mi_bready_4\,
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[2]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__0_n_0\
);
\m_valid_i_i_1__9\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg_0\,
O => \^m_valid_i_reg_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => \^m_payload_i_reg[2]_0\,
R => \^m_valid_i_reg_0\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
I1 => p_29_in,
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^mi_bready_4\,
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
\m_axi_bid[35]\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC;
signal \s_ready_i_i_1__3_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__2_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__2_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__3_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__3_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
\m_axi_bid[23]\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__1_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_1_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__1_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__1_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
p_108_out : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__0_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\last_rr_hot[2]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_108_out,
O => \chosen_reg[2]\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
m_valid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => m_valid_i_i_2_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_2_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__0_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__0_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
\chosen_reg[4]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
p_88_out : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^p_1_in\ : STD_LOGIC;
signal s_ready_i_i_2_n_0 : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
p_1_in <= \^p_1_in\;
\aresetn_d[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(1),
I1 => aresetn,
O => \aresetn_d_reg[1]\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => p_0_in(1),
R => '0'
);
\last_rr_hot[4]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_88_out,
O => \chosen_reg[4]\
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]_0\
);
s_ready_i_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(1),
O => \^p_1_in\
);
s_ready_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_1\,
O => s_ready_i_i_2_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i_i_2_n_0,
Q => \^m_axi_bready\(0),
R => \^p_1_in\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\skid_buffer_reg[34]_0\ : out STD_LOGIC;
\r_cmd_pop_4__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_23_in : in STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_25_in : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \s_ready_i_i_1__6_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 34 );
signal \^skid_buffer_reg[34]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__3\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__3\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__3\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__3\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__3\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__3\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__3\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__3\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__3\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__3\ : label is "soft_lutpair114";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0);
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\skid_buffer_reg[34]_0\ <= \^skid_buffer_reg[34]_0\;
\gen_master_slots[4].r_issuing_cnt[32]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
I1 => \chosen_reg[4]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \r_cmd_pop_4__1\
);
\m_payload_i[34]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_25_in,
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(0),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(1),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(2),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(3),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(4),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[40]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(5),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(6),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(7),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(8),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(9),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(10),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(11),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_valid_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^skid_buffer_reg[34]_0\,
I1 => p_23_in,
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[4]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__6\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[4]\(0),
I3 => \^skid_buffer_reg[34]_0\,
I4 => p_23_in,
O => \s_ready_i_i_1__6_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__6_n_0\,
Q => \^skid_buffer_reg[34]_0\,
R => p_1_in
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => p_25_in,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[3]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_3__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[4]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_39_in : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\chosen_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_3__1\ : STD_LOGIC;
signal \s_ready_i_i_1__7_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_3\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_3\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__7\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__2\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__2\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__2\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__2\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__2\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__2\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__2\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__2\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__2\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__2\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__2\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__2\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__2\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__2\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair110";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[3]\ <= \^m_axi_rready[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_3__1\ <= \^r_cmd_pop_3__1\;
\gen_master_slots[3].r_issuing_cnt[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1),
I1 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2),
I2 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0),
I3 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(3),
I4 => \^r_cmd_pop_3__1\,
I5 => p_39_in,
O => E(0)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[3]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_3__1\
);
\gen_no_arbiter.s_ready_i[0]_i_38__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_3__1\,
I1 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0),
I2 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(3),
I3 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1),
I4 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\last_rr_hot[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => p_82_out,
O => \chosen_reg[4]\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__6\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[3]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[3]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__7\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[3]\(0),
I3 => \^m_axi_rready[3]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__7_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__7_n_0\,
Q => \^m_axi_rready[3]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[2]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_2__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_57_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[24]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\chosen_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0\ : STD_LOGIC;
signal \^m_axi_rready[2]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_2__1\ : STD_LOGIC;
signal \s_ready_i_i_1__8_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__6\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair85";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[2]\ <= \^m_axi_rready[2]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_2__1\ <= \^r_cmd_pop_2__1\;
\gen_master_slots[2].r_issuing_cnt[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1),
I1 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2),
I2 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0),
I3 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3),
I4 => \^r_cmd_pop_2__1\,
I5 => p_57_in,
O => E(0)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[2]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_2__1\
);
\gen_no_arbiter.s_ready_i[0]_i_26__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ECA0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0\,
I1 => \gen_master_slots[3].r_issuing_cnt_reg[24]\,
I2 => D(0),
I3 => D(1),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_37__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_2__1\,
I1 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0),
I2 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3),
I3 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1),
I4 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0\
);
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__7\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[2]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[2]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__8\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[2]\(0),
I3 => \^m_axi_rready[2]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__8_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__8_n_0\,
Q => \^m_axi_rready[2]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_1__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_75_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\chosen_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0\ : STD_LOGIC;
signal \^m_axi_rready[1]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_1__1\ : STD_LOGIC;
signal \s_ready_i_i_1__5_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__5\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair62";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[1]\ <= \^m_axi_rready[1]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_1__1\ <= \^r_cmd_pop_1__1\;
\gen_master_slots[1].r_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1),
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3),
I4 => \^r_cmd_pop_1__1\,
I5 => p_75_in,
O => E(0)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[1]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_1__1\
);
\gen_no_arbiter.s_ready_i[0]_i_25__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0\,
I1 => D(0),
I2 => ADDRESS_HIT_0,
I3 => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_35__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_1__1\,
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1),
I4 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[1]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[1]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[1]\(0),
I3 => \^m_axi_rready[1]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__5_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__5_n_0\,
Q => \^m_axi_rready[1]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_0__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : in STD_LOGIC;
p_102_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\chosen_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[0]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_0__1\ : STD_LOGIC;
signal \s_ready_i_i_1__4_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__4\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair40";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[0]\ <= \^m_axi_rready[0]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_0__1\ <= \^r_cmd_pop_0__1\;
\gen_master_slots[0].r_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1),
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2),
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3),
I4 => \^r_cmd_pop_0__1\,
I5 => p_93_in,
O => E(0)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[0]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_0__1\
);
\gen_no_arbiter.s_ready_i[0]_i_36__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_0__1\,
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0),
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1),
I4 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\last_rr_hot[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => p_102_out,
O => \chosen_reg[2]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[0]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[0]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[0]\(0),
I3 => \^m_axi_rready[0]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__4_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__4_n_0\,
Q => \^m_axi_rready[0]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc is
port (
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
resp_select : in STD_LOGIC_VECTOR ( 0 to 0 );
f_mux4_return : in STD_LOGIC_VECTOR ( 46 downto 0 );
st_mr_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_0 : in STD_LOGIC;
\thread_valid_0__2\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\thread_valid_3__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_4 : in STD_LOGIC;
\thread_valid_4__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_7 : in STD_LOGIC;
\thread_valid_7__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_6 : in STD_LOGIC;
\thread_valid_6__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_5 : in STD_LOGIC;
\thread_valid_5__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_2 : in STD_LOGIC;
\thread_valid_2__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_1 : in STD_LOGIC;
\thread_valid_1__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc : entity is "generic_baseblocks_v2_1_0_mux_enc";
end zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc is
signal \any_pop__1\ : STD_LOGIC;
signal \^s_axi_rid[0]\ : STD_LOGIC;
signal \^s_axi_rid[10]\ : STD_LOGIC;
signal \^s_axi_rid[11]\ : STD_LOGIC;
signal \^s_axi_rid[1]\ : STD_LOGIC;
signal \^s_axi_rid[2]\ : STD_LOGIC;
signal \^s_axi_rid[3]\ : STD_LOGIC;
signal \^s_axi_rid[4]\ : STD_LOGIC;
signal \^s_axi_rid[5]\ : STD_LOGIC;
signal \^s_axi_rid[6]\ : STD_LOGIC;
signal \^s_axi_rid[7]\ : STD_LOGIC;
signal \^s_axi_rid[8]\ : STD_LOGIC;
signal \^s_axi_rid[9]\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[0].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[10].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[11].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[12].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[13].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[15].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[16].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[17].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[18].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[19].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[1].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[20].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[21].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[22].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[23].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[24].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[25].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[26].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[27].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[28].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[29].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[2].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[30].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[31].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[32].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[33].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[34].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[35].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[36].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[37].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[38].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[39].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[3].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[40].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[41].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[42].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[43].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[44].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[45].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[46].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[47].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[4].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[5].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[6].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[7].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[8].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[9].mux_s2_inst\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_34__0\ : label is "soft_lutpair128";
begin
\s_axi_rid[0]\ <= \^s_axi_rid[0]\;
\s_axi_rid[10]\ <= \^s_axi_rid[10]\;
\s_axi_rid[11]\ <= \^s_axi_rid[11]\;
\s_axi_rid[1]\ <= \^s_axi_rid[1]\;
\s_axi_rid[2]\ <= \^s_axi_rid[2]\;
\s_axi_rid[3]\ <= \^s_axi_rid[3]\;
\s_axi_rid[4]\ <= \^s_axi_rid[4]\;
\s_axi_rid[5]\ <= \^s_axi_rid[5]\;
\s_axi_rid[6]\ <= \^s_axi_rid[6]\;
\s_axi_rid[7]\ <= \^s_axi_rid[7]\;
\s_axi_rid[8]\ <= \^s_axi_rid[8]\;
\s_axi_rid[9]\ <= \^s_axi_rid[9]\;
s_axi_rlast(0) <= \^s_axi_rlast\(0);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(0),
I1 => st_mr_rid(0),
O => \^s_axi_rid[0]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(10),
I1 => st_mr_rid(10),
O => \^s_axi_rid[10]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(11),
I1 => st_mr_rid(11),
O => \^s_axi_rid[11]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(12),
I1 => '1',
O => s_axi_rresp(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(13),
I1 => '1',
O => s_axi_rresp(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(14),
I1 => '0',
O => s_axi_rdata(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[16].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(15),
I1 => '0',
O => s_axi_rdata(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[17].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(16),
I1 => '0',
O => s_axi_rdata(2),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[18].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(17),
I1 => '0',
O => s_axi_rdata(3),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[19].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(18),
I1 => '0',
O => s_axi_rdata(4),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(1),
I1 => st_mr_rid(1),
O => \^s_axi_rid[1]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[20].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(19),
I1 => '0',
O => s_axi_rdata(5),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[21].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(20),
I1 => '0',
O => s_axi_rdata(6),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[22].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(21),
I1 => '0',
O => s_axi_rdata(7),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[23].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(22),
I1 => '0',
O => s_axi_rdata(8),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[24].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(23),
I1 => '0',
O => s_axi_rdata(9),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[25].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(24),
I1 => '0',
O => s_axi_rdata(10),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[26].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(25),
I1 => '0',
O => s_axi_rdata(11),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[27].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(26),
I1 => '0',
O => s_axi_rdata(12),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[28].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(27),
I1 => '0',
O => s_axi_rdata(13),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[29].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(28),
I1 => '0',
O => s_axi_rdata(14),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(2),
I1 => st_mr_rid(2),
O => \^s_axi_rid[2]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[30].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(29),
I1 => '0',
O => s_axi_rdata(15),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[31].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(30),
I1 => '0',
O => s_axi_rdata(16),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[32].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(31),
I1 => '0',
O => s_axi_rdata(17),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[33].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(32),
I1 => '0',
O => s_axi_rdata(18),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[34].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(33),
I1 => '0',
O => s_axi_rdata(19),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[35].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(34),
I1 => '0',
O => s_axi_rdata(20),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[36].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(35),
I1 => '0',
O => s_axi_rdata(21),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[37].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(36),
I1 => '0',
O => s_axi_rdata(22),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[38].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(37),
I1 => '0',
O => s_axi_rdata(23),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[39].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(38),
I1 => '0',
O => s_axi_rdata(24),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(3),
I1 => st_mr_rid(3),
O => \^s_axi_rid[3]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[40].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(39),
I1 => '0',
O => s_axi_rdata(25),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[41].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(40),
I1 => '0',
O => s_axi_rdata(26),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[42].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(41),
I1 => '0',
O => s_axi_rdata(27),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[43].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(42),
I1 => '0',
O => s_axi_rdata(28),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[44].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(43),
I1 => '0',
O => s_axi_rdata(29),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[45].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(44),
I1 => '0',
O => s_axi_rdata(30),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[46].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(45),
I1 => '0',
O => s_axi_rdata(31),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[47].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(46),
I1 => \m_payload_i_reg[34]\(0),
O => \^s_axi_rlast\(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(4),
I1 => st_mr_rid(4),
O => \^s_axi_rid[4]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(5),
I1 => st_mr_rid(5),
O => \^s_axi_rid[5]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(6),
I1 => st_mr_rid(6),
O => \^s_axi_rid[6]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(7),
I1 => st_mr_rid(7),
O => \^s_axi_rid[7]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(8),
I1 => st_mr_rid(8),
O => \^s_axi_rid[8]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(9),
I1 => st_mr_rid(9),
O => \^s_axi_rid[9]\,
S => resp_select(0)
);
\gen_multi_thread.accept_cnt[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A65"
)
port map (
I0 => Q(0),
I1 => \any_pop__1\,
I2 => S_AXI_ARREADY(0),
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFF2200D"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => \any_pop__1\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Q(3),
I4 => \any_pop__1\,
I5 => S_AXI_ARREADY(0),
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF0800FFAE0051"
)
port map (
I0 => Q(1),
I1 => S_AXI_ARREADY(0),
I2 => \any_pop__1\,
I3 => Q(0),
I4 => Q(3),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_0,
I1 => \any_pop__1\,
I2 => \thread_valid_0__2\,
I3 => CO(0),
O => E(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_1,
I1 => \any_pop__1\,
I2 => \thread_valid_1__2\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_2,
I1 => \any_pop__1\,
I2 => \thread_valid_2__2\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_3,
I1 => \any_pop__1\,
I2 => \thread_valid_3__2\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_4,
I1 => \any_pop__1\,
I2 => \thread_valid_4__2\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_5,
I1 => \any_pop__1\,
I2 => \thread_valid_5__2\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_6,
I1 => \any_pop__1\,
I2 => \thread_valid_6__2\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_7,
I1 => \any_pop__1\,
I2 => \thread_valid_7__2\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_rready(0),
I1 => \^s_axi_rlast\(0),
I2 => \chosen_reg[0]\,
O => \any_pop__1\
);
\gen_no_arbiter.s_ready_i[0]_i_34__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_axi_rlast\(0),
I1 => s_axi_rready(0),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\i__carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \^s_axi_rid[11]\,
O => S(3)
);
\i__carry_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \^s_axi_rid[8]\,
O => S(2)
);
\i__carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \^s_axi_rid[5]\,
O => S(1)
);
\i__carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \^s_axi_rid[2]\,
O => S(0)
);
p_10_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
p_10_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
p_10_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
p_10_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
p_12_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
p_12_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
p_12_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
p_12_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
p_14_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3)
);
p_14_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2)
);
p_14_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1)
);
p_14_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
p_2_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
p_2_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
p_2_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
p_2_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
p_4_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
p_4_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
p_4_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
p_4_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
p_6_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
p_6_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
p_6_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
p_6_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
p_8_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3)
);
p_8_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2)
);
p_8_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1)
);
p_8_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ is
port (
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
p_0_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
resp_select : in STD_LOGIC_VECTOR ( 0 to 0 );
f_mux4_return : in STD_LOGIC_VECTOR ( 13 downto 0 );
st_mr_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
cmd_push_0 : in STD_LOGIC;
\thread_valid_0__2\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\thread_valid_3__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_4 : in STD_LOGIC;
\thread_valid_4__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_7 : in STD_LOGIC;
\thread_valid_7__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_6 : in STD_LOGIC;
\thread_valid_6__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_5 : in STD_LOGIC;
\thread_valid_5__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_2 : in STD_LOGIC;
\thread_valid_2__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_1 : in STD_LOGIC;
\thread_valid_1__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ : entity is "generic_baseblocks_v2_1_0_mux_enc";
end \zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ is
signal \any_pop__1\ : STD_LOGIC;
signal \^p_0_out\ : STD_LOGIC;
signal \^s_axi_bid[0]\ : STD_LOGIC;
signal \^s_axi_bid[10]\ : STD_LOGIC;
signal \^s_axi_bid[11]\ : STD_LOGIC;
signal \^s_axi_bid[1]\ : STD_LOGIC;
signal \^s_axi_bid[2]\ : STD_LOGIC;
signal \^s_axi_bid[3]\ : STD_LOGIC;
signal \^s_axi_bid[4]\ : STD_LOGIC;
signal \^s_axi_bid[5]\ : STD_LOGIC;
signal \^s_axi_bid[6]\ : STD_LOGIC;
signal \^s_axi_bid[7]\ : STD_LOGIC;
signal \^s_axi_bid[8]\ : STD_LOGIC;
signal \^s_axi_bid[9]\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[0].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[10].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[11].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[12].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[13].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[15].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[1].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[2].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[3].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[4].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[5].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[6].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[7].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[8].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[9].mux_s2_inst\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1\ : label is "soft_lutpair162";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1\ : label is "soft_lutpair162";
begin
p_0_out <= \^p_0_out\;
\s_axi_bid[0]\ <= \^s_axi_bid[0]\;
\s_axi_bid[10]\ <= \^s_axi_bid[10]\;
\s_axi_bid[11]\ <= \^s_axi_bid[11]\;
\s_axi_bid[1]\ <= \^s_axi_bid[1]\;
\s_axi_bid[2]\ <= \^s_axi_bid[2]\;
\s_axi_bid[3]\ <= \^s_axi_bid[3]\;
\s_axi_bid[4]\ <= \^s_axi_bid[4]\;
\s_axi_bid[5]\ <= \^s_axi_bid[5]\;
\s_axi_bid[6]\ <= \^s_axi_bid[6]\;
\s_axi_bid[7]\ <= \^s_axi_bid[7]\;
\s_axi_bid[8]\ <= \^s_axi_bid[8]\;
\s_axi_bid[9]\ <= \^s_axi_bid[9]\;
\gen_fpga.gen_mux_5_8[0].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(0),
I1 => st_mr_bid(0),
O => \^s_axi_bid[0]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(10),
I1 => st_mr_bid(10),
O => \^s_axi_bid[10]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(11),
I1 => st_mr_bid(11),
O => \^s_axi_bid[11]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(12),
I1 => '1',
O => s_axi_bresp(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(13),
I1 => '1',
O => s_axi_bresp(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => '1',
I1 => '1',
O => \^p_0_out\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(1),
I1 => st_mr_bid(1),
O => \^s_axi_bid[1]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(2),
I1 => st_mr_bid(2),
O => \^s_axi_bid[2]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(3),
I1 => st_mr_bid(3),
O => \^s_axi_bid[3]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(4),
I1 => st_mr_bid(4),
O => \^s_axi_bid[4]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(5),
I1 => st_mr_bid(5),
O => \^s_axi_bid[5]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(6),
I1 => st_mr_bid(6),
O => \^s_axi_bid[6]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(7),
I1 => st_mr_bid(7),
O => \^s_axi_bid[7]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(8),
I1 => st_mr_bid(8),
O => \^s_axi_bid[8]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(9),
I1 => st_mr_bid(9),
O => \^s_axi_bid[9]\,
S => resp_select(0)
);
\gen_multi_thread.accept_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A65"
)
port map (
I0 => Q(0),
I1 => \any_pop__1\,
I2 => \m_ready_d_reg[1]\,
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFF2200D"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \any_pop__1\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Q(3),
I4 => \any_pop__1\,
I5 => \m_ready_d_reg[1]\,
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF0800FFAE0051"
)
port map (
I0 => Q(1),
I1 => \m_ready_d_reg[1]\,
I2 => \any_pop__1\,
I3 => Q(0),
I4 => Q(3),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_0,
I1 => \any_pop__1\,
I2 => \thread_valid_0__2\,
I3 => CO(0),
O => E(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_1,
I1 => \any_pop__1\,
I2 => \thread_valid_1__2\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_2,
I1 => \any_pop__1\,
I2 => \thread_valid_2__2\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_3,
I1 => \any_pop__1\,
I2 => \thread_valid_3__2\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_4,
I1 => \any_pop__1\,
I2 => \thread_valid_4__2\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_5,
I1 => \any_pop__1\,
I2 => \thread_valid_5__2\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_6,
I1 => \any_pop__1\,
I2 => \thread_valid_6__2\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_7,
I1 => \any_pop__1\,
I2 => \thread_valid_7__2\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_bready(0),
I1 => \^p_0_out\,
I2 => m_valid_i_reg,
O => \any_pop__1\
);
\i__carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \^s_axi_bid[11]\,
O => S(3)
);
\i__carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \^s_axi_bid[8]\,
O => S(2)
);
\i__carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \^s_axi_bid[5]\,
O => S(1)
);
\i__carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \^s_axi_bid[2]\,
O => S(0)
);
\p_10_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
\p_10_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
\p_10_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
\p_10_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
\p_12_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
\p_12_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
\p_12_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
\p_12_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
\p_14_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3)
);
\p_14_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2)
);
\p_14_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1)
);
\p_14_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
\p_2_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
\p_2_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
\p_2_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
\p_2_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
\p_4_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
\p_4_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
\p_4_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
\p_4_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
\p_6_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
\p_6_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
\p_6_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
\p_6_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
\p_8_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3)
);
\p_8_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2)
);
\p_8_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1)
);
\p_8_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor is
port (
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\s_axi_rvalid[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
st_mr_rid : in STD_LOGIC_VECTOR ( 59 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
match : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
\s_axi_araddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : in STD_LOGIC;
st_mr_rmesg : in STD_LOGIC_VECTOR ( 135 downto 0 );
\m_payload_i_reg[34]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_62_out : in STD_LOGIC;
p_102_out : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
p_40_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_arid[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor : entity is "axi_crossbar_v2_1_14_si_transactor";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \accum_push_5__0\ : STD_LOGIC;
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 58 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal aid_match_00_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal \aid_match_0__0\ : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal aid_match_10_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal \aid_match_1__0\ : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal aid_match_20_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal \aid_match_2__0\ : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal aid_match_30_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal \aid_match_3__0\ : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal aid_match_40_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal \aid_match_4__0\ : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal aid_match_50_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal \aid_match_5__0\ : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal aid_match_60_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal \aid_match_6__0\ : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal aid_match_70_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal \aid_match_7__0\ : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal f_mux4_return : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \gen_multi_thread.accept_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_47\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_48\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_49\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_50\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_51\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_52\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_53\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_54\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_55\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_56\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_57\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_58\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_59\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_60\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_61\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_62\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_63\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_64\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_65\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_66\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_67\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_68\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_69\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_70\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_71\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_72\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_73\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_74\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_75\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_76\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_77\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_78\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_79\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_80\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_81\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_82\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_83\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_84\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_85\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_86\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_87\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_88\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_89\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_90\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_91\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_28_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_31_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal resp_select : STD_LOGIC_VECTOR ( 2 to 2 );
signal \^s_axi_rvalid[0]\ : STD_LOGIC;
signal \thread_valid_0__2\ : STD_LOGIC;
signal \thread_valid_1__2\ : STD_LOGIC;
signal \thread_valid_2__2\ : STD_LOGIC;
signal \thread_valid_3__2\ : STD_LOGIC;
signal \thread_valid_4__2\ : STD_LOGIC;
signal \thread_valid_5__2\ : STD_LOGIC;
signal \thread_valid_6__2\ : STD_LOGIC;
signal \thread_valid_7__2\ : STD_LOGIC;
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1\ : label is "soft_lutpair155";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2__0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3__0\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4__0\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3__0\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2__0\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5__0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_10__0\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_13__0\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_16__0\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_19__0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_20__0\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_27__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_29__0\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_32__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_33__0\ : label is "soft_lutpair155";
begin
D(0) <= \^d\(0);
\s_axi_rvalid[0]\ <= \^s_axi_rvalid[0]\;
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_00_carry_i_1_n_0,
S(2) => aid_match_00_carry_i_2_n_0,
S(1) => aid_match_00_carry_i_3_n_0,
S(0) => aid_match_00_carry_i_4_n_0
);
aid_match_00_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
O => aid_match_00_carry_i_1_n_0
);
aid_match_00_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
O => aid_match_00_carry_i_2_n_0
);
aid_match_00_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
O => aid_match_00_carry_i_3_n_0
);
aid_match_00_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
O => aid_match_00_carry_i_4_n_0
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_10_carry_i_1_n_0,
S(2) => aid_match_10_carry_i_2_n_0,
S(1) => aid_match_10_carry_i_3_n_0,
S(0) => aid_match_10_carry_i_4_n_0
);
aid_match_10_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
I5 => \s_axi_arid[11]\(11),
O => aid_match_10_carry_i_1_n_0
);
aid_match_10_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
I5 => \s_axi_arid[11]\(8),
O => aid_match_10_carry_i_2_n_0
);
aid_match_10_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
I5 => \s_axi_arid[11]\(5),
O => aid_match_10_carry_i_3_n_0
);
aid_match_10_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
I5 => \s_axi_arid[11]\(2),
O => aid_match_10_carry_i_4_n_0
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_20_carry_i_1_n_0,
S(2) => aid_match_20_carry_i_2_n_0,
S(1) => aid_match_20_carry_i_3_n_0,
S(0) => aid_match_20_carry_i_4_n_0
);
aid_match_20_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
O => aid_match_20_carry_i_1_n_0
);
aid_match_20_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
O => aid_match_20_carry_i_2_n_0
);
aid_match_20_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
O => aid_match_20_carry_i_3_n_0
);
aid_match_20_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
O => aid_match_20_carry_i_4_n_0
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_30_carry_i_1_n_0,
S(2) => aid_match_30_carry_i_2_n_0,
S(1) => aid_match_30_carry_i_3_n_0,
S(0) => aid_match_30_carry_i_4_n_0
);
aid_match_30_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
O => aid_match_30_carry_i_1_n_0
);
aid_match_30_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
O => aid_match_30_carry_i_2_n_0
);
aid_match_30_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
O => aid_match_30_carry_i_3_n_0
);
aid_match_30_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
O => aid_match_30_carry_i_4_n_0
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_40_carry_i_1_n_0,
S(2) => aid_match_40_carry_i_2_n_0,
S(1) => aid_match_40_carry_i_3_n_0,
S(0) => aid_match_40_carry_i_4_n_0
);
aid_match_40_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
O => aid_match_40_carry_i_1_n_0
);
aid_match_40_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
O => aid_match_40_carry_i_2_n_0
);
aid_match_40_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
O => aid_match_40_carry_i_3_n_0
);
aid_match_40_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
O => aid_match_40_carry_i_4_n_0
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_50_carry_i_1_n_0,
S(2) => aid_match_50_carry_i_2_n_0,
S(1) => aid_match_50_carry_i_3_n_0,
S(0) => aid_match_50_carry_i_4_n_0
);
aid_match_50_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
O => aid_match_50_carry_i_1_n_0
);
aid_match_50_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
O => aid_match_50_carry_i_2_n_0
);
aid_match_50_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
O => aid_match_50_carry_i_3_n_0
);
aid_match_50_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
O => aid_match_50_carry_i_4_n_0
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_60_carry_i_1_n_0,
S(2) => aid_match_60_carry_i_2_n_0,
S(1) => aid_match_60_carry_i_3_n_0,
S(0) => aid_match_60_carry_i_4_n_0
);
aid_match_60_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
O => aid_match_60_carry_i_1_n_0
);
aid_match_60_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
O => aid_match_60_carry_i_2_n_0
);
aid_match_60_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
O => aid_match_60_carry_i_3_n_0
);
aid_match_60_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
O => aid_match_60_carry_i_4_n_0
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_70_carry_i_1_n_0,
S(2) => aid_match_70_carry_i_2_n_0,
S(1) => aid_match_70_carry_i_3_n_0,
S(0) => aid_match_70_carry_i_4_n_0
);
aid_match_70_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
O => aid_match_70_carry_i_1_n_0
);
aid_match_70_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
O => aid_match_70_carry_i_2_n_0
);
aid_match_70_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
O => aid_match_70_carry_i_3_n_0
);
aid_match_70_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
O => aid_match_70_carry_i_4_n_0
);
\gen_multi_thread.accept_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.accept_cnt[0]_i_1_n_0\,
Q => \gen_multi_thread.accept_cnt_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.mux_resp_multi_thread_n_58\,
Q => \gen_multi_thread.accept_cnt_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.mux_resp_multi_thread_n_57\,
Q => \gen_multi_thread.accept_cnt_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.mux_resp_multi_thread_n_56\,
Q => \gen_multi_thread.accept_cnt_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp_8
port map (
E(0) => E(0),
Q(4 downto 0) => Q(4 downto 0),
SR(0) => SR(0),
S_AXI_ARREADY(0) => S_AXI_ARREADY(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
f_mux4_return(46 downto 14) => f_mux4_return(47 downto 15),
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0\,
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.accept_cnt_reg__0\(3),
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ => \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\,
\m_payload_i_reg[0]\(0) => \m_payload_i_reg[0]\(0),
\m_payload_i_reg[0]_0\(0) => \m_payload_i_reg[0]_0\(0),
\m_payload_i_reg[0]_1\(0) => \m_payload_i_reg[0]_1\(0),
\m_payload_i_reg[0]_2\(0) => \m_payload_i_reg[0]_2\(0),
\m_payload_i_reg[34]\(0) => \m_payload_i_reg[34]\(0),
\m_payload_i_reg[34]_0\(0) => \m_payload_i_reg[34]_1\(0),
\m_payload_i_reg[34]_1\(0) => \m_payload_i_reg[34]_2\(0),
\m_payload_i_reg[34]_2\(0) => \m_payload_i_reg[34]_3\(0),
\m_payload_i_reg[34]_3\(0) => \m_payload_i_reg[34]_4\(0),
\m_payload_i_reg[34]_4\ => \gen_multi_thread.mux_resp_multi_thread_n_59\,
m_valid_i => m_valid_i,
m_valid_i_reg => m_valid_i_reg,
m_valid_i_reg_0 => m_valid_i_reg_0,
match => match,
p_102_out => p_102_out,
p_122_out => p_122_out,
p_40_out => p_40_out,
p_62_out => p_62_out,
p_82_out => p_82_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(0) => r_issuing_cnt(0),
resp_select(0) => resp_select(2),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rready(0) => s_axi_rready(0),
\s_axi_rvalid[0]\ => \^s_axi_rvalid[0]\,
st_mr_rid(47 downto 0) => st_mr_rid(47 downto 0),
st_mr_rmesg(135 downto 0) => st_mr_rmesg(135 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(0),
I1 => cmd_push_0,
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(2),
I3 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(1),
I1 => cmd_push_0,
I2 => active_cnt(0),
I3 => active_cnt(3),
I4 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\,
Q => active_cnt(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\,
Q => active_cnt(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\,
Q => active_cnt(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\,
Q => active_cnt(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"E222"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => aid_match_00,
I3 => S_AXI_ARREADY(0),
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_1,
I1 => active_cnt(8),
I2 => active_cnt(10),
I3 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(9),
I1 => cmd_push_1,
I2 => active_cnt(8),
I3 => active_cnt(11),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(8),
I1 => cmd_push_1,
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\,
Q => active_cnt(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\,
Q => active_cnt(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\,
Q => active_cnt(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\,
Q => active_cnt(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => aid_match_10,
I4 => S_AXI_ARREADY(0),
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(16),
I1 => cmd_push_2,
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_2,
I1 => active_cnt(16),
I2 => active_cnt(18),
I3 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(17),
I1 => cmd_push_2,
I2 => active_cnt(16),
I3 => active_cnt(19),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\,
Q => active_cnt(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\,
Q => active_cnt(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\,
Q => active_cnt(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\,
Q => active_cnt(19),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80008000800080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => \thread_valid_2__2\,
I4 => aid_match_20,
I5 => S_AXI_ARREADY(0),
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
O => \thread_valid_0__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
O => \thread_valid_1__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
O => \thread_valid_2__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(24),
I1 => cmd_push_3,
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(26),
I3 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(25),
I1 => cmd_push_3,
I2 => active_cnt(24),
I3 => active_cnt(27),
I4 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\,
Q => active_cnt(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\,
Q => active_cnt(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\,
Q => active_cnt(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\,
Q => active_cnt(27),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[26]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I2 => \thread_valid_3__2\,
I3 => aid_match_30,
I4 => S_AXI_ARREADY(0),
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(32),
I1 => cmd_push_4,
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_4,
I1 => active_cnt(32),
I2 => active_cnt(34),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(33),
I1 => cmd_push_4,
I2 => active_cnt(32),
I3 => active_cnt(35),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\,
Q => active_cnt(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\,
Q => active_cnt(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\,
Q => active_cnt(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\,
Q => active_cnt(35),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
I1 => \thread_valid_3__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \thread_valid_4__2\,
I4 => aid_match_40,
I5 => S_AXI_ARREADY(0),
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555557FFFFFFFF"
)
port map (
I0 => \thread_valid_0__2\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
I5 => \thread_valid_2__2\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
O => \thread_valid_3__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
O => \thread_valid_4__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(40),
I1 => cmd_push_5,
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_5,
I1 => active_cnt(40),
I2 => active_cnt(42),
I3 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(41),
I1 => cmd_push_5,
I2 => active_cnt(40),
I3 => active_cnt(43),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\,
Q => active_cnt(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\,
Q => active_cnt(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\,
Q => active_cnt(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\,
Q => active_cnt(43),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[42]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I2 => \thread_valid_5__2\,
I3 => aid_match_50,
I4 => S_AXI_ARREADY(0),
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(48),
I1 => cmd_push_6,
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_6,
I1 => active_cnt(48),
I2 => active_cnt(50),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(49),
I1 => cmd_push_6,
I2 => active_cnt(48),
I3 => active_cnt(51),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\,
Q => active_cnt(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\,
Q => active_cnt(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\,
Q => active_cnt(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\,
Q => active_cnt(51),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \thread_valid_5__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \thread_valid_6__2\,
I4 => aid_match_60,
I5 => S_AXI_ARREADY(0),
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
O => \thread_valid_5__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(51),
I2 => active_cnt(49),
I3 => active_cnt(48),
O => \thread_valid_6__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(56),
I1 => cmd_push_7,
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_7,
I1 => active_cnt(56),
I2 => active_cnt(58),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(57),
I1 => cmd_push_7,
I2 => active_cnt(56),
I3 => active_cnt(59),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
O => \thread_valid_7__2\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\,
Q => active_cnt(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\,
Q => active_cnt(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\,
Q => active_cnt(58),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\,
Q => active_cnt(59),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_araddr[30]\(2),
I1 => \s_axi_araddr[30]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_araddr[30]\(2),
I1 => \s_axi_araddr[30]\(1),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF404040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \aid_match_7__0\,
I4 => S_AXI_ARREADY(0),
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55555557"
)
port map (
I0 => \thread_valid_3__2\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
O => \accum_push_5__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => \thread_valid_6__2\,
I5 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\,
I4 => \aid_match_6__0\,
I5 => \aid_match_7__0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
O => \aid_match_7__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_00,
I1 => \thread_valid_0__2\,
I2 => aid_match_10,
I3 => \thread_valid_1__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_20,
I1 => \thread_valid_2__2\,
I2 => aid_match_30,
I3 => \thread_valid_3__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_40,
I1 => \thread_valid_4__2\,
I2 => aid_match_50,
I3 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(48),
I1 => active_cnt(49),
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => aid_match_60,
O => \aid_match_6__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(58),
R => SR(0)
);
\gen_multi_thread.mux_resp_multi_thread\: entity work.zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc
port map (
CO(0) => p_14_out,
D(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
D(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
D(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\,
E(0) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg__0\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_60\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_61\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_62\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_63\,
S_AXI_ARREADY(0) => S_AXI_ARREADY(0),
\chosen_reg[0]\ => \^s_axi_rvalid[0]\,
cmd_push_0 => cmd_push_0,
cmd_push_1 => cmd_push_1,
cmd_push_2 => cmd_push_2,
cmd_push_3 => cmd_push_3,
cmd_push_4 => cmd_push_4,
cmd_push_5 => cmd_push_5,
cmd_push_6 => cmd_push_6,
cmd_push_7 => cmd_push_7,
f_mux4_return(46 downto 14) => f_mux4_return(47 downto 15),
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3) => \gen_multi_thread.mux_resp_multi_thread_n_88\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2) => \gen_multi_thread.mux_resp_multi_thread_n_89\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1) => \gen_multi_thread.mux_resp_multi_thread_n_90\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_91\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_84\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_85\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_86\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_87\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_80\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_81\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_82\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_83\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_76\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_77\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_78\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_79\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_72\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_73\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_74\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_75\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_68\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_69\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_70\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_71\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_64\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_65\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_66\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_67\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_multi_thread.mux_resp_multi_thread_n_59\,
\m_payload_i_reg[34]\(0) => \m_payload_i_reg[34]_0\(0),
resp_select(0) => resp_select(2),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => \s_axi_rid[0]\,
\s_axi_rid[10]\ => \s_axi_rid[10]\,
\s_axi_rid[11]\ => \s_axi_rid[11]\,
\s_axi_rid[1]\ => \s_axi_rid[1]\,
\s_axi_rid[2]\ => \s_axi_rid[2]\,
\s_axi_rid[3]\ => \s_axi_rid[3]\,
\s_axi_rid[4]\ => \s_axi_rid[4]\,
\s_axi_rid[5]\ => \s_axi_rid[5]\,
\s_axi_rid[6]\ => \s_axi_rid[6]\,
\s_axi_rid[7]\ => \s_axi_rid[7]\,
\s_axi_rid[8]\ => \s_axi_rid[8]\,
\s_axi_rid[9]\ => \s_axi_rid[9]\,
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
st_mr_rid(11 downto 0) => st_mr_rid(59 downto 48),
\thread_valid_0__2\ => \thread_valid_0__2\,
\thread_valid_1__2\ => \thread_valid_1__2\,
\thread_valid_2__2\ => \thread_valid_2__2\,
\thread_valid_3__2\ => \thread_valid_3__2\,
\thread_valid_4__2\ => \thread_valid_4__2\,
\thread_valid_5__2\ => \thread_valid_5__2\,
\thread_valid_6__2\ => \thread_valid_6__2\,
\thread_valid_7__2\ => \thread_valid_7__2\
);
\gen_no_arbiter.m_target_hot_i[4]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => match,
O => \^d\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
I4 => aid_match_30,
O => \aid_match_3__0\
);
\gen_no_arbiter.s_ready_i[0]_i_11__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(17),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(18),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
I4 => aid_match_20,
O => \aid_match_2__0\
);
\gen_no_arbiter.s_ready_i[0]_i_14__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(9),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(8),
O => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(10),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
I4 => aid_match_10,
O => \aid_match_1__0\
);
\gen_no_arbiter.s_ready_i[0]_i_17__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(1),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(2),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
I4 => aid_match_00,
O => \aid_match_0__0\
);
\gen_no_arbiter.s_ready_i[0]_i_20__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(49),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(48),
O => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(50),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(57),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(56),
O => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_23__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(58),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_27__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(41),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(40),
O => \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_28\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(42),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_29__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
I4 => aid_match_50,
O => \aid_match_5__0\
);
\gen_no_arbiter.s_ready_i[0]_i_30__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(33),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(32),
O => \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(34),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_31_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_32__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
I4 => aid_match_40,
O => \aid_match_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_33__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
I1 => \gen_multi_thread.accept_cnt_reg__0\(2),
I2 => \gen_multi_thread.accept_cnt_reg__0\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\,
I2 => \aid_match_3__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\,
I5 => \aid_match_2__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\,
I2 => \aid_match_1__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\,
I5 => \aid_match_0__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\,
I2 => \aid_match_6__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0\,
I5 => \aid_match_7__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\,
I2 => \aid_match_5__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_31_n_0\,
I5 => \aid_match_4__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(25),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(26),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_60\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_61\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_62\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_63\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_80\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_81\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_82\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_83\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_84\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_85\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_86\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_87\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_88\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_89\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_90\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_91\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_64\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_65\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_66\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_67\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_68\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_69\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_70\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_71\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_72\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_73\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_74\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_75\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_76\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_77\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_78\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_79\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
port (
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].w_issuing_cnt_reg[24]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\s_axi_bvalid[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
st_mr_bid : in STD_LOGIC_VECTOR ( 59 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
p_84_in : in STD_LOGIC;
p_66_in : in STD_LOGIC;
p_48_in : in STD_LOGIC;
p_101_in : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
match : in STD_LOGIC;
ADDRESS_HIT_0 : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
st_mr_bmesg : in STD_LOGIC_VECTOR ( 7 downto 0 );
p_68_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_awid[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ : entity is "axi_crossbar_v2_1_14_si_transactor";
end \zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \accum_push_5__0\ : STD_LOGIC;
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 58 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal \aid_match_00_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal \aid_match_0__0\ : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal \aid_match_10_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal \aid_match_1__0\ : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal \aid_match_20_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal \aid_match_2__0\ : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal \aid_match_30_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal \aid_match_3__0\ : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal \aid_match_40_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal \aid_match_4__0\ : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal \aid_match_50_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal \aid_match_5__0\ : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal \aid_match_60_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal \aid_match_6__0\ : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal \aid_match_70_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal \aid_match_7__0\ : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal f_mux4_return : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_15\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_16\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_17\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_18\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_19\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_20\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_21\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_22\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_23\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_24\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_25\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_26\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_27\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_28\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_29\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_30\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_31\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_32\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_33\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_34\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_35\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_36\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_37\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_38\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_39\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_40\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_41\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_42\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_43\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_44\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_45\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_46\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_47\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_48\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_49\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_50\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_51\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_52\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_53\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_54\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_55\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_56\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_57\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_58\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_23_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_29_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_32_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_35_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal resp_select : STD_LOGIC_VECTOR ( 2 to 2 );
signal \^s_axi_bvalid[0]\ : STD_LOGIC;
signal \thread_valid_0__2\ : STD_LOGIC;
signal \thread_valid_1__2\ : STD_LOGIC;
signal \thread_valid_2__2\ : STD_LOGIC;
signal \thread_valid_3__2\ : STD_LOGIC;
signal \thread_valid_4__2\ : STD_LOGIC;
signal \thread_valid_5__2\ : STD_LOGIC;
signal \thread_valid_6__2\ : STD_LOGIC;
signal \thread_valid_7__2\ : STD_LOGIC;
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1__0\ : label is "soft_lutpair189";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3\ : label is "soft_lutpair177";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4\ : label is "soft_lutpair178";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\ : label is "soft_lutpair188";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\ : label is "soft_lutpair188";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\ : label is "soft_lutpair187";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\ : label is "soft_lutpair187";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\ : label is "soft_lutpair185";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\ : label is "soft_lutpair185";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\ : label is "soft_lutpair182";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\ : label is "soft_lutpair182";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2\ : label is "soft_lutpair180";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\ : label is "soft_lutpair186";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\ : label is "soft_lutpair186";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_10\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_13\ : label is "soft_lutpair178";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_16\ : label is "soft_lutpair177";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_19\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_20\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_28__0\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_30\ : label is "soft_lutpair180";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_33\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_35\ : label is "soft_lutpair189";
begin
D(2 downto 0) <= \^d\(2 downto 0);
SR(0) <= \^sr\(0);
\s_axi_bvalid[0]\ <= \^s_axi_bvalid[0]\;
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_00_carry_i_1__0_n_0\,
S(2) => \aid_match_00_carry_i_2__0_n_0\,
S(1) => \aid_match_00_carry_i_3__0_n_0\,
S(0) => \aid_match_00_carry_i_4__0_n_0\
);
\aid_match_00_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
O => \aid_match_00_carry_i_1__0_n_0\
);
\aid_match_00_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8),
O => \aid_match_00_carry_i_2__0_n_0\
);
\aid_match_00_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
O => \aid_match_00_carry_i_3__0_n_0\
);
\aid_match_00_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
O => \aid_match_00_carry_i_4__0_n_0\
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_10_carry_i_1__0_n_0\,
S(2) => \aid_match_10_carry_i_2__0_n_0\,
S(1) => \aid_match_10_carry_i_3__0_n_0\,
S(0) => \aid_match_10_carry_i_4__0_n_0\
);
\aid_match_10_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
I5 => \s_axi_awid[11]\(11),
O => \aid_match_10_carry_i_1__0_n_0\
);
\aid_match_10_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8),
I5 => \s_axi_awid[11]\(8),
O => \aid_match_10_carry_i_2__0_n_0\
);
\aid_match_10_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
I5 => \s_axi_awid[11]\(5),
O => \aid_match_10_carry_i_3__0_n_0\
);
\aid_match_10_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
I5 => \s_axi_awid[11]\(2),
O => \aid_match_10_carry_i_4__0_n_0\
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_20_carry_i_1__0_n_0\,
S(2) => \aid_match_20_carry_i_2__0_n_0\,
S(1) => \aid_match_20_carry_i_3__0_n_0\,
S(0) => \aid_match_20_carry_i_4__0_n_0\
);
\aid_match_20_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
O => \aid_match_20_carry_i_1__0_n_0\
);
\aid_match_20_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8),
O => \aid_match_20_carry_i_2__0_n_0\
);
\aid_match_20_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
O => \aid_match_20_carry_i_3__0_n_0\
);
\aid_match_20_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
O => \aid_match_20_carry_i_4__0_n_0\
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_30_carry_i_1__0_n_0\,
S(2) => \aid_match_30_carry_i_2__0_n_0\,
S(1) => \aid_match_30_carry_i_3__0_n_0\,
S(0) => \aid_match_30_carry_i_4__0_n_0\
);
\aid_match_30_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
O => \aid_match_30_carry_i_1__0_n_0\
);
\aid_match_30_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8),
O => \aid_match_30_carry_i_2__0_n_0\
);
\aid_match_30_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
O => \aid_match_30_carry_i_3__0_n_0\
);
\aid_match_30_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
O => \aid_match_30_carry_i_4__0_n_0\
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_40_carry_i_1__0_n_0\,
S(2) => \aid_match_40_carry_i_2__0_n_0\,
S(1) => \aid_match_40_carry_i_3__0_n_0\,
S(0) => \aid_match_40_carry_i_4__0_n_0\
);
\aid_match_40_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
O => \aid_match_40_carry_i_1__0_n_0\
);
\aid_match_40_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8),
O => \aid_match_40_carry_i_2__0_n_0\
);
\aid_match_40_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
O => \aid_match_40_carry_i_3__0_n_0\
);
\aid_match_40_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
O => \aid_match_40_carry_i_4__0_n_0\
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_50_carry_i_1__0_n_0\,
S(2) => \aid_match_50_carry_i_2__0_n_0\,
S(1) => \aid_match_50_carry_i_3__0_n_0\,
S(0) => \aid_match_50_carry_i_4__0_n_0\
);
\aid_match_50_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
O => \aid_match_50_carry_i_1__0_n_0\
);
\aid_match_50_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8),
O => \aid_match_50_carry_i_2__0_n_0\
);
\aid_match_50_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
O => \aid_match_50_carry_i_3__0_n_0\
);
\aid_match_50_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
O => \aid_match_50_carry_i_4__0_n_0\
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_60_carry_i_1__0_n_0\,
S(2) => \aid_match_60_carry_i_2__0_n_0\,
S(1) => \aid_match_60_carry_i_3__0_n_0\,
S(0) => \aid_match_60_carry_i_4__0_n_0\
);
\aid_match_60_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
O => \aid_match_60_carry_i_1__0_n_0\
);
\aid_match_60_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8),
O => \aid_match_60_carry_i_2__0_n_0\
);
\aid_match_60_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
O => \aid_match_60_carry_i_3__0_n_0\
);
\aid_match_60_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
O => \aid_match_60_carry_i_4__0_n_0\
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_70_carry_i_1__0_n_0\,
S(2) => \aid_match_70_carry_i_2__0_n_0\,
S(1) => \aid_match_70_carry_i_3__0_n_0\,
S(0) => \aid_match_70_carry_i_4__0_n_0\
);
\aid_match_70_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
O => \aid_match_70_carry_i_1__0_n_0\
);
\aid_match_70_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8),
O => \aid_match_70_carry_i_2__0_n_0\
);
\aid_match_70_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
O => \aid_match_70_carry_i_3__0_n_0\
);
\aid_match_70_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
O => \aid_match_70_carry_i_4__0_n_0\
);
\gen_multi_thread.accept_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\,
Q => \gen_multi_thread.accept_cnt_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_26\,
Q => \gen_multi_thread.accept_cnt_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_25\,
Q => \gen_multi_thread.accept_cnt_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_24\,
Q => \gen_multi_thread.accept_cnt_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_arbiter_resp
port map (
ADDRESS_HIT_0 => ADDRESS_HIT_0,
E(0) => E(0),
Q(0) => \gen_multi_thread.accept_cnt_reg\(3),
SR(0) => \^sr\(0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0),
\gen_master_slots[2].w_issuing_cnt_reg[16]\(0) => \gen_master_slots[2].w_issuing_cnt_reg[16]\(0),
\gen_master_slots[3].w_issuing_cnt_reg[24]\(0) => \gen_master_slots[3].w_issuing_cnt_reg[24]\(0),
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_35_n_0\,
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]\(0) => \gen_no_arbiter.s_ready_i_reg[0]\(0),
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_no_arbiter.s_ready_i_reg[0]_0\,
m_valid_i => m_valid_i,
m_valid_i_reg => m_valid_i_reg,
m_valid_i_reg_0 => m_valid_i_reg_0,
match => match,
p_0_out => p_0_out_0,
p_101_in => p_101_in,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_68_out => p_68_out,
p_84_in => p_84_in,
p_88_out => p_88_out,
resp_select(0) => resp_select(2),
\s_axi_awaddr[30]\(2 downto 0) => \s_axi_awaddr[30]\(2 downto 0),
s_axi_bready(0) => s_axi_bready(0),
\s_axi_bvalid[0]\ => \^s_axi_bvalid[0]\,
s_ready_i_reg(4 downto 0) => Q(4 downto 0),
st_mr_bid(47 downto 0) => st_mr_bid(47 downto 0),
st_mr_bmesg(7 downto 0) => st_mr_bmesg(7 downto 0),
w_issuing_cnt(16 downto 0) => w_issuing_cnt(16 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(0),
I1 => cmd_push_0,
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(2),
I3 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(1),
I1 => cmd_push_0,
I2 => active_cnt(0),
I3 => active_cnt(3),
I4 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\,
Q => active_cnt(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\,
Q => active_cnt(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\,
Q => active_cnt(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\,
Q => active_cnt(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E222"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => aid_match_00,
I3 => \m_ready_d_reg[1]\,
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(1),
Q => active_target(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(2),
Q => active_target(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_1,
I1 => active_cnt(8),
I2 => active_cnt(10),
I3 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(9),
I1 => cmd_push_1,
I2 => active_cnt(8),
I3 => active_cnt(11),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(8),
I1 => cmd_push_1,
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\,
Q => active_cnt(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\,
Q => active_cnt(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\,
Q => active_cnt(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\,
Q => active_cnt(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => aid_match_10,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(2),
Q => active_target(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(1),
Q => active_target(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(16),
I1 => cmd_push_2,
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_2,
I1 => active_cnt(16),
I2 => active_cnt(18),
I3 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(17),
I1 => cmd_push_2,
I2 => active_cnt(16),
I3 => active_cnt(19),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\,
Q => active_cnt(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\,
Q => active_cnt(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\,
Q => active_cnt(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\,
Q => active_cnt(19),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80008000800080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => \thread_valid_2__2\,
I4 => aid_match_20,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
O => \thread_valid_0__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
O => \thread_valid_1__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
O => \thread_valid_2__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(1),
Q => active_target(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(2),
Q => active_target(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(24),
I1 => cmd_push_3,
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(26),
I3 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(25),
I1 => cmd_push_3,
I2 => active_cnt(24),
I3 => active_cnt(27),
I4 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\,
Q => active_cnt(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\,
Q => active_cnt(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\,
Q => active_cnt(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\,
Q => active_cnt(27),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I2 => \thread_valid_3__2\,
I3 => aid_match_30,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(1),
Q => active_target(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(2),
Q => active_target(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(32),
I1 => cmd_push_4,
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_4,
I1 => active_cnt(32),
I2 => active_cnt(34),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(33),
I1 => cmd_push_4,
I2 => active_cnt(32),
I3 => active_cnt(35),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\,
Q => active_cnt(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\,
Q => active_cnt(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\,
Q => active_cnt(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\,
Q => active_cnt(35),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
I1 => \thread_valid_3__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \thread_valid_4__2\,
I4 => aid_match_40,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555557FFFFFFFF"
)
port map (
I0 => \thread_valid_0__2\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
I5 => \thread_valid_2__2\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
O => \thread_valid_3__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
O => \thread_valid_4__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(1),
Q => active_target(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(2),
Q => active_target(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(40),
I1 => cmd_push_5,
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_5,
I1 => active_cnt(40),
I2 => active_cnt(42),
I3 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(41),
I1 => cmd_push_5,
I2 => active_cnt(40),
I3 => active_cnt(43),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\,
Q => active_cnt(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\,
Q => active_cnt(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\,
Q => active_cnt(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\,
Q => active_cnt(43),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[42]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I2 => \thread_valid_5__2\,
I3 => aid_match_50,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(1),
Q => active_target(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(2),
Q => active_target(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(48),
I1 => cmd_push_6,
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_6,
I1 => active_cnt(48),
I2 => active_cnt(50),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(49),
I1 => cmd_push_6,
I2 => active_cnt(48),
I3 => active_cnt(51),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\,
Q => active_cnt(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\,
Q => active_cnt(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\,
Q => active_cnt(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\,
Q => active_cnt(51),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \thread_valid_5__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \thread_valid_6__2\,
I4 => aid_match_60,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
O => \thread_valid_5__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(51),
I2 => active_cnt(49),
I3 => active_cnt(48),
O => \thread_valid_6__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(1),
Q => active_target(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(2),
Q => active_target(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(56),
I1 => cmd_push_7,
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_7,
I1 => active_cnt(56),
I2 => active_cnt(58),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(57),
I1 => cmd_push_7,
I2 => active_cnt(56),
I3 => active_cnt(59),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
O => \thread_valid_7__2\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\,
Q => active_cnt(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\,
Q => active_cnt(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\,
Q => active_cnt(58),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\,
Q => active_cnt(59),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_awaddr[30]\(2),
I1 => \s_axi_awaddr[30]\(0),
O => \^d\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_awaddr[30]\(2),
I1 => \s_axi_awaddr[30]\(1),
O => \^d\(1)
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF404040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \aid_match_7__0\,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55555557"
)
port map (
I0 => \thread_valid_3__2\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
O => \accum_push_5__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => \thread_valid_6__2\,
I5 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\,
I4 => \aid_match_6__0\,
I5 => \aid_match_7__0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
O => \aid_match_7__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_00,
I1 => \thread_valid_0__2\,
I2 => aid_match_10,
I3 => \thread_valid_1__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_20,
I1 => \thread_valid_2__2\,
I2 => aid_match_30,
I3 => \thread_valid_3__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_40,
I1 => \thread_valid_4__2\,
I2 => aid_match_50,
I3 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(48),
I1 => active_cnt(49),
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => aid_match_60,
O => \aid_match_6__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(1),
Q => active_target(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(2),
Q => active_target(58),
R => \^sr\(0)
);
\gen_multi_thread.mux_resp_multi_thread\: entity work.\zqynq_lab_1_design_xbar_0_generic_baseblocks_v2_1_0_mux_enc__parameterized0\
port map (
CO(0) => p_14_out,
D(2) => \gen_multi_thread.mux_resp_multi_thread_n_24\,
D(1) => \gen_multi_thread.mux_resp_multi_thread_n_25\,
D(0) => \gen_multi_thread.mux_resp_multi_thread_n_26\,
E(0) => \gen_multi_thread.mux_resp_multi_thread_n_15\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_27\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_28\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_29\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_30\,
cmd_push_0 => cmd_push_0,
cmd_push_1 => cmd_push_1,
cmd_push_2 => cmd_push_2,
cmd_push_3 => cmd_push_3,
cmd_push_4 => cmd_push_4,
cmd_push_5 => cmd_push_5,
cmd_push_6 => cmd_push_6,
cmd_push_7 => cmd_push_7,
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_23\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_22\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_21\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_16\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_43\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_44\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_45\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_46\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_17\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_39\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_40\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_41\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_42\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_20\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_35\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_36\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_37\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_38\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_19\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_31\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_32\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_33\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_34\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_18\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11 downto 0),
\m_ready_d_reg[1]\ => \m_ready_d_reg[1]\,
m_valid_i_reg => \^s_axi_bvalid[0]\,
p_0_out => p_0_out_0,
resp_select(0) => resp_select(2),
\s_axi_bid[0]\ => \s_axi_bid[0]\,
\s_axi_bid[10]\ => \s_axi_bid[10]\,
\s_axi_bid[11]\ => \s_axi_bid[11]\,
\s_axi_bid[1]\ => \s_axi_bid[1]\,
\s_axi_bid[2]\ => \s_axi_bid[2]\,
\s_axi_bid[3]\ => \s_axi_bid[3]\,
\s_axi_bid[4]\ => \s_axi_bid[4]\,
\s_axi_bid[5]\ => \s_axi_bid[5]\,
\s_axi_bid[6]\ => \s_axi_bid[6]\,
\s_axi_bid[7]\ => \s_axi_bid[7]\,
\s_axi_bid[8]\ => \s_axi_bid[8]\,
\s_axi_bid[9]\ => \s_axi_bid[9]\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
st_mr_bid(11 downto 0) => st_mr_bid(59 downto 48),
\thread_valid_0__2\ => \thread_valid_0__2\,
\thread_valid_1__2\ => \thread_valid_1__2\,
\thread_valid_2__2\ => \thread_valid_2__2\,
\thread_valid_3__2\ => \thread_valid_3__2\,
\thread_valid_4__2\ => \thread_valid_4__2\,
\thread_valid_5__2\ => \thread_valid_5__2\,
\thread_valid_6__2\ => \thread_valid_6__2\,
\thread_valid_7__2\ => \thread_valid_7__2\
);
\gen_no_arbiter.m_target_hot_i[4]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => match,
O => \^d\(2)
);
\gen_no_arbiter.s_ready_i[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
I4 => aid_match_30,
O => \aid_match_3__0\
);
\gen_no_arbiter.s_ready_i[0]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(17),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(18),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
I4 => aid_match_20,
O => \aid_match_2__0\
);
\gen_no_arbiter.s_ready_i[0]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(9),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(8),
O => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(10),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
I4 => aid_match_10,
O => \aid_match_1__0\
);
\gen_no_arbiter.s_ready_i[0]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(1),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(2),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
I4 => aid_match_00,
O => \aid_match_0__0\
);
\gen_no_arbiter.s_ready_i[0]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(49),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(48),
O => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(50),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(57),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(56),
O => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(58),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_28__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(41),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(40),
O => \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_29\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(42),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_29_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\,
I2 => \aid_match_3__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\,
I5 => \aid_match_2__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_30\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
I4 => aid_match_50,
O => \aid_match_5__0\
);
\gen_no_arbiter.s_ready_i[0]_i_31__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(33),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(32),
O => \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_32\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(34),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_32_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
I4 => aid_match_40,
O => \aid_match_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
I1 => \gen_multi_thread.accept_cnt_reg\(2),
I2 => \gen_multi_thread.accept_cnt_reg\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_35_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\,
I2 => \aid_match_1__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\,
I5 => \aid_match_0__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\,
I2 => \aid_match_6__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\,
I5 => \aid_match_7__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_29_n_0\,
I2 => \aid_match_5__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_32_n_0\,
I5 => \aid_match_4__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(25),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(26),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_27\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_28\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_29\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_30\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_31\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_32\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_33\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_34\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_35\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_36\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_37\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_38\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_39\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_40\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_41\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_42\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_43\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_44\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_45\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_46\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
\write_cs0__0\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
match : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo : entity is "axi_data_fifo_v2_1_12_axic_reg_srl_fifo";
end zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
signal \/FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal areset_d1 : STD_LOGIC;
signal fifoaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[2].srl_nx1_n_1\ : STD_LOGIC;
signal load_s1 : STD_LOGIC;
signal \m_aready0__3\ : STD_LOGIC;
signal \m_aready__1\ : STD_LOGIC;
signal m_avalid : STD_LOGIC;
signal m_select_enc : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \m_valid_i__0\ : STD_LOGIC;
signal m_valid_i_n_0 : STD_LOGIC;
signal p_0_in5_out : STD_LOGIC;
signal p_0_in8_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in8_in : signal is "yes";
signal p_9_in : STD_LOGIC;
attribute RTL_KEEP of p_9_in : signal is "yes";
signal push : STD_LOGIC;
signal \s_ready_i1__4\ : STD_LOGIC;
signal \s_ready_i_i_1__9_n_0\ : STD_LOGIC;
signal \^ss_wr_awready\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[2]\ : label is "1";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair191";
attribute SOFT_HLUTNM of \m_axi_wvalid[1]_INST_0\ : label is "soft_lutpair191";
attribute SOFT_HLUTNM of \m_axi_wvalid[2]_INST_0\ : label is "soft_lutpair192";
attribute SOFT_HLUTNM of \m_axi_wvalid[3]_INST_0\ : label is "soft_lutpair192";
begin
ss_wr_awready <= \^ss_wr_awready\;
\/FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20202F20"
)
port map (
I0 => s_axi_awvalid(0),
I1 => m_ready_d(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[1]_i_1_n_0\
);
\/FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0B0B0BF"
)
port map (
I0 => m_ready_d(0),
I1 => s_axi_awvalid(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[2]_i_1_n_0\
);
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"008A0000"
)
port map (
I0 => \m_aready__1\,
I1 => m_ready_d(0),
I2 => s_axi_awvalid(0),
I3 => p_9_in,
I4 => p_0_in8_in,
O => \FSM_onehot_state[0]_i_1_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF488F488F488"
)
port map (
I0 => \m_aready__1\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => \m_valid_i__0\
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00007500"
)
port map (
I0 => \m_aready__1\,
I1 => m_ready_d(0),
I2 => s_axi_awvalid(0),
I3 => p_0_in8_in,
I4 => p_9_in,
O => \FSM_onehot_state[3]_i_2_n_0\
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[0]_i_1_n_0\,
Q => p_9_in,
S => areset_d1
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \/FSM_onehot_state[1]_i_1_n_0\,
Q => p_0_in8_in,
R => areset_d1
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \/FSM_onehot_state[2]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[2]\,
R => areset_d1
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[3]_i_2_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => areset_d1
);
areset_d1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => SR(0),
Q => areset_d1,
R => '0'
);
\gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000800000"
)
port map (
I0 => s_axi_wlast(0),
I1 => m_avalid,
I2 => s_axi_wvalid(0),
I3 => m_select_enc(0),
I4 => m_select_enc(2),
I5 => m_select_enc(1),
O => \write_cs0__0\
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => push,
I3 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FF77008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(0),
I3 => push,
I4 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8FFFFFF770000008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(0),
I3 => fifoaddr(1),
I4 => push,
I5 => fifoaddr(2),
O => \gen_rep[0].fifoaddr[2]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[2]_i_1_n_0\,
Q => fifoaddr(2),
S => SR(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.\zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\
port map (
D(0) => D(0),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
m_select_enc(0) => m_select_enc(0),
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
push => push,
\s_axi_awaddr[30]\(1) => \s_axi_awaddr[30]\(2),
\s_axi_awaddr[30]\(0) => \s_axi_awaddr[30]\(0),
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[1].srl_nx1\: entity work.\zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\
port map (
D(0) => D(1),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
m_select_enc(0) => m_select_enc(1),
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
push => push,
\s_axi_awaddr[30]\(1 downto 0) => \s_axi_awaddr[30]\(2 downto 1),
\storage_data1_reg[1]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[2].srl_nx1\: entity work.\zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\
port map (
D(0) => D(2),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
\m_aready0__3\ => \m_aready0__3\,
\m_aready__1\ => \m_aready__1\,
m_avalid => m_avalid,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_ready_d(0) => m_ready_d(0),
m_select_enc(2 downto 0) => m_select_enc(2 downto 0),
match => match,
out0(1) => p_0_in8_in,
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
p_22_in => p_22_in,
push => push,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => \^ss_wr_awready\,
\storage_data1_reg[2]\ => \gen_srls[0].gen_rep[2].srl_nx1_n_1\
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(1)
);
\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(2)
);
\m_axi_wvalid[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(3)
);
m_valid_i: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF400F400F400"
)
port map (
I0 => \m_aready__1\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => m_valid_i_n_0
);
m_valid_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(1),
I3 => fifoaddr(0),
I4 => fifoaddr(2),
I5 => push,
O => p_0_in5_out
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => m_valid_i_n_0,
Q => m_avalid,
R => areset_d1
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => m_avalid,
I1 => \m_aready0__3\,
O => s_axi_wready(0)
);
\s_ready_i_i_1__9\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0FFF0F8"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => areset_d1,
I3 => \s_ready_i1__4\,
I4 => \^ss_wr_awready\,
O => \s_ready_i_i_1__9_n_0\
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000700000000000"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(2),
I3 => fifoaddr(1),
I4 => fifoaddr(0),
I5 => push,
O => \s_ready_i1__4\
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__9_n_0\,
Q => \^ss_wr_awready\,
R => SR(0)
);
\storage_data1[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0FCA0A0A0ECA0A0"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[3]\,
I1 => p_9_in,
I2 => \m_aready__1\,
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => p_0_in8_in,
O => load_s1
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
Q => m_select_enc(0),
R => '0'
);
\storage_data1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[1].srl_nx1_n_0\,
Q => m_select_enc(1),
R => '0'
);
\storage_data1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[2].srl_nx1_n_1\,
Q => m_select_enc(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice is
port (
p_128_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_0__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\chosen_reg[2]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : in STD_LOGIC;
p_102_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice is
begin
b_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\
port map (
D(13 downto 0) => D(13 downto 0),
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\chosen_reg[2]\ => \chosen_reg[2]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_128_out,
p_108_out => p_108_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[0]\(0) => \chosen_reg[0]\(0),
\chosen_reg[0]_0\(0) => \chosen_reg[0]_0\(0),
\chosen_reg[2]\ => \chosen_reg[2]\,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => \m_axi_rready[0]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_122_out,
p_102_out => p_102_out,
p_1_in => p_1_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 is
port (
p_108_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_102_out : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_1__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_75_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\m_axi_bid[23]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1 is
begin
b_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\
port map (
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
\m_axi_bid[23]\(13 downto 0) => \m_axi_bid[23]\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_108_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\
port map (
ADDRESS_HIT_0 => ADDRESS_HIT_0,
D(0) => D(0),
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[1]\(0) => \chosen_reg[1]\(0),
\chosen_reg[1]_0\(0) => \chosen_reg[1]_0\(0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0) => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[1]\ => \m_axi_rready[1]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_102_out,
p_1_in => p_1_in,
p_75_in => p_75_in,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 is
port (
p_88_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_82_out : out STD_LOGIC;
\m_axi_rready[2]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_2__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_57_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[24]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_axi_bid[35]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2 is
begin
b_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\
port map (
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
\m_axi_bid[35]\(13 downto 0) => \m_axi_bid[35]\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_88_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\
port map (
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[2]\(0) => \chosen_reg[2]\(0),
\chosen_reg[2]_0\(0) => \chosen_reg[2]_0\(0),
\gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0) => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0),
\gen_master_slots[3].r_issuing_cnt_reg[24]\ => \gen_master_slots[3].r_issuing_cnt_reg[24]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[2]\ => \m_axi_rready[2]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_82_out,
p_1_in => p_1_in,
p_57_in => p_57_in,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_3 is
port (
p_68_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
p_62_out : out STD_LOGIC;
\m_axi_rready[3]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_3__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[4]\ : out STD_LOGIC;
\chosen_reg[4]_0\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_39_in : in STD_LOGIC;
p_82_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_3 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_3;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_3 is
signal \^p_1_in\ : STD_LOGIC;
begin
p_1_in <= \^p_1_in\;
b_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\
port map (
D(13 downto 0) => D(13 downto 0),
Q(0) => Q(0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\aresetn_d_reg[1]_1\ => \aresetn_d_reg[1]_1\,
\chosen_reg[4]\ => \chosen_reg[4]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_68_out,
p_1_in => \^p_1_in\,
p_88_out => p_88_out,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]_0\,
\chosen_reg[3]\(0) => \chosen_reg[3]\(0),
\chosen_reg[3]_0\(0) => \chosen_reg[3]_0\(0),
\chosen_reg[4]\ => \chosen_reg[4]\,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(3 downto 0) => \gen_master_slots[3].r_issuing_cnt_reg[27]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[3]\ => \m_axi_rready[3]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_62_out,
p_1_in => \^p_1_in\,
p_39_in => p_39_in,
p_82_out => p_82_out,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_4 is
port (
p_46_out : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
mi_bready_4 : out STD_LOGIC;
p_40_out : out STD_LOGIC;
mi_rready_4 : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
\r_cmd_pop_4__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_29_in : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_23_in : in STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_25_in : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_4 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_4;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_4 is
signal \^m_valid_i_reg\ : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
b_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
D(11 downto 0) => D(11 downto 0),
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(11 downto 0),
\m_payload_i_reg[2]_0\ => p_46_out,
m_valid_i_reg_0 => \^m_valid_i_reg\,
mi_bready_4 => mi_bready_4,
p_1_in => p_1_in,
p_29_in => p_29_in,
s_axi_bready(0) => s_axi_bready(0),
s_ready_i_reg_0 => s_ready_i_reg
);
r_pipe: entity work.\zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \^m_valid_i_reg\,
\chosen_reg[4]\(0) => \chosen_reg[4]\(0),
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => \gen_axi.s_axi_rid_i_reg[11]\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0),
m_valid_i_reg_0 => p_40_out,
p_1_in => p_1_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
s_axi_rready(0) => s_axi_rready(0),
\skid_buffer_reg[34]_0\ => mi_rready_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_wdata_router is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
\write_cs0__0\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
match : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_wdata_router : entity is "axi_crossbar_v2_1_14_wdata_router";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_wdata_router;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_wdata_router is
begin
wrouter_aw_fifo: entity work.zqynq_lab_1_design_xbar_0_axi_data_fifo_v2_1_12_axic_reg_srl_fifo
port map (
D(2 downto 0) => D(2 downto 0),
SR(0) => SR(0),
aclk => aclk,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
m_ready_d(0) => m_ready_d(0),
match => match,
p_22_in => p_22_in,
\s_axi_awaddr[30]\(2 downto 0) => \s_axi_awaddr[30]\(2 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
\write_cs0__0\ => \write_cs0__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_crossbar is
port (
M_AXI_RREADY : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
\m_axi_arqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
\s_axi_awready[0]\ : out STD_LOGIC;
\s_axi_bvalid[0]\ : out STD_LOGIC;
\s_axi_rvalid[0]\ : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 68 downto 0 );
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
aresetn : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_crossbar : entity is "axi_crossbar_v2_1_14_crossbar";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_crossbar;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_crossbar is
signal \^q\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 4 to 4 );
signal aa_mi_arvalid : STD_LOGIC;
signal aa_mi_awtarget_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal aa_sa_awvalid : STD_LOGIC;
signal addr_arbiter_ar_n_79 : STD_LOGIC;
signal addr_arbiter_ar_n_80 : STD_LOGIC;
signal addr_arbiter_ar_n_81 : STD_LOGIC;
signal addr_arbiter_ar_n_82 : STD_LOGIC;
signal addr_arbiter_ar_n_83 : STD_LOGIC;
signal addr_arbiter_ar_n_84 : STD_LOGIC;
signal addr_arbiter_ar_n_85 : STD_LOGIC;
signal addr_arbiter_ar_n_86 : STD_LOGIC;
signal addr_arbiter_ar_n_87 : STD_LOGIC;
signal addr_arbiter_ar_n_88 : STD_LOGIC;
signal addr_arbiter_ar_n_89 : STD_LOGIC;
signal addr_arbiter_ar_n_90 : STD_LOGIC;
signal addr_arbiter_ar_n_99 : STD_LOGIC;
signal addr_arbiter_aw_n_23 : STD_LOGIC;
signal addr_arbiter_aw_n_25 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_54\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_55\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_6\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_53\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_53\ : STD_LOGIC;
signal \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_55\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_56\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_57\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_7\ : STD_LOGIC;
signal \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[4].reg_slice_mi_n_1\ : STD_LOGIC;
signal \gen_master_slots[4].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst/chosen\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst/chosen_9\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\ : STD_LOGIC;
signal \^m_axi_arqos[15]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d_12 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_valid_i : STD_LOGIC;
signal m_valid_i_10 : STD_LOGIC;
signal match : STD_LOGIC;
signal match_3 : STD_LOGIC;
signal mi_arready_4 : STD_LOGIC;
signal mi_awready_4 : STD_LOGIC;
signal \mi_awready_mux__3\ : STD_LOGIC;
signal mi_bready_4 : STD_LOGIC;
signal mi_rready_4 : STD_LOGIC;
signal p_101_in : STD_LOGIC;
signal p_102_out : STD_LOGIC;
signal p_104_out : STD_LOGIC;
signal p_108_out : STD_LOGIC;
signal p_122_out : STD_LOGIC;
signal p_124_out : STD_LOGIC;
signal p_128_out : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_22_in : STD_LOGIC;
signal p_23_in : STD_LOGIC;
signal p_25_in : STD_LOGIC;
signal p_28_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_29_in : STD_LOGIC;
signal p_32_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_39_in : STD_LOGIC;
signal p_40_out : STD_LOGIC;
signal p_42_out : STD_LOGIC;
signal p_46_out : STD_LOGIC;
signal p_48_in : STD_LOGIC;
signal p_57_in : STD_LOGIC;
signal p_62_out : STD_LOGIC;
signal p_64_out : STD_LOGIC;
signal p_66_in : STD_LOGIC;
signal p_68_out : STD_LOGIC;
signal p_75_in : STD_LOGIC;
signal p_82_out : STD_LOGIC;
signal p_84_in : STD_LOGIC;
signal p_84_out : STD_LOGIC;
signal p_88_out : STD_LOGIC;
signal p_93_in : STD_LOGIC;
signal \r_cmd_pop_0__1\ : STD_LOGIC;
signal \r_cmd_pop_1__1\ : STD_LOGIC;
signal \r_cmd_pop_2__1\ : STD_LOGIC;
signal \r_cmd_pop_3__1\ : STD_LOGIC;
signal \r_cmd_pop_4__1\ : STD_LOGIC;
signal r_issuing_cnt : STD_LOGIC_VECTOR ( 32 downto 0 );
signal \r_pipe/p_1_in\ : STD_LOGIC;
signal \r_pipe/p_1_in_5\ : STD_LOGIC;
signal \r_pipe/p_1_in_6\ : STD_LOGIC;
signal \r_pipe/p_1_in_7\ : STD_LOGIC;
signal \r_pipe/p_1_in_8\ : STD_LOGIC;
signal \read_cs__0\ : STD_LOGIC;
signal reset : STD_LOGIC;
signal \^s_axi_awready[0]\ : STD_LOGIC;
signal s_axi_rlast_i0 : STD_LOGIC;
signal s_axi_rvalid_i : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal s_ready_i0_11 : STD_LOGIC;
signal \s_ready_i0__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \sa_wm_awready_mux__3\ : STD_LOGIC;
signal splitter_aw_mi_n_0 : STD_LOGIC;
signal splitter_aw_mi_n_1 : STD_LOGIC;
signal splitter_aw_mi_n_10 : STD_LOGIC;
signal splitter_aw_mi_n_11 : STD_LOGIC;
signal splitter_aw_mi_n_12 : STD_LOGIC;
signal splitter_aw_mi_n_2 : STD_LOGIC;
signal splitter_aw_mi_n_3 : STD_LOGIC;
signal splitter_aw_mi_n_4 : STD_LOGIC;
signal splitter_aw_mi_n_5 : STD_LOGIC;
signal splitter_aw_mi_n_6 : STD_LOGIC;
signal splitter_aw_mi_n_7 : STD_LOGIC;
signal splitter_aw_mi_n_8 : STD_LOGIC;
signal splitter_aw_mi_n_9 : STD_LOGIC;
signal ss_aa_awready : STD_LOGIC;
signal ss_wr_awready : STD_LOGIC;
signal ss_wr_awvalid : STD_LOGIC;
signal st_aa_awtarget_enc : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_bid : STD_LOGIC_VECTOR ( 59 downto 0 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 10 downto 0 );
signal st_mr_rid : STD_LOGIC_VECTOR ( 59 downto 0 );
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 139 downto 0 );
signal w_issuing_cnt : STD_LOGIC_VECTOR ( 32 downto 0 );
signal write_cs01_out : STD_LOGIC;
signal \write_cs0__0\ : STD_LOGIC;
begin
Q(68 downto 0) <= \^q\(68 downto 0);
S_AXI_ARREADY(0) <= \^s_axi_arready\(0);
\m_axi_arqos[15]\(68 downto 0) <= \^m_axi_arqos[15]\(68 downto 0);
\s_axi_awready[0]\ <= \^s_axi_awready[0]\;
addr_arbiter_ar: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
D(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
D(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
E(0) => s_ready_i0,
Q(0) => aa_mi_artarget_hot(4),
SR(0) => reset,
S_AXI_ARREADY(0) => \^s_axi_arready\(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
\gen_axi.s_axi_rid_i_reg[11]\(0) => s_axi_rvalid_i,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(2) => addr_arbiter_ar_n_79,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(1) => addr_arbiter_ar_n_80,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(0) => addr_arbiter_ar_n_81,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(2) => addr_arbiter_ar_n_82,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(1) => addr_arbiter_ar_n_83,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(0) => addr_arbiter_ar_n_84,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(2) => addr_arbiter_ar_n_88,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(1) => addr_arbiter_ar_n_89,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(0) => addr_arbiter_ar_n_90,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(2) => addr_arbiter_ar_n_85,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(1) => addr_arbiter_ar_n_86,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(0) => addr_arbiter_ar_n_87,
\gen_master_slots[4].r_issuing_cnt_reg[32]\ => addr_arbiter_ar_n_99,
\m_axi_arqos[15]\(68 downto 0) => \^m_axi_arqos[15]\(68 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_valid_i => m_valid_i,
match => match,
mi_arready_4 => mi_arready_4,
p_23_in => p_23_in,
p_39_in => p_39_in,
p_57_in => p_57_in,
p_75_in => p_75_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(16) => r_issuing_cnt(32),
r_issuing_cnt(15 downto 12) => r_issuing_cnt(27 downto 24),
r_issuing_cnt(11 downto 8) => r_issuing_cnt(19 downto 16),
r_issuing_cnt(7 downto 4) => r_issuing_cnt(11 downto 8),
r_issuing_cnt(3 downto 0) => r_issuing_cnt(3 downto 0),
\read_cs__0\ => \read_cs__0\,
\s_axi_araddr[24]\(0) => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\,
\s_axi_arqos[3]\(68 downto 0) => \s_axi_arqos[3]\(68 downto 0),
s_axi_rlast_i0 => s_axi_rlast_i0
);
addr_arbiter_aw: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_addr_arbiter_0
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4\,
D(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\,
D(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
E(0) => s_ready_i0_11,
Q(4 downto 0) => aa_mi_awtarget_hot(4 downto 0),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
\chosen_reg[4]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(4),
\gen_master_slots[4].w_issuing_cnt_reg[32]\ => addr_arbiter_aw_n_25,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_23,
\m_axi_awqos[15]\(68 downto 0) => \^q\(68 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_ready_d(1 downto 0) => m_ready_d_12(1 downto 0),
m_ready_d_0(0) => m_ready_d(0),
m_valid_i => m_valid_i_10,
match => match_3,
mi_awready_4 => mi_awready_4,
\mi_awready_mux__3\ => \mi_awready_mux__3\,
p_101_in => p_101_in,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_84_in => p_84_in,
\s_axi_awaddr[24]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
\s_axi_awqos[3]\(68 downto 0) => D(68 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
\s_ready_i0__1\(0) => \s_ready_i0__1\(0),
\sa_wm_awready_mux__3\ => \sa_wm_awready_mux__3\,
ss_aa_awready => ss_aa_awready,
w_issuing_cnt(0) => w_issuing_cnt(32),
write_cs01_out => write_cs01_out
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr_slave.decerr_slave_inst\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_decerr_slave
port map (
E(0) => s_axi_rvalid_i,
Q(0) => aa_mi_awtarget_hot(4),
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_no_arbiter.m_mesg_i_reg[11]\(11 downto 0) => \^q\(11 downto 0),
\gen_no_arbiter.m_mesg_i_reg[51]\(19 downto 12) => \^m_axi_arqos[15]\(51 downto 44),
\gen_no_arbiter.m_mesg_i_reg[51]\(11 downto 0) => \^m_axi_arqos[15]\(11 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[4]\(0) => aa_mi_artarget_hot(4),
\m_payload_i_reg[13]\(11 downto 0) => p_32_in(11 downto 0),
m_ready_d(0) => m_ready_d_12(1),
\m_ready_d_reg[1]\ => splitter_aw_mi_n_3,
mi_arready_4 => mi_arready_4,
mi_awready_4 => mi_awready_4,
mi_bready_4 => mi_bready_4,
mi_rready_4 => mi_rready_4,
p_22_in => p_22_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
p_29_in => p_29_in,
\read_cs__0\ => \read_cs__0\,
s_axi_rlast_i0 => s_axi_rlast_i0,
\skid_buffer_reg[46]\(11 downto 0) => p_28_in(11 downto 0),
write_cs01_out => write_cs01_out,
\write_cs0__0\ => \write_cs0__0\
);
\gen_master_slots[0].r_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(0),
O => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].r_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\,
Q => r_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_81,
Q => r_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_80,
Q => r_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_79,
Q => r_issuing_cnt(3),
R => reset
);
\gen_master_slots[0].reg_slice_mi\: entity work.zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice
port map (
D(13 downto 2) => m_axi_bid(11 downto 0),
D(1 downto 0) => m_axi_bresp(1 downto 0),
E(0) => \gen_master_slots[0].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[0]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(0),
\chosen_reg[0]_0\(0) => \r_pipe/p_1_in_8\,
\chosen_reg[2]\ => \gen_master_slots[0].reg_slice_mi_n_54\,
\chosen_reg[2]_0\ => \gen_master_slots[0].reg_slice_mi_n_55\,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => r_issuing_cnt(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_124_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(1 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(34 downto 3),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(1 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_6\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => M_AXI_RREADY(0),
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
p_102_out => p_102_out,
p_108_out => p_108_out,
p_122_out => p_122_out,
p_128_out => p_128_out,
p_1_in => p_1_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[0].w_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(0),
O => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].w_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\,
Q => w_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_12,
Q => w_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_11,
Q => w_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_10,
Q => w_issuing_cnt(3),
R => reset
);
\gen_master_slots[1].r_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(8),
O => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].r_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_83,
Q => r_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_82,
Q => r_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\,
Q => r_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_84,
Q => r_issuing_cnt(9),
R => reset
);
\gen_master_slots[1].reg_slice_mi\: entity work.zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_1
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
E(0) => \gen_master_slots[1].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(1),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[1]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(1),
\chosen_reg[1]_0\(0) => \r_pipe/p_1_in_7\,
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_6\,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0) => r_issuing_cnt(11 downto 8),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_104_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(36 downto 35),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(69 downto 38),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(4 downto 3),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_53\,
\m_axi_bid[23]\(13 downto 2) => m_axi_bid(23 downto 12),
\m_axi_bid[23]\(1 downto 0) => m_axi_bresp(3 downto 2),
m_axi_bready(0) => m_axi_bready(1),
m_axi_bvalid(0) => m_axi_bvalid(1),
m_axi_rdata(31 downto 0) => m_axi_rdata(63 downto 32),
m_axi_rid(11 downto 0) => m_axi_rid(23 downto 12),
m_axi_rlast(0) => m_axi_rlast(1),
\m_axi_rready[1]\ => M_AXI_RREADY(1),
m_axi_rresp(1 downto 0) => m_axi_rresp(3 downto 2),
m_axi_rvalid(0) => m_axi_rvalid(1),
p_102_out => p_102_out,
p_108_out => p_108_out,
p_1_in => p_1_in,
p_75_in => p_75_in,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[1].w_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(8),
O => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].w_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_1,
Q => w_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_0,
Q => w_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\,
Q => w_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_2,
Q => w_issuing_cnt(9),
R => reset
);
\gen_master_slots[2].r_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(16),
O => \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\
);
\gen_master_slots[2].r_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\,
Q => r_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_90,
Q => r_issuing_cnt(17),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_89,
Q => r_issuing_cnt(18),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_88,
Q => r_issuing_cnt(19),
R => reset
);
\gen_master_slots[2].reg_slice_mi\: entity work.zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_2
port map (
D(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
E(0) => \gen_master_slots[2].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(2),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2),
\chosen_reg[2]_0\(0) => \r_pipe/p_1_in\,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0) => r_issuing_cnt(19 downto 16),
\gen_master_slots[3].r_issuing_cnt_reg[24]\ => \gen_master_slots[3].reg_slice_mi_n_7\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_84_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(71 downto 70),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(104 downto 73),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(7 downto 6),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[2].reg_slice_mi_n_53\,
\m_axi_bid[35]\(13 downto 2) => m_axi_bid(35 downto 24),
\m_axi_bid[35]\(1 downto 0) => m_axi_bresp(5 downto 4),
m_axi_bready(0) => m_axi_bready(2),
m_axi_bvalid(0) => m_axi_bvalid(2),
m_axi_rdata(31 downto 0) => m_axi_rdata(95 downto 64),
m_axi_rid(11 downto 0) => m_axi_rid(35 downto 24),
m_axi_rlast(0) => m_axi_rlast(2),
\m_axi_rready[2]\ => M_AXI_RREADY(2),
m_axi_rresp(1 downto 0) => m_axi_rresp(5 downto 4),
m_axi_rvalid(0) => m_axi_rvalid(2),
p_1_in => p_1_in,
p_57_in => p_57_in,
p_82_out => p_82_out,
p_88_out => p_88_out,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[2].w_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(16),
O => \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\
);
\gen_master_slots[2].w_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\,
Q => w_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_6,
Q => w_issuing_cnt(17),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_5,
Q => w_issuing_cnt(18),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_4,
Q => w_issuing_cnt(19),
R => reset
);
\gen_master_slots[3].r_issuing_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(24),
O => \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\
);
\gen_master_slots[3].r_issuing_cnt_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\,
Q => r_issuing_cnt(24),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_87,
Q => r_issuing_cnt(25),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_86,
Q => r_issuing_cnt(26),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_85,
Q => r_issuing_cnt(27),
R => reset
);
\gen_master_slots[3].reg_slice_mi\: entity work.zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_3
port map (
D(13 downto 2) => m_axi_bid(47 downto 36),
D(1 downto 0) => m_axi_bresp(7 downto 6),
E(0) => \gen_master_slots[3].reg_slice_mi_n_5\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(3),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \gen_master_slots[3].reg_slice_mi_n_57\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_1\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(3),
\chosen_reg[3]_0\(0) => \r_pipe/p_1_in_5\,
\chosen_reg[4]\ => \gen_master_slots[3].reg_slice_mi_n_55\,
\chosen_reg[4]_0\ => \gen_master_slots[3].reg_slice_mi_n_56\,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(3 downto 0) => r_issuing_cnt(27 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(47 downto 36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_64_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(106 downto 105),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(139 downto 108),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(47 downto 36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(10 downto 9),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[3].reg_slice_mi_n_7\,
m_axi_bready(0) => m_axi_bready(3),
m_axi_bvalid(0) => m_axi_bvalid(3),
m_axi_rdata(31 downto 0) => m_axi_rdata(127 downto 96),
m_axi_rid(11 downto 0) => m_axi_rid(47 downto 36),
m_axi_rlast(0) => m_axi_rlast(3),
\m_axi_rready[3]\ => M_AXI_RREADY(3),
m_axi_rresp(1 downto 0) => m_axi_rresp(7 downto 6),
m_axi_rvalid(0) => m_axi_rvalid(3),
p_1_in => p_1_in,
p_39_in => p_39_in,
p_62_out => p_62_out,
p_68_out => p_68_out,
p_82_out => p_82_out,
p_88_out => p_88_out,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[3].w_issuing_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(24),
O => \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\
);
\gen_master_slots[3].w_issuing_cnt_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\,
Q => w_issuing_cnt(24),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_9,
Q => w_issuing_cnt(25),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_8,
Q => w_issuing_cnt(26),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_7,
Q => w_issuing_cnt(27),
R => reset
);
\gen_master_slots[4].r_issuing_cnt_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_ar_n_99,
Q => r_issuing_cnt(32),
R => reset
);
\gen_master_slots[4].reg_slice_mi\: entity work.zqynq_lab_1_design_xbar_0_axi_register_slice_v2_1_13_axi_register_slice_4
port map (
D(11 downto 0) => p_32_in(11 downto 0),
E(0) => \r_pipe/p_1_in_6\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(4),
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_master_slots[3].reg_slice_mi_n_57\,
\chosen_reg[4]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(4),
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => p_28_in(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 1) => st_mr_rid(59 downto 48),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => p_42_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(11 downto 0) => st_mr_bid(59 downto 48),
m_valid_i_reg => \gen_master_slots[4].reg_slice_mi_n_1\,
mi_bready_4 => mi_bready_4,
mi_rready_4 => mi_rready_4,
p_1_in => p_1_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
p_29_in => p_29_in,
p_40_out => p_40_out,
p_46_out => p_46_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0),
s_ready_i_reg => \gen_master_slots[4].reg_slice_mi_n_5\
);
\gen_master_slots[4].w_issuing_cnt_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_aw_n_25,
Q => w_issuing_cnt(32),
R => reset
);
\gen_slave_slots[0].gen_si_read.si_transactor_ar\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
D(0) => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\,
E(0) => s_ready_i0,
Q(4 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(4 downto 0),
SR(0) => reset,
S_AXI_ARREADY(0) => \^s_axi_arready\(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_53\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_53\,
\m_payload_i_reg[0]\(0) => \r_pipe/p_1_in_8\,
\m_payload_i_reg[0]_0\(0) => \r_pipe/p_1_in_7\,
\m_payload_i_reg[0]_1\(0) => \r_pipe/p_1_in_5\,
\m_payload_i_reg[0]_2\(0) => \r_pipe/p_1_in\,
\m_payload_i_reg[34]\(0) => \r_pipe/p_1_in_6\,
\m_payload_i_reg[34]_0\(0) => p_42_out,
\m_payload_i_reg[34]_1\(0) => p_64_out,
\m_payload_i_reg[34]_2\(0) => p_124_out,
\m_payload_i_reg[34]_3\(0) => p_84_out,
\m_payload_i_reg[34]_4\(0) => p_104_out,
m_valid_i => m_valid_i,
m_valid_i_reg => \gen_master_slots[3].reg_slice_mi_n_55\,
m_valid_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_54\,
match => match,
p_102_out => p_102_out,
p_122_out => p_122_out,
p_40_out => p_40_out,
p_62_out => p_62_out,
p_82_out => p_82_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(0) => r_issuing_cnt(32),
\s_axi_araddr[30]\(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
\s_axi_araddr[30]\(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
\s_axi_araddr[30]\(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
\s_axi_arid[11]\(11 downto 0) => \s_axi_arqos[3]\(11 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => \s_axi_rid[0]\,
\s_axi_rid[10]\ => \s_axi_rid[10]\,
\s_axi_rid[11]\ => \s_axi_rid[11]\,
\s_axi_rid[1]\ => \s_axi_rid[1]\,
\s_axi_rid[2]\ => \s_axi_rid[2]\,
\s_axi_rid[3]\ => \s_axi_rid[3]\,
\s_axi_rid[4]\ => \s_axi_rid[4]\,
\s_axi_rid[5]\ => \s_axi_rid[5]\,
\s_axi_rid[6]\ => \s_axi_rid[6]\,
\s_axi_rid[7]\ => \s_axi_rid[7]\,
\s_axi_rid[8]\ => \s_axi_rid[8]\,
\s_axi_rid[9]\ => \s_axi_rid[9]\,
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
\s_axi_rvalid[0]\ => \s_axi_rvalid[0]\,
st_mr_rid(59 downto 0) => st_mr_rid(59 downto 0),
st_mr_rmesg(135 downto 104) => st_mr_rmesg(139 downto 108),
st_mr_rmesg(103 downto 70) => st_mr_rmesg(106 downto 73),
st_mr_rmesg(69 downto 36) => st_mr_rmesg(71 downto 38),
st_mr_rmesg(35 downto 2) => st_mr_rmesg(36 downto 3),
st_mr_rmesg(1 downto 0) => st_mr_rmesg(1 downto 0)
);
\gen_slave_slots[0].gen_si_write.si_transactor_aw\: entity work.\zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_si_transactor__parameterized0\
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4\,
D(2) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
D(1 downto 0) => st_aa_awtarget_enc(1 downto 0),
E(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
Q(4 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(4 downto 0),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
\gen_master_slots[2].w_issuing_cnt_reg[16]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
\gen_master_slots[3].w_issuing_cnt_reg[24]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
\gen_no_arbiter.s_ready_i_reg[0]\(0) => s_ready_i0_11,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_23,
\m_ready_d_reg[1]\ => \^s_axi_awready[0]\,
m_valid_i => m_valid_i_10,
m_valid_i_reg => \gen_master_slots[3].reg_slice_mi_n_56\,
m_valid_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_55\,
match => match_3,
p_101_in => p_101_in,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_68_out => p_68_out,
p_84_in => p_84_in,
p_88_out => p_88_out,
\s_axi_awaddr[30]\(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\,
\s_axi_awaddr[30]\(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\,
\s_axi_awaddr[30]\(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
\s_axi_awid[11]\(11 downto 0) => D(11 downto 0),
\s_axi_bid[0]\ => \s_axi_bid[0]\,
\s_axi_bid[10]\ => \s_axi_bid[10]\,
\s_axi_bid[11]\ => \s_axi_bid[11]\,
\s_axi_bid[1]\ => \s_axi_bid[1]\,
\s_axi_bid[2]\ => \s_axi_bid[2]\,
\s_axi_bid[3]\ => \s_axi_bid[3]\,
\s_axi_bid[4]\ => \s_axi_bid[4]\,
\s_axi_bid[5]\ => \s_axi_bid[5]\,
\s_axi_bid[6]\ => \s_axi_bid[6]\,
\s_axi_bid[7]\ => \s_axi_bid[7]\,
\s_axi_bid[8]\ => \s_axi_bid[8]\,
\s_axi_bid[9]\ => \s_axi_bid[9]\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
\s_axi_bvalid[0]\ => \s_axi_bvalid[0]\,
st_mr_bid(59 downto 0) => st_mr_bid(59 downto 0),
st_mr_bmesg(7 downto 6) => st_mr_bmesg(10 downto 9),
st_mr_bmesg(5 downto 4) => st_mr_bmesg(7 downto 6),
st_mr_bmesg(3 downto 2) => st_mr_bmesg(4 downto 3),
st_mr_bmesg(1 downto 0) => st_mr_bmesg(1 downto 0),
w_issuing_cnt(16) => w_issuing_cnt(32),
w_issuing_cnt(15 downto 12) => w_issuing_cnt(27 downto 24),
w_issuing_cnt(11 downto 8) => w_issuing_cnt(19 downto 16),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
\gen_slave_slots[0].gen_si_write.splitter_aw_si\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter
port map (
aclk => aclk,
aresetn_d => aresetn_d,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
\s_axi_awready[0]\ => \^s_axi_awready[0]\,
s_axi_awvalid(0) => s_axi_awvalid(0),
ss_aa_awready => ss_aa_awready,
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid
);
\gen_slave_slots[0].gen_si_write.wdata_router_w\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_wdata_router
port map (
D(2) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
D(1 downto 0) => st_aa_awtarget_enc(1 downto 0),
SR(0) => reset,
aclk => aclk,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
m_ready_d(0) => m_ready_d(1),
match => match_3,
p_22_in => p_22_in,
\s_axi_awaddr[30]\(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\,
\s_axi_awaddr[30]\(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\,
\s_axi_awaddr[30]\(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
\write_cs0__0\ => \write_cs0__0\
);
splitter_aw_mi: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_splitter_5
port map (
D(2) => splitter_aw_mi_n_0,
D(1) => splitter_aw_mi_n_1,
D(0) => splitter_aw_mi_n_2,
Q(3 downto 0) => aa_mi_awtarget_hot(3 downto 0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\chosen_reg[3]\(3 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(3 downto 0),
\gen_axi.s_axi_awready_i_reg\ => splitter_aw_mi_n_3,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(2) => splitter_aw_mi_n_10,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(1) => splitter_aw_mi_n_11,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(0) => splitter_aw_mi_n_12,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(2) => splitter_aw_mi_n_4,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(1) => splitter_aw_mi_n_5,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(0) => splitter_aw_mi_n_6,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(2) => splitter_aw_mi_n_7,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(1) => splitter_aw_mi_n_8,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(0) => splitter_aw_mi_n_9,
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_ready_d(1 downto 0) => m_ready_d_12(1 downto 0),
\mi_awready_mux__3\ => \mi_awready_mux__3\,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_68_out => p_68_out,
p_88_out => p_88_out,
s_axi_bready(0) => s_axi_bready(0),
\s_ready_i0__1\(0) => \s_ready_i0__1\(0),
\sa_wm_awready_mux__3\ => \sa_wm_awready_mux__3\,
w_issuing_cnt(15 downto 12) => w_issuing_cnt(27 downto 24),
w_issuing_cnt(11 downto 8) => w_issuing_cnt(19 downto 16),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001101000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "axi_crossbar_v2_1_14_axi_crossbar";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
end zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 127 downto 96 );
signal \^m_axi_arburst\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \^m_axi_arcache\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_arqos\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 127 downto 96 );
signal \^m_axi_awburst\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \^m_axi_awcache\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 31 downto 24 );
signal \^m_axi_awlock\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^m_axi_awprot\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_awqos\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_awsize\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\(0) <= s_axi_wlast(0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(127 downto 96) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(95 downto 64) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(63 downto 32) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(31 downto 0) <= \^m_axi_araddr\(127 downto 96);
m_axi_arburst(7 downto 6) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(5 downto 4) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(3 downto 2) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(1 downto 0) <= \^m_axi_arburst\(7 downto 6);
m_axi_arcache(15 downto 12) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(11 downto 8) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(7 downto 4) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(3 downto 0) <= \^m_axi_arcache\(15 downto 12);
m_axi_arid(47 downto 36) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(35 downto 24) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(23 downto 12) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
m_axi_arlen(31 downto 24) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(23 downto 16) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(15 downto 8) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlock(3) <= \^m_axi_arlock\(3);
m_axi_arlock(2) <= \^m_axi_arlock\(3);
m_axi_arlock(1) <= \^m_axi_arlock\(3);
m_axi_arlock(0) <= \^m_axi_arlock\(3);
m_axi_arprot(11 downto 9) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(11 downto 9);
m_axi_arqos(15 downto 12) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(11 downto 8) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(7 downto 4) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(3 downto 0) <= \^m_axi_arqos\(15 downto 12);
m_axi_arregion(15) <= \<const0>\;
m_axi_arregion(14) <= \<const0>\;
m_axi_arregion(13) <= \<const0>\;
m_axi_arregion(12) <= \<const0>\;
m_axi_arregion(11) <= \<const0>\;
m_axi_arregion(10) <= \<const0>\;
m_axi_arregion(9) <= \<const0>\;
m_axi_arregion(8) <= \<const0>\;
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(11 downto 9) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(8 downto 6) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(5 downto 3) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(2 downto 0) <= \^m_axi_arsize\(11 downto 9);
m_axi_aruser(3) <= \<const0>\;
m_axi_aruser(2) <= \<const0>\;
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(127 downto 96) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(95 downto 64) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(63 downto 32) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(31 downto 0) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awburst(7 downto 6) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(5 downto 4) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(3 downto 2) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(1 downto 0) <= \^m_axi_awburst\(7 downto 6);
m_axi_awcache(15 downto 12) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(11 downto 8) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(7 downto 4) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(3 downto 0) <= \^m_axi_awcache\(15 downto 12);
m_axi_awid(47 downto 36) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(35 downto 24) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(23 downto 12) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(11 downto 0) <= \^m_axi_awid\(11 downto 0);
m_axi_awlen(31 downto 24) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(23 downto 16) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(15 downto 8) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlock(3) <= \^m_axi_awlock\(3);
m_axi_awlock(2) <= \^m_axi_awlock\(3);
m_axi_awlock(1) <= \^m_axi_awlock\(3);
m_axi_awlock(0) <= \^m_axi_awlock\(3);
m_axi_awprot(11 downto 9) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(8 downto 6) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(5 downto 3) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(2 downto 0) <= \^m_axi_awprot\(11 downto 9);
m_axi_awqos(15 downto 12) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(11 downto 8) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(7 downto 4) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(3 downto 0) <= \^m_axi_awqos\(15 downto 12);
m_axi_awregion(15) <= \<const0>\;
m_axi_awregion(14) <= \<const0>\;
m_axi_awregion(13) <= \<const0>\;
m_axi_awregion(12) <= \<const0>\;
m_axi_awregion(11) <= \<const0>\;
m_axi_awregion(10) <= \<const0>\;
m_axi_awregion(9) <= \<const0>\;
m_axi_awregion(8) <= \<const0>\;
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(11 downto 9) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(8 downto 6) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(5 downto 3) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(2 downto 0) <= \^m_axi_awsize\(11 downto 9);
m_axi_awuser(3) <= \<const0>\;
m_axi_awuser(2) <= \<const0>\;
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(127 downto 96) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(47) <= \<const0>\;
m_axi_wid(46) <= \<const0>\;
m_axi_wid(45) <= \<const0>\;
m_axi_wid(44) <= \<const0>\;
m_axi_wid(43) <= \<const0>\;
m_axi_wid(42) <= \<const0>\;
m_axi_wid(41) <= \<const0>\;
m_axi_wid(40) <= \<const0>\;
m_axi_wid(39) <= \<const0>\;
m_axi_wid(38) <= \<const0>\;
m_axi_wid(37) <= \<const0>\;
m_axi_wid(36) <= \<const0>\;
m_axi_wid(35) <= \<const0>\;
m_axi_wid(34) <= \<const0>\;
m_axi_wid(33) <= \<const0>\;
m_axi_wid(32) <= \<const0>\;
m_axi_wid(31) <= \<const0>\;
m_axi_wid(30) <= \<const0>\;
m_axi_wid(29) <= \<const0>\;
m_axi_wid(28) <= \<const0>\;
m_axi_wid(27) <= \<const0>\;
m_axi_wid(26) <= \<const0>\;
m_axi_wid(25) <= \<const0>\;
m_axi_wid(24) <= \<const0>\;
m_axi_wid(23) <= \<const0>\;
m_axi_wid(22) <= \<const0>\;
m_axi_wid(21) <= \<const0>\;
m_axi_wid(20) <= \<const0>\;
m_axi_wid(19) <= \<const0>\;
m_axi_wid(18) <= \<const0>\;
m_axi_wid(17) <= \<const0>\;
m_axi_wid(16) <= \<const0>\;
m_axi_wid(15) <= \<const0>\;
m_axi_wid(14) <= \<const0>\;
m_axi_wid(13) <= \<const0>\;
m_axi_wid(12) <= \<const0>\;
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(3) <= \^s_axi_wlast\(0);
m_axi_wlast(2) <= \^s_axi_wlast\(0);
m_axi_wlast(1) <= \^s_axi_wlast\(0);
m_axi_wlast(0) <= \^s_axi_wlast\(0);
m_axi_wstrb(15 downto 12) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(3) <= \<const0>\;
m_axi_wuser(2) <= \<const0>\;
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_samd.crossbar_samd\: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_crossbar
port map (
D(68 downto 65) => s_axi_awqos(3 downto 0),
D(64 downto 61) => s_axi_awcache(3 downto 0),
D(60 downto 59) => s_axi_awburst(1 downto 0),
D(58 downto 56) => s_axi_awprot(2 downto 0),
D(55) => s_axi_awlock(0),
D(54 downto 52) => s_axi_awsize(2 downto 0),
D(51 downto 44) => s_axi_awlen(7 downto 0),
D(43 downto 12) => s_axi_awaddr(31 downto 0),
D(11 downto 0) => s_axi_awid(11 downto 0),
M_AXI_RREADY(3 downto 0) => m_axi_rready(3 downto 0),
Q(68 downto 65) => \^m_axi_awqos\(15 downto 12),
Q(64 downto 61) => \^m_axi_awcache\(15 downto 12),
Q(60 downto 59) => \^m_axi_awburst\(7 downto 6),
Q(58 downto 56) => \^m_axi_awprot\(11 downto 9),
Q(55) => \^m_axi_awlock\(3),
Q(54 downto 52) => \^m_axi_awsize\(11 downto 9),
Q(51 downto 44) => \^m_axi_awlen\(31 downto 24),
Q(43 downto 12) => \^m_axi_awaddr\(127 downto 96),
Q(11 downto 0) => \^m_axi_awid\(11 downto 0),
S_AXI_ARREADY(0) => s_axi_arready(0),
aclk => aclk,
aresetn => aresetn,
\m_axi_arqos[15]\(68 downto 65) => \^m_axi_arqos\(15 downto 12),
\m_axi_arqos[15]\(64 downto 61) => \^m_axi_arcache\(15 downto 12),
\m_axi_arqos[15]\(60 downto 59) => \^m_axi_arburst\(7 downto 6),
\m_axi_arqos[15]\(58 downto 56) => \^m_axi_arprot\(11 downto 9),
\m_axi_arqos[15]\(55) => \^m_axi_arlock\(3),
\m_axi_arqos[15]\(54 downto 52) => \^m_axi_arsize\(11 downto 9),
\m_axi_arqos[15]\(51 downto 44) => \^m_axi_arlen\(7 downto 0),
\m_axi_arqos[15]\(43 downto 12) => \^m_axi_araddr\(127 downto 96),
\m_axi_arqos[15]\(11 downto 0) => \^m_axi_arid\(11 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bid(47 downto 0) => m_axi_bid(47 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(47 downto 0) => m_axi_rid(47 downto 0),
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
\s_axi_arqos[3]\(68 downto 65) => s_axi_arqos(3 downto 0),
\s_axi_arqos[3]\(64 downto 61) => s_axi_arcache(3 downto 0),
\s_axi_arqos[3]\(60 downto 59) => s_axi_arburst(1 downto 0),
\s_axi_arqos[3]\(58 downto 56) => s_axi_arprot(2 downto 0),
\s_axi_arqos[3]\(55) => s_axi_arlock(0),
\s_axi_arqos[3]\(54 downto 52) => s_axi_arsize(2 downto 0),
\s_axi_arqos[3]\(51 downto 44) => s_axi_arlen(7 downto 0),
\s_axi_arqos[3]\(43 downto 12) => s_axi_araddr(31 downto 0),
\s_axi_arqos[3]\(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
\s_axi_awready[0]\ => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
\s_axi_bid[0]\ => s_axi_bid(0),
\s_axi_bid[10]\ => s_axi_bid(10),
\s_axi_bid[11]\ => s_axi_bid(11),
\s_axi_bid[1]\ => s_axi_bid(1),
\s_axi_bid[2]\ => s_axi_bid(2),
\s_axi_bid[3]\ => s_axi_bid(3),
\s_axi_bid[4]\ => s_axi_bid(4),
\s_axi_bid[5]\ => s_axi_bid(5),
\s_axi_bid[6]\ => s_axi_bid(6),
\s_axi_bid[7]\ => s_axi_bid(7),
\s_axi_bid[8]\ => s_axi_bid(8),
\s_axi_bid[9]\ => s_axi_bid(9),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
\s_axi_bvalid[0]\ => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => s_axi_rid(0),
\s_axi_rid[10]\ => s_axi_rid(10),
\s_axi_rid[11]\ => s_axi_rid(11),
\s_axi_rid[1]\ => s_axi_rid(1),
\s_axi_rid[2]\ => s_axi_rid(2),
\s_axi_rid[3]\ => s_axi_rid(3),
\s_axi_rid[4]\ => s_axi_rid(4),
\s_axi_rid[5]\ => s_axi_rid(5),
\s_axi_rid[6]\ => s_axi_rid(6),
\s_axi_rid[7]\ => s_axi_rid(7),
\s_axi_rid[8]\ => s_axi_rid(8),
\s_axi_rid[9]\ => s_axi_rid(9),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
\s_axi_rvalid[0]\ => s_axi_rvalid(0),
s_axi_wlast(0) => \^s_axi_wlast\(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_xbar_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_xbar_0 : entity is "zqynq_lab_1_design_xbar_0,axi_crossbar_v2_1_14_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_xbar_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zqynq_lab_1_design_xbar_0 : entity is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2.1";
end zqynq_lab_1_design_xbar_0;
architecture STRUCTURE of zqynq_lab_1_design_xbar_0 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "128'b00000000000000000000000000001101000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 8;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
begin
inst: entity work.zqynq_lab_1_design_xbar_0_axi_crossbar_v2_1_14_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(127 downto 0) => m_axi_araddr(127 downto 0),
m_axi_arburst(7 downto 0) => m_axi_arburst(7 downto 0),
m_axi_arcache(15 downto 0) => m_axi_arcache(15 downto 0),
m_axi_arid(47 downto 0) => m_axi_arid(47 downto 0),
m_axi_arlen(31 downto 0) => m_axi_arlen(31 downto 0),
m_axi_arlock(3 downto 0) => m_axi_arlock(3 downto 0),
m_axi_arprot(11 downto 0) => m_axi_arprot(11 downto 0),
m_axi_arqos(15 downto 0) => m_axi_arqos(15 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arregion(15 downto 0) => m_axi_arregion(15 downto 0),
m_axi_arsize(11 downto 0) => m_axi_arsize(11 downto 0),
m_axi_aruser(3 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awaddr(127 downto 0) => m_axi_awaddr(127 downto 0),
m_axi_awburst(7 downto 0) => m_axi_awburst(7 downto 0),
m_axi_awcache(15 downto 0) => m_axi_awcache(15 downto 0),
m_axi_awid(47 downto 0) => m_axi_awid(47 downto 0),
m_axi_awlen(31 downto 0) => m_axi_awlen(31 downto 0),
m_axi_awlock(3 downto 0) => m_axi_awlock(3 downto 0),
m_axi_awprot(11 downto 0) => m_axi_awprot(11 downto 0),
m_axi_awqos(15 downto 0) => m_axi_awqos(15 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awregion(15 downto 0) => m_axi_awregion(15 downto 0),
m_axi_awsize(11 downto 0) => m_axi_awsize(11 downto 0),
m_axi_awuser(3 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bid(47 downto 0) => m_axi_bid(47 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_buser(3 downto 0) => B"0000",
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(47 downto 0) => m_axi_rid(47 downto 0),
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rready(3 downto 0) => m_axi_rready(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_ruser(3 downto 0) => B"0000",
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wid(47 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(47 downto 0),
m_axi_wlast(3 downto 0) => m_axi_wlast(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wuser(3 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
| mit |
dawsonjon/FPGA-TX | fpga_tx/bsp_components/serial_out.vhd | 23 | 3390 | --------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
| mit |
dawsonjon/FPGA-TX | synthesis/nexys_4/tx/serial_out.vhd | 23 | 3390 | --------------------------------------------------------------------------------
---
--- SERIAL OUTPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Output Component
---
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity serial_output is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic := '1';
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic := '1'
);
end entity serial_output;
architecture RTL of serial_output is
constant CLOCK_DIVIDER : Unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/BAUD_RATE, 12);
signal BAUD_COUNT : Unsigned(11 downto 0) := (others => '0');
signal DATA : std_logic_vector(7 downto 0) := (others => '0');
signal X16CLK_EN : std_logic := '0';
signal S_IN1_ACK : std_logic := '0';
type STATE_TYPE is (IDLE, START, WAIT_EN, TX0, TX1, TX2, TX3, TX4, TX5, TX6, TX7, STOP);
signal STATE : STATE_TYPE := IDLE;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER - 1 then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
case STATE is
when IDLE =>
TX <= '1';
S_IN1_ACK <= '1';
if S_IN1_ACK = '1' and IN1_STB = '1' then
S_IN1_ACK <= '0';
DATA <= IN1;
STATE <= WAIT_EN;
end if;
when WAIT_EN =>
if X16CLK_EN = '1' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' then
STATE <= TX0;
end if;
TX <= '0';
when TX0 =>
if X16CLK_EN = '1' then
STATE <= TX1;
end if;
TX <= DATA(0);
when TX1 =>
if X16CLK_EN = '1' then
STATE <= TX2;
end if;
TX <= DATA(1);
when TX2 =>
if X16CLK_EN = '1' then
STATE <= TX3;
end if;
TX <= DATA(2);
when TX3 =>
if X16CLK_EN = '1' then
STATE <= TX4;
end if;
TX <= DATA(3);
when TX4 =>
if X16CLK_EN = '1' then
STATE <= TX5;
end if;
TX <= DATA(4);
when TX5 =>
if X16CLK_EN = '1' then
STATE <= TX6;
end if;
TX <= DATA(5);
when TX6 =>
if X16CLK_EN = '1' then
STATE <= TX7;
end if;
TX <= DATA(6);
when TX7 =>
if X16CLK_EN = '1' then
STATE <= STOP;
end if;
TX <= DATA(7);
when STOP =>
if X16CLK_EN = '1' then
STATE <= IDLE;
end if;
TX <= '1';
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
TX <= '1';
S_IN1_ACK <= '0';
end if;
end process;
IN1_ACK <= S_IN1_ACK;
end architecture RTL;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_xbar_0/zynq_design_1_xbar_0_stub.vhdl | 1 | 6981 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:30:16 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_xbar_0/zynq_design_1_xbar_0_stub.vhdl
-- Design : zynq_design_1_xbar_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zynq_design_1_xbar_0 is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end zynq_design_1_xbar_0;
architecture stub of zynq_design_1_xbar_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awid[23:0],m_axi_awaddr[63:0],m_axi_awlen[15:0],m_axi_awsize[5:0],m_axi_awburst[3:0],m_axi_awlock[1:0],m_axi_awcache[7:0],m_axi_awprot[5:0],m_axi_awregion[7:0],m_axi_awqos[7:0],m_axi_awvalid[1:0],m_axi_awready[1:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast[1:0],m_axi_wvalid[1:0],m_axi_wready[1:0],m_axi_bid[23:0],m_axi_bresp[3:0],m_axi_bvalid[1:0],m_axi_bready[1:0],m_axi_arid[23:0],m_axi_araddr[63:0],m_axi_arlen[15:0],m_axi_arsize[5:0],m_axi_arburst[3:0],m_axi_arlock[1:0],m_axi_arcache[7:0],m_axi_arprot[5:0],m_axi_arregion[7:0],m_axi_arqos[7:0],m_axi_arvalid[1:0],m_axi_arready[1:0],m_axi_rid[23:0],m_axi_rdata[63:0],m_axi_rresp[3:0],m_axi_rlast[1:0],m_axi_rvalid[1:0],m_axi_rready[1:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2";
begin
end;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ipshared/e9ee/hdl/axi_cdma_v4_1_vh_rfs.vhd | 1 | 598894 | -------------------------------------------------------------------------------
-- axi_cdma_pkg
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_pkg.vhd
-- Description: This package contains various constants and functions for
-- AXI DMA operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
package axi_cdma_pkg is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-- Find minimum required btt width
function required_btt_width1 (dwidth,
burst_size,
btt_width : integer)
return integer;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- AXI Responce Values
-------------------------------------------------------------------------------
constant OKAY_RESP : std_logic_vector(1 downto 0) := "00";
constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01";
constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10";
constant DECERR_RESP : std_logic_vector(1 downto 0) := "11";
-------------------------------------------------------------------------------
-- Misc Constants
-------------------------------------------------------------------------------
constant NUM_REG_TOTAL : integer := 18;
constant NUM_REG_PER_CHANNEL : integer := 6;
constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1;
--constant CMD_BASE_WIDTH : integer := 40;
constant CMD_BASE_WIDTH : integer := 104;
constant BUFFER_LENGTH_WIDTH : integer := 23;
-- Constants Used in Desc Updates
constant DESC_STS_TYPE : std_logic := '1';
constant DESC_DATA_TYPE : std_logic := '0';
constant DESC_LAST : std_logic := '1';
constant DESC_NOT_LAST : std_logic := '0';
-- Interrupt Coalescing
constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0');
constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001";
constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0');
constant MTBF_STAGES : integer := 4;
-------------------------------------------------------------------------------
-- Register Bit Constants
-------------------------------------------------------------------------------
-- DMACR
constant DMACR_RESERVED0_BIT : integer := 0;
constant DMACR_TAILPEN_BIT : integer := 1;
constant DMACR_RESET_BIT : integer := 2;
constant DMACR_SGMODE_BIT : integer := 3;
constant DMACR_KHREAD_BIT : integer := 4;
constant DMACR_KHWRITE_BIT : integer := 5;
--constant DMACR_RESERVED4_BIT : integer := 4;
--constant DMACR_RESERVED5_BIT : integer := 5;
constant DMACR_CYCLIC_BIT : integer := 6;
constant DMACR_RESERVED7_BIT : integer := 7;
constant DMACR_RESERVED8_BIT : integer := 8;
constant DMACR_RESERVED9_BIT : integer := 9;
constant DMACR_RESERVED10_BIT : integer := 10;
constant DMACR_RESERVED11_BIT : integer := 11;
constant DMACR_IOC_IRQEN_BIT : integer := 12;
constant DMACR_DLY_IRQEN_BIT : integer := 13;
constant DMACR_ERR_IRQEN_BIT : integer := 14;
constant DMACR_RESERVED15_BIT : integer := 15;
constant DMACR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMACR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMACR_IRQDELAY_LSB_BIT : integer := 24;
constant DMACR_IRQDELAY_MSB_BIT : integer := 31;
-- DMASR
constant DMASR_HALTED_BIT : integer := 0;
constant DMASR_IDLE_BIT : integer := 1;
constant DMASR_CMPLT_BIT : integer := 2;
constant DMASR_ERROR_BIT : integer := 3;
constant DMASR_DMAINTERR_BIT : integer := 4;
constant DMASR_DMASLVERR_BIT : integer := 5;
constant DMASR_DMADECERR_BIT : integer := 6;
constant DMASR_RESERVED7_BIT : integer := 7;
constant DMASR_SGINTERR_BIT : integer := 8;
constant DMASR_SGSLVERR_BIT : integer := 9;
constant DMASR_SGDECERR_BIT : integer := 10;
constant DMASR_RESERVED11_BIT : integer := 11;
constant DMASR_IOCIRQ_BIT : integer := 12;
constant DMASR_DLYIRQ_BIT : integer := 13;
constant DMASR_ERRIRQ_BIT : integer := 14;
constant DMASR_RESERVED15_BIT : integer := 15;
constant DMASR_IRQTHRESH_LSB_BIT : integer := 16;
constant DMASR_IRQTHRESH_MSB_BIT : integer := 23;
constant DMASR_IRQDELAY_LSB_BIT : integer := 24;
constant DMASR_IRQDELAY_MSB_BIT : integer := 31;
-- CURDESC
constant CURDESC_LOWER_MSB_BIT : integer := 31;
constant CURDESC_LOWER_LSB_BIT : integer := 6;
constant CURDESC_RESERVED_BIT5 : integer := 5;
constant CURDESC_RESERVED_BIT4 : integer := 4;
constant CURDESC_RESERVED_BIT3 : integer := 3;
constant CURDESC_RESERVED_BIT2 : integer := 2;
constant CURDESC_RESERVED_BIT1 : integer := 1;
constant CURDESC_RESERVED_BIT0 : integer := 0;
-- TAILDESC
constant TAILDESC_LOWER_MSB_BIT : integer := 31;
constant TAILDESC_LOWER_LSB_BIT : integer := 6;
constant TAILDESC_RESERVED_BIT5 : integer := 5;
constant TAILDESC_RESERVED_BIT4 : integer := 4;
constant TAILDESC_RESERVED_BIT3 : integer := 3;
constant TAILDESC_RESERVED_BIT2 : integer := 2;
constant TAILDESC_RESERVED_BIT1 : integer := 1;
constant TAILDESC_RESERVED_BIT0 : integer := 0;
-- BTT
constant BTT_MSB_BIT : integer := 22;
-- DataMover Command / Status Constants
constant DATAMOVER_CMDDONE_BIT : integer := 7;
constant DATAMOVER_SLVERR_BIT : integer := 6;
constant DATAMOVER_DECERR_BIT : integer := 5;
constant DATAMOVER_INTERR_BIT : integer := 4;
constant DATAMOVER_TAGMSB_BIT : integer := 3;
constant DATAMOVER_TAGLSB_BIT : integer := 0;
-- Descriptor Control Bits
constant DESC_BLENGTH_LSB_BIT : integer := 0;
constant DESC_BLENGTH_MSB_BIT : integer := 22;
constant DESC_RSVD23_BIT : integer := 23;
constant DESC_RSVD24_BIT : integer := 24;
constant DESC_RSVD25_BIT : integer := 25;
constant DESC_EOF_BIT : integer := 26;
constant DESC_SOF_BIT : integer := 27;
constant DESC_RSVD28_BIT : integer := 28;
constant DESC_RSVD29_BIT : integer := 29;
constant DESC_RSVD30_BIT : integer := 30;
constant DESC_IOC_BIT : integer := 31;
-- Descriptor Status Bits
constant DESC_STS_CMPLTD_BIT : integer := 31;
constant DESC_STS_DECERR_BIT : integer := 30;
constant DESC_STS_SLVERR_BIT : integer := 29;
constant DESC_STS_INTERR_BIT : integer := 28;
constant DESC_STS_RXSOF_BIT : integer := 27;
constant DESC_STS_RXEOF_BIT : integer := 26;
constant DESC_STS_RSVD25_BIT : integer := 25;
constant DESC_STS_RSVD24_BIT : integer := 24;
constant DESC_STS_RSVD23_BIT : integer := 23;
constant DESC_STS_XFRDBYTS_MSB_BIT : integer := 22;
constant DESC_STS_XFRDBYTS_LSB_BIT : integer := 0;
-- DataMover Command / Status Constants
constant DATAMOVER_STS_CMDDONE_BIT : integer := 7;
constant DATAMOVER_STS_SLVERR_BIT : integer := 6;
constant DATAMOVER_STS_DECERR_BIT : integer := 5;
constant DATAMOVER_STS_INTERR_BIT : integer := 4;
constant DATAMOVER_STS_TAGMSB_BIT : integer := 3;
constant DATAMOVER_STS_TAGLSB_BIT : integer := 0;
constant DATAMOVER_STS_TAGEOF_BIT : integer := 1;
constant DATAMOVER_STS_TLAST_BIT : integer := 31;
constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0;
constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22;
constant DATAMOVER_CMD_TYPE_BIT : integer := 23;
constant DATAMOVER_CMD_DSALSB_BIT : integer := 24;
constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29;
constant DATAMOVER_CMD_EOF_BIT : integer := 30;
constant DATAMOVER_CMD_DRR_BIT : integer := 31;
constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32;
-- Note: Bit offset require adding ADDR WIDTH to get to actual bit index
constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31;
constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32;
constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35;
constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36;
constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39;
end axi_cdma_pkg;
-------------------------------------------------------------------------------
-- PACKAGE BODY
-------------------------------------------------------------------------------
package body axi_cdma_pkg is
-------------------------------------------------------------------------------
-- Function to determine minimum bits required for BTT_SIZE field
-------------------------------------------------------------------------------
function required_btt_width1 ( dwidth,
burst_size,
btt_width : integer)
return integer is
variable min_width : integer;
begin
min_width := clog2((dwidth/8)*burst_size)+1;
if(min_width > btt_width)then
return min_width;
else
return btt_width;
end if;
end function required_btt_width1;
end package body axi_cdma_pkg;
-------------------------------------------------------------------------------
-- axi_cdma_pulse_gen.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_pulse_gen.vhd
--
-- Description:
-- This file is the design for a parameterizable pulse width generator.
-- The input Sig_In is either Positive Edge or Negative detected
-- which triggers a pulse generator. Allowed pulse widths are 1 to
-- 64 input clock periods.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library axi_cdma_v4_1_14;
use axi_cdma_v4_1_14.axi_cdma_pkg.all;
------------------------------------------------------------------------------
entity axi_cdma_pulse_gen is
generic (
C_INCLUDE_SYNCHRO : Integer range 0 to 1 := 0;
-- 0 = Do not include synchronizer registers
-- 1 = Include synchronizer registers
C_POS_EDGE_TRIG : Integer range 0 to 1 := 1;
-- 0 = Negative Edge Triggered Pulse
-- 1 = Positive Edge Triggered Pulse
C_PULSE_WIDTH_CLKS : integer range 1 to 64 := 4
-- Desired Output Pulse width (in Clk_In periods)
);
port (
-- Input synchronization clock
Clk_In : In std_logic;
-- Module reset (active high)
Rst_In : In std_logic;
-- Input trigger signal
Sig_in : In std_logic;
-- Output pulse
Pulse_Out : Out std_logic
);
end entity axi_cdma_pulse_gen;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma_pulse_gen is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions Declarations
-------------------------------------------------------------------------------
-- none
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
Constant ADJUSTED_CLKs : integer := C_PULSE_WIDTH_CLKS+1;
-------------------------------------------------------------------------------
-- Internal Signal Declaration
-------------------------------------------------------------------------------
-- System module reset interconnect signals
signal sig_pulse_out : std_logic;
signal sig_to_edge_detect_reg : std_logic;
signal sig_pulse_trigger : std_logic;
signal sig_shift_reg : std_logic_vector(0 to ADJUSTED_CLKs-1);
-- Addition of synchronizer front-end
signal sig_synchro_reg1_cdc_tig : std_logic;
signal sig_synchro_reg2 : std_logic;
signal sig_to_edge_detect : std_logic;
-- ATTRIBUTE async_reg OF sig_synchro_reg1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_synchro_reg2 : SIGNAL IS "true";
-------------------------------------------------------------------------------
begin -- architecture body
-- Output Port assignments
Pulse_Out <= sig_pulse_out ;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_SYNCHRO_REGS
--
-- If Generate Description:
-- This IfGen omits the implementation of a double register
-- synchronizer on the input signal.
--
------------------------------------------------------------
OMIT_SYNCHRO_REGS : if (C_INCLUDE_SYNCHRO = 0) generate
begin
sig_to_edge_detect <= Sig_In;
end generate OMIT_SYNCHRO_REGS;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_SYNCHRO_REGS
--
-- If Generate Description:
-- This IfGen includes the implementation of a double
-- register synchronizer on the input signal.
--
------------------------------------------------------------
INCLUDE_SYNCHRO_REGS : if (C_INCLUDE_SYNCHRO = 1) generate
begin
sig_to_edge_detect <= sig_synchro_reg2;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_SYNCHRO_REGS
--
-- Process Description:
--
--
-------------------------------------------------------------
DO_SYNCHRO_REGS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Sig_In,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk_In,
scndry_resetn => '0',
scndry_out => sig_synchro_reg2,
scndry_vect_out => open
);
-- DO_SYNCHRO_REGS : process (Clk_In)
-- begin
-- if (Clk_In'event and Clk_In = '1') then
-- if (Rst_In = '1') then
-- sig_synchro_reg1_cdc_tig <= '0';
-- sig_synchro_reg2 <= '0';
-- else
-- sig_synchro_reg1_cdc_tig <= Sig_In;
-- sig_synchro_reg2 <= sig_synchro_reg1_cdc_tig;
-- end if;
-- end if;
-- end process DO_SYNCHRO_REGS;
end generate INCLUDE_SYNCHRO_REGS;
------------------------------------------------------------
-- If Generate
--
-- Label: POSITIVE_EDGE_TRIGGER
--
-- If Generate Description:
-- Generate Pulse trigger from Positive edge detection on
-- the input signal
--
--
------------------------------------------------------------
POSITIVE_EDGE_TRIGGER : if (C_POS_EDGE_TRIG = 1) generate
begin
-- Do positive edge detection on input signal, This becomes
-- the trigger for generating the output pulse.
sig_pulse_trigger <= sig_to_edge_detect and not(sig_to_edge_detect_reg);
end generate POSITIVE_EDGE_TRIGGER;
------------------------------------------------------------
-- If Generate
--
-- Label: NEGATIVE_EDGE_TRIGGER
--
-- If Generate Description:
-- Generate Pulse trigger from negative edge detection on
-- the input signal
--
--
------------------------------------------------------------
NEGATIVE_EDGE_TRIGGER : if (C_POS_EDGE_TRIG = 0) generate
begin
-- Do negative edge detection on input signal, This becomes
-- the trigger for generating the output pulse.
sig_pulse_trigger <= not(sig_to_edge_detect) and sig_to_edge_detect_reg;
end generate NEGATIVE_EDGE_TRIGGER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SIG_IN
--
-- Process Description:
-- This process registers the input signal for use in the
-- edge detection logic.
--
-------------------------------------------------------------
REG_SIG_IN : process (Clk_In)
begin
if (Clk_In'event and Clk_In = '1') then
if (Rst_In = '1') then
sig_to_edge_detect_reg <= '0';
else
sig_to_edge_detect_reg <= sig_to_edge_detect;
end if;
end if;
end process REG_SIG_IN;
------------------------------------------------------------
-- If Generate
--
-- Label: DO_SINGLE_CLK_PULSE
--
-- If Generate Description:
--
-- Handles single clock pulse width case
--
------------------------------------------------------------
DO_SINGLE_CLK_PULSE : if (C_PULSE_WIDTH_CLKS = 1) generate
begin
sig_shift_reg <= (others => '0'); -- house keeping
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SINGLE_PULSE
--
-- Process Description:
-- This process registers a single pulse case.
--
-------------------------------------------------------------
REG_SINGLE_PULSE : process (Clk_In)
begin
if (Clk_In'event and Clk_In = '1') then
if (Rst_In = '1') then
sig_pulse_out <= '0';
else
sig_pulse_out <= sig_pulse_trigger;
end if;
end if;
end process REG_SINGLE_PULSE;
end generate DO_SINGLE_CLK_PULSE;
------------------------------------------------------------
-- If Generate
--
-- Label: DO_MULTI_CLK_PULSE
--
-- If Generate Description:
--
-- Handles Multi clock pulse width case
--
------------------------------------------------------------
DO_MULTI_CLK_PULSE : if (C_PULSE_WIDTH_CLKS >= 2) generate
begin
-----------------------------------------------------------------------------
-- Implement the Shift register logic
-----------------------------------------------------------------------------
-- The output pulse is ripped from the final stage of the shift register
sig_pulse_out <= sig_shift_reg(ADJUSTED_CLKs-1);
-- Tie the shift register input stage to 0
sig_shift_reg(0) <= '0';
------------------------------------------------------------
-- For Generate
--
-- Label: DO_SHIF_REG
--
-- For Generate Description:
-- This For Gen implements a parameterizable shift
-- register for the pulse generator. The trigger presets
-- all of the register segments and then zeros are shifted
-- into the pipe until all stages are cleared. The resulting
-- pulse out is equal to the number of stages in the shift
-- register.
--
--
--
------------------------------------------------------------
DO_SHIF_REG : for reg_index in 1 to ADJUSTED_CLKs-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_SHIFT_REG_SEGMENT
--
-- Process Description:
-- This process implements a single register segment of
-- of the pulse generator shift register.
--
-------------------------------------------------------------
DO_SHIFT_REG_SEGMENT : process (Clk_In)
begin
if (Clk_In'event and Clk_In = '1') then
if (Rst_In = '1') then -- Clear the reg
sig_shift_reg(reg_index) <= '0';
elsif (sig_pulse_trigger = '1') then -- preset the reg
sig_shift_reg(reg_index) <= '1';
else -- shift stuff through
sig_shift_reg(reg_index) <= sig_shift_reg(reg_index-1);
end if;
end if;
end process DO_SHIFT_REG_SEGMENT;
end generate DO_SHIF_REG;
-----------------------------------------------------------------------------
-- End of Shift register logic
-----------------------------------------------------------------------------
end generate DO_MULTI_CLK_PULSE;
end architecture implementation;
-------------------------------------------------------------------------------
-- axi_cdma_reset
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_reset.vhd
-- Description: This entity is reset module entity for the AXI DMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_cdma_v4_1_14;
use axi_cdma_v4_1_14.axi_cdma_pulse_gen;
use axi_cdma_v4_1_14.axi_cdma_pkg.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
entity axi_cdma_reset is
Generic (
C_AXI_LITE_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the AXI Lite Register interface needs to
-- be asynchronous to the CDMA data transport path clocking
-- 0 = Use same clocking as data path (Primary)
-- 1 = Use special AXI Lite clock for the axi lite interface
C_SOFT_RST_TIME_CLKS : integer range 1 to 64 := 8
-- Specifies the time of the soft reset assertion in
-- axi_aclk clock periods.
);
port (
-- Primary Clock and Reset Sources
axi_aclk : in std_logic ;--
axi_resetn : in std_logic ;--
-- AXI Lite Clock and Reset Sources
axi_lite_aclk : in std_logic ;--
axi_lite_resetn : in std_logic ;--
-- HW Reset out to the axi4-lite bus side interface logic
rst2lite_bside_reset : Out std_logic ;
-- HW Reset out to the axi4-lite core side interface logic
rst2lite_cside_reset : Out std_logic ;
-- HW Reset out to the register module logic
rst2reg_reset : Out std_logic ;
-- HW Reset out to the simple controller module logic
rst2cntlr_reset : Out std_logic ;
-- HW Reset out to the SG controller module logic
rst2sgcntlr_reset : Out std_logic ;
-- HW Reset out to the SG module
rst2sg_resetn : Out std_logic ;
-- HW Reset out to the datamover module
rst2dm_resetn : Out std_logic ;
-- Soft Reset Request from Register module
reg2rst_soft_reset_in : in std_logic ;
-- Soft Reset clear to the Register module
rst2reg_soft_reset_clr : Out std_logic ;
-- Halt request to the Simple Controller
rst2cntlr_halt : Out std_logic ;
-- Halt complete from the Simple Controller
cntlr2rst_halt_cmplt : in std_logic ;
-- Halt request to the SG Controller
rst2sg_halt : Out std_logic ;
-- Halt complete from the SG Controller
sg2rst_halt_cmplt : in std_logic ;
-- Halt request to the DataMover MM2S function
rst2dm_mm2s_halt : Out std_logic ;
-- Halt complete from the DataMover MM2S function
dm2rst_mm2s_halt_cmplt : in std_logic ;
-- Halt request to the DataMover S2MM function
rst2dm_s2mm_halt : Out std_logic ;
-- Halt complete from the DataMover S2MM function
dm2rst_s2mm_halt_cmplt : in std_logic
);
end axi_cdma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant INCLUDE_SYNCHRONIZERS : integer := 1 ;
Constant NO_SYNCHRONIZERS : integer := 0 ;
Constant POSITIVE_EDGE_TRIGGER : integer := 1 ;
Constant NEGATIVE_EDGE_TRIGGER : integer := 0 ;
Constant TWO_CLKS : integer := 2 ;
Constant ONE_CLK : integer := 1 ;
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant POR_WIDTH : integer := 8 ;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sig_local_hw_reset_reg : std_logic := '0';
signal sig_lite_bside_hw_reset_reg : std_logic := '0';
signal sig_lite_cside_hw_reset_reg : std_logic := '0';
signal sig_composite_reg_reset : std_logic := '0';
signal sig_composite_cntlr_reset : std_logic := '0';
signal sig_composite_sgcntlr_reset : std_logic := '0';
signal sig_composite_sg_reset_n : std_logic := '0';
signal sig_composite_dm_reset_n : std_logic := '0';
signal sig_dm_soft_reset_n : std_logic := '0';
signal sig_rst2reg_soft_reset : std_logic := '0';
signal sig_rst2reg_soft_reset_trig : std_logic := '0';
signal sig_rst2reg_soft_reset_clr : std_logic := '0';
signal sig_soft_reset : std_logic := '0';
signal sig_soft_reset_reg : std_logic := '0';
signal sig_trig_soft_reset : std_logic := '0';
signal sig_halt_request : std_logic := '0';
signal sig_halt_cmplt : std_logic := '0';
signal sig_axi_por_reg1 : std_logic := '0';
signal sig_axi_por_reg2 : std_logic := '0';
signal sig_axi_por_reg3 : std_logic := '0';
signal sig_axi_por_reg4 : std_logic := '0';
signal sig_axi_por_reg5 : std_logic := '0';
signal sig_axi_por_reg6 : std_logic := '0';
signal sig_axi_por_reg7 : std_logic := '0';
signal sig_axi_por_reg8 : std_logic := '0';
signal sig_axi_por2rst : std_logic := '0';
signal sig_axi_por2rst_out : std_logic := '0';
signal sig_axilite_por_reg1 : std_logic := '0';
signal sig_axilite_por_reg2 : std_logic := '0';
signal sig_axilite_por_reg3 : std_logic := '0';
signal sig_axilite_por_reg4 : std_logic := '0';
signal sig_axilite_por_reg5 : std_logic := '0';
signal sig_axilite_por_reg6 : std_logic := '0';
signal sig_axilite_por_reg7 : std_logic := '0';
signal sig_axilite_por_reg8 : std_logic := '0';
signal sig_axilite_por2rst : std_logic := '0';
signal sig_axilite_por2rst_out : std_logic := '0';
-- Register duplication attribute assignments to control fanout
-- on reset signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_lite_bside_hw_reset_reg : signal is "TRUE";
Attribute KEEP of sig_lite_cside_hw_reset_reg : signal is "TRUE";
Attribute KEEP of sig_composite_reg_reset : signal is "TRUE";
Attribute KEEP of sig_composite_cntlr_reset : signal is "TRUE";
Attribute KEEP of sig_composite_sgcntlr_reset : signal is "TRUE";
Attribute KEEP of sig_composite_sg_reset_n : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_lite_bside_hw_reset_reg : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_lite_cside_hw_reset_reg : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_composite_reg_reset : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_composite_cntlr_reset : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_composite_sgcntlr_reset : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_composite_sg_reset_n : signal is "no";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Assign Reset Output Ports
rst2lite_bside_reset <= sig_lite_bside_hw_reset_reg ;
rst2lite_cside_reset <= sig_lite_cside_hw_reset_reg ;
rst2reg_reset <= sig_composite_reg_reset ;
rst2cntlr_reset <= sig_composite_cntlr_reset ;
rst2sgcntlr_reset <= sig_composite_sgcntlr_reset ;
rst2sg_resetn <= sig_composite_sg_reset_n ;
rst2dm_resetn <= sig_composite_dm_reset_n ;
-- Assign the soft Reset Request and Clear Ports
sig_rst2reg_soft_reset <= reg2rst_soft_reset_in ;
rst2reg_soft_reset_clr <= sig_rst2reg_soft_reset_clr ;
-- Assign the Halt and Halt Cmplt Ports
rst2cntlr_halt <= sig_halt_request;
rst2sg_halt <= sig_halt_request;
rst2dm_mm2s_halt <= sig_halt_request;
rst2dm_s2mm_halt <= sig_halt_request;
------------------------------------------------------------
-- Start Power On Reset (POR) Logic
------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: AXI_POR_REG1
--
-- Process Description:
-- This process generates an 4-clock wide pulse that
-- only occurs immediately after FPGA initialization. This
-- pulse is used to initialize reset logic synchronous to
-- the Main axi_aclk Clock until the Bus Reset occurs.
--
-------------------------------------------------------------
AXI_POR_REG1 : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
sig_axi_por_reg1 <= '1';
sig_axi_por_reg2 <= sig_axi_por_reg1;
sig_axi_por_reg3 <= sig_axi_por_reg2;
sig_axi_por_reg4 <= sig_axi_por_reg3;
sig_axi_por_reg5 <= sig_axi_por_reg4;
sig_axi_por_reg6 <= sig_axi_por_reg5;
sig_axi_por_reg7 <= sig_axi_por_reg6;
sig_axi_por_reg8 <= sig_axi_por_reg7;
sig_axi_por2rst_out <= sig_axi_por2rst ;
end if;
end process AXI_POR_REG1;
sig_axi_por2rst <= not(sig_axi_por_reg1 and
sig_axi_por_reg2 and
sig_axi_por_reg3 and
sig_axi_por_reg4 and
sig_axi_por_reg5 and
sig_axi_por_reg6 and
sig_axi_por_reg7 and
sig_axi_por_reg8 );
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: AXILITE_POR_REG1
--
-- Process Description:
-- This process generates an 8-clock wide pulse that
-- only occurs immediately after FPGA initialization. This
-- pulse is used to initialize reset logic synchronous to
-- the axi_lite_aclk Clock until the Bus Reset occurs.
--
-------------------------------------------------------------
AXILITE_POR_REG1 : process (axi_lite_aclk)
begin
if (axi_lite_aclk'event and axi_lite_aclk = '1') then
sig_axilite_por_reg1 <= '1';
sig_axilite_por_reg2 <= sig_axilite_por_reg1;
sig_axilite_por_reg3 <= sig_axilite_por_reg2;
sig_axilite_por_reg4 <= sig_axilite_por_reg3;
sig_axilite_por_reg5 <= sig_axilite_por_reg4;
sig_axilite_por_reg6 <= sig_axilite_por_reg5;
sig_axilite_por_reg7 <= sig_axilite_por_reg6;
sig_axilite_por_reg8 <= sig_axilite_por_reg7;
sig_axilite_por2rst_out <= sig_axilite_por2rst ;
end if;
end process AXILITE_POR_REG1;
sig_axilite_por2rst <= not(sig_axilite_por_reg1 and
sig_axilite_por_reg2 and
sig_axilite_por_reg3 and
sig_axilite_por_reg4 and
sig_axilite_por_reg5 and
sig_axilite_por_reg6 and
sig_axilite_por_reg7 and
sig_axilite_por_reg8);
------------------------------------------------------------
-- End of Power On Reset (POR) Logic
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Reset Logic Distribution
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_AXI_LITE_SYNC2AXI
--
-- If Generate Description:
-- Generate resets based on AXI Lite clock being the same
-- as the main axi4 clock (synchronous).
--
--
------------------------------------------------------------
GEN_AXI_LITE_SYNC2AXI : if (C_AXI_LITE_IS_ASYNC = 0) generate
begin
sig_composite_dm_reset_n <= axi_resetn and axi_lite_resetn and sig_dm_soft_reset_n;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SYNC_SOFT_RST_FLOP
--
-- Process Description:
-- FLOP for registering the input axi_resetn (inverted).
--
-------------------------------------------------------------
IMP_SYNC_SOFT_RST_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
If (sig_axi_por2rst_out = '1') Then
sig_local_hw_reset_reg <= '1';
sig_composite_reg_reset <= '1';
sig_composite_cntlr_reset <= '1';
sig_composite_sgcntlr_reset <= '1';
sig_composite_sg_reset_n <= '0';
sig_dm_soft_reset_n <= '0';
else
sig_local_hw_reset_reg <= not(axi_resetn) or not(axi_lite_resetn);
sig_composite_reg_reset <= not(axi_resetn) or not(axi_lite_resetn) or sig_soft_reset;
sig_composite_cntlr_reset <= not(axi_resetn) or not(axi_lite_resetn) or sig_soft_reset;
sig_composite_sgcntlr_reset <= not(axi_resetn) or not(axi_lite_resetn) or sig_soft_reset;
sig_composite_sg_reset_n <= axi_resetn and axi_lite_resetn and not(sig_soft_reset);
sig_dm_soft_reset_n <= not(sig_soft_reset);
End if;
end if;
end process IMP_SYNC_SOFT_RST_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SYNC_AXI_LITE_HW_RST_FLOP
--
-- Process Description:
-- FLOP for registering the reset for the AXi Lite Interface.
-- Since the axi_lite_aclk is the same as the axi_aclk,
-- the Bus side and Core side resets can be the same.
-- Note that soft reset is excluded from the AXI Lite reset
-- generation logic.
--
-------------------------------------------------------------
IMP_SYNC_AXI_LITE_HW_RST_FLOP : process (axi_lite_aclk)
begin
if (axi_lite_aclk'event and axi_lite_aclk = '1') then
if (sig_axilite_por2rst = '1') then
sig_lite_bside_hw_reset_reg <= '1';
sig_lite_cside_hw_reset_reg <= '1';
else
sig_lite_bside_hw_reset_reg <= not(axi_lite_resetn) or
not(axi_resetn);
sig_lite_cside_hw_reset_reg <= not(axi_lite_resetn) or
not(axi_resetn);
end if;
end if;
end process IMP_SYNC_AXI_LITE_HW_RST_FLOP;
end generate GEN_AXI_LITE_SYNC2AXI;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_AXI_LITE_ASYNC2AXI
--
-- If Generate Description:
-- Generate resets based on AXI Lite clock being different
-- from the main axi4 clock (asynchronous).
--
--
------------------------------------------------------------
GEN_AXI_LITE_ASYNC2AXI : if (C_AXI_LITE_IS_ASYNC = 1) generate
ATTRIBUTE async_reg : STRING;
signal sig_axi_lite_rst_rsync_min_pulse : std_logic := '0';
signal sig_axi_lite_rst_reg : std_logic := '0';
signal sig_axi_lite_rst_rsync : std_logic := '0';
signal sig_axi_lite_rst_rsync_d1_cdc_tig : std_logic := '0';
signal sig_axi_lite_rst_rsync_d2 : std_logic := '0';
signal sig_axi_rst_rsync_min_pulse : std_logic := '0';
signal sig_axi_rst_reg : std_logic := '0';
signal sig_axi_rst_rsync : std_logic := '0';
signal sig_axi_rst_rsync_d1_cdc_tig : std_logic := '0';
signal sig_axi_rst_rsync_d2 : std_logic := '0';
signal sig_cside2bside_rsync_d1_cdc_tig : std_logic := '0';
signal sig_cside2bside_rsync_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF sig_axi_lite_rst_rsync_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF sig_axi_lite_rst_rsync_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF sig_axi_rst_rsync_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF sig_axi_rst_rsync_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF sig_cside2bside_rsync_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF sig_cside2bside_rsync_d2 : SIGNAL IS "true";
begin
----------------------------------------------------------------
-- AXI Lite RESET to AXI Clock synchronizers
----------------------------------------------------------------
-- Assign a composite reset derived from the AXI Lite Resetn
-- that consistes of a minimum pulse width reset or the resync'd
-- AXI Lite Reset, whichever is asserted longer.
sig_axi_lite_rst_rsync <= sig_axi_lite_rst_rsync_d2 or
sig_axi_lite_rst_rsync_min_pulse;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LITE2AXI_RSYNC
--
-- Process Description:
-- First stage Synchronizer for the AXI_LITE RESETN to AXI
-- clock domain.
--
-------------------------------------------------------------
IMP_LITE2AXI_RSYNC : process (axi_lite_aclk)
begin
if (axi_lite_aclk'event and axi_lite_aclk = '1') then
if (sig_axilite_por2rst = '1') then
sig_axi_lite_rst_reg <= '1';
else
sig_axi_lite_rst_reg <= not(axi_lite_resetn);
end if;
end if;
end process IMP_LITE2AXI_RSYNC;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ALITE_RST_RESYNC
--
-- Process Description:
-- Second stage synchronizers for the axi lite resetn to
-- AXi clock domain.
--
-------------------------------------------------------------
IMP_ALITE_RST_RESYNC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_axi_lite_rst_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_aclk,
scndry_resetn => '0',
scndry_out => sig_axi_lite_rst_rsync_d2,
scndry_vect_out => open
);
-- IMP_ALITE_RST_RESYNC : process (axi_aclk)
-- begin
-- if (axi_aclk'event and axi_aclk = '1') then
-- if (sig_axi_por2rst = '1') then
--
-- sig_axi_lite_rst_rsync_d1_cdc_tig <= '1';
-- sig_axi_lite_rst_rsync_d2 <= '1';
--
-- else
--
-- sig_axi_lite_rst_rsync_d1_cdc_tig <= sig_axi_lite_rst_reg;
-- sig_axi_lite_rst_rsync_d2 <= sig_axi_lite_rst_rsync_d1_cdc_tig;
--
-- end if;
-- end if;
-- end process IMP_ALITE_RST_RESYNC;
----------------------------------------------------------------
-- AXI RESET to AXI Lite Clock synchronizers
----------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_AXI_RST_REG
--
-- Process Description:
-- First stage register for synchronizer for AXI_RESETN to
-- AXI Lite Clock Domain.
--
-------------------------------------------------------------
IMP_AXI_RST_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_axi_por2rst = '1') then
sig_axi_rst_reg <= '1';
else
sig_axi_rst_reg <= not(axi_resetn);
end if;
end if;
end process IMP_AXI_RST_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_AXI2LITE_RSYNC
--
-- Process Description:
-- Second stage Synchronizers for the AXI_RESETN to AXI
-- Lite clock domain.
--
-------------------------------------------------------------
IMP_AXI2LITE_RSYNC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_axi_rst_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_lite_aclk,
scndry_resetn => '0',
scndry_out => sig_axi_rst_rsync_d2,
scndry_vect_out => open
);
-- IMP_AXI2LITE_RSYNC : process (axi_lite_aclk)
-- begin
-- if (axi_lite_aclk'event and axi_lite_aclk = '1') then
-- if (sig_axilite_por2rst = '1') then
--
-- sig_axi_rst_rsync_d1_cdc_tig <= '1';
-- sig_axi_rst_rsync_d2 <= '1';
--
-- else
--
-- sig_axi_rst_rsync_d1_cdc_tig <= sig_axi_rst_reg;
-- sig_axi_rst_rsync_d2 <= sig_axi_rst_rsync_d1_cdc_tig;
--
-- end if;
--
-- end if;
-- end process IMP_AXI2LITE_RSYNC;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_AXI_LITE_DELAY
--
-- Process Description:
-- Special Synchronizers for ensuring the Bus side always
-- comes out of reset after the C_side does.
--
-------------------------------------------------------------
IMP_AXI_LITE_DELAY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_lite_cside_hw_reset_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_lite_aclk,
scndry_resetn => '0',
scndry_out => sig_cside2bside_rsync_d2,
scndry_vect_out => open
);
-- IMP_AXI_LITE_DELAY : process (axi_lite_aclk)
-- begin
-- if (axi_lite_aclk'event and axi_lite_aclk = '1') then
-- if (sig_axilite_por2rst = '1') then
--
-- sig_cside2bside_rsync_d1_cdc_tig <= '1';
-- sig_cside2bside_rsync_d2 <= '1';
--
-- else
--
-- sig_cside2bside_rsync_d1_cdc_tig <= sig_lite_cside_hw_reset_reg;
-- sig_cside2bside_rsync_d2 <= sig_cside2bside_rsync_d1_cdc_tig;
--
-- end if;
--
-- end if;
-- end process IMP_AXI_LITE_DELAY;
sig_axi_rst_rsync <= sig_axi_rst_rsync_d2 or
sig_cside2bside_rsync_d2;
------------------------------------------------------------
-- Instance: I_AXI_LITE_RST_RSYNC
--
-- Description:
-- This PulsGen synchronizes the AXI Lite Reset to the Main
-- AXI Clock and assures a minimum reset pulse width.
--
------------------------------------------------------------
I_AXI_LITE_RST_RSYNC : entity axi_cdma_v4_1_14.axi_cdma_pulse_gen
generic map (
C_INCLUDE_SYNCHRO => INCLUDE_SYNCHRONIZERS ,
C_POS_EDGE_TRIG => NEGATIVE_EDGE_TRIGGER ,
C_PULSE_WIDTH_CLKS => C_SOFT_RST_TIME_CLKS
)
port map (
Clk_In => axi_aclk ,
--Rst_In => LOGIC_LOW ,
Rst_In => sig_axi_por2rst ,
Sig_in => axi_lite_resetn ,
--Pulse_Out => sig_axi_lite_rst_rsync
Pulse_Out => sig_axi_lite_rst_rsync_min_pulse
);
------------------------------------------------------------
-- Instance: I_AXI_RST_RSYNC
--
-- Description:
-- This PulsGen synchronizes the AXI Reset to the AXI Lite
-- Clock
--
------------------------------------------------------------
I_AXI_RST_RSYNC : entity axi_cdma_v4_1_14.axi_cdma_pulse_gen
generic map (
C_INCLUDE_SYNCHRO => INCLUDE_SYNCHRONIZERS ,
C_POS_EDGE_TRIG => NEGATIVE_EDGE_TRIGGER ,
C_PULSE_WIDTH_CLKS => C_SOFT_RST_TIME_CLKS
)
port map (
Clk_In => axi_lite_aclk ,
-- Rst_In => LOGIC_LOW ,
Rst_In => sig_axilite_por2rst ,
Sig_in => axi_resetn ,
Pulse_Out => sig_axi_rst_rsync_min_pulse
);
sig_composite_dm_reset_n <= axi_resetn and
not(sig_axi_lite_rst_rsync) and
sig_dm_soft_reset_n;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ASYNC_SOFT_RST_FLOP
--
-- Process Description:
-- FLOP for registering the input axi_resetn (inverted).
--
-------------------------------------------------------------
IMP_ASYNC_SOFT_RST_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_axi_por2rst = '1') then
sig_local_hw_reset_reg <= '1';
sig_composite_reg_reset <= '1';
sig_composite_cntlr_reset <= '1';
sig_composite_sgcntlr_reset <= '1';
sig_composite_sg_reset_n <= '0';
sig_dm_soft_reset_n <= '0';
else
sig_local_hw_reset_reg <= not(axi_resetn) or
--not(sig_axi_lite_rst_rsync);
sig_axi_lite_rst_rsync;
sig_composite_reg_reset <= not(axi_resetn) or
sig_axi_lite_rst_rsync or
sig_soft_reset;
sig_composite_cntlr_reset <= not(axi_resetn) or
sig_axi_lite_rst_rsync or
sig_soft_reset;
sig_composite_sgcntlr_reset <= not(axi_resetn) or
sig_axi_lite_rst_rsync or
sig_soft_reset;
sig_composite_sg_reset_n <= axi_resetn and
not(sig_axi_lite_rst_rsync) and
not(sig_soft_reset);
sig_dm_soft_reset_n <= not(sig_soft_reset);
end if;
end if;
end process IMP_ASYNC_SOFT_RST_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ASYNC_ALITE_BSIDE_RST
--
-- Process Description:
-- FLOP for registering the reset for the AXi Lite
-- Bus side Interface.
-- Note that soft reset is excluded from the AXI Lite reset
-- generation logic.
--
-------------------------------------------------------------
IMP_ASYNC_ALITE_BSIDE_RST : process (axi_lite_aclk)
begin
if (axi_lite_aclk'event and axi_lite_aclk = '1') then
if (sig_axilite_por2rst = '1') then
sig_lite_bside_hw_reset_reg <= '1';
else
sig_lite_bside_hw_reset_reg <= not(axi_lite_resetn) or
sig_axi_rst_rsync_min_pulse or
sig_axi_rst_rsync;
end if;
end if;
end process IMP_ASYNC_ALITE_BSIDE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ASYNC_ALITE_CSIDE_RST
--
-- Process Description:
-- FLOP for registering the reset for the AXi Lite
-- Core side Interface.
-- Note that soft reset is excluded from the AXI Lite reset
-- generation logic.
--
-- Note that the Core side of the AXI Lite interface is
-- clocked with axi_aclk which is async to axi_lite_aclk in
-- this IfGen case.
--
-------------------------------------------------------------
IMP_ASYNC_ALITE_CSIDE_RST : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
If (sig_axi_por2rst_out = '1') Then
sig_lite_cside_hw_reset_reg <= '1';
else
sig_lite_cside_hw_reset_reg <= not(axi_resetn) or
sig_axi_lite_rst_rsync;
End if;
end if;
end process IMP_ASYNC_ALITE_CSIDE_RST;
end generate GEN_AXI_LITE_ASYNC2AXI;
-------------------------------------------------------------------------------
-- Pulse Generator Logic for Soft Reset
-------------------------------------------------------------------------------
sig_trig_soft_reset <= sig_halt_cmplt;
------------------------------------------------------------
-- Instance: I_SOFT_RST_PULSEGEN
--
-- Description:
-- Generates a active high pulse for the specified number
-- of clock periods
--
------------------------------------------------------------
I_SOFT_RST_PULSEGEN : entity axi_cdma_v4_1_14.axi_cdma_pulse_gen
generic map (
C_INCLUDE_SYNCHRO => NO_SYNCHRONIZERS ,
C_POS_EDGE_TRIG => POSITIVE_EDGE_TRIGGER ,
C_PULSE_WIDTH_CLKS => C_SOFT_RST_TIME_CLKS
)
port map (
Clk_In => axi_aclk ,
Rst_In => sig_local_hw_reset_reg ,
Sig_in => sig_trig_soft_reset ,
Pulse_Out => sig_soft_reset
);
------------------------------------------------------------
-- Instance: I_SOFT_RST_CLR_PULSE
--
-- Description:
-- Generates a active high pulse for 2 clocks when soft reset
-- is deasserted.
--
------------------------------------------------------------
I_SOFT_RST_CLR_PULSE : entity axi_cdma_v4_1_14.axi_cdma_pulse_gen
generic map (
C_INCLUDE_SYNCHRO => NO_SYNCHRONIZERS ,
C_POS_EDGE_TRIG => NEGATIVE_EDGE_TRIGGER ,
C_PULSE_WIDTH_CLKS => TWO_CLKS
)
port map (
Clk_In => axi_aclk ,
Rst_In => sig_local_hw_reset_reg ,
Sig_in => sig_soft_reset ,
Pulse_Out => sig_rst2reg_soft_reset_clr
);
-------------------------------------------------------------------------------
-- Halt Request and Complete Logic
-------------------------------------------------------------------------------
------------------------------------------------------------
-- Instance: I_SOFT_RST_POS_EDGE_DTCT
--
-- Description:
-- Generates a active high pulse for 1 clocks when soft reset
-- request from the register module is asserted.
--
------------------------------------------------------------
I_SOFT_RST_POS_EDGE_DTCT : entity axi_cdma_v4_1_14.axi_cdma_pulse_gen
generic map (
C_INCLUDE_SYNCHRO => NO_SYNCHRONIZERS ,
C_POS_EDGE_TRIG => POSITIVE_EDGE_TRIGGER ,
C_PULSE_WIDTH_CLKS => ONE_CLK
)
port map (
Clk_In => axi_aclk ,
Rst_In => sig_local_hw_reset_reg ,
Sig_in => sig_rst2reg_soft_reset ,
Pulse_Out => sig_rst2reg_soft_reset_trig
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_FLOP
--
-- Process Description:
-- Implements the flop for the Halt Request that is a
-- precurser to a soft reset.
--
-------------------------------------------------------------
IMP_HALT_REQ_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_local_hw_reset_reg = '1' or
sig_soft_reset = '1') then
sig_halt_request <= '0';
elsif (sig_rst2reg_soft_reset_trig = '1') then
sig_halt_request <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_HALT_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_CMPLT_FLOP
--
-- Process Description:
-- Implements the flop for the Halt Completion from all
-- modules.
--
-------------------------------------------------------------
IMP_HALT_CMPLT_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (sig_local_hw_reset_reg = '1' or
sig_soft_reset = '1' or
sig_halt_request = '0') then
sig_halt_cmplt <= '0';
else
sig_halt_cmplt <= cntlr2rst_halt_cmplt and
sg2rst_halt_cmplt and
dm2rst_mm2s_halt_cmplt and
dm2rst_s2mm_halt_cmplt;
end if;
end if;
end process IMP_HALT_CMPLT_FLOP;
end implementation;
-------------------------------------------------------------------------------
-- axi_cdma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_lite_if.vhd
-- Description: This entity is AXI Lite Interface Module for the AXI DMA
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_cdma_v4_1_14;
use axi_cdma_v4_1_14.axi_cdma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
entity axi_cdma_lite_if is
generic(
C_NUM_CE : integer := 8 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32
);
port (
-- Async clock input
ip2axi_aclk : in std_logic ; --
ip2axi_aresetn : in std_logic ; --
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ; --
s_axi_lite_aresetn : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
-- User IP Interface --
axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
axi2ip_rdce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) --
);
end axi_cdma_lite_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Register I/F Address offset
constant ADDR_OFFSET : integer := clog2(C_S_AXI_LITE_DATA_WIDTH/8);
-- Register I/F CE number
constant CE_ADDR_SIZE : integer := clog2(C_NUM_CE);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- AXI Lite slave interface signals
signal awvalid : std_logic := '0';
signal awaddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal wvalid : std_logic := '0';
signal wdata : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal arvalid : std_logic := '0';
signal araddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awvalid_d1 : std_logic := '0';
signal awvalid_re : std_logic := '0';
signal awready_i : std_logic := '0';
signal wvalid_d1 : std_logic := '0';
signal wvalid_re : std_logic := '0';
signal wready_i : std_logic := '0';
signal bvalid_i : std_logic := '0';
signal wr_addr_cap : std_logic := '0';
signal wr_data_cap : std_logic := '0';
-- AXI to IP interface signals
signal axi2ip_wraddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wren : std_logic := '0';
signal wrce : std_logic_vector(C_NUM_CE-1 downto 0);
signal rdce : std_logic_vector(C_NUM_CE-1 downto 0) := (others => '0');
signal arvalid_d1 : std_logic := '0';
signal arvalid_re : std_logic := '0';
signal arvalid_re_d1 : std_logic := '0';
signal arvalid_i : std_logic := '0';
signal arready_i : std_logic := '0';
signal rvalid : std_logic := '0';
signal axi2ip_rdaddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axi_lite_rvalid_i : std_logic := '0';
signal read_in_progress : std_logic := '0'; -- CR607165
signal rst_rvalid_re : std_logic := '0'; -- CR576999
signal rst_wvalid_re : std_logic := '0'; -- CR576999
signal rdy : std_logic := '0';
signal rdy1 : std_logic := '0';
signal wr_in_progress : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
s_axi_lite_wready <= wready_i;
s_axi_lite_awready <= awready_i;
s_axi_lite_arready <= arready_i;
s_axi_lite_bvalid <= bvalid_i;
-------------------------------------------------------------------------------
-- Register AXI Inputs
-------------------------------------------------------------------------------
REG_INPUTS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awvalid <= '0' ;
awaddr <= (others => '0') ;
wvalid <= '0' ;
wdata <= (others => '0') ;
arvalid <= '0' ;
araddr <= (others => '0') ;
else
awvalid <= s_axi_lite_awvalid ;
awaddr <= s_axi_lite_awaddr ;
wvalid <= s_axi_lite_wvalid ;
wdata <= s_axi_lite_wdata ;
arvalid <= s_axi_lite_arvalid ;
araddr <= s_axi_lite_araddr ;
end if;
end if;
end process REG_INPUTS;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
-------------------------------------------------------------------------------
-- Assert Write Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
-- awvalid_re <= '0'; -- CR605883
else
awvalid_d1 <= awvalid;
-- awvalid_re <= awvalid and not awvalid_d1; -- CR605883
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
-- wvalid_re <= '0';
else
wvalid_d1 <= wvalid;
-- wvalid_re <= wvalid and not wvalid_d1; -- CR605883
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
WRITE_IN_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wr_in_progress <= '0';
elsif(awvalid_re = '1')then
wr_in_progress <= '1';
end if;
end if;
end process WRITE_IN_PROGRESS;
-- CR605883 (CDC) provide pure register output to synchronizers
--wvalid_re <= wvalid and not wvalid_d1 and not rst_wvalid_re;
-------------------------------------------------------------------------------
-- Capture assertion of wvalid to indicate that we have captured
-- valid data
-------------------------------------------------------------------------------
WRDATA_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_data_cap <= '0';
elsif(wvalid_re = '1')then
wr_data_cap <= '1';
end if;
end if;
end process WRDATA_CAP_FLAG;
REG_WREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1') then
rdy <= '0';
elsif (wr_data_cap = '1' and wr_addr_cap = '1') then
rdy <= '1';
end if;
wready_i <= rdy;
awready_i <= rdy;
rdy1 <= rdy;
end if;
end process REG_WREADY;
WRADDR_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_addr_cap <= '0';
elsif(awvalid_re = '1')then
wr_addr_cap <= '1';
end if;
end if;
end process WRADDR_CAP_FLAG;
-------------------------------------------------------------------------------
-- Capture Write Address
-------------------------------------------------------------------------------
REG_WRITE_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
-- axi2ip_wraddr_i <= (others => '0');
-- Register address on valid
elsif(awvalid_re = '1')then
-- axi2ip_wraddr_i <= awaddr;
end if;
end if;
end process REG_WRITE_ADDRESS;
-------------------------------------------------------------------------------
-- Capture Write Data
-------------------------------------------------------------------------------
REG_WRITE_DATA : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrdata_i <= (others => '0');
-- Register address and assert ready
elsif(wvalid_re = '1')then
axi2ip_wrdata_i <= wdata;
end if;
end if;
end process REG_WRITE_DATA;
-------------------------------------------------------------------------------
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
-- axi2ip_wren <= '1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
axi2ip_wren <= rdy; -- or rdy1;
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when s_axi_lite_awaddr
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrce <= (others => '0');
-- axi2ip_wrdata <= (others => '0');
else
axi2ip_wrce <= wrce;
-- axi2ip_wrdata <= axi2ip_wrdata_i;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= s_axi_lite_wdata;
-------------------------------------------------------------------------------
-- Write Response
-------------------------------------------------------------------------------
s_axi_lite_bresp <= OKAY_RESP;
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy1 = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
end generate GEN_SYNC_WRITE;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 1 generate
-- Data support
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
signal ip_wvalid_d1_cdc_to : std_logic := '0';
signal ip_wvalid_d2 : std_logic := '0';
signal ip_wvalid_re : std_logic := '0';
signal wr_wvalid_re_cdc_from : std_logic := '0';
signal wr_data_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal wdata_d1_cdc_to : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal wdata_d2 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_cdc_tig : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal ip_data_cap : std_logic := '0';
-- Address support
signal ip_awvalid_d1_cdc_to : std_logic := '0';
signal ip_awvalid_d2 : std_logic := '0';
signal ip_awvalid_re : std_logic := '0';
signal wr_awvalid_re_cdc_from : std_logic := '0';
signal wr_addr_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal awaddr_d1_cdc_tig : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awaddr_d2 : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip_addr_cap : std_logic := '0';
-- Bvalid support
signal lite_data_cap_d1 : std_logic := '0';
signal lite_data_cap_d2 : std_logic := '0';
signal lite_addr_cap_d1 : std_logic := '0';
signal lite_addr_cap_d2 : std_logic := '0';
signal lite_axi2ip_wren : std_logic := '0';
signal awvalid_cdc_from : std_logic := '0';
signal awvalid_cdc_to : std_logic := '0';
signal awvalid_to : std_logic := '0';
signal awvalid_to2 : std_logic := '0';
-- ATTRIBUTE async_reg OF awvalid_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF awvalid_to : SIGNAL IS "true";
signal wvalid_cdc_from : std_logic := '0';
signal wvalid_cdc_to : std_logic := '0';
signal wvalid_to : std_logic := '0';
signal wvalid_to2 : std_logic := '0';
-- ATTRIBUTE async_reg OF wvalid_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF wvalid_to : SIGNAL IS "true";
signal rdy_cdc_to : std_logic := '0';
signal rdy_cdc_from : std_logic := '0';
signal rdy_to : std_logic := '0';
signal rdy_to2 : std_logic := '0';
signal rdy_to2_cdc_from : std_logic := '0';
signal rdy_out : std_logic := '0';
-- ATTRIBUTE async_reg OF rdy_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF rdy_to : SIGNAL IS "true";
Attribute KEEP of rdy_to2_cdc_from : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of rdy_to2_cdc_from : signal is "no";
signal rdy_back_cdc_to : std_logic := '0';
signal rdy_back_to : std_logic :='0';
-- ATTRIBUTE async_reg OF rdy_back_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF rdy_back_to : SIGNAL IS "true";
signal rdy_back : std_logic := '0';
signal rdy_shut : std_logic := '0';
begin
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
else
awvalid_d1 <= awvalid;
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
else
wvalid_d1 <= wvalid;
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
--*************************************************************************
--** Write Address Support
--*************************************************************************
AWVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_cdc_from <= '0';
elsif(awvalid_re = '1')then
awvalid_cdc_from <= '1';
end if;
end if;
end process AWVLD_CDC_FROM;
AWVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => awvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => awvalid_to,
scndry_vect_out => open
);
-- AWVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- awvalid_cdc_to <= awvalid_cdc_from;
-- awvalid_to <= awvalid_cdc_to;
-- end if;
-- end process AWVLD_CDC_TO;
AWVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
awvalid_to2 <= '0';
else
awvalid_to2 <= awvalid_to;
end if;
end if;
end process AWVLD_CDC_TO2;
ip_awvalid_re <= awvalid_to and (not awvalid_to2);
WVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_cdc_from <= '0';
elsif(wvalid_re = '1')then
wvalid_cdc_from <= '1';
end if;
end if;
end process WVLD_CDC_FROM;
WVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => wvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => wvalid_to,
scndry_vect_out => open
);
-- WVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- wvalid_cdc_to <= wvalid_cdc_from;
-- wvalid_to <= wvalid_cdc_to;
-- end if;
-- end process WVLD_CDC_TO;
WVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
wvalid_to2 <= '0';
else
wvalid_to2 <= wvalid_to;
end if;
end if;
end process WVLD_CDC_TO2;
ip_wvalid_re <= wvalid_to and (not wvalid_to2);
REG_WADDR_TO_IPCLK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_awaddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => awaddr_d1_cdc_tig
);
REG_WADDR_TO_IPCLK1 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_wdata,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => axi2ip_wrdata_cdc_tig
);
-- Double register address in
-- REG_WADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- awaddr_d1_cdc_tig <= (others => '0');
-- -- axi2ip_wraddr_i <= (others => '0');
-- axi2ip_wrdata_cdc_tig <= (others => '0');
-- else
-- awaddr_d1_cdc_tig <= s_axi_lite_awaddr;
-- axi2ip_wrdata_cdc_tig <= s_axi_lite_wdata;
-- -- axi2ip_wraddr_i <= awaddr_d1_cdc_tig; -- CR605883
-- end if;
-- end if;
-- end process REG_WADDR_TO_IPCLK;
-- Flag that address has been captured
REG_IP_ADDR_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_addr_cap <= '0';
elsif(ip_awvalid_re = '1')then
ip_addr_cap <= '1';
end if;
end if;
end process REG_IP_ADDR_CAP;
REG_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then -- or rdy = '1') then
rdy <= '0';
elsif (ip_data_cap = '1' and ip_addr_cap = '1') then
rdy <= '1';
end if;
end if;
end process REG_WREADY;
REG3_WREADY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => rdy_to2_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => rdy_back_to,
scndry_vect_out => open
);
-- REG3_WREADY : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- rdy_back_cdc_to <= rdy_to2_cdc_from;
-- rdy_back_to <= rdy_back_cdc_to;
-- end if;
-- end process REG3_WREADY;
REG3_WREADY2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0') then
rdy_back <= '0';
else
rdy_back <= rdy_back_to;
end if;
end if;
end process REG3_WREADY2;
rdy_shut <= rdy_back_to and (not rdy_back);
REG1_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then
rdy_cdc_from <= '0';
elsif (rdy = '1') then
rdy_cdc_from <= '1';
end if;
end if;
end process REG1_WREADY;
REG2_WREADY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => rdy_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => rdy_to,
scndry_vect_out => open
);
-- REG2_WREADY : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- rdy_cdc_to <= rdy_cdc_from;
-- rdy_to <= rdy_cdc_to;
-- end if;
-- end process REG2_WREADY;
REG2_WREADY2 : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0') then
rdy_to2 <= '0';
rdy_to2_cdc_from <= '0';
else
rdy_to2 <= rdy_to;
rdy_to2_cdc_from <= rdy_to;
end if;
end if;
end process REG2_WREADY2;
rdy_out <= not (rdy_to) and rdy_to2;
wready_i <= rdy_out;
awready_i <= rdy_out;
--*************************************************************************
--** Write Data Support
--*************************************************************************
-------------------------------------------------------------------------------
-- Capture write data
-------------------------------------------------------------------------------
-- WRDATA_S_H : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- wr_data_cdc_from <= (others => '0');
-- elsif(wvalid_re = '1')then
-- wr_data_cdc_from <= wdata;
-- end if;
-- end if;
-- end process WRDATA_S_H;
-- Flag that data has been captured
REG_IP_DATA_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_data_cap <= '0';
elsif(ip_wvalid_re = '1')then
ip_data_cap <= '1';
end if;
end if;
end process REG_IP_DATA_CAP;
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
axi2ip_wren <= rdy;
-- axi2ip_wren <= '1' when ip_data_cap = '1' and ip_addr_cap = '1'
-- else '0';
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when awaddr_d1_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_wrce <= (others => '0');
else
axi2ip_wrce <= wrce;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= axi2ip_wrdata_cdc_tig; --s_axi_lite_wdata;
--*************************************************************************
--** Write Response Support
--*************************************************************************
-- Minimum of 2 IP clocks for addr and data capture, therefore delaying
-- Lite clock addr and data capture by 2 Lite clocks will guarenttee bvalid
-- responce occurs after write data acutally written.
-- REG_ALIGN_CAP : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_data_cap_d1 <= '0';
-- lite_data_cap_d2 <= '0';
-- lite_addr_cap_d1 <= '0';
-- lite_addr_cap_d2 <= '0';
-- else
-- lite_data_cap_d1 <= rdy; --wr_data_cap;
-- lite_data_cap_d2 <= lite_data_cap_d1;
-- lite_addr_cap_d1 <= rdy; --wr_addr_cap;
-- lite_addr_cap_d2 <= lite_addr_cap_d1;
-- end if;
-- end if;
-- end process REG_ALIGN_CAP;
-- Pseudo write enable used simply to assert bvalid
-- lite_axi2ip_wren <= rdy; --'1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy_out = '1')then
-- elsif(lite_axi2ip_wren = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
s_axi_lite_bresp <= OKAY_RESP;
end generate GEN_ASYNC_WRITE;
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
-------------------------------------------------------------------------------
-- Assert Read Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_ARVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
arvalid_d1 <= '0';
else
arvalid_d1 <= arvalid;
end if;
end if;
end process REG_ARVALID;
arvalid_re <= arvalid and not arvalid_d1
and not rst_rvalid_re and not read_in_progress; -- CR607165
-- register for proper alignment
REG_ARREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_i <= '0';
else
arready_i <= arvalid_re;
end if;
end if;
end process REG_ARREADY;
-- Always respond 'okay' axi lite read
s_axi_lite_rresp <= OKAY_RESP;
s_axi_lite_rvalid <= s_axi_lite_rvalid_i;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_READ : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
read_in_progress <= '0'; --Not used for sync mode (CR607165)
-------------------------------------------------------------------------------
-- Capture Read Address
-------------------------------------------------------------------------------
REG_READ_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
-- Register address on valid
elsif(arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr;
end if;
end if;
end process REG_READ_ADDRESS;
-------------------------------------------------------------------------------
-- Generate RdCE based on address match to address bar
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= arvalid_re_d1
when axi2ip_rdaddr_i((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
--axi2ip_rdce <= (others => '0');
axi2ip_rdaddr <= (others => '0');
else
--axi2ip_rdce <= rdce;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Sample and hold rdce value until rvalid assertion
REG_RDCE_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
axi2ip_rdce <= (others => '0');
elsif(arvalid_re_d1 = '1')then
axi2ip_rdce <= rdce;
end if;
end if;
end process REG_RDCE_OUT;
-- Register for proper alignment
REG_RVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arvalid_re_d1 <= '0';
rvalid <= '0';
else
arvalid_re_d1 <= arvalid_re;
rvalid <= arvalid_re_d1;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
s_axi_lite_rdata <= ip2axi_rddata;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_SYNC_READ;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_READ : if C_AXI_LITE_IS_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal ip_arvalid_d1_cdc_tig : std_logic := '0';
signal ip_arvalid_d2 : std_logic := '0';
signal ip_arvalid_d3 : std_logic := '0';
signal ip_arvalid_re : std_logic := '0';
signal araddr_d1_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d2 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d3 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_cdc_from : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d1_cdc_to : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d2 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
-- ATTRIBUTE async_reg OF ip_arvalid_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ip_arvalid_d2 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF araddr_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF araddr_d2 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF lite_rdata_d1_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF lite_rdata_d2 : SIGNAL IS "true";
signal p_pulse_s_h : std_logic := '0';
signal p_pulse_s_h_clr : std_logic := '0';
signal s_pulse_d1 : std_logic := '0';
signal s_pulse_d2 : std_logic := '0';
signal s_pulse_d3 : std_logic := '0';
signal s_pulse_re : std_logic := '0';
signal p_pulse_re_d1 : std_logic := '0';
signal p_pulse_re_d2 : std_logic := '0';
signal p_pulse_re_d3 : std_logic := '0';
signal arready_d1 : std_logic := '0'; -- CR605883
signal arready_d2 : std_logic := '0'; -- CR605883
signal arready_d3 : std_logic := '0'; -- CR605883
signal arready_d4 : std_logic := '0'; -- CR605883
signal arready_d5 : std_logic := '0'; -- CR605883
signal arready_d6 : std_logic := '0'; -- CR605883
signal arready_d7 : std_logic := '0'; -- CR605883
signal arready_d8 : std_logic := '0'; -- CR605883
signal arready_d9 : std_logic := '0'; -- CR605883
signal arready_d10 : std_logic := '0'; -- CR605883
signal arready_d11 : std_logic := '0'; -- CR605883
signal arready_d12 : std_logic := '0'; -- CR605883
begin
-- CR607165
-- Flag to prevent overlapping reads
RD_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
read_in_progress <= '0';
elsif(arvalid_re = '1')then
read_in_progress <= '1';
end if;
end if;
end process RD_PROGRESS;
-- Double register address in
REG_RADDR_TO_IPCLK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_araddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => araddr_d3
);
-- REG_RADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- araddr_d1_cdc_tig <= (others => '0');
-- araddr_d2 <= (others => '0');
-- araddr_d3 <= (others => '0');
-- else
-- araddr_d1_cdc_tig <= s_axi_lite_araddr;
-- araddr_d2 <= araddr_d1_cdc_tig;
-- araddr_d3 <= araddr_d2;
-- end if;
-- end if;
-- end process REG_RADDR_TO_IPCLK;
-- Latch and hold read address
REG_ARADDR_PROCESS : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr_d3;
end if;
end if;
end process REG_ARADDR_PROCESS;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
-- Register awready into IP clock domain. awready
-- is a 1 axi_lite clock delay of the rising edge of
-- arvalid. This provides a signal that asserts when
-- araddr is known to be stable.
REG_ARVALID_TO_IPCLK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => arready_i,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => ip_arvalid_d2,
scndry_vect_out => open
);
REG_ARVALID_TO_IPCLK1 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
-- ip_arvalid_d1_cdc_tig <= '0';
-- ip_arvalid_d2 <= '0';
ip_arvalid_d3 <= '0';
else
-- ip_arvalid_d1_cdc_tig <= arready_i;
-- ip_arvalid_d2 <= ip_arvalid_d1_cdc_tig;
ip_arvalid_d3 <= ip_arvalid_d2;
end if;
end if;
end process REG_ARVALID_TO_IPCLK1;
ip_arvalid_re <= ip_arvalid_d2 and not ip_arvalid_d3;
-------------------------------------------------------------------------------
-- Generate Read CE's
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= ip_arvalid_re
when araddr_d3((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register RDCE and RD Data out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdce <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdce <= rdce;
else
axi2ip_rdce <= (others => '0');
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Generate sample and hold pulse to capture read data from IP
REG_RVALID : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
rvalid <= '0';
else
rvalid <= ip_arvalid_re;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Sample and hold read data from IP
-------------------------------------------------------------------------------
S_H_READ_DATA : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
lite_rdata_cdc_from <= (others => '0');
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
lite_rdata_cdc_from <= ip2axi_rddata;
end if;
end if;
end process S_H_READ_DATA;
-- Cross read data to axi_lite clock domain
REG_DATA2LITE_CLOCK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => '0', --lite_rdata_cdc_from,
prmry_vect_in => lite_rdata_cdc_from,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => open, --lite_rdata_d2,
scndry_vect_out => lite_rdata_d2
);
-- REG_DATA2LITE_CLOCK : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_rdata_d1_cdc_to <= (others => '0');
-- lite_rdata_d2 <= (others => '0');
-- else
-- lite_rdata_d1_cdc_to <= lite_rdata_cdc_from;
-- lite_rdata_d2 <= lite_rdata_d1_cdc_to;
-- end if;
-- end if;
-- end process REG_DATA2LITE_CLOCK;
-- CR605883 (CDC) modified to remove
-- Because axi_lite_aclk must be less than or equal to ip2axi_aclk
-- then read data will appear a maximum 6 clocks from assertion
-- of arready.
REG_ALIGN_RDATA_LATCH : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_d1 <= '0';
arready_d2 <= '0';
arready_d3 <= '0';
arready_d4 <= '0';
arready_d5 <= '0';
arready_d6 <= '0';
arready_d7 <= '0';
arready_d8 <= '0';
arready_d9 <= '0';
arready_d10 <= '0';
arready_d11 <= '0';
arready_d12 <= '0';
else
arready_d1 <= arready_i;
arready_d2 <= arready_d1;
arready_d3 <= arready_d2;
arready_d4 <= arready_d3;
arready_d5 <= arready_d4;
arready_d6 <= arready_d5;
arready_d7 <= arready_d6;
arready_d8 <= arready_d7;
arready_d9 <= arready_d8;
arready_d10 <= arready_d9;
arready_d11 <= arready_d10;
arready_d12 <= arready_d11;
end if;
end if;
end process REG_ALIGN_RDATA_LATCH;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
-- CR605883
--elsif(s_pulse_re = '1')then
elsif(arready_d12 = '1')then
s_axi_lite_rdata <= lite_rdata_d2;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_ASYNC_READ;
end implementation;
-------------------------------------------------------------------------------
-- axi_cdma_register
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_register.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_cdma_v4_1_14;
use axi_cdma_v4_1_14.axi_cdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_cdma_register is
generic(
C_CDMA_BUILD_MODE : integer range 0 to 1 := 0 ;
C_NUM_REGISTERS : integer range 0 to 16 := 6 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
);
port (
-- Input Clock
axi_aclk : in std_logic ;
-- Input Reset (active high)
axi_reset : in std_logic ;
-- AXI Interface Control
axi2ip_wrce : in std_logic_vector
(C_NUM_REGISTERS-1 downto 0) ;
-- AXI Interface Write Data
axi2ip_wrdata : in std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- Composite Interrupt Output
introut : out std_logic ;
-- Composite error Output
error_out : out std_logic ;
-- Soft Reset Set Control
soft_reset_request : out std_logic ;
-- Soft Reset Clear
soft_reset_clr : in std_logic ;
-- DMA Go Control
dma_go : Out std_logic ;
-- SG Mode control
dma_sg_mode : Out std_logic ;
-- Key Hole Read
dma_keyhole_read : Out std_logic ;
-- Key Hole Write
dma_keyhole_write : Out std_logic ;
-- Key Hole Write
dma_cyclic : Out std_logic ;
-- CDMASR Idle bit set
idle_set : in std_logic ;
-- CDMASR Idle bit clear
idle_clr : in std_logic ;
-- CDMASR Idle bit clear
ioc_irq_set : in std_logic ;
-- CDMASR Delay Interrupt set
dly_irq_set : in std_logic ;
-- CDMASR Delay Interrupt Counter value
irqdelay_status : in std_logic_vector(7 downto 0) ;
-- CDMASR Threshold Interrupt Counter value
irqthresh_status : in std_logic_vector(7 downto 0) ;
-- CDMASR Threshold Interrupt Counter value write enable
irqthresh_wren : out std_logic ;
-- CDMASR Delay Interrupt Counter value write enable
irqdelay_wren : out std_logic ;
-- Composite DataMover Internal Error flag
dma_interr_set : in std_logic ;
-- Composite DataMover Slave Error flag
dma_slverr_set : in std_logic ;
-- Composite DataMover Decode Error flag
dma_decerr_set : in std_logic ;
-- SG Descriptor Fetch internal error flag
ftch_interr_set : in std_logic ;
-- SG Descriptor Fetch slave error flag
ftch_slverr_set : in std_logic ;
-- SG Descriptor Fetch decode error flag
ftch_decerr_set : in std_logic ;
-- SG Descriptor Fetch error address
ftch_error_addr : in std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- SG Descriptor Update internal error flag
updt_interr_set : in std_logic ;
-- SG Descriptor Fetch slave error flag
updt_slverr_set : in std_logic ;
-- SG Descriptor Fetch decode error flag
updt_decerr_set : in std_logic ;
-- SG Descriptor Fetch error address
updt_error_addr : in std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- SG CURDESC Update (in from SG)
update_curdesc : in std_logic ;
-- SG CURDESC Update address value
new_curdesc : in std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- Tailpointer Register Updated flag
tailpntr_updated : out std_logic ;
-- Current Descriptor Register Updated flag
currdesc_updated : out std_logic ;
-- CDMA Control Register value
dmacr : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Status Register value
dmasr : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Current Descriptor Register LS value
curdesc_lsb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Current Descriptor Register MS value
curdesc_msb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Tailpointer Register LS value
taildesc_lsb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Tailpointer Register MS value
taildesc_msb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Source Address Register LS value
src_addr_lsb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Source Address Register MS value
src_addr_msb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA destination Register LS value
dest_addr_lsb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA destination Register MS value
dest_addr_msb : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA BTT Register value
btt : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0)
);
end axi_cdma_register;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma_register is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant DMACR_INDEX : integer := 0; -- DMACR Register index
constant DMASR_INDEX : integer := 1; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 2; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 3; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 4; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 5; -- TAILDESC MSB Reg index
constant SA_LSB_INDEX : integer := 6; -- SA LSB Reg index
constant SA_MSB_INDEX : integer := 7; -- SA MSB Reg index
constant DA_LSB_INDEX : integer := 8; -- DA LSB Reg index
constant DA_MSB_INDEX : integer := 9; -- DA MSB Reg index
constant BTT_INDEX : integer := 10; -- BTT Reg index
constant BTT_WIDTH : integer := 23; -- BTT Field width
constant BTT_RSVD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH -
BTT_WIDTH; -- BTT Reserved field width
constant BTT_RESERVED_BITS : std_logic_vector(BTT_RSVD_WIDTH-1 downto 0) :=
(others => '0'); -- Set the reserved value
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
Constant SIMPLE_DISABLE : boolean := (C_CDMA_BUILD_MODE = 0);
-- 0 = Simple mode only
-- Used to reset registers not
-- used in Simple DMA only mode
Constant ALWAYS_DISABLE : boolean := TRUE; -- Used to disable
Constant DMACR_THRESH_WIDTH : integer := 8;
Constant THRESH_DEFAULT : std_logic_vector(DMACR_IRQTHRESH_MSB_BIT downto
DMACR_IRQTHRESH_LSB_BIT) :=
STD_LOGIC_VECTOR(
TO_UNSIGNED(C_CDMA_BUILD_MODE,
DMACR_THRESH_WIDTH));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
-- DMASR Signals
signal idle : std_logic := '0';
signal sig_composite_error : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_interr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal error_d1 : std_logic := '0';
signal error_re : std_logic := '0';
signal err_irq : std_logic := '0';
signal tailpntr_updated_d1, tailpntr_updated_d2 : std_logic;
signal sig_sg_included : std_logic := '0';
signal sg_ftch_error : std_logic := '0';
signal sg_updt_error : std_logic := '0';
signal error_pointer_set : std_logic := '0';
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
signal sig_irqdelay_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_irqthresh_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_sa_register_lsb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_sa_register_msb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_da_register_lsb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_da_register_msb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_register : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dma_go : std_logic := '0';
signal sig_dma_go_set : std_logic := '0';
signal sig_dma_go_clr : std_logic := '0';
signal sig_dma_sg_mode : std_logic := '0';
signal sig_dly_irqen_masked : std_logic := '0';
signal sig_dly_irqen_reg : std_logic := '0';
signal sig_ioc_irqen_reg : std_logic := '0';
signal sig_err_irqen_reg : std_logic := '0';
signal sig_dma_khwrite_mode : std_logic;
signal sig_dma_khread_mode : std_logic;
signal sig_dma_cyclic_mode : std_logic;
signal sig_btt_register_del : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i ;
taildesc_msb <= taildesc_msb_i ;
dma_sg_mode <= sig_dma_sg_mode ;
dma_keyhole_write <= sig_dma_khwrite_mode;
dma_keyhole_read <= sig_dma_khread_mode;
dma_cyclic <= sig_dma_cyclic_mode;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DMACR_DELAY : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
irqdelay_wren <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren <= '1';
else
irqdelay_wren <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= THRESH_DEFAULT;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
irqthresh_wren <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren <= '1';
else
irqthresh_wren <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Key Hole READ Mode Bit (Bit 4)
-------------------------------------------------------------------------------
DMAKHR_MODE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1') then
dmacr_i(DMACR_KHREAD_BIT) <= '0';
dmacr_i(DMACR_CYCLIC_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KHREAD_BIT) <= axi2ip_wrdata(DMACR_KHREAD_BIT);
dmacr_i(DMACR_CYCLIC_BIT) <= axi2ip_wrdata(DMACR_CYCLIC_BIT);
end if;
end if;
end process DMAKHR_MODE;
sig_dma_cyclic_mode <= dmacr_i(DMACR_CYCLIC_BIT);
sig_dma_khread_mode <= dmacr_i(DMACR_KHREAD_BIT);
-------------------------------------------------------------------------------
-- DMACR - Key Hole WRITE Mode Bit (Bit 5)
-------------------------------------------------------------------------------
DMAKHW_MODE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1') then
dmacr_i(DMACR_KHWRITE_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KHWRITE_BIT) <= axi2ip_wrdata(DMACR_KHWRITE_BIT);
end if;
end if;
end process DMAKHW_MODE;
sig_dma_khwrite_mode <= dmacr_i(DMACR_KHWRITE_BIT);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DMACR_SIMPLE
--
-- If Generate Description:
-- Implement the DMA Control Register discrete bits
-- for Simple DMA only build case. The Delay interrupt
-- enable bit is unused and always '0'.
--
------------------------------------------------------------
GEN_DMACR_SIMPLE : if (C_CDMA_BUILD_MODE = 0) generate
begin
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register
-------------------------------------------------------------------------------
DMACR_REGISTER_SIMPLE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED7_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED7_BIT) <=
ZERO_VALUE(DMACR_RESERVED15_BIT) -- bit 15
& axi2ip_wrdata(DMACR_ERR_IRQEN_BIT) -- bit 14
& '0' -- bit 13 (always 0 in Simple only)
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT) -- bit 12
& ZERO_VALUE(DMACR_RESERVED11_BIT downto
DMACR_RESERVED7_BIT);-- bits 11 downto 4
end if;
end if;
end process DMACR_REGISTER_SIMPLE;
end generate GEN_DMACR_SIMPLE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DMACR_SG
--
-- If Generate Description:
-- Implement the DMA Control Register discrete bits
-- for SG Enabled build case. The Delay interrupt
-- enable bit is active when not in Simple Mode.
--
------------------------------------------------------------
GEN_DMACR_SG : if (C_CDMA_BUILD_MODE = 1) generate
begin
dmacr_i(DMACR_RESERVED15_BIT) <= '0' ;
dmacr_i(DMACR_ERR_IRQEN_BIT) <= sig_err_irqen_reg;
dmacr_i(DMACR_DLY_IRQEN_BIT) <= sig_dly_irqen_reg;
dmacr_i(DMACR_IOC_IRQEN_BIT) <= sig_ioc_irqen_reg;
dmacr_i(DMACR_RESERVED11_BIT downto
DMACR_RESERVED7_BIT ) <= (others => '0') ;
-------------------------------------------------------------------------------
-- DMACR - Delay Interrupt Enable Register bit
-------------------------------------------------------------------------------
IMP_DMACR_DLY_IRQEN : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
sig_dly_irqen_reg <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
sig_dly_irqen_reg <= axi2ip_wrdata(DMACR_DLY_IRQEN_BIT);
end if;
end if;
end process IMP_DMACR_DLY_IRQEN;
-------------------------------------------------------------------------------
-- DMACR - IOC Interrupt Enable Register bit
-------------------------------------------------------------------------------
IMP_DMACR_IOC_IRQEN : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1') then
sig_ioc_irqen_reg <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
sig_ioc_irqen_reg <= axi2ip_wrdata(DMACR_IOC_IRQEN_BIT);
end if;
end if;
end process IMP_DMACR_IOC_IRQEN;
-------------------------------------------------------------------------------
-- DMACR - Error Interrupt Enable Register bit
-------------------------------------------------------------------------------
IMP_DMACR_ERR_IRQEN : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1') then
sig_err_irqen_reg <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
sig_err_irqen_reg <= axi2ip_wrdata(DMACR_ERR_IRQEN_BIT);
end if;
end if;
end process IMP_DMACR_ERR_IRQEN;
end generate GEN_DMACR_SG;
-------------------------------------------------------------------------------
-- DMACR - Tail Pointer Enable Bit (Bit 1)
-- Fixed at 0 for simple dma only
-- Fixed at 1 (when SG included) for this release of
-- axi cdma.
-------------------------------------------------------------------------------
dmacr_i(DMACR_TAILPEN_BIT) <= '1'
when C_CDMA_BUILD_MODE = 1
else '0';
-------------------------------------------------------------------------------
-- DMACR - Reset Bit (Bit 2)
-------------------------------------------------------------------------------
DMACR_RESET : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
Elsif (dmacr_i(DMACR_RESET_BIT) = '1') Then
dmacr_i(DMACR_RESET_BIT) <= '1'; -- can't clear by write once set
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_request <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- DMACR - SG Mode Bit (Bit 3)
-------------------------------------------------------------------------------
DMASG_MODE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
dmacr_i(DMACR_SGMODE_BIT) <= '0';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_SGMODE_BIT) <= axi2ip_wrdata(DMACR_SGMODE_BIT);
end if;
end if;
end process DMASG_MODE;
sig_dma_sg_mode <= dmacr_i(DMACR_SGMODE_BIT);
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
-- Run/Stop removed from CDMA
dmacr_i(DMACR_RESERVED0_BIT) <= '0';
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1)
--
-- Set by cdma controller indicating DMA is active (= 0)
-- or stopped (= 1).
---------------------------------------------------------------------------
DMASR_IDLE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1'or
idle_clr = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
---------------------------------------------------------------------------
-- DMA Status SG Included (BIT 3)
---------------------------------------------------------------------------
-- Set the DMASR.SGIncld bit
sig_sg_included <= '1'
when C_CDMA_BUILD_MODE = 1
else '0';
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
sig_composite_error <= dma_interr
or dma_slverr
or dma_decerr
or sg_interr
or sg_slverr
or sg_decerr;
-- Scatter Gather Error
--sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
-- SG Update Errors or DMA errors assert flag on descriptor update
-- Used to latch current descriptor pointer
--sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
-- or dma_interr or dma_slverr or dma_decerr;
-- Map out to halt opposing channel
error_out <= sig_composite_error;
ERROR_DEL : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
sg_ftch_error <= '0';
sg_updt_error <= '0';
else
sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
or dma_interr or dma_slverr or dma_decerr;
end if;
end if;
end process ERROR_DEL;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
DMASR_DMAINTERR : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
dma_interr <= '0';
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status SG Internal Error bit (BIT 8)
---------------------------------------------------------------------------
DMASR_SGINTERR : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
sg_interr <= '0';
elsif(ftch_interr_set = '1' or updt_interr_set = '1')then
sg_interr <= '1';
end if;
end if;
end process DMASR_SGINTERR;
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 13)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
sig_dma_sg_mode = '0' or -- clear if in Simple Mode
SIMPLE_DISABLE)then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 14)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERROR_RE : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
error_d1 <= '0';
else
error_d1 <= sig_composite_error;
end if;
end if;
end process GEN_ERROR_RE;
-- Generate rising edge pulse on error
error_re <= sig_composite_error and not error_d1;
DMASR_ERRIRQ : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or error_re;
elsif(error_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Status IRQ Threshold (BIT 23 - 16)
---------------------------------------------------------------------------
sig_irqthresh_status <= (others => '0')
when SIMPLE_DISABLE
Else irqthresh_status;
---------------------------------------------------------------------------
-- DMA Status IRQ Delay (BIT 31 - 24)
---------------------------------------------------------------------------
sig_irqdelay_status <= (others => '0')
when SIMPLE_DISABLE
Else irqdelay_status;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= sig_irqdelay_status -- Bits 31 downto 24
& sig_irqthresh_status -- Bits 23 downto 16
& '0' -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& '0' -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& sg_interr -- Bit 8
& '0' -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& sig_sg_included -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& '0'; -- Bit 0
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
sig_dma_sg_mode = '0' or
SIMPLE_DISABLE)then
curdesc_lsb_i <= (others => '0');
error_pointer_set <= '0';
currdesc_updated <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set <= '1';
currdesc_updated <= '0';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set <= '1';
-- currdesc_updated <= '0';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1')then
curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
error_pointer_set <= '0';
currdesc_updated <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and dmasr_i(DMASR_IDLE_BIT) = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT)
& ZERO_VALUE(CURDESC_RESERVED_BIT5
downto CURDESC_RESERVED_BIT0);
error_pointer_set <= '0';
currdesc_updated <= '1';
else
currdesc_updated <= '0';
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
sig_dma_sg_mode = '0' or
SIMPLE_DISABLE)then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT)
& ZERO_VALUE(TAILDESC_RESERVED_BIT5
downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
SA_MSB_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
sig_sa_register_msb <= (others => '0');
elsif(axi2ip_wrce(SA_MSB_INDEX) = '1')then
sig_sa_register_msb <= axi2ip_wrdata;
end if;
end if;
end process SA_MSB_REGISTER;
src_addr_msb <= sig_sa_register_msb;
DA_MSB_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
sig_da_register_msb <= (others => '0');
elsif(axi2ip_wrce(DA_MSB_INDEX) = '1')then
sig_da_register_msb <= axi2ip_wrdata;
end if;
end if;
end process DA_MSB_REGISTER;
dest_addr_msb <= sig_da_register_msb;
CURDESC_MSB_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
sig_dma_sg_mode = '0' or
SIMPLE_DISABLE)then
curdesc_msb_i <= (others => '0');
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1')then
curdesc_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and dmasr_i(DMASR_IDLE_BIT) = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
sig_dma_sg_mode = '0' or
SIMPLE_DISABLE)then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
sig_sa_register_msb <= (others => '0');
src_addr_msb <= sig_sa_register_msb;
sig_da_register_msb <= (others => '0');
dest_addr_msb <= sig_da_register_msb;
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
TAILPNTR_UPDT_PROCESS : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
TAILPNTR_UPDT_PROCESS : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
end generate GEN_TAILUPDATE_EQL64;
TAILPNTR_UPDT_PROCESS11 : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
SIMPLE_DISABLE)then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS11;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
---------------------------------------------------------------------------
-- Simple DMA Source Address (SA) LSB Register
---------------------------------------------------------------------------
SA_LSB_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
sig_sa_register_lsb <= (others => '0');
elsif(axi2ip_wrce(SA_LSB_INDEX) = '1')then
sig_sa_register_lsb <= axi2ip_wrdata;
end if;
end if;
end process SA_LSB_REGISTER;
src_addr_lsb <= sig_sa_register_lsb;
---------------------------------------------------------------------------
-- Simple DMA Source Address (SA) MSB Register
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Simple DMA Destination Address (DA) LSB Register
---------------------------------------------------------------------------
DA_LSB_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
sig_da_register_lsb <= (others => '0');
elsif(axi2ip_wrce(DA_LSB_INDEX) = '1')then
sig_da_register_lsb <= axi2ip_wrdata;
end if;
end if;
end process DA_LSB_REGISTER;
dest_addr_lsb <= sig_da_register_lsb;
---------------------------------------------------------------------------
-- Simple DMA Destination Address (DA) MSB Register
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Simple DMA Bytes to Transfer (BTT) Register
---------------------------------------------------------------------------
BTT_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
sig_btt_register <= (others => '0');
elsif(axi2ip_wrce(BTT_INDEX) = '1')then
sig_btt_register(BTT_WIDTH-1 downto 0) <=
axi2ip_wrdata(BTT_WIDTH-1 downto 0);
end if;
end if;
end process BTT_REGISTER;
PULSE_REGISTER : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1')then
sig_btt_register_del <= '0';
else
sig_btt_register_del <= axi2ip_wrce(BTT_INDEX);
end if;
end if;
end process PULSE_REGISTER;
--sig_dma_go_set <= axi2ip_wrce(BTT_INDEX);
sig_dma_go_set <= axi2ip_wrce(BTT_INDEX) and (not sig_btt_register_del);
btt <= BTT_RESERVED_BITS &
sig_btt_register(BTT_WIDTH-1 downto 0);
---------------------------------------------------------------------------
-- Simple DMA GO Control
---------------------------------------------------------------------------
IMP_DMA_GO_REG : process(axi_aclk)
begin
if(axi_aclk'EVENT and axi_aclk = '1')then
if(axi_reset = '1' or
sig_dma_go_clr = '1')then
sig_dma_go <= '0';
elsif(sig_dma_go_set = '1')then
sig_dma_go <= '1';
end if;
end if;
end process IMP_DMA_GO_REG;
sig_dma_go_clr <= idle_clr ; -- Clear the GO when IDLE is cleared
dma_go <= sig_dma_go; -- assign the dma_go output
end implementation;
-------------------------------------------------------------------------------
-- axi_cdma_reg_module
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_reg_module.vhd
-- Description: This entity is AXI DMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_cdma_v4_1_14;
use axi_cdma_v4_1_14.axi_cdma_pkg.all;
use axi_cdma_v4_1_14.axi_cdma_lite_if;
use axi_cdma_v4_1_14.axi_cdma_register;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
entity axi_cdma_reg_module is
generic(
C_CDMA_BUILD_MODE : integer range 0 to 1 := 0 ;
-- Indicates the as-built topology of the AXI CDMA
-- 0 = Simple DMA only support
-- 1 = Simple DMA and Scatter Gather support included
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 6 ;
-- Address width of the AXI Lite Interface (bits)
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
-- Data width of the AXI Lite Interface (bits)
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
-- Specifies if the AXI Lite Register interface needs to
-- be asynchronous to the CDMA data transport path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special AXI Lite clock for the axi lite interface
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Address width of the SG AXI Interface (bits)
);
port (
---------------------------------------------------------------------------------
-- AXI4-Lite Interface
---------------------------------------------------------------------------------
-- AXI Lite Clock (needs to be the same as axi4-lite clock when
-- C_AXI_LITE_IS_ASYNC = 0 ) -- AXI4-Lite
axi_lite_aclk : in std_logic ;-- AXI4-Lite
-- AXI Lite Bus Side Reset (synchronized to the axi_lite_aclk)
axi_lite_reset : in std_logic ;-- AXI4-Lite
-- AXI Lite Core side Reset (synchronized to the axi_aclk)
axi_lite_cside_reset : in std_logic ;-- AXI4-Lite
-- AXI Lite Write Address Channel -- AXI4-Lite
s_axi_lite_awvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_awready : out std_logic ;-- AXI4-Lite
s_axi_lite_awaddr : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Write Data Channel -- AXI4-Lite
s_axi_lite_wvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_wready : out std_logic ;-- AXI4-Lite
s_axi_lite_wdata : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Write Response Channel -- AXI4-Lite
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ;-- AXI4-Lite
s_axi_lite_bvalid : out std_logic ;-- AXI4-Lite
s_axi_lite_bready : in std_logic ;-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Read Address Channel -- AXI4-Lite
s_axi_lite_arvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_arready : out std_logic ;-- AXI4-Lite
s_axi_lite_araddr : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI Lite Read Data Channel -- AXI4-Lite
s_axi_lite_rvalid : out std_logic ;-- AXI4-Lite
s_axi_lite_rready : in std_logic ;-- AXI4-Lite
s_axi_lite_rdata : out std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);-- AXI4-Lite
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ;-- AXI4-Lite
-- Primary Input Clock for everything other than AXI4-Lite
axi_aclk : In std_logic ;
-- Primary Input Reset synchronized to axi_aclk
axi_reg_reset : In std_logic ;
-- Composite Interrupt Output
reg_introut : out std_logic ;
-- Composite error Output
reg_error_out : out std_logic ;
-- Soft Reset Set Control
reg_soft_reset_request : out std_logic ;
-- Soft Reset Clear
reg_soft_reset_clr : in std_logic ;
-- DMA Go Control
reg_dma_go : Out std_logic ;
-- SG Mode control
reg_dma_sg_mode : Out std_logic ;
-- Key Hole read
dma_keyhole_read : Out std_logic ;
-- Key Hole write
dma_keyhole_write : Out std_logic ;
-- Cyclic feature
dma_cyclic : Out std_logic ;
-- CDMASR Idle bit set
reg_idle_set : in std_logic ;
-- CDMASR Idle bit clear
reg_idle_clr : in std_logic ;
-- CDMASR Interrupt on Complet set
reg_ioc_irq_set : in std_logic ;
-- CDMASR Delay Interrupt set
reg_dly_irq_set : in std_logic ;
-- CDMASR Delay Interrupt Counter value
reg_irqdelay_status : in std_logic_vector(7 downto 0) ;
-- CDMASR Threshold Interrupt Counter value
reg_irqthresh_status : in std_logic_vector(7 downto 0) ;
-- CDMASR Threshold Interrupt Counter value write enable
reg_irqthresh_wren : out std_logic ;
-- CDMASR Delay Interrupt Counter value write enable
reg_irqdelay_wren : out std_logic ;
-- Composite DataMover Internal Error flag
reg_dma_interr_set : in std_logic ;
-- Composite DataMover Slave Error flag
reg_dma_slverr_set : in std_logic ;
-- Composite DataMover Decode Error flag
reg_dma_decerr_set : in std_logic ;
-- SG Descriptor Fetch internal error flag
reg_ftch_interr_set : in std_logic ;
-- SG Descriptor Fetch slave error flag
reg_ftch_slverr_set : in std_logic ;
-- SG Descriptor Fetch decode error flag
reg_ftch_decerr_set : in std_logic ;
-- SG Descriptor Fetch error address
reg_ftch_error_addr : in std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- SG Descriptor Update internal error flag
reg_updt_interr_set : in std_logic ;
-- SG Descriptor Fetch slave error flag
reg_updt_slverr_set : in std_logic ;
-- SG Descriptor Fetch decode error flag
reg_updt_decerr_set : in std_logic ;
-- SG Descriptor Fetch error address
reg_updt_error_addr : in std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- SG CURDESC Update Write enable
reg_new_curdesc_wren : in std_logic ;
-- SG CURDESC Update address value
reg_new_curdesc : in std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- Tailpointer Register Updated flag
reg_tailpntr_updated : out std_logic ;
-- Current Descriptor Register Updated flag
reg_currdesc_updated : out std_logic ;
-- CDMA Control Register value
reg_dmacr : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ;
-- CDMA Status Register value
reg_dmasr : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- CDMA Current Descriptor Register value
reg_curdesc : out std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- CDMA Tailpointer Register value
reg_taildesc : out std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
-- CDMA Source Address Register value
reg_src_addr : out std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
-- CDMA destination Register value
reg_dest_addr : out std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
-- CDMA BTT Register value
reg_btt : out std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0)
);
end axi_cdma_reg_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma_reg_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant CDMA_NUM_REG : Integer := 16;
Constant DMACR_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000000000001";
Constant DMASR_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000000000010";
Constant CURDESC_LS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000000000100";
Constant CURDESC_MS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000000001000";
Constant TAILDESC_LS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000000010000";
Constant TAILDESC_MS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000000100000";
Constant SA_LS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000001000000";
Constant SA_MS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000010000000";
Constant DA_LS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000000100000000";
Constant DA_MS_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000001000000000";
Constant BTT_REG_CE : std_logic_vector(CDMA_NUM_REG-1 downto 0) :=
"0000010000000000";
-------------------------------------------------------------------------------
-- Signal / Type Declarations
---------------------------- ---------------------------------------------------
signal sig_axi2ip_wrce : std_logic_vector(CDMA_NUM_REG - 1 downto 0) := (others => '0');
signal sig_axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_axi2ip_rdce : std_logic_vector(CDMA_NUM_REG - 1 downto 0) := (others => '0');
signal sig_ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_curdesc_lsb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_curdesc_msb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_taildesc_lsb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_taildesc_msb : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_src_addr_lsb : std_logic_vector(c_s_axi_lite_data_width-1 downto 0) := (others => '0');
signal sig_dest_addr_lsb : std_logic_vector(c_s_axi_lite_data_width-1 downto 0) := (others => '0');
signal sig_src_addr_msb : std_logic_vector(c_s_axi_lite_data_width-1 downto 0) := (others => '0');
signal sig_dest_addr_msb : std_logic_vector(c_s_axi_lite_data_width-1 downto 0) := (others => '0');
signal sig_btt : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_lite_bside_resetn : std_logic := '0';
signal sig_axi_lite_cside_resetn : std_logic := '0';
signal sig_interrupt_out : std_logic := '0';
signal sig_reg2out_irpt : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Reset Inversions for the AXI Lite IF
sig_axi_lite_bside_resetn <= not(axi_lite_reset);
sig_axi_lite_cside_resetn <= not(axi_lite_cside_reset);
-- Register Outputs
reg_dmacr <= sig_dmacr;
reg_dmasr <= sig_dmasr;
reg_curdesc (31 downto 0) <= sig_curdesc_lsb;
reg_taildesc (31 downto 0) <= sig_taildesc_lsb;
reg_src_addr (31 downto 0) <= sig_src_addr_lsb;
reg_dest_addr (31 downto 0) <= sig_dest_addr_lsb;
reg_btt <= sig_btt;
-- Composite Interrupt Output
reg_introut <= sig_interrupt_out ;
GEN_64_BIT_ADDR : if (C_M_AXI_SG_ADDR_WIDTH = 64) generate
begin
reg_curdesc (63 downto 32) <= sig_curdesc_msb;
reg_taildesc (63 downto 32) <= sig_taildesc_msb;
reg_src_addr (63 downto 32) <= sig_src_addr_msb;
reg_dest_addr (63 downto 32) <= sig_dest_addr_msb;
end generate GEN_64_BIT_ADDR;
------------------------------------------------------------
-- Instance: I_AXI_LITE
--
-- Description:
-- Instance for the AXI Lite Interface Module
--
------------------------------------------------------------
I_AXI_LITE : entity axi_cdma_v4_1_14.axi_cdma_lite_if
generic map(
C_NUM_CE => CDMA_NUM_REG ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH
)
port map(
-- AXI Lite Clock and Reset
s_axi_lite_aclk => axi_lite_aclk ,
s_axi_lite_aresetn => sig_axi_lite_bside_resetn ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- User IP Interface
-- IP side Interface clock and Reset inputs
-- Used when C_AXI_LITE_IS_ASYNC = 1
ip2axi_aclk => axi_aclk ,
ip2axi_aresetn => sig_axi_lite_cside_resetn,
axi2ip_wrce => sig_axi2ip_wrce ,
axi2ip_wrdata => sig_axi2ip_wrdata ,
axi2ip_rdce => sig_axi2ip_rdce ,
axi2ip_rdaddr => open ,
ip2axi_rddata => sig_ip2axi_rddata
);
-------------------------------------------------------------------------------
-- AXI LITE READ MUX
-------------------------------------------------------------------------------
AXI_LITE_READ_MUX : process(sig_axi2ip_rdce ,
sig_dmacr ,
sig_dmasr ,
sig_curdesc_lsb ,
sig_taildesc_lsb ,
sig_curdesc_msb ,
sig_taildesc_msb ,
sig_src_addr_lsb ,
sig_src_addr_msb ,
sig_dest_addr_lsb,
sig_dest_addr_msb,
sig_btt)
begin
-- Read Mux
case sig_axi2ip_rdce is
---------------------------------
When DMACR_REG_CE =>
sig_ip2axi_rddata <= sig_dmacr;
---------------------------------
When DMASR_REG_CE =>
sig_ip2axi_rddata <= sig_dmasr;
---------------------------------
When CURDESC_LS_REG_CE =>
sig_ip2axi_rddata <= sig_curdesc_lsb;
---------------------------------
When CURDESC_MS_REG_CE =>
sig_ip2axi_rddata <= sig_curdesc_msb;
---------------------------------
When TAILDESC_LS_REG_CE =>
sig_ip2axi_rddata <= sig_taildesc_lsb;
---------------------------------
When TAILDESC_MS_REG_CE =>
sig_ip2axi_rddata <= sig_taildesc_msb;
---------------------------------
When SA_LS_REG_CE =>
sig_ip2axi_rddata <= sig_src_addr_lsb;
---------------------------------
When SA_MS_REG_CE =>
sig_ip2axi_rddata <= sig_src_addr_msb;
---------------------------------
When DA_LS_REG_CE =>
sig_ip2axi_rddata <= sig_dest_addr_lsb;
---------------------------------
When DA_MS_REG_CE =>
sig_ip2axi_rddata <= sig_dest_addr_msb;
---------------------------------
When BTT_REG_CE =>
sig_ip2axi_rddata <= sig_btt;
---------------------------------
when others =>
sig_ip2axi_rddata <= (others => '0');
end case;
end process AXI_LITE_READ_MUX;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_IRPT_RESYNC
--
-- If Generate Description:
-- The AXI clock and the AXI Lite clock are the same so
-- synchronization registers are not required.
--
------------------------------------------------------------
GEN_NO_IRPT_RESYNC : if (C_AXI_LITE_IS_ASYNC = 0) generate
begin
sig_interrupt_out <= sig_reg2out_irpt;
end generate GEN_NO_IRPT_RESYNC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_IRPT_RESYNC
--
-- If Generate Description:
-- The AXI clock and the AXI Lite clock are not the same so
-- synchronization registers are are required.
--
------------------------------------------------------------
GEN_IRPT_RESYNC : if (C_AXI_LITE_IS_ASYNC = 1) generate
ATTRIBUTE async_reg : STRING;
signal lsig_sync_reg1_cdc_tig : std_logic := '0';
signal lsig_sync_reg2 : std_logic := '0';
--ATTRIBUTE async_reg OF lsig_sync_reg1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lsig_sync_reg2 : SIGNAL IS "true";
begin
sig_interrupt_out <= lsig_sync_reg2;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SYNC_IRPT_SYNC_REG
--
-- Process Description:
-- Implements the syncronization registers for the AXI
-- to AXI Lite clock domain crossing of the interrupt out.
--
-------------------------------------------------------------
IMP_SYNC_IRPT_SYNC_REG : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_reg2out_irpt,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_lite_aclk,
scndry_resetn => '0',
scndry_out => lsig_sync_reg2,
scndry_vect_out => open
);
-- IMP_SYNC_IRPT_SYNC_REG : process (axi_lite_aclk)
-- begin
-- if (axi_lite_aclk'event and axi_lite_aclk = '1') then
-- -- if (axi_lite_reset = '1') then
--
-- -- lsig_sync_reg1 <= '0';
-- -- lsig_sync_reg2 <= '0';
--
-- -- else
--
-- lsig_sync_reg1_cdc_tig <= sig_reg2out_irpt;
-- lsig_sync_reg2 <= lsig_sync_reg1_cdc_tig;
--
-- -- end if;
-- end if;
-- end process IMP_SYNC_IRPT_SYNC_REG;
end generate GEN_IRPT_RESYNC;
------------------------------------------------------------
-- Instance: I_REGISTER_BLOCK
--
-- Description:
-- Instance of the AXI CDMA register block.
--
------------------------------------------------------------
I_REGISTER_BLOCK : entity axi_cdma_v4_1_14.axi_cdma_register
generic map (
C_CDMA_BUILD_MODE => C_CDMA_BUILD_MODE ,
C_NUM_REGISTERS => CDMA_NUM_REG ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-- Secondary Clock / Reset
axi_aclk => axi_aclk ,
axi_reset => axi_reg_reset ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrce => sig_axi2ip_wrce ,
axi2ip_wrdata => sig_axi2ip_wrdata ,
-- Composite Interrupt Output
introut => sig_reg2out_irpt ,
-- Composite error Output
error_out => reg_error_out ,
-- Soft Reset Control
soft_reset_request => reg_soft_reset_request ,
soft_reset_clr => reg_soft_reset_clr ,
-- DMA Go Control
dma_go => reg_dma_go ,
-- SG Mode control
dma_sg_mode => reg_dma_sg_mode ,
-- Key Hole write
dma_keyhole_write => dma_keyhole_write ,
-- Key Hole read
dma_keyhole_read => dma_keyhole_read ,
-- Key Hole read
dma_cyclic => dma_cyclic ,
-- DMASR Register bit control/status
idle_set => reg_idle_set ,
idle_clr => reg_idle_clr ,
ioc_irq_set => reg_ioc_irq_set ,
dly_irq_set => reg_dly_irq_set ,
irqdelay_status => reg_irqdelay_status ,
irqthresh_status => reg_irqthresh_status ,
irqthresh_wren => reg_irqthresh_wren ,
irqdelay_wren => reg_irqdelay_wren ,
-- DataMover Errors
dma_interr_set => reg_dma_interr_set ,
dma_slverr_set => reg_dma_slverr_set ,
dma_decerr_set => reg_dma_decerr_set ,
-- SG Descriptor Fetch errors
ftch_interr_set => reg_ftch_interr_set ,
ftch_slverr_set => reg_ftch_slverr_set ,
ftch_decerr_set => reg_ftch_decerr_set ,
ftch_error_addr => reg_ftch_error_addr ,
-- SG Descriptor Update errors
updt_interr_set => reg_updt_interr_set ,
updt_slverr_set => reg_updt_slverr_set ,
updt_decerr_set => reg_updt_decerr_set ,
updt_error_addr => reg_updt_error_addr ,
-- SG CURDESC Update (from SG)
update_curdesc => reg_new_curdesc_wren ,
new_curdesc => reg_new_curdesc ,
-- SG Detected SW Register Update
tailpntr_updated => reg_tailpntr_updated ,
currdesc_updated => reg_currdesc_updated ,
-- Register State Out
dmacr => sig_dmacr ,
dmasr => sig_dmasr ,
curdesc_lsb => sig_curdesc_lsb ,
curdesc_msb => sig_curdesc_msb ,
taildesc_lsb => sig_taildesc_lsb ,
taildesc_msb => sig_taildesc_msb ,
src_addr_lsb => sig_src_addr_lsb ,
src_addr_msb => sig_src_addr_msb ,
dest_addr_lsb => sig_dest_addr_lsb ,
dest_addr_msb => sig_dest_addr_msb ,
btt => sig_btt
);
end implementation;
-------------------------------------------------------------------------------
-- axi_cdma_sfifo_autord.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_sfifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- synchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_9;
use lib_fifo_v1_0_9.sync_fifo_fg;
-------------------------------------------------------------------------------
entity axi_cdma_sfifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 128;
C_DATA_CNT_WIDTH : integer := 8;
C_NEED_ALMOST_EMPTY : Integer range 0 to 1 := 0;
C_NEED_ALMOST_FULL : Integer range 0 to 1 := 0;
C_USE_BLKMEM : Integer range 0 to 1 := 1;
-- 1 = Use Block RAM
-- 0 = USE SRL
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
SFIFO_Sinit : In std_logic; -- Reset
SFIFO_Clk : In std_logic; -- Clock
SFIFO_Wr_en : In std_logic; -- Write enable
SFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); -- Write Data input
SFIFO_Rd_en : In std_logic; -- Read Enable
SFIFO_Clr_Rd_Data_Valid : In std_logic; -- Clear the Read data valid
-- Outputs
SFIFO_DValid : Out std_logic; -- Read Data Valid indication
SFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); -- Read Data out
SFIFO_Full : Out std_logic; -- FIFO Full flag
SFIFO_Empty : Out std_logic; -- FIFO empty flag
SFIFO_Almost_full : Out std_logic; -- FIFO almost Full flag
SFIFO_Almost_empty : Out std_logic; -- FIFO almost empty flag
SFIFO_Rd_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); -- Read count
SFIFO_Rd_count_minus1 : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); -- Read count minus 1
SFIFO_Wr_count : Out std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0); -- Write count
SFIFO_Rd_ack : Out std_logic -- Read acknowledge
);
end entity axi_cdma_sfifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_cdma_sfifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- none
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal raw_data_cnt_lil_end : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_int : natural := 0;
signal raw_data_count_corr : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
signal raw_data_count_corr_minus1 : std_logic_vector(C_DATA_CNT_WIDTH-1 downto 0) := (others => '0');
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_SFIFO_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_sfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
begin
-- Bit ordering translations
write_data_lil_end <= SFIFO_Din; -- translate from Big Endian to little
-- endian.
SFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
-- Other port usages and assignments
SFIFO_Rd_ack <= sig_sfifo_rdack;
SFIFO_Almost_empty <= corrected_almost_empty;
SFIFO_Empty <= sig_SFIFO_empty; --corrected_empty;
SFIFO_Wr_count <= raw_data_cnt_lil_end;
SFIFO_Rd_count <= raw_data_count_corr;
SFIFO_Rd_count_minus1 <= raw_data_count_corr_minus1;
SFIFO_DValid <= sig_sfifo_rdack; --sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= SFIFO_Rd_en; -- or autoread;
------------------------------------------------------------
-- Instance: I_SYNC_FIFOGEN_FIFO
--
-- Description:
-- Instance for the synchronous fifo from proc common.
--
------------------------------------------------------------
I_SYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_9.sync_fifo_fg
generic map(
C_FAMILY => C_FAMILY, -- requred for FIFO Gen
C_DCOUNT_WIDTH => C_DATA_CNT_WIDTH,
C_ENABLE_RLOCS => 0,
C_HAS_DCOUNT => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 1,
C_HAS_WR_ERR => 0,
C_MEMORY_TYPE => C_USE_BLKMEM,
C_PORTS_DIFFER => 0,
C_RD_ACK_LOW => 0,
C_READ_DATA_WIDTH => C_DWIDTH,
C_READ_DEPTH => C_DEPTH,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_WRITE_DATA_WIDTH => C_DWIDTH,
C_WRITE_DEPTH => C_DEPTH,
C_PRELOAD_REGS => 1, -- 1 = first word fall through
C_PRELOAD_LATENCY => 0, -- 0 = first word fall through
C_USE_EMBEDDED_REG => 1, -- 0 ;
C_XPM_FIFO => 1
)
port map(
Clk => SFIFO_Clk,
Sinit => SFIFO_Sinit,
Din => write_data_lil_end,
Wr_en => SFIFO_Wr_en,
Rd_en => fifo_read_enable,
Dout => read_data_lil_end,
Almost_full => open,
Full => SFIFO_Full,
Empty => sig_SFIFO_empty,
Rd_ack => sig_sfifo_rdack,
Wr_ack => open,
Rd_err => open,
Wr_err => open,
Data_count => raw_data_cnt_lil_end
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Read Ack assert & hold logic Needed because....
-------------------------------------------------------------------------------
-- 1) The CoreGen Sync FIFO has to be read once to get valid
-- data to the read data port.
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been used. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
SFIFO_Sinit or
SFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_sfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (SFIFO_Clk)
begin
if (SFIFO_Clk'event and SFIFO_Clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_SFIFO_empty = '0') -- and the FIFO is not empty
Else '0';
raw_data_count_int <= CONV_INTEGER(raw_data_cnt_lil_end);
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_EMPTY
--
-- If Generate Description:
-- This IFGen corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
INCLUDE_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 1) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
Signal raw_data_count_int_corr_minus1 : integer := 0;
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT_IAE
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and includes the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT_IAE : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
raw_data_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
raw_data_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
raw_data_count_int_corr_minus1 <= raw_data_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT_IAE;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
raw_data_count_corr_minus1 <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr_minus1,
C_DATA_CNT_WIDTH);
end generate INCLUDE_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_EMPTY
--
-- If Generate Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
------------------------------------------------------------
OMIT_ALMOST_EMPTY : if (C_NEED_ALMOST_EMPTY = 0) generate
-- local signals
Signal raw_data_count_int_corr : integer := 0;
begin
corrected_almost_empty <= '0'; -- always low
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function and omits the generation of the
-- Almost_Empty flag.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_SFIFO_empty,
raw_data_count_int)
begin
if (sig_rddata_valid = '0') then
raw_data_count_int_corr <= 0;
corrected_empty <= '1';
elsif (sig_SFIFO_empty = '1') then -- rddata valid and fifo empty
raw_data_count_int_corr <= 1;
corrected_empty <= '0';
Elsif (raw_data_count_int = 1) Then -- rddata valid and fifo almost empty
raw_data_count_int_corr <= 2;
corrected_empty <= '0';
else -- rddata valid and modify rd count from FIFO
raw_data_count_int_corr <= raw_data_count_int+1;
corrected_empty <= '0';
end if;
end process CORRECT_RD_CNT;
raw_data_count_corr <= CONV_STD_LOGIC_VECTOR(raw_data_count_int_corr,
C_DATA_CNT_WIDTH);
end generate OMIT_ALMOST_EMPTY;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Includes the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
INCLUDE_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 1) generate
-- Local Constants
Constant ALMOST_FULL_VALUE : integer := 2**(C_DATA_CNT_WIDTH-1)-1;
begin
SFIFO_Almost_full <= '1'
When raw_data_count_int = ALMOST_FULL_VALUE
Else '0';
end generate INCLUDE_ALMOST_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_ALMOST_FULL
--
-- If Generate Description:
-- This IfGen Omits the generation of the Amost_Full flag.
--
--
------------------------------------------------------------
OMIT_ALMOST_FULL : if (C_NEED_ALMOST_FULL = 0) generate
begin
SFIFO_Almost_full <= '0'; -- always low
end generate OMIT_ALMOST_FULL;
end imp;
-------------------------------------------------------------------------------
-- axi_cdma_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_sf.vhd
--
-- Description:
-- This file implements the AXI CDMA store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control interfaces. The design is such that predictive address
-- pipelining can be supported on the AXI Read Bus without over-commiting
-- the internal Data FIFO and potentially throttling the Read Data Channel
-- if the Data FIFO goes full. On the AXI Write side, the Write Master is
-- only allowed to post AXI WRite Requests if the associated write data needed
-- to complete the Write Data transfer is present in the Data FIFO. In
-- addition, the Write side logic is such that Write transfer requests can
-- be pipelined to the AXI bus based on the Data FIFO contents but ahead of
-- the actual Write Data transfers.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
use lib_pkg_v1_0_2.lib_pkg.clog2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library axi_cdma_v4_1_14;
use axi_cdma_v4_1_14.axi_cdma_sfifo_autord;
-------------------------------------------------------------------------------
entity axi_cdma_sf is
generic (
C_WR_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter indicates the depth of the DataMover
-- write address pipelining queues for the Main data transport
-- channels. The effective address pipelining on the AXI4
-- Write Address Channel will be the value assigned plus 2.
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max burst length being used by the external
-- AXI4 Master for each AXI4 transfer request.
C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- Indicates if the external Master is utilizing a DRE on
-- the stream input to this module.
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock input
aclk : in std_logic;
-- Primary synchronization clock for the Master side
-- interface and internal logic. It is also used
-- for the User interface synchronization when
-- C_STSCMD_IS_ASYNC = 0.
-- Reset input
reset : in std_logic;
-- Reset used for the internal syncronization logic
-- DataMover Read Side Address Pipelining Control Interface ---------------
ok_to_post_rd_addr : Out Std_logic;
-- Indicates that the transfer token pool has at least
-- one token available to borrow
rd_addr_posted : In std_logic;
-- Indication that a read address has been posted to AXI4
rd_xfer_cmplt : In std_logic;
-- Indicates that the Datamover has completed a Read Data
-- transfer on the AXI4
-- Read Side Stream In from DataMover MM2S -----------------------------------
sf2sin_tready : Out Std_logic;
-- DRE Stream READY input
sin2sf_tvalid : In std_logic;
-- DRE Stream VALID Output
sin2sf_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0);
-- DRE Stream DATA input
sin2sf_tkeep : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- DRE Stream STRB input
sin2sf_tlast : In std_logic;
-- DRE Xfer LAST input
-- DataMover Write Side Address Pipelining Control Interface --------------
ok_to_post_wr_addr : Out Std_logic;
-- Indicates that the internal FIFO has enough data
-- physically present to supply one more max length
-- burst transfer or a completion burst
-- (tlast asserted)
wr_addr_posted : In std_logic;
-- Indication that a write address has been posted to AXI4
wr_xfer_cmplt : In Std_logic;
-- Indicates that the Datamover has completed a Write Data
-- transfer on the AXI4
wr_ld_nxt_len : in std_logic;
-- Active high pulse indicating a new transfer LEN qualifier
-- has been queued to the DataMover Write Data Controller
wr_len : in std_logic_vector(7 downto 0);
-- The actual LEN qualifier value that has been queued to the
-- DataMover Write Data Controller
-- Write Side Stream Out to DataMover S2MM -------------------------------
sout2sf_tready : In std_logic;
-- Write READY input from the Stream Master
sf2sout_tvalid : Out std_logic;
-- Write VALID output to the Stream Master
sf2sout_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0);
-- Write DATA output to the Stream Master
sf2sout_tkeep : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- Write DATA output to the Stream Master
sf2sout_tlast : Out std_logic
-- Write LAST output to the Stream Master
);
end entity axi_cdma_sf;
architecture implementation of axi_cdma_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbcntr_width
--
-- Function Description:
-- simple function to set the width of the burst counter
-- based on the parameterized max burst length.
--
-------------------------------------------------------------------
function funct_get_dbcntr_width (max_burst_length : integer)
return integer is
Variable temp_width : integer := 0;
begin
case max_burst_length is
when 2 =>
temp_width := 1;
when 4 =>
temp_width := 2;
when 8 =>
temp_width := 3;
when 16 =>
temp_width := 4;
when 32 =>
temp_width := 5;
when 64 =>
temp_width := 6;
when 128 =>
temp_width := 7;
when others => -- 256 beats
temp_width := 8;
end case;
Return (temp_width);
end function funct_get_dbcntr_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_pwr2_depth
--
-- Function Description:
-- Rounds up to the next power of 2 depth value in an input
-- range of 1 to 8192
--
-------------------------------------------------------------------
function funct_get_pwr2_depth (min_depth : integer) return integer is
Variable var_temp_depth : Integer := 16;
begin
if (min_depth = 1) then
var_temp_depth := 1;
elsif (min_depth = 2) then
var_temp_depth := 2;
elsif (min_depth <= 4) then
var_temp_depth := 4;
elsif (min_depth <= 8) then
var_temp_depth := 8;
elsif (min_depth <= 16) then
var_temp_depth := 16;
elsif (min_depth <= 32) then
var_temp_depth := 32;
elsif (min_depth <= 64) then
var_temp_depth := 64;
elsif (min_depth <= 128) then
var_temp_depth := 128;
elsif (min_depth <= 256) then
var_temp_depth := 256;
elsif (min_depth <= 512) then
var_temp_depth := 512;
elsif (min_depth <= 1024) then
var_temp_depth := 1024;
elsif (min_depth <= 2048) then
var_temp_depth := 2048;
elsif (min_depth <= 4096) then
var_temp_depth := 4096;
else -- assume 8192 depth
var_temp_depth := 8192;
end if;
Return (var_temp_depth);
end function funct_get_pwr2_depth;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_wrcnt_lsrip
--
-- Function Description:
-- Calculates the ls index of the upper slice of the data fifo
-- write count needed to repesent one max burst worth of data
-- present in the fifo.
--
-------------------------------------------------------------------
function funct_get_wrcnt_lsrip (max_burst_dbeats : integer) return integer is
Variable temp_ls_index : Integer := 0;
begin
if (max_burst_dbeats <= 2) then
temp_ls_index := 1;
elsif (max_burst_dbeats <= 4) then
temp_ls_index := 2;
elsif (max_burst_dbeats <= 8) then
temp_ls_index := 3;
elsif (max_burst_dbeats <= 16) then
temp_ls_index := 4;
elsif (max_burst_dbeats <= 32) then
temp_ls_index := 5;
elsif (max_burst_dbeats <= 64) then
temp_ls_index := 6;
elsif (max_burst_dbeats <= 128) then
temp_ls_index := 7;
else
temp_ls_index := 8;
end if;
Return (temp_ls_index);
end function funct_get_wrcnt_lsrip;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stall_thresh
--
-- Function Description:
-- Calculates the Stall threshold for the input side of the Data
-- FIFO. If DRE is being used by the DataMover, then the threshold
-- must be reduced to account for the potential of an extra write
-- databeat per request (DRE alignment dependent).
--
-------------------------------------------------------------------
function funct_get_stall_thresh (dre_is_used : integer;
max_xfer_length : integer;
data_fifo_depth : integer;
pipeline_delay_clks : integer;
fifo_settling_clks : integer) return integer is
Constant DRE_PIPE_DELAY : integer := 2; -- clks
Variable var_num_max_xfers_allowed : Integer := 0;
Variable var_dre_dbeat_overhead : Integer := 0;
Variable var_delay_fudge_factor : Integer := 0;
Variable var_thresh_headroom : Integer := 0;
Variable var_stall_thresh : Integer := 0;
begin
var_num_max_xfers_allowed := data_fifo_depth/max_xfer_length;
var_dre_dbeat_overhead := var_num_max_xfers_allowed * dre_is_used;
var_delay_fudge_factor := (dre_is_used * DRE_PIPE_DELAY) +
pipeline_delay_clks +
fifo_settling_clks;
var_thresh_headroom := max_xfer_length +
var_dre_dbeat_overhead +
var_delay_fudge_factor;
-- Scale the result to be in max transfer length increments
var_stall_thresh := (data_fifo_depth - var_thresh_headroom)/max_xfer_length;
Return (var_stall_thresh);
end function funct_get_stall_thresh;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant WSTB_WIDTH : integer := C_STREAM_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_STREAM_DWIDTH+
WSTB_WIDTH +
TLAST_WIDTH;
Constant DATA_OUT_MSB_INDEX : integer := C_STREAM_DWIDTH-1;
Constant DATA_OUT_LSB_INDEX : integer := 0;
Constant TSTRB_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant TSTRB_OUT_MSB_INDEX : integer := (TSTRB_OUT_LSB_INDEX+WSTB_WIDTH)-1;
Constant TLAST_OUT_INDEX : integer := TSTRB_OUT_MSB_INDEX+1;
Constant DBEAT_CNTR_WIDTH : integer := funct_get_dbcntr_width(C_MAX_BURST_LEN);
Constant MAX_BURST_DBEATS : Unsigned(DBEAT_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, DBEAT_CNTR_WIDTH);
Constant DBC_ONE : Unsigned(DBEAT_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DBEAT_CNTR_WIDTH);
Constant TOKEN_POOL_SIZE : integer := C_SF_FIFO_DEPTH / C_MAX_BURST_LEN;
Constant TOKEN_CNTR_WIDTH : integer := clog2(TOKEN_POOL_SIZE)+1;
Constant TOKEN_CNT_ZERO : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_ONE : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_MAX : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(TOKEN_POOL_SIZE, TOKEN_CNTR_WIDTH);
Constant THRESH_COMPARE_WIDTH : integer := TOKEN_CNTR_WIDTH+2;
Constant RD_PATH_PIPE_DEPTH : integer := 2; -- clocks excluding DRE
Constant WRCNT_SETTLING_TIME : integer := 2; -- data fifo push or pop settling clocks
Constant RD_ADDR_POST_STALL_THRESH : integer :=
funct_get_stall_thresh(C_DRE_IS_USED ,
C_MAX_BURST_LEN ,
C_SF_FIFO_DEPTH ,
RD_PATH_PIPE_DEPTH ,
WRCNT_SETTLING_TIME);
Constant RD_ADDR_POST_STALL_THRESH_US : Unsigned(THRESH_COMPARE_WIDTH-1 downto 0) :=
TO_UNSIGNED(RD_ADDR_POST_STALL_THRESH ,
THRESH_COMPARE_WIDTH);
Constant WR_LEN_FIFO_DWIDTH : integer := 8;
Constant WR_LEN_FIFO_DEPTH : integer := funct_get_pwr2_depth(C_WR_ADDR_PIPE_DEPTH + 2);
Constant LEN_CNTR_WIDTH : integer := 8;
Constant LEN_CNT_ZERO : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, LEN_CNTR_WIDTH);
Constant LEN_CNT_ONE : Unsigned(LEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, LEN_CNTR_WIDTH);
Constant WR_XFER_CNTR_WIDTH : integer := 8;
Constant WR_XFER_CNT_ZERO : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, WR_XFER_CNTR_WIDTH);
Constant WR_XFER_CNT_ONE : Unsigned(WR_XFER_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, WR_XFER_CNTR_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector(WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cnt_unsgnd : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_wrcnt_mblen_slice : unsigned(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX) := (others => '0');
signal sig_ok_to_post_rd_addr : std_logic := '0';
signal sig_rd_addr_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_taking_last_token : std_logic := '0';
signal sig_stall_rd_addr_posts : std_logic := '0';
signal sig_incr_token_cntr : std_logic := '0';
signal sig_decr_token_cntr : std_logic := '0';
signal sig_token_eq_max : std_logic := '0';
signal sig_token_eq_zero : std_logic := '0';
signal sig_token_eq_one : std_logic := '0';
signal sig_token_cntr : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_tokens_commited : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_commit_plus_actual : unsigned(THRESH_COMPARE_WIDTH-1 downto 0) := (others => '0');
signal sig_ok_to_post_wr_addr : std_logic := '0';
signal sig_wr_addr_posted : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_wr_ld_nxt_len : std_logic := '0';
signal sig_push_len_fifo : std_logic := '0';
signal sig_pop_len_fifo : std_logic := '0';
signal sig_len_fifo_full : std_logic := '0';
signal sig_len_fifo_empty : std_logic := '0';
signal sig_len_fifo_data_in : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_data_out : std_logic_vector(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_len_fifo_len_out_un : unsigned(WR_LEN_FIFO_DWIDTH-1 downto 0) := (others => '0');
signal sig_uncom_wrcnt : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_sub_len_uncom_wrcnt : std_logic := '0';
signal sig_incr_uncom_wrcnt : std_logic := '0';
signal sig_resized_fifo_len : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_num_wr_dbeats_needed : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_enough_dbeats_rcvd : std_logic := '0';
begin --(architecture implementation)
-- Read Side (MM2S) Control Flags port connections
ok_to_post_rd_addr <= sig_ok_to_post_rd_addr ;
sig_rd_addr_posted <= rd_addr_posted ;
sig_rd_xfer_cmplt <= rd_xfer_cmplt ;
-- Write Side (S2MM) Control Flags port connections
ok_to_post_wr_addr <= sig_ok_to_post_wr_addr ;
sig_wr_addr_posted <= wr_addr_posted ;
sig_wr_xfer_cmplt <= wr_xfer_cmplt ;
sig_wr_ld_nxt_len <= wr_ld_nxt_len ;
sig_len_fifo_data_in <= wr_len ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_strm_sin_ready <= not(sig_data_fifo_full); -- Throttle if Read Side Data fifo goes full.
-- This should never happen if read address
-- posting control is working properly.
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
----------------------------------------------------------------
-- Token Counter Logic
-- Predicting fifo space availability at some point in the
-- future is based on managing a virtual pool of transfer tokens.
-- A token represents 1 max length burst worth of space in the
-- Data FIFO.
----------------------------------------------------------------
-- calculate how many tokens are commited to pending transfers
sig_tokens_commited <= TOKEN_CNT_MAX - sig_token_cntr;
-- Decrement the token counter when a token is
-- borrowed
sig_decr_token_cntr <= '1'
when (sig_rd_addr_posted = '1' and
sig_token_eq_zero = '0')
else '0';
-- Increment the token counter when a
-- token is returned.
sig_incr_token_cntr <= '1'
when (sig_rd_xfer_cmplt = '1' and
sig_token_eq_max = '0')
else '0';
-- Detect when the xfer token count is at max value
sig_token_eq_max <= '1'
when (sig_token_cntr = TOKEN_CNT_MAX)
Else '0';
-- Detect when the xfer token count is at one
sig_token_eq_one <= '1'
when (sig_token_cntr = TOKEN_CNT_ONE)
Else '0';
-- Detect when the xfer token count is at zero
sig_token_eq_zero <= '1'
when (sig_token_cntr = TOKEN_CNT_ZERO)
Else '0';
-- Look ahead to see if the xfer token pool is going empty
sig_taking_last_token <= '1'
When (sig_token_eq_one = '1' and
sig_rd_addr_posted = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_CMTR
--
-- Process Description:
-- Implements the Token counter
--
-------------------------------------------------------------
IMP_TOKEN_CMTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' ) then
sig_token_cntr <= TOKEN_CNT_MAX;
elsif (sig_incr_token_cntr = '1' and
sig_decr_token_cntr = '0') then
sig_token_cntr <= sig_token_cntr + TOKEN_CNT_ONE;
elsif (sig_incr_token_cntr = '0' and
sig_decr_token_cntr = '1') then
sig_token_cntr <= sig_token_cntr - TOKEN_CNT_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_TOKEN_CMTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_AVAIL_FLAG
--
-- Process Description:
-- Implements the flag indicating that the AXI Read Master
-- can post a read address request on the AXI4 bus.
--
-- Read address posting can occur if:
--
-- - The write side LEN fifo is not empty.
-- - The commited plus actual Data FIFO space is less than
-- the stall threshold (a max length read burst can fit
-- in the data FIFO without overflow).
-- - The max allowed commited read count has not been reached.
--
-- The flag is cleared after each address has been posted to
-- ensure a second unauthotized post occurs.
-------------------------------------------------------------
IMP_TOKEN_AVAIL_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_rd_addr_posted = '1') then
sig_ok_to_post_rd_addr <= '0';
else
sig_ok_to_post_rd_addr <= not(sig_stall_rd_addr_posts) and -- the commited Data FIFO space is approaching full
not(sig_token_eq_zero) and -- max allowed pending reads has not been reached
not(sig_taking_last_token); -- the max allowed pending reads is about to be reached
end if;
end if;
end process IMP_TOKEN_AVAIL_FLAG;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
-- FIFO Output to output stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid ;
sig_sf2sout_tdata <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_sf2sout_tkeep <= sig_data_fifo_data_out(TSTRB_OUT_MSB_INDEX downto
TSTRB_OUT_LSB_INDEX);
sig_sf2sout_tlast <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
-- Stall Threshold calculations
sig_fifo_wr_cnt_unsgnd <= UNSIGNED(sig_data_fifo_wr_cnt);
sig_wrcnt_mblen_slice <= sig_fifo_wr_cnt_unsgnd(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX);
sig_commit_plus_actual <= RESIZE(sig_tokens_commited, THRESH_COMPARE_WIDTH) +
RESIZE(sig_wrcnt_mblen_slice, THRESH_COMPARE_WIDTH);
-- Compare the commited read space plus the actual used space against the
-- stall threshold. Assert the read address posting stall flag if the
-- threshold is met or exceeded.
sig_stall_rd_addr_posts <= '1'
when (sig_commit_plus_actual > RD_ADDR_POST_STALL_THRESH_US)
Else '0';
-- FIFO Rd/WR Controls
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
sig_pop_data_fifo <= sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= sin2sf_tlast &
sin2sf_tkeep &
sin2sf_tdata;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_cdma_v4_1_14.axi_cdma_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
--------------------------------------------------------------------
-- Write Side Control Logic
--------------------------------------------------------------------
-- Convert the LEN fifo data output to unsigned
sig_len_fifo_len_out_un <= unsigned(sig_len_fifo_data_out);
-- Resize the unsigned LEN output to the Data FIFO writecount width
sig_resized_fifo_len <= RESIZE(sig_len_fifo_len_out_un , DATA_FIFO_CNT_WIDTH);
-- The actual number of databeats needed for the queued write transfer
-- is the current LEN fifo output plus 1.
sig_num_wr_dbeats_needed <= sig_resized_fifo_len + UNCOM_WRCNT_1;
-- Compare the uncommited receved data beat count to that needed
-- for the next queued write request.
sig_enough_dbeats_rcvd <= '1'
When (sig_num_wr_dbeats_needed <= sig_uncom_wrcnt)
else '0';
-- Increment the uncommited databeat counter on a good input
-- stream databeat (Read Side of SF)
sig_incr_uncom_wrcnt <= sig_good_sin_strm_dbeat;
-- Subtract the current number of databeats needed from the
-- uncommited databeat counter when the associated transfer
-- address/qualifiers have been posted to the AXI Write
-- Address Channel
sig_sub_len_uncom_wrcnt <= sig_wr_addr_posted;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_UNCOM_DBEAT_CNTR
--
-- Process Description:
-- Implements the counter that keeps track of the received read
-- data beat count that has not been commited to a transfer on
-- the write side with a Write Address posting.
--
-------------------------------------------------------------
IMP_UNCOM_DBEAT_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_uncom_wrcnt <= UNCOM_WRCNT_0;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_resized_fifo_len;
elsif (sig_incr_uncom_wrcnt = '1' and
sig_sub_len_uncom_wrcnt = '0') then
sig_uncom_wrcnt <= sig_uncom_wrcnt + UNCOM_WRCNT_1;
elsif (sig_incr_uncom_wrcnt = '0' and
sig_sub_len_uncom_wrcnt = '1') then
sig_uncom_wrcnt <= sig_uncom_wrcnt - sig_num_wr_dbeats_needed;
else
null; -- hold current value
end if;
end if;
end process IMP_UNCOM_DBEAT_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_ADDR_POST_FLAG
--
-- Process Description:
-- Implements the flag indicating that the pending write
-- transfer's data beat count has been received on the input
-- side of the Data FIFO. This means the Write side can post
-- the associated write address to the AXI4 bus and the
-- associated write data transfer can complete without CDMA
-- throttling the Write Data Channel.
--
-- The flag is cleared immediately after an address is posted
-- to prohibit a second unauthorized posting while the control
-- logic stabilizes to the next LEN FIFO value
--.
-------------------------------------------------------------
IMP_WR_ADDR_POST_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_wr_addr_posted = '1') then
sig_ok_to_post_wr_addr <= '0';
else
sig_ok_to_post_wr_addr <= not(sig_len_fifo_empty) and
sig_enough_dbeats_rcvd;
end if;
end if;
end process IMP_WR_ADDR_POST_FLAG;
-------------------------------------------------------------
-- LEN FIFO logic
sig_push_len_fifo <= sig_wr_ld_nxt_len and
not(sig_len_fifo_full);
sig_pop_len_fifo <= wr_addr_posted and
not(sig_len_fifo_empty);
------------------------------------------------------------
-- Instance: I_WR_LEN_FIFO
--
-- Description:
-- Implement the LEN FIFO using SRL FIFO elements
--
------------------------------------------------------------
I_WR_LEN_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => WR_LEN_FIFO_DWIDTH ,
C_DEPTH => WR_LEN_FIFO_DEPTH ,
C_FAMILY => C_FAMILY
)
port map (
Clk => aclk ,
Reset => reset ,
FIFO_Write => sig_push_len_fifo ,
Data_In => sig_len_fifo_data_in ,
FIFO_Read => sig_pop_len_fifo ,
Data_Out => sig_len_fifo_data_out ,
FIFO_Empty => sig_len_fifo_empty ,
FIFO_Full => sig_len_fifo_full ,
Addr => open
);
end implementation;
-------------------------------------------------------------------------------
-- axi_cdma_simple_cntlr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_simple_cntlr.vhd
-- Description: This entity is reset module entity for the AXI DMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_cdma_simple_cntlr is
Generic (
C_DM_CMD_WIDTH : integer := 72;
C_DM_DATA_WIDTH : integer := 32;
C_DM_MM2S_STATUS_WIDTH : integer := 8;
C_DM_S2MM_STATUS_WIDTH : integer := 8;
C_ADDR_WIDTH : integer := 32;
C_BTT_WIDTH : integer := 23;
C_FAMILY : String := "virtex7"
);
port (
-- Clock Input
axi_aclk : in std_logic ;
-- Reset Input (active high)
axi_reset : in std_logic ;
-- Halt request from the Reset module
rst2cntlr_halt : in std_logic ;
-- Halt complete status to the Reset module
cntlr2rst_halt_cmplt : out std_logic ;
-- Register Module transfer Start Control
reg2cntlr_go : in std_logic ;
-- Register Module SG Mode Control
reg2cntlr_sg_mode : in std_logic ;
-- MM2S Type of Burst, 1 is increment, 0 is fixed
burst_type_read : in std_logic;
-- S2MM Type of Burst, 1 is increment, 0 is fixed
burst_type_write : in std_logic;
-- Transfer Source address from the Register Module
reg2cntlr_src_addr : in std_logic_vector(C_ADDR_WIDTH-1 downto 0);
-- Transfer Destination address from the Register Module
reg2cntlr_dest_addr : in std_logic_vector(C_ADDR_WIDTH-1 downto 0);
-- Transfer BTT from the Register Module
reg2cntlr_btt : in std_logic_vector(C_BTT_WIDTH-1 downto 0);
-- Register Module Status Register Idle Bit set control
cntlr2reg_idle_set : out std_logic ;
-- Register Module Status Register Idle Bit clear control
cntlr2reg_idle_clr : out std_logic ;
-- Register Module Status Register Interrupt on Complete Bit set control
cntlr2reg_iocirpt_set : out std_logic ;
-- Register Module DataMover decode Error Status bit set control
cntlr2reg_decerr_set : out std_logic ;
-- Register Module DataMover slave Error Status bit set control
cntlr2reg_slverr_set : out std_logic ;
-- Register Module DataMover internal Error Status bit set control
cntlr2reg_interr_set : out std_logic ;
-- DataMover MM2S Command ready (AXI Stream)
mm2s2cntl_cmd_tready : in std_logic ;
-- DataMover MM2S Command tvalid (AXI Stream)
cntl2mm2s_cmd_tvalid : out std_logic ;
-- DataMover MM2S Command Data (AXI Stream)
cntl2mm2s_cmd_tdata : out std_logic_vector(C_DM_CMD_WIDTH-1 downto 0);
-- DataMover MM2S Status ready (AXI Stream)
cntl2mm2s_sts_tready : out std_logic ;
-- DataMover MM2S Status valid (AXI Stream)
mm2s2cntl_sts_tvalid : in std_logic ;
-- DataMover MM2S Status Data (AXI Stream)
mm2s2cntl_sts_tdata : in std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0);
-- DataMover MM2S Status strb (AXI Stream)
mm2s2cntl_sts_tstrb : in std_logic_vector((C_DM_MM2S_STATUS_WIDTH/8)-1 downto 0);
-- DataMover MM2S error discrete
mm2s2cntl_err : in std_logic ;
-- DataMover S2MM Command ready (AXI Stream)
s2mm2cntl_cmd_tready : in std_logic ;
-- DataMover S2MM Command tvalid (AXI Stream)
cntl2s2mm_cmd_tvalid : out std_logic ;
-- DataMover S2MM Command Data (AXI Stream)
cntl2s2mm_cmd_tdata : out std_logic_vector(C_DM_CMD_WIDTH-1 downto 0);
-- DataMover S2MM Status ready (AXI Stream)
cntl2s2mm_sts_tready : out std_logic ;
-- DataMover S2MM Status valid (AXI Stream)
s2mm2cntl_sts_tvalid : in std_logic ;
-- DataMover S2MM Status Data (AXI Stream)
s2mm2cntl_sts_tdata : in std_logic_vector(C_DM_S2MM_STATUS_WIDTH-1 downto 0);
-- DataMover S2MM error discrete
s2mm2cntl_sts_tstrb : in std_logic_vector((C_DM_S2MM_STATUS_WIDTH/8)-1 downto 0);
-- DataMover S2MM error discrete
s2mm2cntl_err : in std_logic
);
end axi_cdma_simple_cntlr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma_simple_cntlr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_calc_offset_bits
--
-- Function Description:
-- Calculates the width of the destination address offset bits
-- needed for populating the MM2S Command DSA field.
--
-------------------------------------------------------------------
function funct_calc_offset_bits (data_width : integer) return integer is
Variable lvar_bits_needed : Integer := 0;
begin
case data_width is
when 32 =>
lvar_bits_needed := 2;
when 64 =>
lvar_bits_needed := 3;
when 128 =>
lvar_bits_needed := 4;
when 256 =>
lvar_bits_needed := 5;
when 512 =>
lvar_bits_needed := 6;
when others => -- 256 bits
lvar_bits_needed := 5;
end case;
Return (lvar_bits_needed);
end function funct_calc_offset_bits;
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant NO_SYNCHRONIZERS : integer := 0;
Constant POSITIVE_EDGE_TRIGGER : integer := 1;
Constant NEGATIVE_EDGE_TRIGGER : integer := 0;
Constant TWO_CLKS : integer := 2;
Constant ONE_CLK : integer := 1;
Constant CMD_TAG_WIDTH : integer := 4;
Constant CMD_DSA_WIDTH : integer := 6;
Constant DSA_ADDR_OFFSET_WIDTH : integer := funct_calc_offset_bits(C_DM_DATA_WIDTH);
Constant CMD_RSVD : std_logic_vector(3 downto 0) := (others => '0');
Constant CMD_DSA_ZEROED : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
Constant BTT_ZERO : std_logic_vector(C_BTT_WIDTH-1 downto 0) := (others => '0');
Constant STS_INTERR_INDEX : integer := 4;
Constant STS_DECERR_INDEX : integer := 5;
Constant STS_SLVERR_INDEX : integer := 6;
Constant STS_OK_INDEX : integer := 7;
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type cdma_sm_type is ( INIT ,
WAIT_FOR_GO ,
LD_DM_CMD ,
GET_MM2S_STATUS,
GET_S2MM_STATUS,
SCORE_STATUS ,
XFER_DONE ,
ERROR_TRAP
);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sig_sm_state : cdma_sm_type := INIT;
signal sig_sm_state_ns : cdma_sm_type := INIT;
signal sig_sm_ld_cmd : std_logic := '0';
signal sig_sm_ld_cmd_ns : std_logic := '0';
signal sig_sm_set_idle : std_logic := '0';
signal sig_sm_set_idle_ns : std_logic := '0';
signal sig_sm_clr_idle : std_logic := '0';
signal sig_sm_clr_idle_ns : std_logic := '0';
signal sig_sm_set_ioc : std_logic := '0';
signal sig_sm_set_ioc_ns : std_logic := '0';
signal sig_sm_set_err : std_logic := '0';
signal sig_sm_set_err_ns : std_logic := '0';
signal sig_sm_pop_mm2s_sts : std_logic := '0';
signal sig_sm_pop_mm2s_sts_ns : std_logic := '0';
signal sig_sm_pop_s2mm_sts : std_logic := '0';
signal sig_sm_pop_s2mm_sts_ns : std_logic := '0';
signal sig_mm2s_s2mm_cmd_rdy : std_logic := '0';
signal sig_cdma_xfer_go : std_logic := '0';
signal sig_mm2s_cmd : std_logic_vector(C_DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s_cmd_valid : std_logic := '0';
signal sig_mm2s_cmd_ready : std_logic := '0';
signal sig_mm2s_sts_tready : std_logic ;
signal sig_mm2s_sts_tvalid : std_logic ;
signal sig_mm2s_sts_tdata : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0);
signal sig_mm2s_sts_tstrb : std_logic_vector((C_DM_MM2S_STATUS_WIDTH/8)-1 downto 0);
signal sig_s2mm_cmd : std_logic_vector(C_DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cmd_valid : std_logic := '0';
signal sig_s2mm_cmd_ready : std_logic := '0';
signal sig_s2mm_sts_tready : std_logic ;
signal sig_s2mm_sts_tvalid : std_logic ;
signal sig_s2mm_sts_tdata : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0);
signal sig_s2mm_sts_tstrb : std_logic_vector((C_DM_MM2S_STATUS_WIDTH/8)-1 downto 0);
signal sig_cmd_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_cntr : unsigned(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s_dsa_offset : std_logic_vector(DSA_ADDR_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s_dsa_field : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s_status_reg : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_status_reg : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s_slverr : std_logic := '0';
signal sig_mm2s_decerr : std_logic := '0';
signal sig_mm2s_interr : std_logic := '0';
signal sig_mm2s_ok : std_logic := '0';
signal sig_s2mm_slverr : std_logic := '0';
signal sig_s2mm_decerr : std_logic := '0';
signal sig_s2mm_interr : std_logic := '0';
signal sig_s2mm_ok : std_logic := '0';
signal sig_mm2s2cntl_err : std_logic := '0';
signal sig_s2mm2cntl_err : std_logic := '0';
signal sig_halt_request : std_logic := '0';
signal sig_halt_cmplt_reg : std_logic := '0';
signal sig_composite_error : std_logic := '0';
signal type_of_burst : std_logic;
signal type_of_burst_wr : std_logic;
signal ZERO_WORD : std_logic_vector (31 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Misc logic
-------------------------------------------------------------------------------
-- GO signal to start the transfer from the Register Module
sig_cdma_xfer_go <= reg2cntlr_go;
-- See if DataMover is ready for next command
sig_mm2s_s2mm_cmd_rdy <= sig_mm2s_cmd_ready and
sig_s2mm_cmd_ready;
-- Since only 1 parent command per CDMA transfer is allowed, a revolving
-- TAG count is not needed for debug support.
sig_cmd_tag <= (others => '0');
-------------------------------------------------------------------------------
-- MM2S Command Generation
-------------------------------------------------------------------------------
cntl2mm2s_cmd_tdata <= sig_mm2s_cmd ;
cntl2mm2s_cmd_tvalid <= sig_mm2s_cmd_valid ;
sig_mm2s_cmd_ready <= mm2s2cntl_cmd_tready ;
sig_mm2s_cmd_valid <= sig_sm_ld_cmd ;
type_of_burst <= '1' and (not burst_type_read);
-- Formulate the MM2S Command
sig_mm2s_cmd <= CMD_RSVD & -- reserved
sig_cmd_tag & -- Tag
reg2cntlr_src_addr & -- Address
'1' & -- DRR bit
'1' & -- EOF bit
sig_mm2s_dsa_field & -- DSA Field Assignment
type_of_burst &
-- '1' & -- Incrementing burst type
reg2cntlr_btt ; -- BTT
-- Rip the Destnation address offset bits
--ORIGINAL : if C_DM_DATA_WIDTH <= 64 generate
--begin
-- Rip the Destnation address offset bits
sig_mm2s_dsa_offset <= reg2cntlr_dest_addr(DSA_ADDR_OFFSET_WIDTH-1 downto 0);
--end generate ORIGINAL;
--NEWDRE : if C_DM_DATA_WIDTH > 64 generate
--begin
-- -- Rip the Destnation address offset bits
-- sig_mm2s_dsa_offset <= (others => '0');
--end generate NEWDRE;
-- Size the dest addr offset to the DSA field width
sig_mm2s_dsa_field <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_mm2s_dsa_offset), CMD_DSA_WIDTH));
-------------------------------------------------------------------------------
-- MM2S Status Reg and logic
-------------------------------------------------------------------------------
cntl2mm2s_sts_tready <= sig_sm_pop_mm2s_sts ;
sig_mm2s_sts_tvalid <= mm2s2cntl_sts_tvalid ;
sig_mm2s_sts_tdata <= mm2s2cntl_sts_tdata ;
sig_mm2s_sts_tstrb <= mm2s2cntl_sts_tstrb ;
-- DataMover MM2S Error discrete
sig_mm2s2cntl_err <= mm2s2cntl_err ;
-- Rip the status bits from the status register
sig_mm2s_interr <= sig_mm2s_status_reg(STS_INTERR_INDEX);
sig_mm2s_decerr <= sig_mm2s_status_reg(STS_DECERR_INDEX);
sig_mm2s_slverr <= sig_mm2s_status_reg(STS_SLVERR_INDEX);
sig_mm2s_ok <= sig_mm2s_status_reg(STS_OK_INDEX) ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MM2S_STATUS_REG
--
-- Process Description:
-- Implements the MM2S status reply holding register.
--
-------------------------------------------------------------
IMP_MM2S_STATUS_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_sm_set_idle = '1') then
sig_mm2s_status_reg <= (others => '0');
elsif (sig_sm_pop_mm2s_sts = '1') then
sig_mm2s_status_reg <= sig_mm2s_sts_tdata;
else
null; -- hold current state
end if;
end if;
end process IMP_MM2S_STATUS_REG;
-------------------------------------------------------------------------------
-- S2MM Command Generation
-------------------------------------------------------------------------------
cntl2s2mm_cmd_tdata <= sig_s2mm_cmd ;
cntl2s2mm_cmd_tvalid <= sig_s2mm_cmd_valid ;
sig_s2mm_cmd_ready <= s2mm2cntl_cmd_tready ;
sig_s2mm_cmd_valid <= sig_sm_ld_cmd ;
type_of_burst_wr <= '1' and (not burst_type_write);
-- Formulate the S2MM Command
sig_s2mm_cmd <= CMD_RSVD & -- reserved
sig_cmd_tag & -- Tag
reg2cntlr_dest_addr & -- Address
'1' & -- DRR bit
'1' & -- EOF bit
CMD_DSA_ZEROED & -- DSA Field Assignment
type_of_burst_wr & -- 1 is increment, 0 is fixed
-- '1' & -- Incrementing burst type
reg2cntlr_btt ; -- BTT
-------------------------------------------------------------------------------
-- S2MM Status Reg and logic
-------------------------------------------------------------------------------
cntl2s2mm_sts_tready <= sig_sm_pop_s2mm_sts ;
sig_s2mm_sts_tvalid <= s2mm2cntl_sts_tvalid ;
sig_s2mm_sts_tdata <= s2mm2cntl_sts_tdata ;
sig_s2mm_sts_tstrb <= s2mm2cntl_sts_tstrb ;
-- DataMover S2MM Error discrete
sig_s2mm2cntl_err <= s2mm2cntl_err ;
-- Rip the status bits from the status register
sig_s2mm_interr <= sig_s2mm_status_reg(STS_INTERR_INDEX);
sig_s2mm_decerr <= sig_s2mm_status_reg(STS_DECERR_INDEX);
sig_s2mm_slverr <= sig_s2mm_status_reg(STS_SLVERR_INDEX);
sig_s2mm_ok <= sig_s2mm_status_reg(STS_OK_INDEX) ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S2MM_STATUS_REG
--
-- Process Description:
-- Implements the MM2S status reply holding register.
--
-------------------------------------------------------------
IMP_S2MM_STATUS_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_sm_set_idle = '1') then
sig_s2mm_status_reg <= (others => '0');
elsif (sig_sm_pop_s2mm_sts = '1') then
sig_s2mm_status_reg <= sig_s2mm_sts_tdata;
else
null; -- hold current state
end if;
end if;
end process IMP_S2MM_STATUS_REG;
-------------------------------------------------------------------------------
-- Bit Set logic to Register Module
-------------------------------------------------------------------------------
-- Idle bit set and clear
cntlr2reg_idle_set <= sig_sm_set_idle;
cntlr2reg_idle_clr <= sig_sm_clr_idle;
-- Set the interrupt on Complete
cntlr2reg_iocirpt_set <= sig_sm_set_ioc;
-- Decode error set logic
cntlr2reg_decerr_set <= sig_sm_set_err and
(sig_s2mm_decerr or
sig_mm2s_decerr);
-- Slave error set logic
cntlr2reg_slverr_set <= sig_sm_set_err and
(sig_s2mm_slverr or
sig_mm2s_slverr);
-- Slave error set logic
cntlr2reg_interr_set <= sig_sm_set_err and
(sig_s2mm_interr or
sig_s2mm2cntl_err or
sig_mm2s_interr or
sig_mm2s2cntl_err);
-- Composite error flag used by the state machine
sig_composite_error <= sig_s2mm_decerr or
sig_mm2s_decerr or
sig_s2mm_slverr or
sig_mm2s_slverr or
sig_s2mm_interr or
sig_s2mm2cntl_err or
sig_mm2s_interr or
sig_mm2s2cntl_err;
-------------------------------------------------------------------------------
-- HALT Logic (Soft Reset)
-------------------------------------------------------------------------------
-- HALT logic
cntlr2rst_halt_cmplt <= sig_halt_cmplt_reg;
sig_halt_request <= rst2cntlr_halt;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_CMPLT_REG
--
-- Process Description:
-- Implements the MM2S status reply holding register.
--
-------------------------------------------------------------
IMP_HALT_CMPLT_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_halt_cmplt_reg <= '0';
elsif (sig_sm_set_idle = '1' and
sig_halt_request = '1') then
sig_halt_cmplt_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_HALT_CMPLT_REG;
-------------------------------------------------------------------------------
-- Simple DMA State Machine
-------------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_CDMA_SM_COMB
--
-- Process Description:
-- Implements the combinatorial portion of the CDMA simple
-- DMA state machine.
--
-------------------------------------------------------------
IMP_CDMA_SM_COMB : process (sig_sm_state ,
sig_cdma_xfer_go ,
sig_mm2s_s2mm_cmd_rdy,
sig_mm2s_sts_tvalid ,
sig_s2mm_sts_tvalid ,
sig_composite_error
)
begin
-- assign the default values
sig_sm_state_ns <= INIT ;
sig_sm_ld_cmd_ns <= '0' ;
sig_sm_set_idle_ns <= '0' ;
sig_sm_clr_idle_ns <= '0' ;
sig_sm_set_ioc_ns <= '0' ;
sig_sm_set_err_ns <= '0' ;
sig_sm_pop_mm2s_sts_ns <= '0' ;
sig_sm_pop_s2mm_sts_ns <= '0' ;
case sig_sm_state is
---------------------------------
when INIT =>
sig_sm_state_ns <= WAIT_FOR_GO ;
sig_sm_set_idle_ns <= '1' ;
---------------------------------
when WAIT_FOR_GO =>
if (sig_cdma_xfer_go = '1' and
sig_mm2s_s2mm_cmd_rdy = '1') then
sig_sm_state_ns <= LD_DM_CMD ;
sig_sm_clr_idle_ns <= '1' ;
else
sig_sm_state_ns <= WAIT_FOR_GO ;
end if;
---------------------------------
when LD_DM_CMD =>
sig_sm_state_ns <= GET_MM2S_STATUS ;
sig_sm_ld_cmd_ns <= '1' ;
---------------------------------
when GET_MM2S_STATUS =>
if (sig_mm2s_sts_tvalid = '1') then
sig_sm_state_ns <= GET_S2MM_STATUS ;
sig_sm_pop_mm2s_sts_ns <= '1' ;
else
sig_sm_state_ns <= GET_MM2S_STATUS ;
end if;
---------------------------------
when GET_S2MM_STATUS =>
if (sig_s2mm_sts_tvalid = '1') then
sig_sm_state_ns <= SCORE_STATUS ;
sig_sm_pop_s2mm_sts_ns <= '1' ;
else
sig_sm_state_ns <= GET_S2MM_STATUS ;
end if;
---------------------------------
when SCORE_STATUS =>
sig_sm_state_ns <= XFER_DONE ;
sig_sm_set_err_ns <= '1' ;
---------------------------------
when XFER_DONE =>
sig_sm_set_ioc_ns <= '1' ;
sig_sm_set_idle_ns <= '1' ;
if (sig_composite_error = '1') then
sig_sm_state_ns <= ERROR_TRAP ;
else
sig_sm_state_ns <= WAIT_FOR_GO ;
end if;
---------------------------------
when ERROR_TRAP =>
sig_sm_state_ns <= ERROR_TRAP ;
---------------------------------
when others =>
sig_sm_state_ns <= INIT ;
end case;
end process IMP_CDMA_SM_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CDMA_SM_REG
--
-- Process Description:
-- Implements the registered portion of the CDMA simple
-- DMA state machine.
--
-------------------------------------------------------------
IMP_CDMA_SM_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_halt_request = '1') then
sig_sm_state <= INIT ;
sig_sm_ld_cmd <= '0' ;
sig_sm_set_idle <= '1' ;
sig_sm_clr_idle <= '0' ;
sig_sm_set_ioc <= '0' ;
sig_sm_set_err <= '0' ;
sig_sm_pop_mm2s_sts <= '0' ;
sig_sm_pop_s2mm_sts <= '0' ;
else
sig_sm_state <= sig_sm_state_ns ;
sig_sm_ld_cmd <= sig_sm_ld_cmd_ns ;
sig_sm_set_idle <= sig_sm_set_idle_ns ;
sig_sm_clr_idle <= sig_sm_clr_idle_ns ;
sig_sm_set_ioc <= sig_sm_set_ioc_ns ;
sig_sm_set_err <= sig_sm_set_err_ns ;
sig_sm_pop_mm2s_sts <= sig_sm_pop_mm2s_sts_ns ;
sig_sm_pop_s2mm_sts <= sig_sm_pop_s2mm_sts_ns ;
end if;
end if;
end process IMP_CDMA_SM_REG;
end implementation;
-------------------------------------------------------------------------------
-- axi_cdma_simple_wrap
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_simple_wrap.vhd
--
-- Description:
--
-- This file is the module wrapper for the AXI CDMA core when parameterized
-- for only Simple Mode DMA operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- VHDL Libraries
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.max2;
library axi_datamover_v5_1_16;
use axi_datamover_v5_1_16.axi_datamover;
library axi_cdma_v4_1_14;
use axi_cdma_v4_1_14.axi_cdma_pkg.all;
use axi_cdma_v4_1_14.axi_cdma_reset;
use axi_cdma_v4_1_14.axi_cdma_reg_module;
use axi_cdma_v4_1_14.axi_cdma_simple_cntlr;
use axi_cdma_v4_1_14.axi_cdma_sf;
-------------------------------------------------------------------------------
entity axi_cdma_simple_wrap is
generic(
-----------------------------------------------------------------------
-- AXI Lite Register Interface Parameters
-----------------------------------------------------------------------
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 6;
-- Address width of the AXI Lite Interface (bits)
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32;
-- Data width of the AXI Lite Interface (bits)
C_AXI_LITE_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the AXI Lite Register interface needs to
-- be asynchronous to the CDMA data transport path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special AXI Lite clock for the axi lite interface
-----------------------------------------------------------------------
-- DataMover Memory Map Master Interface Parameters
-----------------------------------------------------------------------
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32;
-- DataMover Master AXI Memory Map Address Width (bits)
C_M_AXI_DATA_WIDTH : integer range 32 to 1024 := 32;
-- DataMover Master AXI Memory Map Data Width (bits)
C_M_AXI_MAX_BURST_LEN : integer range 2 to 256 := 16;
-- DataMover Maximum burst length to use for AXI MMAP requests
-- Allowed values are 16, 32, 64, 128, and 256 (data beats)
C_INCLUDE_DRE : integer range 0 to 1 := 0;
-- Include or exclude DataMover Data Realignment (DRE)
-- NOTE: DRE is only available for 32 and 64 bit data widths
-- 0 = Exclude DRE
-- 1 = Include DRE
C_USE_DATAMOVER_LITE : integer range 0 to 1 := 0;
-- Enable DataMover Lite mode
-- NOTE: Data widths limited to 32 and 64 bits, max burst
-- limited to 16, 32, and 64 data beats, no DRE, 4K address
-- guarding must be done by SW programmer.
-- 0 = Normal DataMover mode
-- 1 = Lite dataMover mode
C_READ_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter specifies the depth of the DataMover
-- read address pipelining queues for the Main data transport
-- channels. The effective address pipelining on the AXI4 Read
-- Address Channel will be the value assigned plus 2.
C_WRITE_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter specifies the depth of the DataMover
-- write address pipelining queues for the Main data transport
-- channel. The effective address pipelining on the AXI4 Write
-- Address Channel will be the value assigned plus 2.
-----------------------------------------------------------------------
-- Store and Forward Parameters
-----------------------------------------------------------------------
C_INCLUDE_SF : integer range 0 to 1 := 1;
-- This parameter includes includes/omits Store and Forward.
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 128 ;
-- This parameter sets the depth of the Store and Forward FIFO.
-----------------------------------------------------------------------
-- Soft Reset Assertion Time
-----------------------------------------------------------------------
C_SOFT_RST_TIME_CLKS : integer range 1 to 64 := 8;
-- Specifies the time of the soft reset assertion in
-- axi_aclk clock periods.
-----------------------------------------------------------------------
-- Target FPGA Family Parameter
-----------------------------------------------------------------------
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-----------------------------------------------------------------------
-- Primary Clock
-----------------------------------------------------------------------
axi_aclk : in std_logic ;
-----------------------------------------------------------------------
-- Primary Reset Input (active low)
-----------------------------------------------------------------------
axi_resetn : in std_logic ;
-----------------------------------------------------------------------
-- AXI Lite clock
-----------------------------------------------------------------------
axi_lite_aclk : in std_logic ;
-----------------------------------------------------------------------
-- AXI Lite reset
-----------------------------------------------------------------------
axi_lite_resetn : in std_logic ;
-----------------------------------------------------------------------
-- Interrupt output
-----------------------------------------------------------------------
cdma_introut : out std_logic ;
-----------------------------------------------------------------------
-- Error Discrete output
-----------------------------------------------------------------------
cdma_error_out : out std_logic ;
---------------------------------------------------------------------------------
-- AXI Lite Register Access Interface
---------------------------------------------------------------------------------
-- AXI Lite Write Address Channel -- AXI4-Lite
s_axi_lite_awready : out std_logic ;-- AXI4-Lite
s_axi_lite_awvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_awaddr : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Write Data Channel -- AXI4-Lite
s_axi_lite_wready : out std_logic ;-- AXI4-Lite
s_axi_lite_wvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_wdata : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Write Response Channel -- AXI4-Lite
s_axi_lite_bready : in std_logic ;-- AXI4-Lite
s_axi_lite_bvalid : out std_logic ;-- AXI4-Lite
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ;-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Read Address Channel -- AXI4-Lite
s_axi_lite_arready : out std_logic ;-- AXI4-Lite
s_axi_lite_arvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_araddr : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Read Data Channel -- AXI4-Lite
s_axi_lite_rready : in std_logic ;-- AXI4-Lite
s_axi_lite_rvalid : out std_logic ;-- AXI4-Lite
s_axi_lite_rdata : out std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);-- AXI4-Lite
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ;-- AXI4-Lite
----------------------------------------------------------------------------
-- AXI DataMover Read Channel
----------------------------------------------------------------------------
-- DataMover MMap Read Address Channel -- AXI4
m_axi_arready : in std_logic ;-- AXI4
m_axi_arvalid : out std_logic ;-- AXI4
m_axi_araddr : out std_logic_vector -- AXI4
(C_M_AXI_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_arlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_arsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_arburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_arprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_arcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- DataMover MMap Read Data Channel -- AXI4
m_axi_rready : out std_logic ;-- AXI4
m_axi_rvalid : in std_logic ;-- AXI4
m_axi_rdata : in std_logic_vector -- AXI4
(C_M_AXI_DATA_WIDTH-1 downto 0) ;-- AXI4
m_axi_rresp : in std_logic_vector(1 downto 0) ;-- AXI4
m_axi_rlast : in std_logic ;-- AXI4
-----------------------------------------------------------------------------
-- AXI DataMover Write Channel
-----------------------------------------------------------------------------
-- DataMover Write Address Channel -- AXI4
m_axi_awready : in std_logic ;-- AXI4
m_axi_awvalid : out std_logic ;-- AXI4
m_axi_awaddr : out std_logic_vector -- AXI4
(C_M_AXI_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_awlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_awsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_awburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_awprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_awcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- DataMover Write Data Channel -- AXI4
m_axi_wready : in std_logic ;-- AXI4
m_axi_wvalid : out std_logic ;-- AXI4
m_axi_wdata : out std_logic_vector -- AXI4
(C_M_AXI_DATA_WIDTH-1 downto 0) ;-- AXI4
m_axi_wstrb : out std_logic_vector -- AXI4
((C_M_AXI_DATA_WIDTH/8)-1 downto 0);-- AXI4
m_axi_wlast : out std_logic ;-- AXI4
-- AXI4
-- DataMover Write Response Channel -- AXI4
m_axi_bready : out std_logic ;-- AXI4
m_axi_bvalid : in std_logic ;-- AXI4
m_axi_bresp : in std_logic_vector(1 downto 0) ;-- AXI4
-- Debug test vector (Xilinx use only)
axi_cdma_tstvec : out std_logic_vector(31 downto 0)
);
-----------------------------------------------------------------
-- End of PSFUtil MPD attributes
-----------------------------------------------------------------
end axi_cdma_simple_wrap;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma_simple_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
If (need_dre = 1 and
needed_data_width > 64) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- General Use
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant ADDR_ZEROS : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
-- AXI CDMA Build Mode (Simple Only or with SG); 0 = Simple only
constant CDMA_BUILD_MODE : integer := 0;
-- AXI DataMover Include Status FIFO
constant DM_INCLUDE_STS_FIFO : integer := 1;
-- AXI DataMover Command / Status FIFO Depth
constant DM_CMDSTS_FIFO_DEPTH : integer := 1;
-- AXI MM2S DataMover Full mode value
constant MM2S_FULL_MODE : integer := 1;
-- AXI MM2S DataMover Lite mode value
constant MM2S_LITE_MODE : integer := 2;
-- AXI S2MM DataMover Full mode value
constant S2MM_FULL_MODE : integer := 1;
-- AXI S2MM DataMover Lite mode value
constant S2MM_LITE_MODE : integer := 2;
-- AXI DataMover clocking mode
constant DM_USE_SYNC_CLOCKS : integer := 0;
-- AXI DataMover BTT Used width (Set the to the max allowed)
constant DM_BTT_WIDTH : integer := 23;
-- AXI DataMover S2MM DRE Enable (set to disabled)
constant DM_S2MM_DRE_DISABLED : integer := 0;--func_include_dre (C_INCLUDE_DRE, C_M_AXI_DATA_WIDTH);
-- AXI DataMover Include Store and Forward
constant DM_OMIT_S2MM_STORE_FORWARD : integer := 0;
constant DM_ENABLE_S2MM_STORE_FORWARD : integer := 1;
Constant STORE_FORWARD_CNTL : integer := DM_OMIT_S2MM_STORE_FORWARD;
-- AXI DataMover Stream Backend width
constant DM_STREAM_DWIDTH : integer := C_M_AXI_DATA_WIDTH;
-- AXI DataMover Base status vector width
constant BASE_STATUS_WIDTH : integer := 8;
-- AXI DataMover S2MM status stream data width delta
-- if Store and Forward enabled
Constant SF_ADDED_STS_WIDTH : integer := 24;
-- AXI DataMover status stream data width (S2MM is based on mode of operation)
constant DM_MM2S_STATUS_WIDTH : integer := BASE_STATUS_WIDTH;
constant DM_S2MM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH +
(STORE_FORWARD_CNTL *
SF_ADDED_STS_WIDTH);
-- DataMover Command Stream data Width in bits
constant DM_CMD_WIDTH : integer := 72+(C_M_AXI_ADDR_WIDTH-32);
-- constant DM_CMD_WIDTH : integer := 104;
-- CDMA Interupt Delay value zeroed
Constant IRQ_DLY_THRESH_ZEROS : std_logic_vector(7 downto 0) := (others => '0');
-- AXI DataMover pipeline depth constants
Constant DM_READ_ADDR_PIPE_DEPTH : integer := C_READ_ADDR_PIPE_DEPTH;
Constant DM_WRITE_ADDR_PIPE_DEPTH : integer := C_WRITE_ADDR_PIPE_DEPTH;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_max
--
-- Function Description:
-- Returns the greater of two integers.
--
-------------------------------------------------------------------
function funct_get_max (value_in_1 : integer;
value_in_2 : integer)
return integer is
Variable max_value : Integer := 0;
begin
If (value_in_1 > value_in_2) Then
max_value := value_in_1;
else
max_value := value_in_2;
End if;
Return (max_value);
end function funct_get_max;
--------------------------------------
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-- Calculates the minimum needed depth of the CDMA Store and Forward FIFO
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(funct_get_max(4, 4)+2)
* C_M_AXI_MAX_BURST_LEN;
-- Assigns the depth of the CDMA Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Reset Module signals
signal sig_rst2lite_bside_reset : std_logic := '0';
signal sig_rst2lite_cside_reset : std_logic := '0';
signal sig_rst2reg_reset : std_logic := '0';
signal sig_rst2cntlr_reset : std_logic := '0';
signal sig_rst2dm_resetn : std_logic := '0';
signal sig_rst2cntlr_halt : std_logic := '0';
signal sig_cntlr2rst_halt_cmplt : std_logic := '0';
signal sig_dm_mm2s_halt : std_logic := '0';
signal sig_dm_mm2s_halt_cmplt : std_logic := '0';
signal sig_dm_s2mm_halt : std_logic := '0';
signal sig_dm_s2mm_halt_cmplt : std_logic := '0';
-- Register Module Signals
signal sig_reg2cntlr_src_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2cntlr_dest_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2cntlr_btt : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2cntlr_go : std_logic := '0';
signal sig_cntlr2reg_idle_set : std_logic := '0';
signal sig_cntlr2reg_idle_clr : std_logic := '0';
signal sig_cntlr2reg_decerr_set : std_logic := '0';
signal sig_cntlr2reg_slverr_set : std_logic := '0';
signal sig_cntlr2reg_interr_set : std_logic := '0';
signal sig_cntlr2reg_ioc_set : std_logic := '0';
signal sig_cntlr2reg_iocirpt_set : std_logic := '0';
signal sig_reg2rst_soft_reset : std_logic := '0';
signal sig_rst2reg_soft_reset_clr : std_logic := '0';
signal sig_reg2cntlr_sg_mode : std_logic := '0';
-- DataMover MM2S error discrete
signal sig_dm_mm2s_err : std_logic := '0';
-- DataMover MM2S command Stream
signal sig_cntl2mm2s_cmd_tdata : std_logic_vector(DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s2cntl_cmd_tready : std_logic := '0';
signal sig_cntl2mm2s_cmd_tvalid : std_logic := '0';
-- DataMover MM2S status Stream
signal sig_mm2s2cntl_sts_tdata : std_logic_vector(DM_MM2S_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s2cntl_sts_tkeep : std_logic_vector((DM_MM2S_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s2cntl_sts_tvalid : std_logic := '0';
signal sig_cntl2mm2s_sts_tready : std_logic := '0';
-- DataMover S2MM error discrete
signal sig_dm_s2mm_err : std_logic := '0';
-- DataMover S2MM command Stream
signal sig_cntl2s2mm_cmd_tdata : std_logic_vector(DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cntl2s2mm_cmd_tvalid : std_logic := '0';
signal sig_s2mm2cntl_cmd_tready : std_logic := '0';
-- DataMover S2MM status Stream
signal sig_s2mm2cntl_sts_tdata : std_logic_vector(BASE_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm2cntl_sts_tkeep : std_logic_vector((BASE_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm2cntl_sts_tvalid : std_logic := '0';
signal sig_cntl2s2mm_sts_tready : std_logic := '0';
-- DataMover stream loopback hookup
signal sig_mm2s_axis_tready : std_logic := '0';
signal sig_mm2s_axis_tvalid : std_logic := '0';
signal sig_mm2s_axis_tdata : std_logic_vector(DM_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_mm2s_axis_tkeep : std_logic_vector((DM_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_axis_tlast : std_logic := '0';
signal sig_s2mm_axis_tready : std_logic := '0';
signal sig_s2mm_axis_tvalid : std_logic := '0';
signal sig_s2mm_axis_tdata : std_logic_vector(DM_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_axis_tkeep : std_logic_vector((DM_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_axis_tlast : std_logic := '0';
signal sig_dm_s2mm_sts_tdata : std_logic_vector(DM_S2MM_STATUS_WIDTH-1 downto 0)
:= (others => '0'); -- fullfull Store and forward status data width
signal sig_dm_s2mm_sts_tkeep : std_logic_vector((DM_S2MM_STATUS_WIDTH/8)-1 downto 0)
:= (others => '0'); -- Store and forward status strobe width
-- DataMover Address Pipe Controls
signal sig_mm2s_allow_addr_req : std_logic := '0';
signal sig_mm2s_addr_req_posted : std_logic := '0';
signal sig_mm2s_rd_xfer_cmplt : std_logic := '0';
signal sig_s2mm_allow_addr_req : std_logic := '0';
signal sig_s2mm_addr_req_posted : std_logic := '0';
signal sig_s2mm_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
-- store and Forward module Reset
signal sig_sf_reset : std_logic := '0';
signal burst_type : std_logic;
signal dma_keyhole_write : std_logic;
signal dma_keyhole_read : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- AXI CDMA Test Vector (For Xilinx Internal Use Only)
-------------------------------------------------------------------------------
-- Simple Mode
axi_cdma_tstvec(0) <= sig_reg2cntlr_go ;
axi_cdma_tstvec(1) <= sig_cntlr2reg_idle_set ;
axi_cdma_tstvec(2) <= sig_cntlr2reg_idle_clr ;
axi_cdma_tstvec(3) <= sig_cntlr2reg_iocirpt_set ;
axi_cdma_tstvec(4) <= sig_cntlr2reg_decerr_set ;
axi_cdma_tstvec(5) <= sig_cntlr2reg_slverr_set ;
axi_cdma_tstvec(6) <= sig_cntlr2reg_interr_set ;
axi_cdma_tstvec(31 downto 7) <= (others => '0') ;
-- Create a postive reset for the Store and Forward module
-- from the inverted DataMover active low reset.
-- CR591254 change
-- sig_sf_reset <= not(sig_rst2dm_resetn) ;
sig_sf_reset <= sig_rst2cntlr_reset ;
-------------------------------------------------------------------------------
-- Module Instances
-------------------------------------------------------------------------------
------------------------------------------------------------
-- Instance: I_SIMPLE_RST_MODULE
--
-- Description:
-- Instance for the Reset Module used with Simple Mode
-- operation. It manages both hard and soft reset generation
-- and synchronization when the AXI Lite clock and reset are
-- asynchronous to the Primary clock and reset.
--
------------------------------------------------------------
I_SIMPLE_RST_MODULE : entity axi_cdma_v4_1_14.axi_cdma_reset
generic map(
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_SOFT_RST_TIME_CLKS => C_SOFT_RST_TIME_CLKS
)
port map(
-- Primary Clock and Reset Sources
axi_aclk => axi_aclk ,
axi_resetn => axi_resetn ,
-- AXI Lite Clock and Reset Sources
axi_lite_aclk => axi_lite_aclk ,
axi_lite_resetn => axi_lite_resetn ,
-- CDMA Module hard reset outputs
rst2lite_bside_reset => sig_rst2lite_bside_reset ,
rst2lite_cside_reset => sig_rst2lite_cside_reset ,
rst2reg_reset => sig_rst2reg_reset ,
rst2cntlr_reset => sig_rst2cntlr_reset ,
rst2dm_resetn => sig_rst2dm_resetn ,
-- Soft Reset Request from Register module
reg2rst_soft_reset_in => sig_reg2rst_soft_reset ,
rst2reg_soft_reset_clr => sig_rst2reg_soft_reset_clr ,
-- CDMA Controller halt
rst2cntlr_halt => sig_rst2cntlr_halt ,
cntlr2rst_halt_cmplt => sig_cntlr2rst_halt_cmplt ,
-- CDMA SG halt
rst2sg_halt => open ,
sg2rst_halt_cmplt => LOGIC_HIGH ,
-- CDMA DatMover MM2S Halt
rst2dm_mm2s_halt => sig_dm_mm2s_halt ,
dm2rst_mm2s_halt_cmplt => sig_dm_mm2s_halt_cmplt ,
-- CDMA DatMover S2MM Halt
rst2dm_s2mm_halt => sig_dm_s2mm_halt ,
dm2rst_s2mm_halt_cmplt => sig_dm_s2mm_halt_cmplt
);
------------------------------------------------------------
-- Instance: I_SIMPLE_REG_MODULE
--
-- Description:
-- Instance for the Register Module used with Simple Mode
-- operation.
--
------------------------------------------------------------
I_SIMPLE_REG_MODULE : entity axi_cdma_v4_1_14.axi_cdma_reg_module
generic map(
C_CDMA_BUILD_MODE => CDMA_BUILD_MODE ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH
)
port map(
-- AXI Lite Bus Side Clock and Reset
axi_lite_aclk => axi_lite_aclk ,
axi_lite_reset => sig_rst2lite_bside_reset ,
-- AXI Lite Core side Reset
axi_lite_cside_reset => sig_rst2lite_cside_reset ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
-- AXI Lite Read Data Channel
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- Register Clock and Reset
axi_aclk => axi_aclk ,
axi_reg_reset => sig_rst2reg_reset ,
-- Composite Interrupt Output
reg_introut => cdma_introut ,
-- Composite error Output
reg_error_out => cdma_error_out ,
-- Soft Reset Control
reg_soft_reset_request => sig_reg2rst_soft_reset ,
reg_soft_reset_clr => sig_rst2reg_soft_reset_clr ,
-- DMA Go Control
reg_dma_go => sig_reg2cntlr_go ,
-- SG Mode control
reg_dma_sg_mode => sig_reg2cntlr_sg_mode ,
-- Key Hole write
dma_keyhole_write => dma_keyhole_write ,
-- Key Hole read
dma_keyhole_read => dma_keyhole_read ,
-- CDMASR Control
reg_idle_set => sig_cntlr2reg_idle_set ,
reg_idle_clr => sig_cntlr2reg_idle_clr ,
reg_ioc_irq_set => sig_cntlr2reg_iocirpt_set ,
reg_dly_irq_set => LOGIC_LOW ,
reg_irqdelay_status => IRQ_DLY_THRESH_ZEROS ,
reg_irqthresh_status => IRQ_DLY_THRESH_ZEROS ,
reg_irqthresh_wren => open ,
reg_irqdelay_wren => open ,
-- DataMover Errors
reg_dma_decerr_set => sig_cntlr2reg_decerr_set ,
reg_dma_slverr_set => sig_cntlr2reg_slverr_set ,
reg_dma_interr_set => sig_cntlr2reg_interr_set ,
-- SG Descriptor Fetch errors
reg_ftch_interr_set => LOGIC_LOW ,
reg_ftch_slverr_set => LOGIC_LOW ,
reg_ftch_decerr_set => LOGIC_LOW ,
reg_ftch_error_addr => ADDR_ZEROS ,
-- SG Descriptor Update errors
reg_updt_interr_set => LOGIC_LOW ,
reg_updt_slverr_set => LOGIC_LOW ,
reg_updt_decerr_set => LOGIC_LOW ,
reg_updt_error_addr => ADDR_ZEROS ,
-- SG CURDESC Update
reg_new_curdesc_wren => LOGIC_LOW ,
reg_new_curdesc => ADDR_ZEROS ,
-- SG Detected SW Register Update
reg_tailpntr_updated => open ,
reg_currdesc_updated => open ,
-- Register State Out
reg_dmacr => open ,
reg_dmasr => open ,
reg_curdesc => open ,
reg_taildesc => open ,
reg_src_addr => sig_reg2cntlr_src_addr ,
reg_dest_addr => sig_reg2cntlr_dest_addr ,
reg_btt => sig_reg2cntlr_btt
);
------------------------------------------------------------
-- Instance: I_SIMPLE_DMA_CNTLR
--
-- Description:
--
-- Control Logic module for the Simple Mode CDMA operation.
--
------------------------------------------------------------
I_SIMPLE_DMA_CNTLR : entity axi_cdma_v4_1_14.axi_cdma_simple_cntlr
generic map(
C_DM_CMD_WIDTH => DM_CMD_WIDTH ,
C_DM_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_DM_MM2S_STATUS_WIDTH => DM_MM2S_STATUS_WIDTH ,
C_DM_S2MM_STATUS_WIDTH => BASE_STATUS_WIDTH ,
C_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_BTT_WIDTH => DM_BTT_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Clock and reset
axi_aclk => axi_aclk ,
axi_reset => sig_rst2cntlr_reset ,
-- Halt request
rst2cntlr_halt => sig_rst2cntlr_halt ,
cntlr2rst_halt_cmplt => sig_cntlr2rst_halt_cmplt ,
-- Register Module Start and Mode Controls
reg2cntlr_go => sig_reg2cntlr_go ,
reg2cntlr_sg_mode => sig_reg2cntlr_sg_mode ,
burst_type_write => dma_keyhole_write ,
burst_type_read => dma_keyhole_read ,
-- Register Module command qualifiers
reg2cntlr_src_addr => sig_reg2cntlr_src_addr ,
reg2cntlr_dest_addr => sig_reg2cntlr_dest_addr ,
reg2cntlr_btt => sig_reg2cntlr_btt(DM_BTT_WIDTH-1
downto 0) ,
-- General Status Bit controls
cntlr2reg_idle_set => sig_cntlr2reg_idle_set ,
cntlr2reg_idle_clr => sig_cntlr2reg_idle_clr ,
cntlr2reg_iocirpt_set => sig_cntlr2reg_iocirpt_set ,
-- DataMover Error Status bit controls
cntlr2reg_decerr_set => sig_cntlr2reg_decerr_set ,
cntlr2reg_slverr_set => sig_cntlr2reg_slverr_set ,
cntlr2reg_interr_set => sig_cntlr2reg_interr_set ,
-- DataMover MM2S Command Interface Ports (AXI Stream)
mm2s2cntl_cmd_tready => sig_mm2s2cntl_cmd_tready ,
cntl2mm2s_cmd_tvalid => sig_cntl2mm2s_cmd_tvalid ,
cntl2mm2s_cmd_tdata => sig_cntl2mm2s_cmd_tdata ,
-- DataMover MM2S Status Interface Ports (AXI Stream)
cntl2mm2s_sts_tready => sig_cntl2mm2s_sts_tready ,
mm2s2cntl_sts_tvalid => sig_mm2s2cntl_sts_tvalid ,
mm2s2cntl_sts_tdata => sig_mm2s2cntl_sts_tdata ,
mm2s2cntl_sts_tstrb => sig_mm2s2cntl_sts_tkeep ,
-- DataMover MM2S error discrete
mm2s2cntl_err => sig_dm_mm2s_err ,
-- DataMover S2MM Command Interface Ports (AXI Stream)
cntl2s2mm_cmd_tdata => sig_cntl2s2mm_cmd_tdata ,
cntl2s2mm_cmd_tvalid => sig_cntl2s2mm_cmd_tvalid ,
s2mm2cntl_cmd_tready => sig_s2mm2cntl_cmd_tready ,
-- DataMover S2MM Status Interface Ports (AXI Stream)
s2mm2cntl_sts_tdata => sig_s2mm2cntl_sts_tdata ,
s2mm2cntl_sts_tstrb => sig_s2mm2cntl_sts_tkeep ,
s2mm2cntl_sts_tvalid => sig_s2mm2cntl_sts_tvalid ,
cntl2s2mm_sts_tready => sig_cntl2s2mm_sts_tready ,
-- DataMover S2MM error discrete
s2mm2cntl_err => sig_dm_s2mm_err
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DM_LITE
--
-- If Generate Description:
-- Instantiates the AXI DataMover in the Lite configuration.
--
--
------------------------------------------------------------
GEN_DM_LITE : if (C_USE_DATAMOVER_LITE = 1) generate
begin
------------------------------------------------------------
-- Instance: I_DATAMOVER
--
-- Description:
--
-- Data Path DataMover
-- Reads data from the AXI MMAP Read Channel and Writes the data
-- to the AXI MMAP Write Channel via commands from the Controller
-- Module.
--
--
------------------------------------------------------------
I_DATAMOVER_LITE : entity axi_datamover_v5_1_16.axi_datamover
generic map(
C_INCLUDE_MM2S => MM2S_LITE_MODE ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_M_AXIS_MM2S_TDATA_WIDTH => DM_STREAM_DWIDTH ,
C_INCLUDE_MM2S_STSFIFO => DM_INCLUDE_STS_FIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => DM_USE_SYNC_CLOCKS ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_DRE ,
C_MM2S_BURST_SIZE => C_M_AXI_MAX_BURST_LEN ,
C_MM2S_BTT_USED => DM_BTT_WIDTH ,
C_MM2S_ADDR_PIPE_DEPTH => DM_READ_ADDR_PIPE_DEPTH ,
C_MM2S_INCLUDE_SF => 0 ,
C_ENABLE_CACHE_USER => 0,
C_ENABLE_SKID_BUF => "11000" ,
C_CMD_WIDTH => DM_CMD_WIDTH ,
C_INCLUDE_S2MM => S2MM_LITE_MODE ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_S_AXIS_S2MM_TDATA_WIDTH => DM_STREAM_DWIDTH ,
C_INCLUDE_S2MM_STSFIFO => DM_INCLUDE_STS_FIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => DM_USE_SYNC_CLOCKS ,
C_INCLUDE_S2MM_DRE => DM_S2MM_DRE_DISABLED ,
C_S2MM_BURST_SIZE => C_M_AXI_MAX_BURST_LEN ,
C_S2MM_BTT_USED => DM_BTT_WIDTH ,
C_S2MM_SUPPORT_INDET_BTT => STORE_FORWARD_CNTL ,
C_S2MM_ADDR_PIPE_DEPTH => DM_WRITE_ADDR_PIPE_DEPTH ,
C_S2MM_INCLUDE_SF => 0 ,
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => axi_aclk ,
m_axi_mm2s_aresetn => sig_rst2dm_resetn ,
-- MM2S Soft Shutdown
mm2s_halt => sig_dm_mm2s_halt ,
mm2s_halt_cmplt => sig_dm_mm2s_halt_cmplt ,
-- MM2S Error output discrete
mm2s_err => sig_dm_mm2s_err ,
-- Memory Map to Stream Command FIFO and Status FIFO Async CLK/RST --------------
m_axis_mm2s_cmdsts_aclk => LOGIC_LOW ,
m_axis_mm2s_cmdsts_aresetn => LOGIC_HIGH ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => sig_cntl2mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => sig_mm2s2cntl_cmd_tready ,
s_axis_mm2s_cmd_tdata => sig_cntl2mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => sig_mm2s2cntl_sts_tvalid ,
m_axis_mm2s_sts_tready => sig_cntl2mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => sig_mm2s2cntl_sts_tdata ,
m_axis_mm2s_sts_tkeep => sig_mm2s2cntl_sts_tkeep ,
-- Address Posting contols
mm2s_allow_addr_req => sig_mm2s_allow_addr_req ,
mm2s_addr_req_posted => sig_mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => sig_mm2s_rd_xfer_cmplt ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_araddr ,
m_axi_mm2s_arlen => m_axi_arlen ,
m_axi_mm2s_arsize => m_axi_arsize ,
m_axi_mm2s_arburst => m_axi_arburst ,
m_axi_mm2s_arprot => m_axi_arprot ,
m_axi_mm2s_arcache => m_axi_arcache ,
m_axi_mm2s_aruser => open, --m_axi_mm2s_aruser ,
m_axi_mm2s_arvalid => m_axi_arvalid ,
m_axi_mm2s_arready => m_axi_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_rdata ,
m_axi_mm2s_rresp => m_axi_rresp ,
m_axi_mm2s_rlast => m_axi_rlast ,
m_axi_mm2s_rvalid => m_axi_rvalid ,
m_axi_mm2s_rready => m_axi_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => sig_mm2s_axis_tdata ,
m_axis_mm2s_tkeep => sig_mm2s_axis_tkeep ,
m_axis_mm2s_tlast => sig_mm2s_axis_tlast ,
m_axis_mm2s_tvalid => sig_mm2s_axis_tvalid ,
m_axis_mm2s_tready => sig_mm2s_axis_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => axi_aclk ,
m_axi_s2mm_aresetn => sig_rst2dm_resetn ,
-- S2MM Soft Shutdown
s2mm_halt => sig_dm_s2mm_halt ,
s2mm_halt_cmplt => sig_dm_s2mm_halt_cmplt ,
-- S2MM Error output discrete
s2mm_err => sig_dm_s2mm_err ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => LOGIC_LOW ,
m_axis_s2mm_cmdsts_aresetn => LOGIC_HIGH ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => sig_cntl2s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => sig_s2mm2cntl_cmd_tready ,
s_axis_s2mm_cmd_tdata => sig_cntl2s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => sig_s2mm2cntl_sts_tvalid ,
m_axis_s2mm_sts_tready => sig_cntl2s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => sig_s2mm2cntl_sts_tdata ,
m_axis_s2mm_sts_tkeep => sig_s2mm2cntl_sts_tkeep ,
-- Address posting controls
s2mm_allow_addr_req => sig_s2mm_allow_addr_req ,
s2mm_addr_req_posted => sig_s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len ,
s2mm_wr_len => sig_s2mm_wr_len ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_awaddr ,
m_axi_s2mm_awlen => m_axi_awlen ,
m_axi_s2mm_awsize => m_axi_awsize ,
m_axi_s2mm_awburst => m_axi_awburst ,
m_axi_s2mm_awprot => m_axi_awprot ,
m_axi_s2mm_awcache => m_axi_awcache ,
m_axi_s2mm_awuser => open, --m_axi_s2mm_awuser ,
m_axi_s2mm_awvalid => m_axi_awvalid ,
m_axi_s2mm_awready => m_axi_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_wdata ,
m_axi_s2mm_wstrb => m_axi_wstrb ,
m_axi_s2mm_wlast => m_axi_wlast ,
m_axi_s2mm_wvalid => m_axi_wvalid ,
m_axi_s2mm_wready => m_axi_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_bresp ,
m_axi_s2mm_bvalid => m_axi_bvalid ,
m_axi_s2mm_bready => m_axi_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => sig_s2mm_axis_tdata ,
s_axis_s2mm_tkeep => sig_s2mm_axis_tkeep ,
s_axis_s2mm_tlast => sig_s2mm_axis_tlast ,
s_axis_s2mm_tvalid => sig_s2mm_axis_tvalid ,
s_axis_s2mm_tready => sig_s2mm_axis_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
end generate GEN_DM_LITE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DM_FULL
--
-- If Generate Description:
-- Instance for FULL mode DataMover
--
--
------------------------------------------------------------
GEN_DM_FULL : if (C_USE_DATAMOVER_LITE = 0) generate
begin
-- Rip the basic status output from the DataMover S2MM status reply stream
sig_s2mm2cntl_sts_tdata <= sig_dm_s2mm_sts_tdata(BASE_STATUS_WIDTH-1 downto 0);
sig_s2mm2cntl_sts_tkeep <= sig_dm_s2mm_sts_tkeep((BASE_STATUS_WIDTH/8)-1 downto 0);
------------------------------------------------------------
-- Instance: I_DATAMOVER
--
-- Description:
--
-- Data Path DataMover
-- Reads data from the AXI MMAP Read Channel and Writes the data
-- to the AXI MMAP Write Channel via commands from the Controller
-- Module.
--
--
------------------------------------------------------------
I_DATAMOVER_FULL : entity axi_datamover_v5_1_16.axi_datamover
generic map(
C_INCLUDE_MM2S => MM2S_FULL_MODE ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_M_AXIS_MM2S_TDATA_WIDTH => DM_STREAM_DWIDTH ,
C_INCLUDE_MM2S_STSFIFO => DM_INCLUDE_STS_FIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => DM_USE_SYNC_CLOCKS ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_DRE ,
C_MM2S_BURST_SIZE => C_M_AXI_MAX_BURST_LEN ,
C_MM2S_BTT_USED => DM_BTT_WIDTH ,
C_MM2S_ADDR_PIPE_DEPTH => DM_READ_ADDR_PIPE_DEPTH ,
C_MM2S_INCLUDE_SF => 0 ,
C_ENABLE_CACHE_USER => 0,
C_ENABLE_SKID_BUF => "11000" ,
C_CMD_WIDTH => DM_CMD_WIDTH ,
C_INCLUDE_S2MM => S2MM_FULL_MODE ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_S_AXIS_S2MM_TDATA_WIDTH => DM_STREAM_DWIDTH ,
C_INCLUDE_S2MM_STSFIFO => DM_INCLUDE_STS_FIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => DM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => DM_USE_SYNC_CLOCKS ,
C_INCLUDE_S2MM_DRE => DM_S2MM_DRE_DISABLED ,
C_S2MM_BURST_SIZE => C_M_AXI_MAX_BURST_LEN ,
C_S2MM_BTT_USED => DM_BTT_WIDTH ,
C_S2MM_SUPPORT_INDET_BTT => STORE_FORWARD_CNTL ,
C_S2MM_ADDR_PIPE_DEPTH => DM_WRITE_ADDR_PIPE_DEPTH ,
C_S2MM_INCLUDE_SF => 0 ,
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => axi_aclk ,
m_axi_mm2s_aresetn => sig_rst2dm_resetn ,
-- MM2S Soft Shutdown
mm2s_halt => sig_dm_mm2s_halt ,
mm2s_halt_cmplt => sig_dm_mm2s_halt_cmplt ,
-- MM2S Error output discrete
mm2s_err => sig_dm_mm2s_err ,
-- Memory Map to Stream Command FIFO and Status FIFO Async CLK/RST --------------
m_axis_mm2s_cmdsts_aclk => LOGIC_LOW ,
m_axis_mm2s_cmdsts_aresetn => LOGIC_HIGH ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => sig_cntl2mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => sig_mm2s2cntl_cmd_tready ,
s_axis_mm2s_cmd_tdata => sig_cntl2mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => sig_mm2s2cntl_sts_tvalid ,
m_axis_mm2s_sts_tready => sig_cntl2mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => sig_mm2s2cntl_sts_tdata ,
m_axis_mm2s_sts_tkeep => sig_mm2s2cntl_sts_tkeep ,
-- Address Posting contols
mm2s_allow_addr_req => sig_mm2s_allow_addr_req ,
mm2s_addr_req_posted => sig_mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => sig_mm2s_rd_xfer_cmplt ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_araddr ,
m_axi_mm2s_arlen => m_axi_arlen ,
m_axi_mm2s_arsize => m_axi_arsize ,
m_axi_mm2s_arburst => m_axi_arburst ,
m_axi_mm2s_arprot => m_axi_arprot ,
m_axi_mm2s_arcache => m_axi_arcache ,
m_axi_mm2s_aruser => open, --m_axi_arcache ,
m_axi_mm2s_arvalid => m_axi_arvalid ,
m_axi_mm2s_arready => m_axi_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_rdata ,
m_axi_mm2s_rresp => m_axi_rresp ,
m_axi_mm2s_rlast => m_axi_rlast ,
m_axi_mm2s_rvalid => m_axi_rvalid ,
m_axi_mm2s_rready => m_axi_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => sig_mm2s_axis_tdata ,
m_axis_mm2s_tkeep => sig_mm2s_axis_tkeep ,
m_axis_mm2s_tlast => sig_mm2s_axis_tlast ,
m_axis_mm2s_tvalid => sig_mm2s_axis_tvalid ,
m_axis_mm2s_tready => sig_mm2s_axis_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => axi_aclk ,
m_axi_s2mm_aresetn => sig_rst2dm_resetn ,
-- S2MM Soft Shutdown
s2mm_halt => sig_dm_s2mm_halt ,
s2mm_halt_cmplt => sig_dm_s2mm_halt_cmplt ,
-- S2MM Error output discrete
s2mm_err => sig_dm_s2mm_err ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => LOGIC_LOW ,
m_axis_s2mm_cmdsts_aresetn => LOGIC_HIGH ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => sig_cntl2s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => sig_s2mm2cntl_cmd_tready ,
s_axis_s2mm_cmd_tdata => sig_cntl2s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => sig_s2mm2cntl_sts_tvalid ,
m_axis_s2mm_sts_tready => sig_cntl2s2mm_sts_tready ,
-- m_axis_s2mm_sts_tdata => sig_s2mm2cntl_sts_tdata ,
m_axis_s2mm_sts_tdata => sig_dm_s2mm_sts_tdata ,
-- m_axis_s2mm_sts_tkeep => sig_s2mm2cntl_sts_tstrb ,
m_axis_s2mm_sts_tkeep => sig_dm_s2mm_sts_tkeep ,
-- Address posting controls
s2mm_allow_addr_req => sig_s2mm_allow_addr_req ,
s2mm_addr_req_posted => sig_s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len ,
s2mm_wr_len => sig_s2mm_wr_len ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_awaddr ,
m_axi_s2mm_awlen => m_axi_awlen ,
m_axi_s2mm_awsize => m_axi_awsize ,
m_axi_s2mm_awburst => m_axi_awburst ,
m_axi_s2mm_awprot => m_axi_awprot ,
m_axi_s2mm_awcache => m_axi_awcache ,
m_axi_s2mm_awuser => open, --m_axi_awcache ,
m_axi_s2mm_awvalid => m_axi_awvalid ,
m_axi_s2mm_awready => m_axi_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_wdata ,
m_axi_s2mm_wstrb => m_axi_wstrb ,
m_axi_s2mm_wlast => m_axi_wlast ,
m_axi_s2mm_wvalid => m_axi_wvalid ,
m_axi_s2mm_wready => m_axi_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_bresp ,
m_axi_s2mm_bvalid => m_axi_bvalid ,
m_axi_s2mm_bready => m_axi_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => sig_s2mm_axis_tdata ,
s_axis_s2mm_tkeep => sig_s2mm_axis_tkeep ,
s_axis_s2mm_tlast => sig_s2mm_axis_tlast ,
s_axis_s2mm_tvalid => sig_s2mm_axis_tvalid ,
s_axis_s2mm_tready => sig_s2mm_axis_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
end generate GEN_DM_FULL;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_SF
--
-- If Generate Description:
-- This IfGen includes the Store and Forward module
--
--
------------------------------------------------------------
GEN_INCLUDE_SF : if (C_INCLUDE_SF = 1) generate
begin
------------------------------------------------------------
-- Instance: I_STORE_FORWARD
--
-- Description:
-- This is the instance for the AXI CDMA Store and Forward
-- Module.
--
------------------------------------------------------------
I_STORE_FORWARD : entity axi_cdma_v4_1_14.axi_cdma_sf
generic map (
C_WR_ADDR_PIPE_DEPTH => DM_WRITE_ADDR_PIPE_DEPTH,
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MAX_BURST_LEN => C_M_AXI_MAX_BURST_LEN ,
C_DRE_IS_USED => C_INCLUDE_DRE ,
C_STREAM_DWIDTH => C_M_AXI_DATA_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock input
aclk => axi_aclk ,
-- Reset input
reset => sig_sf_reset ,
-- DataMover Read Side Address Pipelining control Interface ----
ok_to_post_rd_addr => sig_mm2s_allow_addr_req ,
rd_addr_posted => sig_mm2s_addr_req_posted ,
rd_xfer_cmplt => sig_mm2s_rd_xfer_cmplt ,
-- Read Side Stream In from DataMover MM2S ---------------------
sf2sin_tready => sig_mm2s_axis_tready ,
sin2sf_tvalid => sig_mm2s_axis_tvalid ,
sin2sf_tdata => sig_mm2s_axis_tdata ,
sin2sf_tkeep => sig_mm2s_axis_tkeep ,
sin2sf_tlast => sig_mm2s_axis_tlast ,
-- DataMover Write Side Address Pipelining control Interface ---
ok_to_post_wr_addr => sig_s2mm_allow_addr_req ,
wr_addr_posted => sig_s2mm_addr_req_posted ,
wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
wr_ld_nxt_len => sig_s2mm_ld_nxt_len ,
wr_len => sig_s2mm_wr_len ,
-- Write Side Stream Out to DataMover S2MM ---------------------
sout2sf_tready => sig_s2mm_axis_tready ,
sf2sout_tvalid => sig_s2mm_axis_tvalid ,
sf2sout_tdata => sig_s2mm_axis_tdata ,
sf2sout_tkeep => sig_s2mm_axis_tkeep ,
sf2sout_tlast => sig_s2mm_axis_tlast
);
end generate GEN_INCLUDE_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_SF
--
-- If Generate Description:
-- This IfGen includes the Store and Forward module
--
--
------------------------------------------------------------
GEN_OMIT_SF : if (C_INCLUDE_SF = 0) generate
begin
sig_mm2s_allow_addr_req <= LOGIC_HIGH;
sig_s2mm_allow_addr_req <= LOGIC_HIGH;
sig_mm2s_axis_tready <= sig_s2mm_axis_tready ;
sig_s2mm_axis_tvalid <= sig_mm2s_axis_tvalid ;
sig_s2mm_axis_tdata <= sig_mm2s_axis_tdata ;
sig_s2mm_axis_tkeep <= sig_mm2s_axis_tkeep ;
sig_s2mm_axis_tlast <= sig_mm2s_axis_tlast ;
end generate GEN_OMIT_SF;
end implementation;
-------------------------------------------------------------------------------
-- axi_cdma_sg_cntlr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_sg_cntlr.vhd
-- Description: This entity is reset module entity for the AXI DMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
library axi_cdma_v4_1_14;
use axi_cdma_v4_1_14.axi_cdma_pulse_gen;
-------------------------------------------------------------------------------
entity axi_cdma_sg_cntlr is
Generic (
C_SG_ADDR_WIDTH : integer := 32;
C_SG_FETCH_DWIDTH : integer := 32;
C_SG_PTR_UPDATE_DWIDTH : integer := 32;
C_SG_STS_UPDATE_DWIDTH : integer := 33;
C_DM_CMD_WIDTH : integer := 72;
C_DM_DATA_WIDTH : integer := 32;
C_DM_MM2S_STATUS_WIDTH : integer := 8;
C_DM_S2MM_STATUS_WIDTH : integer := 8;
C_FAMILY : String := "virtex7"
);
port (
-- Clock Input
axi_aclk : in std_logic ;
-- Reset Input (active high)
axi_reset : in std_logic ;
-- Halt request from the Reset module
rst2sgcntl_halt : in std_logic ;
-- Halt complete status to the Reset module
sgcntl2rst_halt_cmplt : out std_logic ;
-- SG Queue Flush Request
sgcntlr2sg_desc_flush : out std_logic ;
-- Register Module SG Mode Control
reg2sgcntl_sg_mode : in std_logic ;
-- MM2S Type of Burst, 1 is increment, 0 is fixed
burst_type_read : in std_logic;
-- S2MM Type of Burst, 1 is increment, 0 is fixed
burst_type_write : in std_logic;
-- Register Module Tail pointer updated flag
reg2sgcntl_tailpntr_updated : in std_logic ;
-- Register Module Current Desciptor pointer updated flag
reg2sgcntl_currdesc_updated : in std_logic ;
-- Run/Stop Control to SG
sgcntlr2sg_run_stop : out std_logic ;
-- Idle bit set to Register Module Status Register
sgcntl2reg_idle_set : out std_logic ;
-- Idle bit clear to Register Module Status Register
sgcntl2reg_idle_clr : out std_logic ;
-- SOF control to SG
sgcntl2sg_pkt_sof : out std_logic ;
-- EOF control to SG
sgcntl2sg_pkt_eof : out std_logic ;
-- Interrupt on complete status bit set from SG
sg2sgcntl_ioc_irq_set : in std_logic ;
-- Delay Interrupt status bit set from SG
sg2sgcntl_dly_irq_set : in std_logic ;
-- Interrupt on complete status bit set to Register Module
sgcntl2reg_ioc_irq_set : out std_logic ;
-- Delay Interrupt status bit set to Register Module
sgcntl2reg_dly_irq_set : out std_logic ;
-- Descriptor Fetch Stream Interface from SG
sgcntl2sg_ftch_tready : out std_logic ; -- Axi4-Stream
sg2sgcntlr_ftch_tvalid : in std_logic ; -- Axi4-Stream
sg2sgcntlr_ftch_tvalid_new : in std_logic ; -- Axi4-Stream
sg2sgcntlr_ftch_tdata : in std_logic_vector(C_SG_FETCH_DWIDTH-1 downto 0) ; -- Axi4-Stream
sg2sgcntlr_ftch_tdata_new : in std_logic_vector(127+(3*(C_SG_ADDR_WIDTH-32)) downto 0) ; -- Axi4-Stream
sg2sgcntlr_ftch_tlast : in std_logic ; -- Axi4-Stream
sig_sg2sgcntlr_ftch_desc_available : in std_logic;
-- Descriptor Pointer Update Stream to SG
sg2sgcntlr_updptr_tready : in std_logic ; -- Axi4-Stream
sgcntl2sg_updptr_tvalid : out std_logic ; -- Axi4-Stream
sgcntl2sg_updptr_tdata : out std_logic_vector(C_SG_PTR_UPDATE_DWIDTH-1 downto 0) ;-- Axi4-Stream
sgcntl2sg_updptr_tlast : out std_logic ; -- Axi4-Stream
-- Descriptor Status Update Stream to SG
sg2sgcntlr_updsts_tready : in std_logic ; -- Axi4-Stream
sgcntl2sg_updsts_tvalid : out std_logic ; -- Axi4-Stream
sgcntl2sg_updsts_tdata : out std_logic_vector(C_SG_STS_UPDATE_DWIDTH-1 downto 0) ;-- Axi4-Stream
sgcntl2sg_updsts_tlast : out std_logic ; -- Axi4-Stream
-- Descriptor Fetch Idle status from SG
sg2sgcntlr_ftch_idle : in std_logic ;
-- Descriptor Fetch error early from SG
sg2sgcntlr_ftch_err_early : in std_logic ;
-- Descriptor Fetch stale descriptor error from SG
sg2sgcntlr_ftch_stale_desc : in std_logic ;
-- Descriptor Fetch error from SG
sg2sgcntlr_ftch_error : in std_logic ;
-- Descriptor update Idle status from SG
sg2sgcntlr_updt_idle : in std_logic ;
-- Descriptor interrupt on complete bit set from SG
sg2sgcntlr_updt_ioc_irq_set : in std_logic ;
-- Descriptor Update error from SG
sg2sgcntlr_updt_error : in std_logic ;
-- Echo of Main DataMover internal error from SG
sg2sgcntlr_dma_interr_set : in std_logic ;
-- Echo of Main DataMover Slave error from SG
sg2sgcntlr_dma_slverr_set : in std_logic ;
-- Echo of Main DataMover Decode error from SG
sg2sgcntlr_dma_decerr_set : in std_logic ;
-- Echo of Main DataMover internal error to the Register Module
sgcntlr2reg_dma_interr_set : out std_logic ;
-- Echo of Main DataMover Slave error to the Register Module
sgcntlr2reg_dma_slverr_set : out std_logic ;
-- Echo of Main DataMover Decode error to the Register Module
sgcntlr2reg_dma_decerr_set : out std_logic ;
-- Current Descriptor write control to Register Module
sgcntlr2reg_new_curdesc_wren : out std_logic ;
-- Current Descriptor to Register Module
sgcntlr2reg_new_curdesc : out std_logic_vector(C_SG_ADDR_WIDTH-1 downto 0) ;
-- DataMover MM2S Command Interface Ports (AXI Stream)
mm2s2sgcntl_cmd_tready : in std_logic ; -- DM MM2S CMD IF
sgcntl2mm2s_cmd_tvalid : out std_logic ; -- DM MM2S CMD IF
sgcntl2mm2s_cmd_tdata : out std_logic_vector(C_DM_CMD_WIDTH-1 downto 0); -- DM MM2S CMD IF
-- DataMover MM2S Status Interface Ports (AXI Stream)
sgcntl2mm2s_sts_tready : out std_logic ; -- DM MM2S Status IF
mm2s2sgcntl_sts_tvalid : in std_logic ; -- DM MM2S Status IF
mm2s2sgcntl_sts_tdata : in std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0); -- DM MM2S Status IF
mm2s2sgcntl_sts_tstrb : in std_logic_vector((C_DM_MM2S_STATUS_WIDTH/8)-1 downto 0); -- DM MM2S Status IF
-- DataMover MM2S error discrete
mm2s2sgcntl_err : in std_logic ;
-- DataMover MM2S Halt request input
sgcntl2mm2s_halt : Out std_logic ;
-- DataMover MM2S Halt complete flag
mm2s2sgcntl_halt_cmplt : In std_logic ;
-- DataMover S2MM Command Interface Ports (AXI Stream)
s2mm2sgcntl_cmd_tready : in std_logic ; -- DM S2MM CMD IF
sgcntl2s2mm_cmd_tvalid : out std_logic ; -- DM S2MM CMD IF
sgcntl2s2mm_cmd_tdata : out std_logic_vector(C_DM_CMD_WIDTH-1 downto 0); -- DM S2MM CMD IF
-- DataMover S2MM Status Interface Ports (AXI Stream)
sgcntl2s2mm_sts_tready : out std_logic ; -- DM S2MM Status IF
s2mm2sgcntl_sts_tvalid : in std_logic ; -- DM S2MM Status IF
s2mm2sgcntl_sts_tdata : in std_logic_vector(C_DM_S2MM_STATUS_WIDTH-1 downto 0); -- DM S2MM Status IF
s2mm2sgcntl_sts_tstrb : in std_logic_vector((C_DM_S2MM_STATUS_WIDTH/8)-1 downto 0);-- DM S2MM Status IF
-- DataMover S2MM error discrete
s2mm2sgcntl_err : in std_logic ;
-- DataMover S2MM Halt request input
sgcntl2s2mm_halt : Out std_logic ;
-- DataMover S2MM Halt complete flag
s2mm2sgcntl_halt_cmplt : In std_logic
);
end axi_cdma_sg_cntlr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma_sg_cntlr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_calc_offset_bits
--
-- Function Description:
-- Calculates the width of the destination address offset bits
-- needed for populating the MM2S Command DSA field.
--
-------------------------------------------------------------------
function funct_calc_offset_bits (data_width : integer) return integer is
Variable lvar_bits_needed : Integer := 0;
begin
case data_width is
when 32 =>
lvar_bits_needed := 2;
when 64 =>
lvar_bits_needed := 3;
when 128 =>
lvar_bits_needed := 4;
when 256 =>
lvar_bits_needed := 5;
when 512 =>
lvar_bits_needed := 6;
when others => -- 256 bits
lvar_bits_needed := 5;
end case;
Return (lvar_bits_needed);
end function funct_calc_offset_bits;
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant DM_CMD_PEND_WIDTH : integer := 5; -- bits
Constant DM_CMD_PEND_ONE : unsigned(DM_CMD_PEND_WIDTH-1 downto 0) := TO_UNSIGNED(1,DM_CMD_PEND_WIDTH);
Constant DM_CMD_PEND_ZERO : unsigned(DM_CMD_PEND_WIDTH-1 downto 0) := TO_UNSIGNED(0,DM_CMD_PEND_WIDTH);
Constant NO_SYNCHRONIZERS : integer := 0;
Constant POSITIVE_EDGE_TRIGGER : integer := 1;
Constant NEGATIVE_EDGE_TRIGGER : integer := 0;
Constant TWO_CLKS : integer := 2;
Constant ONE_CLK : integer := 1;
Constant CMD_TAG_WIDTH : integer := 4;
Constant CMD_DSA_WIDTH : integer := 6;
Constant DSA_ADDR_OFFSET_WIDTH : integer := funct_calc_offset_bits(C_DM_DATA_WIDTH);
Constant CMD_RSVD : std_logic_vector(3 downto 0) := (others => '0');
Constant CMD_DSA_ZEROED : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
Constant STS_TAG_MS_INDEX : integer := CMD_TAG_WIDTH-1;
Constant STS_INTERR_INDEX : integer := STS_TAG_MS_INDEX+1;
Constant STS_DECERR_INDEX : integer := STS_INTERR_INDEX+1;
Constant STS_SLVERR_INDEX : integer := STS_DECERR_INDEX+1;
Constant STS_OK_INDEX : integer := STS_SLVERR_INDEX+1;
Constant DM_ADDR_FIELD_WIDTH : integer := 32;
Constant DM_BTT_FIELD_WIDTH : integer := 23;
Constant BTT_ZERO : std_logic_vector(DM_BTT_FIELD_WIDTH-1 downto 0) := (others => '0');
Constant TAG_CNT_ONE : unsigned(CMD_TAG_WIDTH-1 downto 0) := TO_UNSIGNED(1,CMD_TAG_WIDTH);
Constant DESCR_DBEAT_CNT_WIDTH : integer := 3; -- bits
Constant DESCR_DBEAT_CNT_ONE : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1,DESCR_DBEAT_CNT_WIDTH);
-- Descriptor Load databeat positions
Constant CDA_LS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(0,DESCR_DBEAT_CNT_WIDTH);
Constant CDA_MS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(1,DESCR_DBEAT_CNT_WIDTH);
-- Constant SA_LS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(2,DESCR_DBEAT_CNT_WIDTH);
Constant SA_LS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(1,DESCR_DBEAT_CNT_WIDTH);
Constant SA_MS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(3,DESCR_DBEAT_CNT_WIDTH);
-- Constant DA_LS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(4,DESCR_DBEAT_CNT_WIDTH);
Constant DA_LS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(2,DESCR_DBEAT_CNT_WIDTH);
Constant DA_MS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(5,DESCR_DBEAT_CNT_WIDTH);
-- Constant BTT : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(6,DESCR_DBEAT_CNT_WIDTH);
Constant BTT : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(3,DESCR_DBEAT_CNT_WIDTH);
Constant STATUS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(7,DESCR_DBEAT_CNT_WIDTH);
-- Status update word reserved field
Constant STATUS_USED_WIDTH : integer := 1 -- Update IOC bit
+ 1 -- Cmplt bit
+ 1 -- DMADecErr bit
+ 1 -- DMASlvErr bit
+ 1 ; -- DMAIntErr bit
Constant STATUS_RSVD_WIDTH : integer := C_SG_STS_UPDATE_DWIDTH - STATUS_USED_WIDTH;
Constant STATUS_RSVD : std_logic_vector(STATUS_RSVD_WIDTH-1 downto 0) := (others => '0');
Constant FTCH_UPDT_CNTR_WIDTH : integer := 5; -- 5 bits wide
Constant FTCH_UPDT_ZERO : unsigned(FTCH_UPDT_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, FTCH_UPDT_CNTR_WIDTH);
Constant FTCH_UPDT_ONE : unsigned(FTCH_UPDT_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, FTCH_UPDT_CNTR_WIDTH);
Constant UPDT_FLTR_WIDTH : integer := 8; -- 8 clocks
Constant UPDT_FLTR_CNTR_WIDTH : integer := 4; -- 4 bits wide
Constant UPDT_FLTR_CNTR_LD_VALUE : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(UPDT_FLTR_WIDTH, UPDT_FLTR_CNTR_WIDTH);
Constant UPDT_FLTR_CNTR_ZERO : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, UPDT_FLTR_CNTR_WIDTH);
Constant UPDT_FLTR_CNTR_ONE : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, UPDT_FLTR_CNTR_WIDTH);
Constant FETCH_LIMIT : integer := 4; -- limit of allowed prefetches for DM Cmds
Constant FTCH_LIMITER_CNTR_WIDTH : integer := 4; -- 4 bits wide (16 values)
Constant FTCH_LIMIT_VALUE : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(FETCH_LIMIT, FTCH_LIMITER_CNTR_WIDTH);
Constant FTCH_LIMITER_CNTR_ZERO : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, FTCH_LIMITER_CNTR_WIDTH);
Constant FTCH_LIMITER_CNTR_ONE : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, FTCH_LIMITER_CNTR_WIDTH);
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-- Define the Fetch State Machine type and states
type sg_fetch_sm_type is (FTCH_IDLE ,
CHK_SG_DM_RDY ,
LOAD_DESC ,
XFER_DONE
);
-- Define the Status State Machine type and states
type sg_status_sm_type is (STS_IDLE ,
GET_MM2S_STATUS ,
GET_S2MM_STATUS ,
DO_UPDATE
);
-- Update Stream arbiter type
type update_arb_type is (ARB_IDLE ,
ARB_GRANT_FETCH ,
ARB_GRANT_STATUS
);
-- shutdown sequencer type
type shtdwn_type is (SHTDWN_IDLE ,
HALT_FTCH_DM ,
WAIT_FTCH_IDLE ,
WAIT_FTCH_UPDATE ,
WAIT_DM_HALT_CMPLT ,
WAIT_STS_IDLE ,
WAIT_STS_UPDATE ,
WAIT_SG_UPDATE ,
SHTDWN_CMPLT
);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
-- Fetch State machine
signal sig_ftch_sm_state : sg_fetch_sm_type := FTCH_IDLE;
signal sig_ftch_sm_state_ns : sg_fetch_sm_type := FTCH_IDLE;
signal sig_ftch_sm_set_getdesc : std_logic := '0';
signal sig_ftch_sm_set_getdesc_ns : std_logic := '0';
signal sig_ftch_sm_ld_dm_cmd : std_logic := '0';
signal sig_ftch_sm_ld_dm_cmd_ns : std_logic := '0';
signal sig_ftch_sm_push_updt : std_logic := '0';
signal sig_ftch_sm_push_updt_ns : std_logic := '0';
signal sig_ftch_sm_done : std_logic := '0';
signal sig_ftch_sm_done_ns : std_logic := '0';
-- Status State machine
signal sig_sts_sm_state : sg_status_sm_type := STS_IDLE;
signal sig_sts_sm_state_ns : sg_status_sm_type := STS_IDLE;
signal sig_sts_sm_pop_mm2s_sts : std_logic := '0';
signal sig_sts_sm_pop_mm2s_sts_ns : std_logic := '0';
signal sig_sts_sm_pop_s2mm_sts : std_logic := '0';
signal sig_sts_sm_pop_s2mm_sts_ns : std_logic := '0';
signal sig_sts_sm_push_updt : std_logic := '0';
signal sig_sts_sm_push_updt_ns : std_logic := '0';
-- High level control
signal sig_sg_active : std_logic := '1';
signal sig_sg_run : std_logic := '0';
signal sig_idle_clr : std_logic := '0';
signal sig_idle_set : std_logic := '0';
signal sig_dm_cmd_pend_cntr : unsigned(DM_CMD_PEND_WIDTH-1 downto 0) := (others => '0');
signal sig_inc_cmd_pending : std_logic := '0';
signal sig_decr_cmd_pending : std_logic := '0';
signal sig_dm_cmd_pend_eq0 : std_logic := '0';
signal sig_composite_idle : std_logic := '0';
-- Soft shutdown support
signal sig_halt_request : std_logic := '0';
signal sig_halt_cmplt_reg : std_logic := '0';
-- DataMover Cmd/Status IF
signal sig_cmd_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_tag_cntr : unsigned(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s_dsa_offset : std_logic_vector(DSA_ADDR_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s_dsa_field : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_dm_slice : std_logic_vector(DM_BTT_FIELD_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s_s2mm_cmd_rdy : std_logic := '0';
signal sig_mm2s_cmd : std_logic_vector(C_DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s_cmd_valid : std_logic := '0';
signal sig_mm2s_cmd_ready : std_logic := '0';
signal sig_mm2s_sts_tready : std_logic ;
signal sig_mm2s_sts_tvalid : std_logic ;
signal sig_mm2s_sts_tdata : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0);
signal sig_s2mm_cmd : std_logic_vector(C_DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cmd_valid : std_logic := '0';
signal sig_s2mm_cmd_ready : std_logic := '0';
signal sig_s2mm_sts_tready : std_logic ;
signal sig_s2mm_sts_tvalid : std_logic ;
signal sig_s2mm_sts_tdata : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0);
-- DataMover Status Scoring and Update
signal sig_mm2s_status_reg : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_status_reg : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s_slverr : std_logic := '0';
signal sig_mm2s_decerr : std_logic := '0';
signal sig_mm2s_interr : std_logic := '0';
signal sig_s2mm_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_slverr : std_logic := '0';
signal sig_s2mm_decerr : std_logic := '0';
signal sig_s2mm_interr : std_logic := '0';
signal sig_mm2s2cntl_err : std_logic := '0';
signal sig_s2mm2cntl_err : std_logic := '0';
signal sig_composite_interr : std_logic := '0';
signal sig_composite_slverr : std_logic := '0';
signal sig_composite_decerr : std_logic := '0';
signal sig_tag_error : std_logic := '0';
-- SG Update Ready signals
signal sig_fetch_updptr_tready : std_logic := '0';
signal sig_status_updsts_tready : std_logic := '0';
-- Descriptor Fetch support
signal sig_fetch_dbeat_cnt : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_good_fetch_dbeat : std_logic := '0';
signal sig_fetch_go : std_logic := '0';
signal sig_fetch_done : std_logic := '0';
signal sig_fetch_last : std_logic := '0';
-- Descriptor fetch holding registers
signal sig_curr_desc_pntr_reg : std_logic_vector(C_SG_FETCH_DWIDTH-1 downto 0) := (others => '0');
signal sig_curr_desc_pntr_reg_64 : std_logic_vector(C_SG_FETCH_DWIDTH-1 downto 0) := (others => '0');
signal sig_src_addr_reg : std_logic_vector(C_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_dest_addr_reg : std_logic_vector(C_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_reg : std_logic_vector(C_SG_FETCH_DWIDTH-1 downto 0) := (others => '0');
-- Descriptor fetch SG update support
signal sig_ld_fetch_update_reg : std_logic := '0';
signal sig_pop_fetch_update_reg : std_logic := '0';
signal sig_fetch_update_reg : std_logic_vector(C_SG_PTR_UPDATE_DWIDTH-1 downto 0) := (others => '0');
signal sig_fetch_update_full_1 : std_logic := '0';
signal sig_fetch_update_empty_1 : std_logic := '0';
signal sig_fetch_update_full : std_logic := '0';
signal sig_fetch_update_empty : std_logic := '0';
signal sig_fetch_update_last : std_logic := '0';
-- Status SG Update support
signal sig_ld_dm_status_reg : std_logic := '0';
signal sig_pop_dm_status_reg : std_logic := '0';
signal sig_dm_status_reg : std_logic_vector(C_SG_STS_UPDATE_DWIDTH-1 downto 0) := (others => '0');
signal sig_dm_status_full : std_logic := '0';
signal sig_dm_status_empty : std_logic := '0';
-- Controlled Shutdown support
Signal sig_shtdwn_sm_state : shtdwn_type := SHTDWN_IDLE;
Signal sig_shtdwn_sm_state_ns : shtdwn_type := SHTDWN_IDLE;
signal sig_shtdwn_sm_flush_sg : std_logic := '0';
signal sig_shtdwn_sm_flush_sg_ns : std_logic := '0';
signal sig_shtdwn_sm_set_ftch_halt : std_logic := '0';
signal sig_shtdwn_sm_set_ftch_halt_ns : std_logic := '0';
signal sig_shtdwn_sm_set_dm_halt : std_logic := '0';
signal sig_shtdwn_sm_set_dm_halt_ns : std_logic := '0';
signal sig_shtdwn_sm_set_sts_halt : std_logic := '0';
signal sig_shtdwn_sm_set_sts_halt_ns : std_logic := '0';
signal sig_shtdwn_sm_set_cmplt : std_logic := '0';
signal sig_shtdwn_sm_set_cmplt_ns : std_logic := '0';
signal sig_do_shutdown : std_logic := '0';
signal sig_sg_error : std_logic := '0';
signal sig_halt_fetch : std_logic := '0';
signal sig_halt_status : std_logic := '0';
signal sig_halt_dm : std_logic := '0';
signal sig_dmhalt_cmplt : std_logic := '0';
signal sig_flush_sg : std_logic := '0';
signal sig_ftchsm_idle : std_logic := '0';
signal sig_stssm_idle : std_logic := '0';
-- SG Idle detection enhancement
signal sig_ftch_updt_cntr : unsigned(FTCH_UPDT_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ftch_updt_cntr : std_logic := '0';
signal sig_decr_ftch_updt_cntr : std_logic := '0';
signal sig_ftch_updt_cntr_eq0 : std_logic := '0';
signal sig_final_updt_idle : std_logic := '0';
signal sig_update_idle_rising : std_logic := '0';
signal sig_shutdown_idle : std_logic := '0';
signal sig_shutdown_idle_rising : std_logic := '0';
signal sig_updt_filter_cntr : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_updt_filter_cntr_eq0 : std_logic := '0';
signal sig_ld_updt_filter_cntr : std_logic := '0';
-- SG Fetch Limiter (lock up avoidance)
signal sig_ftch_limit_cntr : unsigned(FTCH_LIMITER_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ftch_limit_cntr : std_logic := '0';
signal sig_decr_ftch_limit_cntr : std_logic := '0';
signal sig_ftch_limit_cntr_eq0 : std_logic := '0';
signal sig_ftch_limit_cntr_eqlimit : std_logic := '0';
signal type_of_burst_write : std_logic;
signal type_of_burst : std_logic;
signal ZERO_WORD : std_logic_vector (31 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- SG Run/Stop
-------------------------------------------------------------------------------
sgcntlr2sg_run_stop <= sig_sg_run ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SG_RUN_FLOP
--
-- Process Description:
-- Implements the flop for the SG Run control. The Run/Stop
-- control is set when SG Mode is enabled and the Current
-- Descriptor Register is updated by SW (in the Reg Module).
--
-------------------------------------------------------------
IMP_SG_RUN_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
reg2sgcntl_sg_mode = '0') then
sig_sg_run <= '0';
elsif (reg2sgcntl_currdesc_updated = '1') then
sig_sg_run <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_SG_RUN_FLOP;
-------------------------------------------------------------------------------
-- SG Xfer "Really" Done Detection
-------------------------------------------------------------------------------
sig_idle_set <= (not(sig_do_shutdown) and -- not in a shutdown sequence
sig_update_idle_rising and -- update engine done
sig_ftch_updt_cntr_eq0 and -- the last update queued
sig_updt_filter_cntr_eq0 and
sg2sgcntlr_ftch_idle) or -- not in update filter period
sig_shutdown_idle_rising; -- in shutdown and complete
sig_incr_ftch_updt_cntr <= sig_ftch_sm_set_getdesc ;
sig_decr_ftch_updt_cntr <= sig_pop_dm_status_reg ;
sig_ftch_updt_cntr_eq0 <= '1'
when sig_ftch_updt_cntr = FTCH_UPDT_ZERO
Else '0';
sig_final_updt_idle <= sig_ftch_updt_cntr_eq0 and -- all fetches have corresponding updates
sg2sgcntlr_updt_idle ; -- and the SG Update engine is idle
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FTCH_UPDT_CNTR
--
-- Process Description:
-- Implements a counter to keep track of the number of
-- descriptor fetches and updates. This is used to detirmine
-- when SG operation are really completed.
--
-------------------------------------------------------------
IMP_FTCH_UPDT_CNTR : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_ftch_updt_cntr <= FTCH_UPDT_ZERO;
elsif (sig_incr_ftch_updt_cntr = '1' and
sig_decr_ftch_updt_cntr = '0') then
sig_ftch_updt_cntr <= sig_ftch_updt_cntr + FTCH_UPDT_ONE;
Elsif (sig_ftch_updt_cntr_eq0 = '0' and
sig_decr_ftch_updt_cntr = '1' and
sig_incr_ftch_updt_cntr = '0') Then
sig_ftch_updt_cntr <= sig_ftch_updt_cntr - FTCH_UPDT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_FTCH_UPDT_CNTR;
------------------------------------------------------------
-- Instance: I_GEN_SG_IDLE_RISE
--
-- Description:
-- Generates a pulse signaling the last SG update
-- operation has completed.
--
------------------------------------------------------------
I_GEN_SG_IDLE_RISE : entity axi_cdma_v4_1_14.axi_cdma_pulse_gen
generic map (
C_INCLUDE_SYNCHRO => NO_SYNCHRONIZERS ,
C_POS_EDGE_TRIG => POSITIVE_EDGE_TRIGGER ,
C_PULSE_WIDTH_CLKS => ONE_CLK
)
port map (
Clk_In => axi_aclk ,
Rst_In => axi_reset ,
Sig_in => sg2sgcntlr_updt_idle ,
Pulse_Out => sig_update_idle_rising
);
-------------------------------------------------------------------------------
-- Update Filter Counter
--
-- Used to filter the lag between the acceptance of an update by the SG
-- and the Update Idle flag being reset by the SG (going to not idle).
--
-------------------------------------------------------------------------------
-- Start the filter counter when a status update is accepted
-- by the SG Update interface
sig_ld_updt_filter_cntr <= sig_pop_dm_status_reg;
sig_updt_filter_cntr_eq0 <= '1'
when (sig_updt_filter_cntr = UPDT_FLTR_CNTR_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_UPDT_FILTER_CNTR
--
-- Process Description:
-- Implements a counter to filter the time lag between an update
-- being accepted by the SG and the Update Idle Flag being reset
-- by the SG.
--
-------------------------------------------------------------
IMP_UPDT_FILTER_CNTR : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_updt_filter_cntr <= UPDT_FLTR_CNTR_ZERO;
Elsif (sig_ld_updt_filter_cntr = '1') Then
sig_updt_filter_cntr <= UPDT_FLTR_CNTR_LD_VALUE;
Elsif (sig_updt_filter_cntr_eq0 = '0') Then
sig_updt_filter_cntr <= sig_updt_filter_cntr - UPDT_FLTR_CNTR_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_UPDT_FILTER_CNTR;
-------------------------------------------------------------------------------
-- Idle Set and Clear logic
-------------------------------------------------------------------------------
-- The SG operation starts when the Tail Pointer is written by SW in the
-- Register Module
sgcntl2reg_idle_set <= sig_idle_set ;
sgcntl2reg_idle_clr <= sig_idle_clr ;
------------------------------------------------------------
-- Instance: I_GEN_IDLE_CLR
--
-- Description:
-- Generates the Idle Clear pulse of 1 clock width.
--
------------------------------------------------------------
I_GEN_IDLE_CLR : entity axi_cdma_v4_1_14.axi_cdma_pulse_gen
generic map (
C_INCLUDE_SYNCHRO => NO_SYNCHRONIZERS ,
C_POS_EDGE_TRIG => POSITIVE_EDGE_TRIGGER ,
C_PULSE_WIDTH_CLKS => ONE_CLK
)
port map (
Clk_In => axi_aclk ,
Rst_In => axi_reset ,
Sig_in => reg2sgcntl_tailpntr_updated,
Pulse_Out => sig_idle_clr
);
sig_shutdown_idle <= (sig_do_shutdown and -- In a shutdown sequence and
sig_halt_cmplt_reg ); -- shutdown complete
------------------------------------------------------------
-- Instance: I_GEN_IDLE_SET
--
-- Description:
-- Generates the Idle Set pulse of 1 clock width.
--
------------------------------------------------------------
I_GEN_IDLE_SET : entity axi_cdma_v4_1_14.axi_cdma_pulse_gen
generic map (
C_INCLUDE_SYNCHRO => NO_SYNCHRONIZERS ,
C_POS_EDGE_TRIG => POSITIVE_EDGE_TRIGGER ,
C_PULSE_WIDTH_CLKS => ONE_CLK
)
port map (
Clk_In => axi_aclk ,
Rst_In => axi_reset ,
Sig_in => sig_shutdown_idle ,
Pulse_Out => sig_shutdown_idle_rising
);
-- Controls for the DataMover Command pending counter
sig_inc_cmd_pending <= sig_ftch_sm_ld_dm_cmd;
sig_decr_cmd_pending <= sig_sts_sm_push_updt ;
sig_dm_cmd_pend_eq0 <= '1'
when (sig_dm_cmd_pend_cntr = DM_CMD_PEND_ZERO)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DM_CMD_PEND_CNTR
--
-- Process Description:
--
--
-------------------------------------------------------------
IMP_DM_CMD_PEND_CNTR : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_dm_cmd_pend_cntr <= DM_CMD_PEND_ZERO;
elsif (sig_inc_cmd_pending = '1' and
sig_decr_cmd_pending = '0') then
sig_dm_cmd_pend_cntr <= sig_dm_cmd_pend_cntr + DM_CMD_PEND_ONE;
elsif (sig_inc_cmd_pending = '0' and
sig_decr_cmd_pending = '1' and
sig_dm_cmd_pend_eq0 = '0') then
sig_dm_cmd_pend_cntr <= sig_dm_cmd_pend_cntr - DM_CMD_PEND_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_DM_CMD_PEND_CNTR;
-------------------------------------------------------------------------------
-- SOF/EOF control logic
-------------------------------------------------------------------------------
-- Since CDMA does not need to support SOF/EOF concept (no Stream IF) then
-- every descriptor processed is by definition a EOF/SOF case (from the
-- viewpoint of the DataMover and the SG engine).
sgcntl2sg_pkt_sof <= sig_idle_clr or -- Used to stop Delay Timer when a descr is ready or
sig_shtdwn_sm_set_cmplt ; -- Stop delay timer on shutdown completion
sgcntl2sg_pkt_eof <= sig_idle_set ; -- Used to start Delay timer
-------------------------------------------------------------------------------
-- IOC and Delay Interrupt set control logic
-------------------------------------------------------------------------------
-- Just pass these through the SG Controller for now. These were
-- brought through the SG Controller just in case the need arose
-- for some protection from the register module during simple DMA
-- mode.
sgcntl2reg_ioc_irq_set <= sg2sgcntl_ioc_irq_set;
sgcntl2reg_dly_irq_set <= sg2sgcntl_dly_irq_set;
-------------------------------------------------------------------------------
-- Current Descriptor Update to Register module control logic
-------------------------------------------------------------------------------
-- Update the Register module with the latest Descriptor's Current
-- DEscriptor Address when the SG Fetch Update occurs.
sgcntlr2reg_new_curdesc_wren <= sig_ftch_sm_push_updt ;
sgcntlr2reg_new_curdesc (31 downto 0) <= sig_curr_desc_pntr_reg ;
-------------------------------------------------------------------------------
-- SG DMA Error set control logic
-------------------------------------------------------------------------------
-- Just pass these through the SG Controller for now. These were
-- brought through the SG Controller just in case the need arose
-- for some protection from the register module during simple DMA
-- mode.
sgcntlr2reg_dma_interr_set <= sg2sgcntlr_dma_interr_set ;
sgcntlr2reg_dma_slverr_set <= sg2sgcntlr_dma_slverr_set ;
sgcntlr2reg_dma_decerr_set <= sg2sgcntlr_dma_decerr_set ;
-------------------------------------------------------------------------------
-- Misc logic
-------------------------------------------------------------------------------
-- See if DataMover is ready for next command
sig_mm2s_s2mm_cmd_rdy <= sig_mm2s_cmd_ready and
sig_s2mm_cmd_ready;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SG_ACTIVE_FLAG
--
-- Process Description:
-- Internal flag for enable and disable of state machines.
--
-------------------------------------------------------------
IMP_SG_ACTIVE_FLAG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_idle_set = '1') then
-- sig_sg_active <= '0';
elsif (sig_idle_clr = '1') then
-- sig_sg_active <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_SG_ACTIVE_FLAG;
-------------------------------------------------------------------------------
-- FETCH Prefetch Limiter Logic
-------------------------------------------------------------------------------
sig_incr_ftch_limit_cntr <= sig_ftch_sm_set_getdesc ;
sig_decr_ftch_limit_cntr <= sig_pop_dm_status_reg ;
sig_ftch_limit_cntr_eq0 <= '1'
when sig_ftch_limit_cntr = FTCH_LIMITER_CNTR_ZERO
Else '0';
sig_ftch_limit_cntr_eqlimit <= '1'
when sig_ftch_limit_cntr = FTCH_LIMIT_VALUE
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FTCH_LIMIT_CNTR
--
-- Process Description:
-- Implements a counter to keep track of the number of
-- descriptor fetches and updates. This is used to limit the
-- difference to a fixed value to keep the SG Update Queue from
-- going full. The SG Update Queue full can lead to SG lockup.
--
-------------------------------------------------------------
IMP_FTCH_LIMIT_CNTR : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_ftch_limit_cntr <= FTCH_LIMITER_CNTR_ZERO;
elsif (sig_incr_ftch_limit_cntr = '1' and
sig_decr_ftch_limit_cntr = '0') then
sig_ftch_limit_cntr <= sig_ftch_limit_cntr + FTCH_LIMITER_CNTR_ONE;
Elsif (sig_ftch_limit_cntr_eq0 = '0' and
sig_decr_ftch_limit_cntr = '1' and
sig_incr_ftch_limit_cntr = '0') Then
sig_ftch_limit_cntr <= sig_ftch_limit_cntr - FTCH_LIMITER_CNTR_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_FTCH_LIMIT_CNTR;
-------------------------------------------------------------------------------
-- Descriptor Fetch Logic
-------------------------------------------------------------------------------
sgcntl2sg_ftch_tready <= sig_fetch_go or
sig_halt_fetch ; -- force tready high on a shutdown
-- sig_fetch_last <= sg2sgcntlr_ftch_tlast;
sig_fetch_last <= '1'; --sg2sgcntlr_ftch_tlast;
-- sig_good_fetch_dbeat <= sig_fetch_go and
sig_good_fetch_dbeat <= sg2sgcntlr_ftch_tvalid_new;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FETCH_GO_FLOP
--
-- Process Description:
-- Implements the fetch go and done flags
--
-------------------------------------------------------------
IMP_FETCH_GO_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_ftch_sm_done = '1') then
-- sig_fetch_go <= '0';
-- sig_fetch_done <= '0';
elsif (sig_ftch_sm_set_getdesc_ns = '1') then
-- sig_fetch_go <= '1';
-- sig_fetch_done <= '0';
Elsif (sig_good_fetch_dbeat = '1' and
sig_fetch_last = '1') Then
-- sig_fetch_go <= '0';
-- sig_fetch_done <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_FETCH_GO_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FETCH_DB_CNTR
--
-- Process Description:
-- Implements the descriptor fetch data beat counter
--
-------------------------------------------------------------
IMP_FETCH_DB_CNTR : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_ftch_sm_set_getdesc_ns = '1') then
sig_fetch_dbeat_cnt <= (others => '0');
elsif (sig_good_fetch_dbeat = '1' and
sig_fetch_done = '0' and
sig_fetch_last = '0') then
sig_fetch_dbeat_cnt <= sig_fetch_dbeat_cnt +
DESCR_DBEAT_CNT_ONE ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_FETCH_DB_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CURR_DESC_PNTR_REG
--
-- Process Description:
-- Implements the Next descriptor pointer reg. It is
-- cleared when the fetch process is complete.
--
-------------------------------------------------------------
-- IMP_CURR_DESC_PNTR_REG : process (axi_aclk)
-- begin
-- if (axi_aclk'event and axi_aclk = '1') then
-- if (axi_reset = '1' or
-- sig_ftch_sm_done = '1') then
-- sig_curr_desc_pntr_reg <= (others => '0');
-- elsif (sig_good_fetch_dbeat = '1' and
-- sig_fetch_dbeat_cnt = CDA_LS) then
sig_curr_desc_pntr_reg <= sg2sgcntlr_ftch_tdata_new (127 downto 96);
-- else
-- null; -- Hold Current State
-- end if;
-- end if;
-- end process IMP_CURR_DESC_PNTR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SRC_ADDR_REG
--
-- Process Description:
-- Implements the Source Address register. It is
-- cleared when the fetch process is complete.
--
-------------------------------------------------------------
-- IMP_SRC_ADDR_REG : process (axi_aclk)
-- begin
-- if (axi_aclk'event and axi_aclk = '1') then
-- if (axi_reset = '1' or
-- sig_ftch_sm_done = '1') then
-- sig_src_addr_reg <= (others => '0');
-- elsif (sig_good_fetch_dbeat = '1' and
-- sig_fetch_dbeat_cnt = SA_LS) then
sig_src_addr_reg (31 downto 0) <= sg2sgcntlr_ftch_tdata_new (31 downto 0);
-- else
-- null; -- Hold Current State
-- end if;
-- end if;
-- end process IMP_SRC_ADDR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DEST_ADDR_REG
--
-- Process Description:
-- Implements the Destination Address register. It is
-- cleared when the fetch process is complete.
--
-------------------------------------------------------------
-- IMP_DEST_ADDR_REG : process (axi_aclk)
-- begin
-- if (axi_aclk'event and axi_aclk = '1') then
-- if (axi_reset = '1' or
-- sig_ftch_sm_done = '1') then
-- sig_dest_addr_reg <= (others => '0');
-- elsif (sig_good_fetch_dbeat = '1' and
-- sig_fetch_dbeat_cnt = DA_LS) then
sig_dest_addr_reg(31 downto 0) <= sg2sgcntlr_ftch_tdata_new (63 downto 32);
-- else
-- null; -- Hold Current State
-- end if;
-- end if;
-- end process IMP_DEST_ADDR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BTT_REG
--
-- Process Description:
-- Implements the BTT register. It is
-- cleared when the fetch process is complete.
--
-------------------------------------------------------------
-- IMP_BTT_REG : process (axi_aclk)
-- begin
-- if (axi_aclk'event and axi_aclk = '1') then
-- if (axi_reset = '1' or
-- sig_ftch_sm_done = '1') then
-- sig_btt_reg <= (others => '0');
-- elsif (sig_good_fetch_dbeat = '1' and
-- sig_fetch_dbeat_cnt = BTT) then
sig_btt_reg <= sg2sgcntlr_ftch_tdata_new (95 downto 64);
-- else
-- null; -- Hold Current State
-- end if;
-- end if;
-- end process IMP_BTT_REG;
-------------------------------------------------------------------------------
-- Rip the needed BTT bits for the DataMover from the descriptor BTT register
-------------------------------------------------------------------------------
sig_btt_dm_slice <= sig_btt_reg(DM_BTT_FIELD_WIDTH-1 downto 0);
-------------------------------------------------------------------------------
-- Command TAG Generator (just an incrementing counter)
-- The Command tag is used for test and debug to track command execution flow
-- through the DataMover.
-------------------------------------------------------------------------------
sig_cmd_tag <= STD_LOGIC_VECTOR(sig_cmd_tag_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DM_TAG_CNTR
--
-- Process Description:
-- Command tag generator. This is just a simple counter
-- that increments every time a command is loaded into the
-- DataMover. Counter rollover is ok.
--
-------------------------------------------------------------
DM_TAG_CNTR : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
reg2sgcntl_sg_mode = '0') then
sig_cmd_tag_cntr <= (others => '0');
elsif (sig_ftch_sm_ld_dm_cmd = '1') then
sig_cmd_tag_cntr <= sig_cmd_tag_cntr + TAG_CNT_ONE;
else
null; -- hold current state
end if;
end if;
end process DM_TAG_CNTR;
-------------------------------------------------------------------------------
-- MM2S Command Generation
-------------------------------------------------------------------------------
sgcntl2mm2s_cmd_tdata <= sig_mm2s_cmd ;
sgcntl2mm2s_cmd_tvalid <= sig_mm2s_cmd_valid ;
sig_mm2s_cmd_ready <= mm2s2sgcntl_cmd_tready ;
sig_mm2s_cmd_valid <= sig_ftch_sm_ld_dm_cmd ;
type_of_burst <= '1' and (not burst_type_read);
-- Formulate the MM2S Command
sig_mm2s_cmd <= CMD_RSVD & -- reserved
sig_cmd_tag & -- Tag
sig_src_addr_reg & -- Address
'1' & -- DRR bit
'1' & -- EOF bit
sig_mm2s_dsa_field & -- DSA Field Assignment
type_of_burst &
-- '1' & -- Incrementing burst type
sig_btt_dm_slice ; -- BTT
--ORIGINAL : if C_DM_DATA_WIDTH <= 64 generate
--begin
-- Rip the Destnation address offset bits
sig_mm2s_dsa_offset <= sig_dest_addr_reg(DSA_ADDR_OFFSET_WIDTH-1 downto 0);
--end generate ORIGINAL;
--NEWDRE : if C_DM_DATA_WIDTH > 64 generate
--begin
-- -- Rip the Destnation address offset bits
-- sig_mm2s_dsa_offset <= (others => '0');
--end generate NEWDRE;
-- Size the dest addr offset to the DSA field width
sig_mm2s_dsa_field <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_mm2s_dsa_offset), CMD_DSA_WIDTH));
-------------------------------------------------------------------------------
-- MM2S Status Reg and logic
-------------------------------------------------------------------------------
sgcntl2mm2s_sts_tready <= sig_sts_sm_pop_mm2s_sts or
sig_halt_dm ; -- allow status to flush on shutdown
sig_mm2s_sts_tvalid <= mm2s2sgcntl_sts_tvalid ;
sig_mm2s_sts_tdata <= mm2s2sgcntl_sts_tdata ;
-- DataMover MM2S Error discrete
sig_mm2s2cntl_err <= mm2s2sgcntl_err ;
-- Rip the status bits from the status register
sig_mm2s_tag <= sig_mm2s_status_reg(STS_TAG_MS_INDEX downto 0);
sig_mm2s_interr <= sig_mm2s_status_reg(STS_INTERR_INDEX);
sig_mm2s_decerr <= sig_mm2s_status_reg(STS_DECERR_INDEX);
sig_mm2s_slverr <= sig_mm2s_status_reg(STS_SLVERR_INDEX);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_MM2S_STATUS_REG
--
-- Process Description:
-- Implements the MM2S status reply holding register.
--
-------------------------------------------------------------
IMP_MM2S_STATUS_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_sts_sm_push_updt = '1') then
sig_mm2s_status_reg <= (others => '0');
elsif (sig_sts_sm_pop_mm2s_sts = '1') then
sig_mm2s_status_reg <= sig_mm2s_sts_tdata;
else
null; -- hold current state
end if;
end if;
end process IMP_MM2S_STATUS_REG;
-------------------------------------------------------------------------------
-- S2MM Command Generation
-------------------------------------------------------------------------------
sgcntl2s2mm_cmd_tdata <= sig_s2mm_cmd ;
sgcntl2s2mm_cmd_tvalid <= sig_s2mm_cmd_valid ;
sig_s2mm_cmd_ready <= s2mm2sgcntl_cmd_tready ;
sig_s2mm_cmd_valid <= sig_ftch_sm_ld_dm_cmd ;
type_of_burst_write <= '1' and (not burst_type_write);
-- Formulate the S2MM Command
sig_s2mm_cmd <= CMD_RSVD & -- reserved
sig_cmd_tag & -- Tag
sig_dest_addr_reg & -- Address
'1' & -- DRR bit
'1' & -- EOF bit
CMD_DSA_ZEROED & -- DSA Field Assignment
type_of_burst_write &
-- '1' & -- Incrementing burst type
sig_btt_dm_slice ; -- BTT
-------------------------------------------------------------------------------
-- S2MM Status Reg and logic
-------------------------------------------------------------------------------
sgcntl2s2mm_sts_tready <= sig_sts_sm_pop_s2mm_sts or
sig_halt_dm ; -- allow status to flush on shutdown;
sig_s2mm_sts_tvalid <= s2mm2sgcntl_sts_tvalid ;
sig_s2mm_sts_tdata <= s2mm2sgcntl_sts_tdata ;
-- DataMover S2MM Error discrete
sig_s2mm2cntl_err <= s2mm2sgcntl_err ;
-- Rip the status bits from the status register
sig_s2mm_tag <= sig_s2mm_status_reg(STS_TAG_MS_INDEX downto 0);
sig_s2mm_interr <= sig_s2mm_status_reg(STS_INTERR_INDEX);
sig_s2mm_decerr <= sig_s2mm_status_reg(STS_DECERR_INDEX);
sig_s2mm_slverr <= sig_s2mm_status_reg(STS_SLVERR_INDEX);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S2MM_STATUS_REG
--
-- Process Description:
-- Implements the MM2S status reply holding register.
--
-------------------------------------------------------------
IMP_S2MM_STATUS_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_sts_sm_push_updt = '1') then
sig_s2mm_status_reg <= (others => '0');
elsif (sig_sts_sm_pop_s2mm_sts = '1') then
sig_s2mm_status_reg <= sig_s2mm_sts_tdata;
else
null; -- hold current state
end if;
end if;
end process IMP_S2MM_STATUS_REG;
-------------------------------------------------------------------------------
-- Fetch Update words formulation
-------------------------------------------------------------------------------
-- Assign the Fetch update outputs to the SG Fetch Update port
sgcntl2sg_updptr_tvalid <= sig_fetch_update_full ;
sgcntl2sg_updptr_tdata <= sig_fetch_update_reg ;
sgcntl2sg_updptr_tlast <= sig_fetch_update_last ;
sig_fetch_updptr_tready <= sg2sgcntlr_updptr_tready ;
sig_fetch_update_last <= sig_fetch_update_full;-- and
-- not(sig_fetch_update_full_1);
sig_ld_fetch_update_reg <= sig_ftch_sm_push_updt and
sig_fetch_update_empty ;
sig_pop_fetch_update_reg <= sig_fetch_update_full and
sig_fetch_updptr_tready ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FETCH_UPDATE_FLAGS
--
-- Process Description:
-- Implements the Fetch Update Register status flags.
-- Note that this simulates a 2-deep register requiring
-- 2 pops to become empty (not full).
--
-------------------------------------------------------------
IMP_FETCH_UPDATE_FLAGS : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or sig_pop_fetch_update_reg = '1' or
sig_halt_fetch = '1') then
-- sig_fetch_update_full_1 <= '0';
sig_fetch_update_full <= '0';
-- sig_fetch_update_empty_1 <= '1';
sig_fetch_update_empty <= '1';
elsif (sig_ld_fetch_update_reg = '1') then
-- sig_fetch_update_full_1 <= '1';
sig_fetch_update_full <= '1';
-- sig_fetch_update_empty_1 <= '0';
sig_fetch_update_empty <= '0';
-- elsif (sig_pop_fetch_update_reg = '1') then
-- sig_fetch_update_full_1 <= '0';
-- sig_fetch_update_full <= sig_fetch_update_full_1;
-- sig_fetch_update_empty_1 <= '1';
-- sig_fetch_update_empty <= sig_fetch_update_empty_1;
else
null; -- Hold Current State
end if;
end if;
end process IMP_FETCH_UPDATE_FLAGS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FETCH_UPDATE_REG
--
-- Process Description:
-- Implements the fetch update register for the current
-- descriptor address write to the SG Update port.
--
-------------------------------------------------------------
IMP_FETCH_UPDATE_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_pop_fetch_update_reg = '1') then
sig_fetch_update_reg (31 downto 0) <= (others => '0');
elsif (sig_ld_fetch_update_reg = '1') then
sig_fetch_update_reg (31 downto 0) <= sig_curr_desc_pntr_reg; -- Curr Descr Pointer LS
else
null; -- Hold Current State
end if;
end if;
end process IMP_FETCH_UPDATE_REG;
GEN_64_ADDR : if (C_SG_ADDR_WIDTH = 64) generate
begin
IMP_FETCH_UPDATE_REG1 : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_pop_fetch_update_reg = '1') then
sig_fetch_update_reg (63 downto 32) <= (others => '0');
elsif (sig_ld_fetch_update_reg = '1') then
sig_fetch_update_reg (63 downto 32) <= sig_curr_desc_pntr_reg_64; -- Curr Descr Pointer LS
else
null; -- Hold Current State
end if;
end if;
end process IMP_FETCH_UPDATE_REG1;
sgcntlr2reg_new_curdesc (63 downto 32) <= sig_curr_desc_pntr_reg_64 ;
sig_src_addr_reg (63 downto 32) <= sg2sgcntlr_ftch_tdata_new (159 downto 128);
sig_dest_addr_reg(63 downto 32) <= sg2sgcntlr_ftch_tdata_new (191 downto 160);
sig_curr_desc_pntr_reg_64 <= sg2sgcntlr_ftch_tdata_new (223 downto 192);
end generate GEN_64_ADDR;
-------------------------------------------------------------------------------
-- Status DM Error merging
-------------------------------------------------------------------------------
-- If the MM2S Status tag does not match the S2MM Status tag,
-- this is a nasty internal error where a status reply has been
-- dropped by the DataMover. This is a unique condition for the
-- CDMA application.
sig_tag_error <= '0'
When (sig_halt_dm = '1')
else '1'
when (sig_s2mm_tag /= sig_mm2s_tag)
Else '0';
sig_composite_interr <= (sig_s2mm_interr or
sig_mm2s_interr or
sig_tag_error) and
not(sig_halt_dm) ;
sig_composite_slverr <= (sig_s2mm_slverr or
sig_mm2s_slverr) and
not(sig_halt_dm) ;
sig_composite_decerr <= (sig_s2mm_decerr or
sig_mm2s_decerr) and
not(sig_halt_dm) ;
-------------------------------------------------------------------------------
-- Status Update Register Logic
-------------------------------------------------------------------------------
-- Assign Output Stream port to SG Status Update interface
sgcntl2sg_updsts_tvalid <= sig_dm_status_full;
sgcntl2sg_updsts_tdata <= sig_dm_status_reg ;
sgcntl2sg_updsts_tlast <= '1' ;
sig_status_updsts_tready <= sg2sgcntlr_updsts_tready ;
sig_ld_dm_status_reg <= sig_sts_sm_push_updt and
sig_dm_status_empty;
sig_pop_dm_status_reg <= sig_dm_status_full and
sig_status_updsts_tready ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DM_STATUS_REG
--
-- Process Description:
-- Implements the composite transfer status register for the
-- descriptor.
--
-------------------------------------------------------------
IMP_DM_STATUS_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1' or
sig_pop_dm_status_reg = '1' or
sig_halt_status = '1') then
sig_dm_status_reg <= (others => '0');
sig_dm_status_full <= '0';
sig_dm_status_empty <= '1';
elsif (sig_ld_dm_status_reg = '1') then
sig_dm_status_reg <= '1' & -- SG Update IOC bit
'1' & -- Descriptor Cmplt bit
sig_composite_decerr & -- DM Decode Error
sig_composite_slverr & -- DM Slave Error
sig_composite_interr & -- DM Internal Error
STATUS_RSVD ; -- Unused (zeros)
sig_dm_status_full <= '1';
sig_dm_status_empty <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_DM_STATUS_REG;
-------------------------------------------------------------------------------
-- Descriptor Fetch State Machine
-------------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_FETCH_SM_COMB
--
-- Process Description:
-- Implements the combinatorial portion of the Descriptor
-- Fetch from SG state machine.
--
-------------------------------------------------------------
IMP_FETCH_SM_COMB : process (sig_ftch_sm_state ,
sig_halt_fetch ,
sig_sg_active ,
sig_sg2sgcntlr_ftch_desc_available ,
sig_mm2s_s2mm_cmd_rdy ,
sig_fetch_update_empty ,
-- sig_fetch_done ,
sig_ftch_limit_cntr_eqlimit
)
begin
-- assign the default values
sig_ftch_sm_state_ns <= FTCH_IDLE ;
sig_ftch_sm_set_getdesc_ns <= '0' ;
sig_ftch_sm_ld_dm_cmd_ns <= '0' ;
sig_ftch_sm_push_updt_ns <= '0' ;
sig_ftch_sm_done_ns <= '0' ;
case sig_ftch_sm_state is
---------------------------------
when FTCH_IDLE =>
If (sig_sg_active = '1' and
sig_halt_fetch = '0') Then -- Start operations
sig_ftch_sm_state_ns <= CHK_SG_DM_RDY ;
Else -- wait here
sig_ftch_sm_state_ns <= FTCH_IDLE ;
End if;
---------------------------------
when CHK_SG_DM_RDY =>
if (sig_halt_fetch = '1') then
sig_ftch_sm_state_ns <= XFER_DONE ;
elsif (sig_ftch_limit_cntr_eqlimit = '0' and
sig_sg2sgcntlr_ftch_desc_available = '1' and
sig_mm2s_s2mm_cmd_rdy = '1' and
sig_fetch_update_empty = '1') then
sig_ftch_sm_state_ns <= LOAD_DESC ;
sig_ftch_sm_set_getdesc_ns <= '1' ;
sig_ftch_sm_ld_dm_cmd_ns <= '1' ;
sig_ftch_sm_push_updt_ns <= '1' ;
else
sig_ftch_sm_state_ns <= CHK_SG_DM_RDY ;
end if;
---------------------------------
when LOAD_DESC =>
sig_ftch_sm_set_getdesc_ns <= '0' ;
if (sig_halt_fetch = '1') then
sig_ftch_sm_state_ns <= XFER_DONE ;
else --if (sig_fetch_done = '1') then
sig_ftch_sm_state_ns <= XFER_DONE ;
-- sig_ftch_sm_ld_dm_cmd_ns <= '1' ;
-- sig_ftch_sm_push_updt_ns <= '1' ;
-- else
-- sig_ftch_sm_state_ns <= LOAD_DESC ;
end if;
---------------------------------
when XFER_DONE =>
sig_ftch_sm_state_ns <= FTCH_IDLE ;
sig_ftch_sm_done_ns <= '1' ;
---------------------------------
when others =>
sig_ftch_sm_state_ns <= FTCH_IDLE ;
end case;
end process IMP_FETCH_SM_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FETCH_SM_REG
--
-- Process Description:
-- Implements the registered portion of the descriptor Fetch
-- State Machine.
--
-------------------------------------------------------------
IMP_FETCH_SM_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_ftch_sm_state <= FTCH_IDLE ;
sig_ftch_sm_set_getdesc <= '0' ;
sig_ftch_sm_ld_dm_cmd <= '0' ;
sig_ftch_sm_push_updt <= '0' ;
sig_ftch_sm_done <= '0' ;
-- sig_fetch_go <= '0' ;
sig_fetch_done <= '0' ;
else
sig_ftch_sm_state <= sig_ftch_sm_state_ns ;
sig_ftch_sm_set_getdesc <= sig_ftch_sm_set_getdesc_ns ;
-- sig_fetch_go <= sig_ftch_sm_set_getdesc_ns ;
sig_fetch_done <= sig_fetch_go;
sig_ftch_sm_ld_dm_cmd <= sig_ftch_sm_ld_dm_cmd_ns ;
sig_ftch_sm_push_updt <= sig_ftch_sm_push_updt_ns ;
sig_ftch_sm_done <= sig_ftch_sm_done_ns ;
end if;
end if;
end process IMP_FETCH_SM_REG;
sig_fetch_go <= sig_ftch_sm_set_getdesc_ns ;
-------------------------------------------------------------------------------
-- Status Update State Machine
-------------------------------------------------------------------------------
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_STATUS_SM_COMB
--
-- Process Description:
-- Implements the combinatorial portion of the Status Update
-- State Machine.
--
-------------------------------------------------------------
IMP_STATUS_SM_COMB : process (sig_sts_sm_state ,
sig_halt_status ,
sig_sg_active ,
sig_dm_cmd_pend_eq0 ,
sig_mm2s_sts_tvalid ,
sig_s2mm_sts_tvalid ,
sig_dm_status_empty
)
begin
-- assign the default values
sig_sts_sm_state_ns <= STS_IDLE ;
sig_sts_sm_pop_mm2s_sts_ns <= '0' ;
sig_sts_sm_pop_s2mm_sts_ns <= '0' ;
sig_sts_sm_push_updt_ns <= '0' ;
case sig_sts_sm_state is
---------------------------------
when STS_IDLE =>
If (sig_sg_active = '1' and
sig_halt_status = '0') Then -- Start operations
sig_sts_sm_state_ns <= GET_MM2S_STATUS ;
Else -- wait here
sig_sts_sm_state_ns <= STS_IDLE ;
End if;
---------------------------------
when GET_MM2S_STATUS =>
if (sig_halt_status = '1') then
sig_sts_sm_state_ns <= STS_IDLE ;
elsif (sig_mm2s_sts_tvalid = '1') then
sig_sts_sm_state_ns <= GET_S2MM_STATUS ;
sig_sts_sm_pop_mm2s_sts_ns <= '1' ;
else
sig_sts_sm_state_ns <= GET_MM2S_STATUS ;
end if;
---------------------------------
when GET_S2MM_STATUS =>
if (sig_halt_status = '1') then
sig_sts_sm_state_ns <= STS_IDLE ;
elsif (sig_s2mm_sts_tvalid = '1') then
sig_sts_sm_state_ns <= DO_UPDATE ;
sig_sts_sm_pop_s2mm_sts_ns <= '1' ;
else
sig_sts_sm_state_ns <= GET_S2MM_STATUS ;
end if;
---------------------------------
when DO_UPDATE =>
If (sig_dm_status_empty = '1') Then
sig_sts_sm_state_ns <= STS_IDLE ;
sig_sts_sm_push_updt_ns <= '1' ;
Else
sig_sts_sm_state_ns <= DO_UPDATE ;
End if;
---------------------------------
when others => -- shouldn't ever get here
sig_sts_sm_state_ns <= STS_IDLE ;
end case;
end process IMP_STATUS_SM_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STATUS_SM_REG
--
-- Process Description:
-- Implements the registered portion of the Status Update
-- State Machine.
--
-------------------------------------------------------------
IMP_STATUS_SM_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_sts_sm_state <= STS_IDLE ;
sig_sts_sm_pop_mm2s_sts <= '0' ;
sig_sts_sm_pop_s2mm_sts <= '0' ;
sig_sts_sm_push_updt <= '0' ;
else
sig_sts_sm_state <= sig_sts_sm_state_ns ;
sig_sts_sm_pop_mm2s_sts <= sig_sts_sm_pop_mm2s_sts_ns ;
sig_sts_sm_pop_s2mm_sts <= sig_sts_sm_pop_s2mm_sts_ns ;
sig_sts_sm_push_updt <= sig_sts_sm_push_updt_ns ;
end if;
end if;
end process IMP_STATUS_SM_REG;
-------------------------------------------------------------------------------
-- controlled Shutdown State Machine and related logic
-------------------------------------------------------------------------------
-- Reset Module HALT request and complete reply
sig_halt_request <= rst2sgcntl_halt ;
sgcntl2rst_halt_cmplt <= sig_halt_cmplt_reg;
-- SG Descriptor Queue flush request
sgcntlr2sg_desc_flush <= sig_flush_sg ;
-- DataMover Halt requests
sgcntl2mm2s_halt <= sig_halt_dm ;
sgcntl2s2mm_halt <= sig_halt_dm ;
-- Composite DataMover halt complete flag
sig_dmhalt_cmplt <= mm2s2sgcntl_halt_cmplt and
s2mm2sgcntl_halt_cmplt ;
-- Fetch State Machine Idle flag
sig_ftchsm_idle <= '1'
when (sig_ftch_sm_state = FTCH_IDLE)
Else '0';
-- Status State Machine Idle flag
sig_stssm_idle <= '1'
when (sig_sts_sm_state = STS_IDLE)
Else '0';
-- Composite error flag indicating that an error occured
-- during a descriptor fetch or update operation
sig_sg_error <= sg2sgcntlr_ftch_error or
sg2sgcntlr_updt_error ;
-- Formulate the shutdown request decision logic
sig_do_shutdown <= sig_halt_request or
sig_sg_error or
sg2sgcntlr_ftch_stale_desc or
sg2sgcntlr_dma_interr_set or
sg2sgcntlr_dma_slverr_set or
sg2sgcntlr_dma_decerr_set ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_CMPLT_REG
--
-- Process Description:
-- Implements the Halt Complete register.
-- This is sticky and is only cleared by a reset.
--
-------------------------------------------------------------
IMP_HALT_CMPLT_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_halt_cmplt_reg <= '0';
elsif (sig_shtdwn_sm_set_cmplt_ns = '1') then
sig_halt_cmplt_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_HALT_CMPLT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DM_HALT_FLOP
--
-- Process Description:
-- Implements the sticky flag that requests a DataMover
-- HALT.
-- This is sticky and is only cleared by a reset.
--
-------------------------------------------------------------
IMP_DM_HALT_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_halt_dm <= '0';
elsif (sig_shtdwn_sm_set_dm_halt_ns = '1') then
sig_halt_dm <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_DM_HALT_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FTCH_HALT_FLOP
--
-- Process Description:
-- Implements the sticky flag that requests a DataMover
-- HALT.
-- This is sticky and is only cleared by a reset.
--
-------------------------------------------------------------
IMP_FTCH_HALT_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_halt_fetch <= '0';
elsif (sig_shtdwn_sm_set_ftch_halt_ns = '1') then
sig_halt_fetch <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_FTCH_HALT_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DM_SG_FLUSH
--
-- Process Description:
-- Implements the sticky flag that requests a SG
-- Queue flush. The Shutdown state Machine controls
-- when it is set.
-- This is sticky and is only cleared by a reset.
--
-------------------------------------------------------------
IMP_DM_SG_FLUSH : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_flush_sg <= '0';
elsif (sig_shtdwn_sm_flush_sg_ns = '1') then
sig_flush_sg <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_DM_SG_FLUSH;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STS_HALT_FLOP
--
-- Process Description:
-- Implements the sticky flag that requests a Status State
-- Machine halt.
-- This is sticky and is only cleared by a reset.
--
-------------------------------------------------------------
IMP_STS_HALT_FLOP : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_halt_status <= '0';
elsif (sig_shtdwn_sm_set_sts_halt_ns = '1') then
sig_halt_status <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_STS_HALT_FLOP;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_SHTDWN_SM_COMB
--
-- Process Description:
-- Implements the combinatorial portion of the Shutdown
-- State Machine. The shutdown sequence is activated by
-- either a soft reset request from the reset module or
-- by a detected error condition.
--
-------------------------------------------------------------
IMP_SHTDWN_SM_COMB : process (sig_shtdwn_sm_state ,
sig_do_shutdown ,
sg2sgcntlr_ftch_idle ,
sg2sgcntlr_updt_idle ,
sig_ftchsm_idle ,
sig_stssm_idle ,
sig_dm_status_empty ,
sig_fetch_update_empty ,
sig_dmhalt_cmplt ,
sig_sg_error
)
begin
-- assign the default values
sig_shtdwn_sm_state_ns <= SHTDWN_IDLE ;
sig_shtdwn_sm_flush_sg_ns <= '0';
sig_shtdwn_sm_set_ftch_halt_ns <= '0';
sig_shtdwn_sm_set_dm_halt_ns <= '0';
sig_shtdwn_sm_set_sts_halt_ns <= '0';
sig_shtdwn_sm_set_cmplt_ns <= '0';
case sig_shtdwn_sm_state is
---------------------------------
when SHTDWN_IDLE =>
if (sig_do_shutdown = '1') then -- start shutdown sequence
sig_shtdwn_sm_state_ns <= HALT_FTCH_DM;
sig_shtdwn_sm_set_ftch_halt_ns <= '1';
sig_shtdwn_sm_set_dm_halt_ns <= '1';
else -- Stay here
sig_shtdwn_sm_state_ns <= SHTDWN_IDLE ;
end if;
---------------------------------
when HALT_FTCH_DM =>
sig_shtdwn_sm_state_ns <= WAIT_FTCH_IDLE ;
sig_shtdwn_sm_flush_sg_ns <= '1' ;
---------------------------------
when WAIT_FTCH_IDLE =>
if (sig_ftchsm_idle = '1') then
sig_shtdwn_sm_state_ns <= WAIT_FTCH_UPDATE ;
else
sig_shtdwn_sm_state_ns <= WAIT_FTCH_IDLE ;
end if;
---------------------------------
when WAIT_FTCH_UPDATE =>
if (sg2sgcntlr_ftch_idle = '1' and
sig_ftchsm_idle = '1') then
sig_shtdwn_sm_state_ns <= WAIT_DM_HALT_CMPLT ;
else
sig_shtdwn_sm_state_ns <= WAIT_FTCH_UPDATE ;
end if;
---------------------------------
when WAIT_DM_HALT_CMPLT =>
if (sig_dmhalt_cmplt = '1') then
sig_shtdwn_sm_state_ns <= WAIT_STS_IDLE ;
sig_shtdwn_sm_set_sts_halt_ns <= '1' ;
else
sig_shtdwn_sm_state_ns <= WAIT_DM_HALT_CMPLT ;
end if;
---------------------------------
when WAIT_STS_IDLE =>
if (sig_stssm_idle = '1') then
sig_shtdwn_sm_state_ns <= WAIT_STS_UPDATE ;
else
sig_shtdwn_sm_state_ns <= WAIT_STS_IDLE ;
end if;
---------------------------------
when WAIT_STS_UPDATE =>
if (sig_dm_status_empty = '1') then
sig_shtdwn_sm_state_ns <= WAIT_SG_UPDATE ;
else
sig_shtdwn_sm_state_ns <= WAIT_STS_UPDATE ;
end if;
---------------------------------
when WAIT_SG_UPDATE =>
if (sg2sgcntlr_updt_idle = '1') then
sig_shtdwn_sm_state_ns <= SHTDWN_CMPLT ;
sig_shtdwn_sm_set_cmplt_ns <= '1';
else
sig_shtdwn_sm_state_ns <= WAIT_SG_UPDATE ;
end if;
---------------------------------
when SHTDWN_CMPLT =>
sig_shtdwn_sm_state_ns <= SHTDWN_CMPLT ;
sig_shtdwn_sm_set_cmplt_ns <= '1';
---------------------------------
when others => -- shouldn't ever get here
sig_shtdwn_sm_state_ns <= SHTDWN_IDLE ;
end case;
end process IMP_SHTDWN_SM_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_SHTDWN_SM_REG
--
-- Process Description:
-- Implements the registered portion of the shutdown
-- State Machine.
--
-------------------------------------------------------------
IMP_SHTDWN_SM_REG : process (axi_aclk)
begin
if (axi_aclk'event and axi_aclk = '1') then
if (axi_reset = '1') then
sig_shtdwn_sm_state <= SHTDWN_IDLE ;
sig_shtdwn_sm_flush_sg <= '0' ;
sig_shtdwn_sm_set_ftch_halt <= '0' ;
sig_shtdwn_sm_set_dm_halt <= '0' ;
sig_shtdwn_sm_set_sts_halt <= '0' ;
sig_shtdwn_sm_set_cmplt <= '0' ;
else
sig_shtdwn_sm_state <= sig_shtdwn_sm_state_ns ;
sig_shtdwn_sm_flush_sg <= sig_shtdwn_sm_flush_sg_ns ;
sig_shtdwn_sm_set_ftch_halt <= sig_shtdwn_sm_set_ftch_halt_ns ;
sig_shtdwn_sm_set_dm_halt <= sig_shtdwn_sm_set_dm_halt_ns ;
sig_shtdwn_sm_set_sts_halt <= sig_shtdwn_sm_set_sts_halt_ns ;
sig_shtdwn_sm_set_cmplt <= sig_shtdwn_sm_set_cmplt_ns ;
end if;
end if;
end process IMP_SHTDWN_SM_REG;
end implementation;
-------------------------------------------------------------------------------
-- axi_cdma_sg_wrap
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
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--
-------------------------------------------------------------------------------
-- Filename: axi_cdma_sg_wrap.vhd
--
-- Description:
--
-- This file is the module wrapper for the AXI CDMA core when parameterized
-- for only Simple Mode DMA operations.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- VHDL Libraries
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
library axi_datamover_v5_1_16;
use axi_datamover_v5_1_16.axi_datamover;
library axi_sg_v4_1_7;
use axi_sg_v4_1_7.axi_sg;
library axi_cdma_v4_1_14;
use axi_cdma_v4_1_14.axi_cdma_pkg.all;
use axi_cdma_v4_1_14.axi_cdma_reset;
use axi_cdma_v4_1_14.axi_cdma_reg_module;
use axi_cdma_v4_1_14.axi_cdma_simple_cntlr;
use axi_cdma_v4_1_14.axi_cdma_sg_cntlr;
use axi_cdma_v4_1_14.axi_cdma_sf;
-------------------------------------------------------------------------------
entity axi_cdma_sg_wrap is
generic(
-----------------------------------------------------------------------
-- AXI Lite Register Interface Parameters
-----------------------------------------------------------------------
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 6;
-- Address width of the AXI Lite Interface (bits)
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32;
-- Data width of the AXI Lite Interface (bits)
C_AXI_LITE_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the AXI Lite Register interface needs to
-- be asynchronous to the CDMA data transport path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special AXI Lite clock for the axi lite interface
-----------------------------------------------------------------------
-- DataMover Memory Map Master Interface Parameters
-----------------------------------------------------------------------
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32;
-- DataMover Master AXI Memory Map Address Width (bits)
C_M_AXI_DATA_WIDTH : integer range 32 to 1024 := 32;
-- DataMover Master AXI Memory Map Data Width (bits)
C_M_AXI_MAX_BURST_LEN : integer range 2 to 256 := 16;
-- DataMover Maximum burst length to use for AXI MMAP requests
-- Allowed values are 16, 32, 64, 128, and 256 (data beats)
C_INCLUDE_DRE : integer range 0 to 1 := 0;
-- Include or exclude DataMover Data Realignment (DRE)
-- NOTE: DRE is only available for 32 and 64 bit data widths
-- 0 = Exclude DRE
-- 1 = Include DRE
C_USE_DATAMOVER_LITE : integer range 0 to 1 := 0;
-- Enable DataMover Lite mode
-- NOTE: Data widths limited to 32 and 64 bits, max burst
-- limited to 16, 32, and 64 data beats, no DRE, 4K address
-- guarding must be done by SW programmer.
-- 0 = Normal DataMover mode
-- 1 = Lite dataMover mode
C_READ_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter specifies the depth of the DataMover
-- read address pipelining queues for the Main data transport
-- channels. The effective address pipelining on the AXI4 Read
-- Address Channel will be the value assigned plus 2.
C_WRITE_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter specifies the depth of the DataMover
-- write address pipelining queues for the Main data transport
-- channel. The effective address pipelining on the AXI4 Write
-- Address Channel will be the value assigned plus 2.
-----------------------------------------------------------------------
-- Store and Forward Parameters
-----------------------------------------------------------------------
C_INCLUDE_SF : integer range 0 to 1 := 1;
-- This parameter includes includes/omits Store and Forward.
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 128 ;
-- This parameter sets the depth of the Store and Forward FIFO.
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather
-- R/W Port (bits)
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather
-- R/W Port (bits)
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in clock ticks of axi_aclk
-----------------------------------------------------------------------
-- Soft Reset Assertion Time
-----------------------------------------------------------------------
C_SOFT_RST_TIME_CLKS : integer range 1 to 64 := 8;
-- Specifies the time of the soft reset assertion in
-- axi_aclk clock periods.
C_ACTUAL_ADDR : integer range 32 to 64 := 32;
-----------------------------------------------------------------------
-- Target FPGA Family Parameter
-----------------------------------------------------------------------
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-----------------------------------------------------------------------
-- Primary Clock
-----------------------------------------------------------------------
axi_aclk : in std_logic ;
-----------------------------------------------------------------------
-- Primary Reset Input (active low synchronous to axi_aclk)
-----------------------------------------------------------------------
axi_resetn : in std_logic ;
-----------------------------------------------------------------------
-- AXI Lite clock
-----------------------------------------------------------------------
axi_lite_aclk : in std_logic ;
-----------------------------------------------------------------------
-- AXI Lite reset (active low synchronous to axi_lite_aclk)
-----------------------------------------------------------------------
axi_lite_resetn : in std_logic ;
-----------------------------------------------------------------------
-- Interrupt output
-----------------------------------------------------------------------
cdma_introut : out std_logic ;
-----------------------------------------------------------------------
-- Error Discrete output
-----------------------------------------------------------------------
cdma_error_out : out std_logic ;
---------------------------------------------------------------------------------
-- AXI Lite Register Access Interface
---------------------------------------------------------------------------------
-- AXI Lite Write Address Channel -- AXI4-Lite
s_axi_lite_awready : out std_logic ;-- AXI4-Lite
s_axi_lite_awvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_awaddr : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Write Data Channel -- AXI4-Lite
s_axi_lite_wready : out std_logic ;-- AXI4-Lite
s_axi_lite_wvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_wdata : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Write Response Channel -- AXI4-Lite
s_axi_lite_bready : in std_logic ;-- AXI4-Lite
s_axi_lite_bvalid : out std_logic ;-- AXI4-Lite
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ;-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Read Address Channel -- AXI4-Lite
s_axi_lite_arready : out std_logic ;-- AXI4-Lite
s_axi_lite_arvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_araddr : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Read Data Channel -- AXI4-Lite
s_axi_lite_rready : in std_logic ;-- AXI4-Lite
s_axi_lite_rvalid : out std_logic ;-- AXI4-Lite
s_axi_lite_rdata : out std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);-- AXI4-Lite
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ;-- AXI4-Lite
----------------------------------------------------------------------------
-- AXI DataMover Read Channel
----------------------------------------------------------------------------
-- DataMover MMap Read Address Channel -- AXI4
m_axi_arready : in std_logic ;-- AXI4
m_axi_arvalid : out std_logic ;-- AXI4
m_axi_araddr : out std_logic_vector -- AXI4
(C_M_AXI_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_arlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_arsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_arburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_arprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_arcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- DataMover MMap Read Data Channel -- AXI4
m_axi_rready : out std_logic ;-- AXI4
m_axi_rvalid : in std_logic ;-- AXI4
m_axi_rdata : in std_logic_vector -- AXI4
(C_M_AXI_DATA_WIDTH-1 downto 0) ;-- AXI4
m_axi_rresp : in std_logic_vector(1 downto 0) ;-- AXI4
m_axi_rlast : in std_logic ;-- AXI4
-----------------------------------------------------------------------------
-- AXI DataMover Write Channel
-----------------------------------------------------------------------------
-- DataMover Write Address Channel -- AXI4
m_axi_awready : in std_logic ;-- AXI4
m_axi_awvalid : out std_logic ;-- AXI4
m_axi_awaddr : out std_logic_vector -- AXI4
(C_M_AXI_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_awlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_awsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_awburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_awprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_awcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- DataMover Write Data Channel -- AXI4
m_axi_wready : in std_logic ;-- AXI4
m_axi_wvalid : out std_logic ;-- AXI4
m_axi_wdata : out std_logic_vector -- AXI4
(C_M_AXI_DATA_WIDTH-1 downto 0) ;-- AXI4
m_axi_wstrb : out std_logic_vector -- AXI4
((C_M_AXI_DATA_WIDTH/8)-1 downto 0);-- AXI4
m_axi_wlast : out std_logic ;-- AXI4
-- AXI4
-- DataMover Write Response Channel -- AXI4
m_axi_bready : out std_logic ;-- AXI4
m_axi_bvalid : in std_logic ;-- AXI4
m_axi_bresp : in std_logic_vector(1 downto 0) ;-- AXI4
----------------------------------------------------------------------------
-- AXI Scatter Gather Interface
----------------------------------------------------------------------------
-- Scatter Gather Write Address Channel -- AXI4
m_axi_sg_awready : in std_logic ;-- AXI4
m_axi_sg_awvalid : out std_logic ;-- AXI4
m_axi_sg_awaddr : out std_logic_vector -- AXI4
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- Scatter Gather Write Data Channel -- AXI4
m_axi_sg_wready : in std_logic ;-- AXI4
m_axi_sg_wvalid : out std_logic ;-- AXI4
m_axi_sg_wdata : out std_logic_vector -- AXI4
(C_M_AXI_SG_DATA_WIDTH-1 downto 0);-- AXI4
m_axi_sg_wstrb : out std_logic_vector -- AXI4
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0);-- AXI4
m_axi_sg_wlast : out std_logic ;-- AXI4
-- AXI4
-- Scatter Gather Write Response Channel -- AXI4
m_axi_sg_bready : out std_logic ;-- AXI4
m_axi_sg_bvalid : in std_logic ;-- AXI4
m_axi_sg_bresp : in std_logic_vector(1 downto 0) ;-- AXI4
-- AXI4
-- Scatter Gather Read Address Channel -- AXI4
m_axi_sg_arready : in std_logic ;-- AXI4
m_axi_sg_arvalid : out std_logic ;-- AXI4
m_axi_sg_araddr : out std_logic_vector -- AXI4
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- Scatter Gather Read Data Channel -- AXI4
m_axi_sg_rready : out std_logic ;-- AXI4
m_axi_sg_rvalid : in std_logic ;-- AXI4
m_axi_sg_rdata : in std_logic_vector -- AXI4
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ;-- AXI4
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ;-- AXI4
m_axi_sg_rlast : in std_logic ;-- AXI4
-- Debug test vector (Xilinx use only)
axi_cdma_tstvec : out std_logic_vector(31 downto 0)
);
-----------------------------------------------------------------
-- End of PSFUtil MPD attributes
-----------------------------------------------------------------
end axi_cdma_sg_wrap;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma_sg_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
function func_include_dre (need_dre : integer;
needed_data_width : integer) return integer is
Variable include_dre : Integer := 0;
begin
If (need_dre = 1 and
needed_data_width > 64) Then
include_dre := 1;
Else
include_dre := 0;
End if;
Return (include_dre);
end function func_include_dre;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- General Use
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- AXI CDMA Build Mode (This Wrapper is with SG); 1 = Scatter Gather Enabled
constant CDMA_BUILD_MODE : integer := 1;
-- Indicates that ACLK is synchronous to ch1_aclk and ch2_aclk
Constant ACLK_IS_SYNC : integer := 0;
-- SG Channel 1 Include/omit
Constant INCLUDE_CH1 : integer := 1;
-- SG Channel 2 Include/omit
Constant OMIT_CH2 : integer := 0;
-- SG Include Update Engine
Constant INCLUDE_UPDATE_ENG : integer := 1;
-- SG Include Interrupt Controller
Constant INCLUDE_IRPT_CNTLR : integer := 1;
-- SG Include Delay Timer
Constant INCLUDE_DLY_TIMER : integer := 1;
-- SG Fetch Master Stream Width
Constant M_AXIS_SG_TDATA_WIDTH : integer := 32;
-- SG Pointer Update Stream Width
Constant S_AXIS_UPDPTR_TDATA_WIDTH : integer := 32;
-- SG Status Update Stream Width
Constant C_S_AXIS_UPDSTS_TDATA_WIDTH : integer := 33;
-- SG Update Slave Stream Width
Constant S_AXIS_SG_DATA_WIDTH : integer := 34;
-- SG Fetch Descriptor Queue Depth
Constant SG_FTCH_DESC2QUEUE : integer := 4;
-- SG Update Descriptor Queue Depth
--Constant SG_UPDT_DESC2QUEUE : integer := 8;
Constant SG_UPDT_DESC2QUEUE : integer := 4;
-- SG Ch1 number of descriptor words to fetch
Constant SG_CH1_WORDS_TO_FETCH : integer := 8;
-- SG Ch1 number of descriptor words to update
Constant SG_CH1_WORDS_TO_UPDATE : integer := 1;
-- SG Ch1 First Update word offset from desctiptor start
Constant SG_CH1_FIRST_UPDATE_WORD : integer := 7;
-- SG Ch1 Stale Descriptor Error enable
Constant SG_CH1_ENBL_STALE_ERROR : integer := 1;
-- SG Ch2 words to fetch (Not used in CDMA application)
Constant SG_CH2_WORDS_TO_FETCH : integer := 4;
-- SG Ch2 words to update (Not used in CDMA application)
Constant SG_CH2_WORDS_TO_UPDATE : integer := 1;
-- SG Ch2 First Update word offset from desctiptor start (Not used in CDMA application)
Constant SG_CH2_FIRST_UPDATE_WORD : integer := 0;
-- SG Ch2 Stale Descriptor Error enable (Not used in CDMA application)
Constant SG_CH2_ENBL_STALE_ERROR : integer := 0;
-- AXI DataMover Include Status FIFO
constant DM_INCLUDE_STS_FIFO : integer := 1;
-- AXI DataMover Command / Status FIFO Depth
constant DM_SG_CMDSTS_FIFO_DEPTH : integer := 1;
-- AXI MM2S DataMover Full mode value
constant MM2S_FULL_MODE : integer := 1;
-- AXI MM2S DataMover Lite mode value
constant MM2S_LITE_MODE : integer := 2;
-- AXI S2MM DataMover Full mode value
constant S2MM_FULL_MODE : integer := 1;
-- AXI S2MM DataMover LITE mode value
constant S2MM_LITE_MODE : integer := 4;
-- AXI DataMover clocking mode
constant DM_USE_SYNC_CLOCKS : integer := 0;
-- AXI DataMover BTT Used width (Set the to the max allowed)
constant DM_BTT_WIDTH : integer := 23;
-- AXI DataMover S2MM DRE Enable (set to disabled)
constant DM_S2MM_DRE_DISABLED : integer := 0 ;--func_include_dre (C_INCLUDE_DRE, C_M_AXI_DATA_WIDTH);
-- AXI DataMover Include Store and Forward
constant DM_OMIT_S2MM_STORE_FORWARD : integer := 0;
constant DM_ENABLE_S2MM_STORE_FORWARD : integer := 1;
Constant STORE_FORWARD_CNTL : integer := DM_OMIT_S2MM_STORE_FORWARD;
-- AXI DataMover Stream Backend width
constant DM_STREAM_DWIDTH : integer := C_M_AXI_DATA_WIDTH;
-- AXI DataMover Base status vector width
constant BASE_STATUS_WIDTH : integer := 8;
-- AXI DataMover S2MM status stream data width delta
-- if Store and Forward enabled
Constant SF_ADDED_STS_WIDTH : integer := 24;
-- AXI DataMover status stream data width (S2MM is based on mode of operation)
constant DM_MM2S_STATUS_WIDTH : integer := BASE_STATUS_WIDTH;
constant DM_S2MM_STATUS_WIDTH : integer := BASE_STATUS_WIDTH +
(STORE_FORWARD_CNTL *
SF_ADDED_STS_WIDTH);
-- DataMover Command Stream data Width in bits
constant DM_CMD_WIDTH : integer := 72+(C_M_AXI_ADDR_WIDTH-32);
-- constant DM_CMD_WIDTH : integer := 104;
-- SG Delay and Threshold field widths
Constant DLY_THRESH_WIDTH : integer := 8;
-- SG Delay and Threshold zero values
Constant IRQ_DLY_THRESH_ZEROS : std_logic_vector(DLY_THRESH_WIDTH-1 downto 0) := (others => '0');
-- SG Address zero value
Constant SG_ADDR_ZEROS : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- SG Descriptor Fetch data width
Constant SG_FETCH_DWIDTH : integer := M_AXIS_SG_TDATA_WIDTH;
-- SG Descriptor Update data width
Constant SG_UPDATE_DWIDTH : integer := S_AXIS_SG_DATA_WIDTH;
-- SG Pointer Update data value of zeroes
Constant SG_UPDPTR_DATA_ZEROS : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- SG Status Update data value of zeroes
Constant SG_UPDSTS_DATA_ZEROS : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
-- AXI DataMover pipeline depth constants
Constant DM_READ_ADDR_PIPE_DEPTH : integer := C_READ_ADDR_PIPE_DEPTH;
Constant DM_WRITE_ADDR_PIPE_DEPTH : integer := C_WRITE_ADDR_PIPE_DEPTH;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_max
--
-- Function Description:
-- Returns the greater of two integers.
--
-------------------------------------------------------------------
function funct_get_max (value_in_1 : integer;
value_in_2 : integer)
return integer is
Variable max_value : Integer := 0;
begin
If (value_in_1 > value_in_2) Then
max_value := value_in_1;
else
max_value := value_in_2;
End if;
Return (max_value);
end function funct_get_max;
-------------------------------------------------------------------
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-- Calculates the minimum needed depth of the CDMA Store and Forward FIFO
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(funct_get_max(4, 4)+2)
* C_M_AXI_MAX_BURST_LEN;
-- Assigns the depth of the CDMA Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Reset Module signals
signal sig_rst2lite_bside_reset : std_logic := '0';
signal sig_rst2lite_cside_reset : std_logic := '0';
signal sig_rst2reg_reset : std_logic := '0';
signal sig_rst2cntlr_reset : std_logic := '0';
signal sig_rst2sgcntlr_reset : std_logic := '0';
signal sig_rst2sg_resetn : std_logic := '0';
signal sig_rst2dm_resetn : std_logic := '0';
signal sig_rst2cntlr_halt : std_logic := '0';
signal sig_cntlr2rst_halt_cmplt : std_logic := '0';
signal sig_dm_mm2s_halt : std_logic := '0';
signal sig_dm_mm2s_halt_cmplt : std_logic := '0';
signal sig_dm_s2mm_halt : std_logic := '0';
signal sig_dm_s2mm_halt_cmplt : std_logic := '0';
-- Register Module Signals
signal sig_reg2cntlr_src_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2cntlr_dest_addr : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2cntlr_btt : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2cntlr_go : std_logic := '0';
signal sig_cntlr2reg_idle_set : std_logic := '0';
signal sig_cntlr2reg_idle_clr : std_logic := '0';
signal sig_cntlr2reg_decerr_set : std_logic := '0';
signal sig_cntlr2reg_slverr_set : std_logic := '0';
signal sig_cntlr2reg_interr_set : std_logic := '0';
signal sig_cntlr2reg_ioc_set : std_logic := '0';
signal sig_cntlr2reg_iocirpt_set : std_logic := '0';
signal sig_reg2rst_soft_reset : std_logic := '0';
signal sig_rst2reg_soft_reset_clr : std_logic := '0';
signal sig_reg2cntlr_sg_mode : std_logic := '0';
-- DataMover MM2S error discrete
signal sig_dm_mm2s_err : std_logic := '0';
-- DataMover MM2S command Stream
signal sig_cntl2mm2s_cmd_tdata : std_logic_vector(DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s2cntl_cmd_tready : std_logic := '0';
signal sig_cntl2mm2s_cmd_tvalid : std_logic := '0';
-- DataMover MM2S status Stream
signal sig_mm2s2cntl_sts_tdata : std_logic_vector(DM_MM2S_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s2cntl_sts_tstrb : std_logic_vector((DM_MM2S_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s2cntl_sts_tvalid : std_logic := '0';
signal sig_cntl2mm2s_sts_tready : std_logic := '0';
-- DataMover S2MM error discrete
signal sig_dm_s2mm_err : std_logic := '0';
-- DataMover S2MM command Stream
signal sig_cntl2s2mm_cmd_tdata : std_logic_vector(DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cntl2s2mm_cmd_tvalid : std_logic := '0';
signal sig_s2mm2cntl_cmd_tready : std_logic := '0';
-- DataMover S2MM status Stream
signal sig_s2mm2cntl_sts_tdata : std_logic_vector(DM_S2MM_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm2cntl_sts_tstrb : std_logic_vector((DM_S2MM_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm2cntl_sts_tvalid : std_logic := '0';
signal sig_cntl2s2mm_sts_tready : std_logic := '0';
-- DataMover stream loopback hookup
signal sig_mm2s_axis_tdata : std_logic_vector(DM_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_mm2s_axis_tkeep : std_logic_vector((DM_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_axis_tlast : std_logic := '0';
signal sig_mm2s_axis_tvalid : std_logic := '0';
signal sig_mm2s_axis_tready : std_logic := '0';
-- SG/Register signals
signal sig_reg2sg_dmacr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2sg_dmasr : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2sg_curdesc : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2sg_taildesc : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_reg2sgcntlr_currdesc_updated : std_logic := '0';
signal sig_reg2sg_tailpntr_updated : std_logic := '0';
signal sig_reg2sg_irqdelay_wren : std_logic := '0';
signal sig_reg2sg_irqthresh_wren : std_logic := '0';
signal sig_sg2reg_ftch_interr_set : std_logic := '0';
signal sig_sg2reg_ftch_slverr_set : std_logic := '0';
signal sig_sg2reg_ftch_decerr_set : std_logic := '0';
signal sig_sg2reg_updt_interr_set : std_logic := '0';
signal sig_sg2reg_updt_slverr_set : std_logic := '0';
signal sig_sg2reg_updt_decerr_set : std_logic := '0';
signal sig_sg2sgcntlr_ftch_error : std_logic := '0';
signal sig_sg2reg_ftch_error_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_sg2sgcntlr_updt_error : std_logic := '0';
signal sig_sg2reg_updt_error_addr : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_sg2reg_irqdelay_status : std_logic_vector(DLY_THRESH_WIDTH-1 downto 0) := (others => '0');
signal sig_sg2reg_irqthresh_status : std_logic_vector(DLY_THRESH_WIDTH-1 downto 0) := (others => '0');
-- SG Controller signals
signal sig_rst2sgcntl_halt : std_logic := '0';
signal sig_sgcntl2rst_halt_cmplt : std_logic := '0';
signal sig_sgcntl2reg_idle_set : std_logic := '0';
signal sig_sgcntl2reg_idle_clr : std_logic := '0';
signal sig_sgcntl2sg_pkt_sof : std_logic := '0';
signal sig_sgcntl2sg_pkt_eof : std_logic := '0';
signal sig_sg2sgcntl_ioc_irq_set : std_logic := '0';
signal sig_sg2sgcntl_dly_irq_set : std_logic := '0';
signal sig_sgcntl2reg_ioc_irq_set : std_logic := '0';
signal sig_sgcntl2reg_dly_irq_set : std_logic := '0';
signal sig_sg2sgcntlr_ftch_tdata : std_logic_vector(SG_FETCH_DWIDTH-1 downto 0) := (others => '0');
signal sig_sg2sgcntlr_ftch_tdata_new : std_logic_vector(127+(3*(C_M_AXI_ADDR_WIDTH-32)) downto 0) := (others => '0');
signal sig_sg2sgcntlr_ftch_tvalid : std_logic := '0';
signal sig_sg2sgcntlr_ftch_tvalid_new : std_logic := '0';
signal sig_sgcntl2sg_ftch_tready : std_logic := '0';
signal sig_sg2sgcntlr_ftch_tlast : std_logic := '0';
signal sig_sg2sgcntlr_ftch_desc_available : std_logic := '0';
signal sig_sg2sgcntlr_updptr_tready : std_logic := '0';
signal sig_sgcntl2sg_updptr_tvalid : std_logic := '0';
signal sig_sgcntl2sg_updptr_tdata : std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_sgcntl2sg_updptr_tlast : std_logic := '0';
signal sig_sg2sgcntlr_updsts_tready : std_logic := '0';
signal sig_sgcntl2sg_updsts_tvalid : std_logic := '0';
signal sig_sgcntl2sg_updsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_sgcntl2sg_updsts_tlast : std_logic := '0';
signal sig_sgcntlr2sg_run_stop : std_logic := '0';
signal sig_sgcntlr2sg_desc_flush : std_logic := '0';
signal sig_sg2sgcntlr_ftch_idle : std_logic := '0';
signal sig_sg2sgcntlr_ftch_err_early : std_logic := '0';
signal sig_sg2sgcntlr_ftch_stale_desc : std_logic := '0';
signal sig_sg2sgcntlr_updt_idle : std_logic := '0';
signal sig_sg2sgcntlr_updt_ioc_irq_set : std_logic := '0';
signal sig_sg2sgcntlr_dma_interr_set : std_logic := '0';
signal sig_sg2sgcntlr_dma_slverr_set : std_logic := '0';
signal sig_sg2sgcntlr_dma_decerr_set : std_logic := '0';
signal sig_sgcntlr2reg_dma_interr_set : std_logic := '0';
signal sig_sgcntlr2reg_dma_slverr_set : std_logic := '0';
signal sig_sgcntlr2reg_dma_decerr_set : std_logic := '0';
signal sig_sgcntlr2reg_new_curdesc_wren : std_logic := '0';
signal sig_sgcntlr2reg_new_curdesc : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Shared SG and Simple Mode register IF signals
signal sig_composite_idle_set : std_logic := '0';
signal sig_composite_idle_clr : std_logic := '0';
signal sig_composite_iocirpt_set : std_logic := '0';
signal sig_composite_dm_decerr_set : std_logic := '0';
signal sig_composite_dm_slverr_set : std_logic := '0';
signal sig_composite_dm_interr_set : std_logic := '0';
-- DataMover input signals multiplexed between Simple and SG Mode controllers
signal sig_dm_mm2s_cmd_tdata : std_logic_vector(DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_dm_mm2s_cmd_tvalid : std_logic := '0';
signal sig_dm_mm2s_sts_tready : std_logic := '0';
signal sig_dm_s2mm_cmd_tdata : std_logic_vector(DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_dm_s2mm_cmd_tvalid : std_logic := '0';
signal sig_dm_s2mm_sts_tready : std_logic := '0';
-- DataMover output signals shared between the Simple and SG Contorllers
signal sig_dm_mm2s_cmd_tready : std_logic := '0';
signal sig_dm_mm2s_sts_tvalid : std_logic := '0';
signal sig_dm_mm2s_sts_tdata : std_logic_vector(DM_MM2S_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_dm_mm2s_sts_tkeep : std_logic_vector((DM_MM2S_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_dm_s2mm_cmd_tready : std_logic := '0';
signal sig_dm_s2mm_sts_tvalid : std_logic := '0';
-- SG DataMover Interface signals
-- DataMover MM2S error discrete
signal sig_mm2s2sgcntl_err : std_logic := '0';
-- DataMover MM2S command Stream
signal sig_sgcntl2mm2s_cmd_tdata : std_logic_vector(DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_sgcntl2mm2s_cmd_tvalid : std_logic := '0';
signal sig_mm2s2sgcntl_cmd_tready : std_logic := '0';
-- DataMover MM2S status Stream
signal sig_mm2s2sgcntl_sts_tdata : std_logic_vector(DM_MM2S_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_mm2s2sgcntl_sts_tstrb : std_logic_vector((DM_MM2S_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s2sgcntl_sts_tvalid : std_logic := '0';
signal sig_sgcntl2mm2s_sts_tready : std_logic := '0';
-- DataMover S2MM error discrete
signal sig_s2mm2sgcntl_err : std_logic := '0';
-- DataMover S2MM command Stream
signal sig_sgcntl2s2mm_cmd_tdata : std_logic_vector(DM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_sgcntl2s2mm_cmd_tvalid : std_logic := '0';
signal sig_s2mm2sgcntl_cmd_tready : std_logic := '0';
-- DataMover S2MM status Stream
signal sig_s2mm2sgcntl_sts_tdata : std_logic_vector(BASE_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm2sgcntl_sts_tstrb : std_logic_vector((BASE_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm2sgcntl_sts_tvalid : std_logic := '0';
signal sig_sgcntl2s2mm_sts_tready : std_logic := '0';
-- DataMover halt control
signal sig_rst2mm2s_halt : std_logic := '0';
signal sig_rst2s2mm_halt : std_logic := '0';
signal sig_sgcntl2mm2s_halt : std_logic := '0';
signal sig_sgcntl2s2mm_halt : std_logic := '0';
-- DataMover Input Stream
signal sig_s2mm_axis_tready : std_logic := '0';
signal sig_s2mm_axis_tvalid : std_logic := '0';
signal sig_s2mm_axis_tdata : std_logic_vector(DM_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_axis_tkeep : std_logic_vector((DM_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_axis_tlast : std_logic := '0';
signal sig_dm_s2mm_sts_tdata : std_logic_vector(DM_S2MM_STATUS_WIDTH-1 downto 0) := (others => '0');
signal sig_dm_s2mm_sts_tkeep : std_logic_vector((DM_S2MM_STATUS_WIDTH/8)-1 downto 0) := (others => '0');
-- DataMover Address Pipe Controls
signal sig_mm2s_allow_addr_req : std_logic := '0';
signal sig_mm2s_addr_req_posted : std_logic := '0';
signal sig_mm2s_rd_xfer_cmplt : std_logic := '0';
signal sig_s2mm_allow_addr_req : std_logic := '0';
signal sig_s2mm_addr_req_posted : std_logic := '0';
signal sig_s2mm_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
-- store and Forward module Reset
signal sig_sf_reset : std_logic := '0';
signal dma_keyhole_write : std_logic;
signal dma_keyhole_read : std_logic;
signal dma_cyclic : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- AXI CDMA Test Vector (For Xilinx Internal Use Only)
-------------------------------------------------------------------------------
-- Simple Mode (bits 7 downto 0)
axi_cdma_tstvec(0) <= sig_reg2cntlr_go ;
axi_cdma_tstvec(1) <= sig_cntlr2reg_idle_set ;
axi_cdma_tstvec(2) <= sig_cntlr2reg_idle_clr ;
axi_cdma_tstvec(3) <= sig_cntlr2reg_iocirpt_set ;
axi_cdma_tstvec(4) <= sig_cntlr2reg_decerr_set ;
axi_cdma_tstvec(5) <= sig_cntlr2reg_slverr_set ;
axi_cdma_tstvec(6) <= sig_cntlr2reg_interr_set ;
axi_cdma_tstvec(7) <= '0' ;
-- SG Mode bits 31 downto 8)
axi_cdma_tstvec(8) <= sig_sgcntlr2sg_run_stop ;
axi_cdma_tstvec(9) <= sig_sgcntl2sg_pkt_sof ;
axi_cdma_tstvec(10) <= sig_sgcntl2sg_pkt_eof ;
axi_cdma_tstvec(11) <= sig_sgcntl2reg_ioc_irq_set ;
axi_cdma_tstvec(12) <= sig_sgcntl2reg_dly_irq_set ;
axi_cdma_tstvec(13) <= sig_sg2sgcntlr_ftch_error ;
axi_cdma_tstvec(14) <= sig_sg2sgcntlr_ftch_stale_desc ;
axi_cdma_tstvec(15) <= sig_sg2reg_ftch_interr_set ;
axi_cdma_tstvec(16) <= sig_sg2reg_ftch_slverr_set ;
axi_cdma_tstvec(17) <= sig_sg2reg_ftch_decerr_set ;
axi_cdma_tstvec(18) <= sig_sg2sgcntlr_updt_error ;
axi_cdma_tstvec(19) <= sig_sg2reg_updt_interr_set ;
axi_cdma_tstvec(20) <= sig_sg2reg_updt_slverr_set ;
axi_cdma_tstvec(21) <= sig_sg2reg_updt_decerr_set ;
axi_cdma_tstvec(22) <= sig_sgcntlr2reg_dma_interr_set ;
axi_cdma_tstvec(23) <= sig_sgcntlr2reg_dma_slverr_set ;
axi_cdma_tstvec(24) <= sig_sgcntlr2reg_dma_decerr_set ;
axi_cdma_tstvec(31 downto 25) <= (others => '0') ;
-- Create a postive reset for the Store and Forward module
-- from the inverted DataMover active low reset.
-- CR591254 change
-- sig_sf_reset <= not(sig_rst2dm_resetn) ;
sig_sf_reset <= sig_rst2cntlr_reset ;
-------------------------------------------------------------------------------
-- Module Instances
-------------------------------------------------------------------------------
------------------------------------------------------------
-- Instance: I_RST_MODULE
--
-- Description:
-- Instance for the Reset Module used with Simple Mode
-- operation. It manages both hard and soft reset generation.
--
------------------------------------------------------------
I_RST_MODULE : entity axi_cdma_v4_1_14.axi_cdma_reset
generic map(
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_SOFT_RST_TIME_CLKS => C_SOFT_RST_TIME_CLKS
)
port map(
-- Primary Clock and Reset Sources
axi_aclk => axi_aclk ,
axi_resetn => axi_resetn ,
-- AXI Lite Clock and Reset Sources
axi_lite_aclk => axi_lite_aclk ,
axi_lite_resetn => axi_lite_resetn ,
-- CDMA Module hard reset outputs
rst2lite_bside_reset => sig_rst2lite_bside_reset ,
rst2lite_cside_reset => sig_rst2lite_cside_reset ,
rst2reg_reset => sig_rst2reg_reset ,
rst2cntlr_reset => sig_rst2cntlr_reset ,
rst2sgcntlr_reset => sig_rst2sgcntlr_reset ,
rst2sg_resetn => sig_rst2sg_resetn ,
rst2dm_resetn => sig_rst2dm_resetn ,
-- Soft Reset Request from Register module
reg2rst_soft_reset_in => sig_reg2rst_soft_reset ,
rst2reg_soft_reset_clr => sig_rst2reg_soft_reset_clr ,
-- CDMA Simple Controller halt
rst2cntlr_halt => sig_rst2cntlr_halt ,
cntlr2rst_halt_cmplt => sig_cntlr2rst_halt_cmplt ,
-- CDMA SG Controller halt
rst2sg_halt => sig_rst2sgcntl_halt ,
sg2rst_halt_cmplt => sig_sgcntl2rst_halt_cmplt ,
-- CDMA DatMover MM2S Halt
rst2dm_mm2s_halt => sig_rst2mm2s_halt ,
dm2rst_mm2s_halt_cmplt => sig_dm_mm2s_halt_cmplt ,
-- CDMA DatMover S2MM Halt
rst2dm_s2mm_halt => sig_rst2s2mm_halt ,
dm2rst_s2mm_halt_cmplt => sig_dm_s2mm_halt_cmplt
);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: REG_IF_MUX
--
-- Process Description:
-- This process implements a mux for Register Module input
-- signals that are shared between the Simple DMA mode and
-- SG mode operations.
--
-------------------------------------------------------------
REG_IF_MUX : process (sig_reg2cntlr_sg_mode,
sig_sgcntl2reg_idle_set ,
sig_sgcntl2reg_idle_clr ,
sig_sgcntl2reg_ioc_irq_set ,
sig_sgcntlr2reg_dma_decerr_set ,
sig_sgcntlr2reg_dma_slverr_set ,
sig_sgcntlr2reg_dma_interr_set ,
sig_cntlr2reg_idle_set ,
sig_cntlr2reg_idle_clr ,
sig_cntlr2reg_iocirpt_set ,
sig_cntlr2reg_decerr_set ,
sig_cntlr2reg_slverr_set ,
sig_cntlr2reg_interr_set
)
begin
case sig_reg2cntlr_sg_mode is
when '1' => -- SG Mode Enabled
sig_composite_idle_set <= sig_sgcntl2reg_idle_set ;
sig_composite_idle_clr <= sig_sgcntl2reg_idle_clr ;
sig_composite_iocirpt_set <= sig_sgcntl2reg_ioc_irq_set ;
sig_composite_dm_decerr_set <= sig_sgcntlr2reg_dma_decerr_set ;
sig_composite_dm_slverr_set <= sig_sgcntlr2reg_dma_slverr_set ;
sig_composite_dm_interr_set <= sig_sgcntlr2reg_dma_interr_set ;
when others => -- Simple DMA Enabled
sig_composite_idle_set <= sig_cntlr2reg_idle_set ;
sig_composite_idle_clr <= sig_cntlr2reg_idle_clr ;
sig_composite_iocirpt_set <= sig_cntlr2reg_iocirpt_set ;
sig_composite_dm_decerr_set <= sig_cntlr2reg_decerr_set ;
sig_composite_dm_slverr_set <= sig_cntlr2reg_slverr_set ;
sig_composite_dm_interr_set <= sig_cntlr2reg_interr_set ;
end case;
end process REG_IF_MUX;
------------------------------------------------------------
-- Instance: I_HYBRID_REG_MODULE
--
-- Description:
-- Instance for the Register Module used with Simple and
-- SG Mode operations.
--
------------------------------------------------------------
I_HYBRID_REG_MODULE : entity axi_cdma_v4_1_14.axi_cdma_reg_module
generic map(
C_CDMA_BUILD_MODE => CDMA_BUILD_MODE ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH
)
port map(
-- AXI Lite Clock and Reset
axi_lite_aclk => axi_lite_aclk ,
axi_lite_reset => sig_rst2lite_bside_reset ,
-- AXI Lite Core side Reset
axi_lite_cside_reset => sig_rst2lite_cside_reset ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
-- AXI Lite Read Data Channel
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- Register Clock and Reset
axi_aclk => axi_aclk ,
axi_reg_reset => sig_rst2reg_reset ,
-- Composite Interrupt Output
reg_introut => cdma_introut ,
-- Composite error Output
reg_error_out => cdma_error_out ,
-- Soft Reset Control
reg_soft_reset_request => sig_reg2rst_soft_reset ,
reg_soft_reset_clr => sig_rst2reg_soft_reset_clr ,
-- Simple DMA Go Control
reg_dma_go => sig_reg2cntlr_go ,
-- SG Mode control
reg_dma_sg_mode => sig_reg2cntlr_sg_mode ,
-- Key Hole write
dma_keyhole_write => dma_keyhole_write ,
-- Key Hole read
dma_keyhole_read => dma_keyhole_read ,
-- Key Hole read
dma_cyclic => dma_cyclic ,
-- CDMASR Control inputs
reg_idle_set => sig_composite_idle_set ,
reg_idle_clr => sig_composite_idle_clr ,
reg_ioc_irq_set => sig_composite_iocirpt_set ,
reg_dly_irq_set => sig_sgcntl2reg_dly_irq_set ,
-- Status from SG indicating current Delay and Thresh cntr values
reg_irqdelay_status => sig_sg2reg_irqdelay_status ,
reg_irqthresh_status => sig_sg2reg_irqthresh_status ,
-- Controls to SG to load new DMACR Delay and Thresh values
reg_irqthresh_wren => sig_reg2sg_irqthresh_wren ,
reg_irqdelay_wren => sig_reg2sg_irqdelay_wren ,
-- DataMover Errors
reg_dma_decerr_set => sig_composite_dm_decerr_set ,
reg_dma_slverr_set => sig_composite_dm_slverr_set ,
reg_dma_interr_set => sig_composite_dm_interr_set ,
-- SG Descriptor Fetch errors
reg_ftch_interr_set => sig_sg2reg_ftch_interr_set ,
reg_ftch_slverr_set => sig_sg2reg_ftch_slverr_set ,
reg_ftch_decerr_set => sig_sg2reg_ftch_decerr_set ,
reg_ftch_error_addr => sig_sg2reg_ftch_error_addr ,
-- SG Descriptor Update errors
reg_updt_interr_set => sig_sg2reg_updt_interr_set ,
reg_updt_slverr_set => sig_sg2reg_updt_slverr_set ,
reg_updt_decerr_set => sig_sg2reg_updt_decerr_set ,
reg_updt_error_addr => sig_sg2reg_updt_error_addr ,
-- From SG Controller CURDESC Update
reg_new_curdesc_wren => sig_sgcntlr2reg_new_curdesc_wren ,
reg_new_curdesc => sig_sgcntlr2reg_new_curdesc ,
-- To SG TAILDESC Update (also used to start SG operations in SGMode)
reg_tailpntr_updated => sig_reg2sg_tailpntr_updated ,
reg_currdesc_updated => sig_reg2sgcntlr_currdesc_updated,
-- Register State Out
reg_dmacr => sig_reg2sg_dmacr ,
reg_dmasr => sig_reg2sg_dmasr ,
reg_curdesc => sig_reg2sg_curdesc ,
reg_taildesc => sig_reg2sg_taildesc ,
reg_src_addr => sig_reg2cntlr_src_addr ,
reg_dest_addr => sig_reg2cntlr_dest_addr ,
reg_btt => sig_reg2cntlr_btt
);
------------------------------------------------------------
-- Instance: I_SIMPLE_DMA_CNTLR
--
-- Description:
--
-- Control Logic module for the Simple Mode CDMA operation.
--
------------------------------------------------------------
I_SIMPLE_DMA_CNTLR : entity axi_cdma_v4_1_14.axi_cdma_simple_cntlr
generic map(
C_DM_CMD_WIDTH => DM_CMD_WIDTH ,
C_DM_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_DM_MM2S_STATUS_WIDTH => DM_MM2S_STATUS_WIDTH ,
C_DM_S2MM_STATUS_WIDTH => BASE_STATUS_WIDTH ,
C_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_BTT_WIDTH => DM_BTT_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Clock and reset
axi_aclk => axi_aclk ,
axi_reset => sig_rst2cntlr_reset ,
-- Halt request
rst2cntlr_halt => sig_rst2cntlr_halt ,
cntlr2rst_halt_cmplt => sig_cntlr2rst_halt_cmplt ,
-- Register Module Start and Mode Controls
reg2cntlr_go => sig_reg2cntlr_go ,
reg2cntlr_sg_mode => sig_reg2cntlr_sg_mode ,
burst_type_read => dma_keyhole_read ,
burst_type_write => dma_keyhole_write ,
-- Register Module command qualifiers
reg2cntlr_src_addr => sig_reg2cntlr_src_addr ,
reg2cntlr_dest_addr => sig_reg2cntlr_dest_addr ,
reg2cntlr_btt => sig_reg2cntlr_btt(DM_BTT_WIDTH-1
downto 0) ,
-- General Status Bit controls
cntlr2reg_idle_set => sig_cntlr2reg_idle_set ,
cntlr2reg_idle_clr => sig_cntlr2reg_idle_clr ,
cntlr2reg_iocirpt_set => sig_cntlr2reg_iocirpt_set ,
-- DataMover Error Status bit controls
cntlr2reg_decerr_set => sig_cntlr2reg_decerr_set ,
cntlr2reg_slverr_set => sig_cntlr2reg_slverr_set ,
cntlr2reg_interr_set => sig_cntlr2reg_interr_set ,
-- DataMover MM2S Command Interface Ports (AXI Stream)
mm2s2cntl_cmd_tready => sig_mm2s2cntl_cmd_tready ,
cntl2mm2s_cmd_tvalid => sig_cntl2mm2s_cmd_tvalid ,
cntl2mm2s_cmd_tdata => sig_cntl2mm2s_cmd_tdata ,
-- DataMover MM2S Status Interface Ports (AXI Stream)
cntl2mm2s_sts_tready => sig_cntl2mm2s_sts_tready ,
mm2s2cntl_sts_tvalid => sig_mm2s2cntl_sts_tvalid ,
mm2s2cntl_sts_tdata => sig_dm_mm2s_sts_tdata ,
mm2s2cntl_sts_tstrb => sig_dm_mm2s_sts_tkeep ,
-- DataMover MM2S error discrete
mm2s2cntl_err => sig_dm_mm2s_err ,
-- DataMover S2MM Command Interface Ports (AXI Stream)
cntl2s2mm_cmd_tdata => sig_cntl2s2mm_cmd_tdata ,
cntl2s2mm_cmd_tvalid => sig_cntl2s2mm_cmd_tvalid ,
s2mm2cntl_cmd_tready => sig_s2mm2cntl_cmd_tready ,
-- DataMover S2MM Status Interface Ports (AXI Stream)
s2mm2cntl_sts_tdata => sig_s2mm2sgcntl_sts_tdata ,
s2mm2cntl_sts_tstrb => sig_s2mm2sgcntl_sts_tstrb ,
s2mm2cntl_sts_tvalid => sig_s2mm2cntl_sts_tvalid ,
cntl2s2mm_sts_tready => sig_cntl2s2mm_sts_tready ,
-- DataMover S2MM error discrete
s2mm2cntl_err => sig_dm_s2mm_err
);
------------------------------------------------------------
-- Instance: I_SG_CNTLR
--
-- Description:
--
-- Control Logic module for the Scatter Gather Mode CDMA
-- operation.
--
------------------------------------------------------------
I_SG_CNTLR : entity axi_cdma_v4_1_14.axi_cdma_sg_cntlr
generic map(
C_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_SG_FETCH_DWIDTH => SG_FETCH_DWIDTH ,
C_SG_PTR_UPDATE_DWIDTH => C_M_AXI_SG_ADDR_WIDTH, --S_AXIS_UPDPTR_TDATA_WIDTH ,
C_SG_STS_UPDATE_DWIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_DM_CMD_WIDTH => DM_CMD_WIDTH ,
C_DM_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_DM_MM2S_STATUS_WIDTH => DM_MM2S_STATUS_WIDTH ,
C_DM_S2MM_STATUS_WIDTH => BASE_STATUS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Clock and reset
axi_aclk => axi_aclk ,
axi_reset => sig_rst2sgcntlr_reset ,
-- Halt request
rst2sgcntl_halt => sig_rst2sgcntl_halt ,
sgcntl2rst_halt_cmplt => sig_sgcntl2rst_halt_cmplt ,
sgcntlr2sg_desc_flush => sig_sgcntlr2sg_desc_flush ,
-- MM2S Type of Burst, 1 is increment, 0 is fixed
burst_type_read => dma_keyhole_read ,
-- S2MM Type of Burst, 1 is increment, 0 is fixed
burst_type_write => dma_keyhole_write ,
-- Register Module Start and Mode Controls
reg2sgcntl_sg_mode => sig_reg2cntlr_sg_mode ,
reg2sgcntl_tailpntr_updated => sig_reg2sg_tailpntr_updated ,
reg2sgcntl_currdesc_updated => sig_reg2sgcntlr_currdesc_updated ,
-- Misc Controls to SG
sgcntlr2sg_run_stop => sig_sgcntlr2sg_run_stop ,
-- Idle bit control to Register
sgcntl2reg_idle_set => sig_sgcntl2reg_idle_set ,
sgcntl2reg_idle_clr => sig_sgcntl2reg_idle_clr ,
-- SOF/EOF control to SG
sgcntl2sg_pkt_sof => sig_sgcntl2sg_pkt_sof ,
sgcntl2sg_pkt_eof => sig_sgcntl2sg_pkt_eof ,
-- Interrupt status from SG
sg2sgcntl_ioc_irq_set => sig_sg2sgcntl_ioc_irq_set ,
sg2sgcntl_dly_irq_set => sig_sg2sgcntl_dly_irq_set ,
-- Interrupt control to Register
sgcntl2reg_ioc_irq_set => sig_sgcntl2reg_ioc_irq_set ,
sgcntl2reg_dly_irq_set => sig_sgcntl2reg_dly_irq_set ,
-- Descriptor Fetch Stream from SG
sgcntl2sg_ftch_tready => sig_sgcntl2sg_ftch_tready ,
sg2sgcntlr_ftch_tvalid => sig_sg2sgcntlr_ftch_tvalid ,
sg2sgcntlr_ftch_tvalid_new => sig_sg2sgcntlr_ftch_tvalid_new ,
sg2sgcntlr_ftch_tdata => sig_sg2sgcntlr_ftch_tdata ,
sg2sgcntlr_ftch_tdata_new => sig_sg2sgcntlr_ftch_tdata_new ,
sg2sgcntlr_ftch_tlast => sig_sg2sgcntlr_ftch_tlast ,
sig_sg2sgcntlr_ftch_desc_available => sig_sg2sgcntlr_ftch_desc_available ,
-- Descriptor Pointer Update Stream to SG
sg2sgcntlr_updptr_tready => sig_sg2sgcntlr_updptr_tready ,
sgcntl2sg_updptr_tvalid => sig_sgcntl2sg_updptr_tvalid ,
sgcntl2sg_updptr_tdata => sig_sgcntl2sg_updptr_tdata ,
sgcntl2sg_updptr_tlast => sig_sgcntl2sg_updptr_tlast ,
-- Descriptor Status Update Stream to SG
sg2sgcntlr_updsts_tready => sig_sg2sgcntlr_updsts_tready ,
sgcntl2sg_updsts_tvalid => sig_sgcntl2sg_updsts_tvalid ,
sgcntl2sg_updsts_tdata => sig_sgcntl2sg_updsts_tdata ,
sgcntl2sg_updsts_tlast => sig_sgcntl2sg_updsts_tlast ,
-- Descriptor Fetch status from SG
sg2sgcntlr_ftch_idle => sig_sg2sgcntlr_ftch_idle ,
sg2sgcntlr_ftch_err_early => sig_sg2sgcntlr_ftch_err_early ,
sg2sgcntlr_ftch_stale_desc => sig_sg2sgcntlr_ftch_stale_desc ,
sg2sgcntlr_ftch_error => sig_sg2sgcntlr_ftch_error ,
-- Descriptor Update status from SG
sg2sgcntlr_updt_idle => sig_sg2sgcntlr_updt_idle ,
sg2sgcntlr_updt_ioc_irq_set => sig_sg2sgcntlr_updt_ioc_irq_set ,
sg2sgcntlr_updt_error => sig_sg2sgcntlr_updt_error ,
-- Echo of Main DataMover detected errors from SG
sg2sgcntlr_dma_interr_set => sig_sg2sgcntlr_dma_interr_set ,
sg2sgcntlr_dma_slverr_set => sig_sg2sgcntlr_dma_slverr_set ,
sg2sgcntlr_dma_decerr_set => sig_sg2sgcntlr_dma_decerr_set ,
-- Main DM Error bit controls to Register
sgcntlr2reg_dma_interr_set => sig_sgcntlr2reg_dma_interr_set ,
sgcntlr2reg_dma_slverr_set => sig_sgcntlr2reg_dma_slverr_set ,
sgcntlr2reg_dma_decerr_set => sig_sgcntlr2reg_dma_decerr_set ,
-- Current DEscriptor Update control to Register
sgcntlr2reg_new_curdesc_wren => sig_sgcntlr2reg_new_curdesc_wren ,
sgcntlr2reg_new_curdesc => sig_sgcntlr2reg_new_curdesc ,
-- DataMover MM2S Command Interface Ports (AXI Stream)
mm2s2sgcntl_cmd_tready => sig_mm2s2sgcntl_cmd_tready ,
sgcntl2mm2s_cmd_tvalid => sig_sgcntl2mm2s_cmd_tvalid ,
sgcntl2mm2s_cmd_tdata => sig_sgcntl2mm2s_cmd_tdata ,
-- DataMover MM2S Status Interface Ports (AXI Stream)
sgcntl2mm2s_sts_tready => sig_sgcntl2mm2s_sts_tready ,
mm2s2sgcntl_sts_tvalid => sig_mm2s2sgcntl_sts_tvalid ,
mm2s2sgcntl_sts_tdata => sig_dm_mm2s_sts_tdata ,
mm2s2sgcntl_sts_tstrb => sig_dm_mm2s_sts_tkeep ,
-- DataMover MM2S error discrete
mm2s2sgcntl_err => sig_dm_mm2s_err ,
-- DataMover MM2S Halt
sgcntl2mm2s_halt => sig_sgcntl2mm2s_halt ,
mm2s2sgcntl_halt_cmplt => sig_dm_mm2s_halt_cmplt ,
-- DataMover S2MM Command Interface Ports (AXI Stream)
s2mm2sgcntl_cmd_tready => sig_s2mm2sgcntl_cmd_tready ,
sgcntl2s2mm_cmd_tvalid => sig_sgcntl2s2mm_cmd_tvalid ,
sgcntl2s2mm_cmd_tdata => sig_sgcntl2s2mm_cmd_tdata ,
-- DataMover S2MM Status Interface Ports (AXI Stream)
sgcntl2s2mm_sts_tready => sig_sgcntl2s2mm_sts_tready ,
s2mm2sgcntl_sts_tvalid => sig_s2mm2sgcntl_sts_tvalid ,
s2mm2sgcntl_sts_tdata => sig_s2mm2sgcntl_sts_tdata ,
s2mm2sgcntl_sts_tstrb => sig_s2mm2sgcntl_sts_tstrb ,
-- DataMover S2MM error discrete
s2mm2sgcntl_err => sig_dm_s2mm_err ,
-- DataMover MM2S Halt
sgcntl2s2mm_halt => sig_sgcntl2s2mm_halt ,
s2mm2sgcntl_halt_cmplt => sig_dm_s2mm_halt_cmplt
);
-------------------------------------------------------------------------------
-- Scatter Gather Engine
-------------------------------------------------------------------------------
I_SG_ENGINE : entity axi_sg_v4_1_7.axi_sg
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => SG_CH1_WORDS_TO_FETCH ,
C_SG_CH1_WORDS_TO_UPDATE => SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH1_ENBL_STALE_ERROR => SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_WORDS_TO_FETCH => SG_CH2_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_UPDATE => SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => SG_CH2_FIRST_UPDATE_WORD ,
C_SG_CH2_ENBL_STALE_ERROR => SG_CH2_ENBL_STALE_ERROR ,
C_INCLUDE_CH1 => INCLUDE_CH1 ,
C_INCLUDE_CH2 => OMIT_CH2 ,
C_INCLUDE_DESC_UPDATE => INCLUDE_UPDATE_ENG ,
C_INCLUDE_INTRPT => INCLUDE_IRPT_CNTLR ,
C_INCLUDE_DLYTMR => INCLUDE_DLY_TIMER ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ,
C_AXIS_IS_ASYNC => 0 ,
C_ENABLE_MULTI_CHANNEL => 0 ,
C_ENABLE_CDMA => 1 ,
C_NUM_S2MM_CHANNELS => 1 ,
C_NUM_MM2S_CHANNELS => 1 ,
C_ACTUAL_ADDR => C_ACTUAL_ADDR ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => axi_aclk ,
m_axi_mm2s_aclk => axi_aclk ,
p_reset_n => '1' ,
m_axi_sg_aresetn => sig_rst2sg_resetn ,
dm_resetn => sig_rst2dm_resetn ,
sg_ctl => "00000000" ,
-- Scatter Gather Write Address Channel
m_axi_sg_awaddr => m_axi_sg_awaddr ,
m_axi_sg_awlen => m_axi_sg_awlen ,
m_axi_sg_awsize => m_axi_sg_awsize ,
m_axi_sg_awburst => m_axi_sg_awburst ,
m_axi_sg_awprot => m_axi_sg_awprot ,
m_axi_sg_awcache => m_axi_sg_awcache ,
m_axi_sg_awuser => open, --m_axi_sg_awcache ,
m_axi_sg_awvalid => m_axi_sg_awvalid ,
m_axi_sg_awready => m_axi_sg_awready ,
-- Scatter Gather Write Data Channel
m_axi_sg_wdata => m_axi_sg_wdata ,
m_axi_sg_wstrb => m_axi_sg_wstrb ,
m_axi_sg_wlast => m_axi_sg_wlast ,
m_axi_sg_wvalid => m_axi_sg_wvalid ,
m_axi_sg_wready => m_axi_sg_wready ,
-- Scatter Gather Write Response Channel
m_axi_sg_bresp => m_axi_sg_bresp ,
m_axi_sg_bvalid => m_axi_sg_bvalid ,
m_axi_sg_bready => m_axi_sg_bready ,
-- Scatter Gather Read Address Channel
m_axi_sg_araddr => m_axi_sg_araddr ,
m_axi_sg_arlen => m_axi_sg_arlen ,
m_axi_sg_arsize => m_axi_sg_arsize ,
m_axi_sg_arburst => m_axi_sg_arburst ,
m_axi_sg_arprot => m_axi_sg_arprot ,
m_axi_sg_arcache => m_axi_sg_arcache ,
m_axi_sg_aruser => open, --m_axi_sg_arcache ,
m_axi_sg_arvalid => m_axi_sg_arvalid ,
m_axi_sg_arready => m_axi_sg_arready ,
-- Memory Map to Stream Scatter Gather Read Data Channel
m_axi_sg_rdata => m_axi_sg_rdata ,
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rlast => m_axi_sg_rlast ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
m_axi_sg_rready => m_axi_sg_rready ,
-- Channel 1 Control and Status
ch1_run_stop => sig_sgcntlr2sg_run_stop ,
ch1_cyclic => dma_cyclic,
ch1_desc_flush => sig_sgcntlr2sg_desc_flush ,
ch1_cntrl_strm_stop => '0' ,
ch1_ftch_idle => sig_sg2sgcntlr_ftch_idle ,
ch1_ftch_interr_set => sig_sg2reg_ftch_interr_set ,
ch1_ftch_slverr_set => sig_sg2reg_ftch_slverr_set ,
ch1_ftch_decerr_set => sig_sg2reg_ftch_decerr_set ,
ch1_ftch_err_early => sig_sg2sgcntlr_ftch_err_early ,
ch1_ftch_stale_desc => sig_sg2sgcntlr_ftch_stale_desc ,
ch1_updt_idle => sig_sg2sgcntlr_updt_idle ,
ch1_updt_ioc_irq_set => sig_sg2sgcntlr_updt_ioc_irq_set ,
ch1_updt_interr_set => sig_sg2reg_updt_interr_set ,
ch1_updt_slverr_set => sig_sg2reg_updt_slverr_set ,
ch1_updt_decerr_set => sig_sg2reg_updt_decerr_set ,
ch1_dma_interr_set => sig_sg2sgcntlr_dma_interr_set ,
ch1_dma_slverr_set => sig_sg2sgcntlr_dma_slverr_set ,
ch1_dma_decerr_set => sig_sg2sgcntlr_dma_decerr_set ,
ch1_tailpntr_enabled => sig_reg2sg_dmacr(DMACR_TAILPEN_BIT) ,
ch1_taildesc_wren => sig_reg2sg_tailpntr_updated ,
ch1_taildesc => sig_reg2sg_taildesc ,
ch1_curdesc => sig_reg2sg_curdesc ,
-- Channel 1 Interrupt Coalescing Signals
ch1_irqthresh_rstdsbl => LOGIC_LOW ,
ch1_dlyirq_dsble => sig_reg2sg_dmasr(DMASR_DLYIRQ_BIT) ,
ch1_irqdelay_wren => sig_reg2sg_irqdelay_wren ,
ch1_irqdelay => sig_reg2sg_dmacr(DMACR_IRQDELAY_MSB_BIT downto
DMACR_IRQDELAY_LSB_BIT) ,
ch1_irqthresh_wren => sig_reg2sg_irqthresh_wren ,
ch1_irqthresh => sig_reg2sg_dmacr(DMACR_IRQTHRESH_MSB_BIT downto
DMACR_IRQTHRESH_LSB_BIT) ,
ch1_packet_sof => sig_sgcntl2sg_pkt_sof ,
ch1_packet_eof => sig_sgcntl2sg_pkt_eof ,
ch1_ioc_irq_set => sig_sg2sgcntl_ioc_irq_set ,
ch1_dly_irq_set => sig_sg2sgcntl_dly_irq_set ,
ch1_irqdelay_status => sig_sg2reg_irqdelay_status ,
ch1_irqthresh_status => sig_sg2reg_irqthresh_status ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => axi_aclk ,
m_axis_ch1_ftch_tdata => sig_sg2sgcntlr_ftch_tdata ,
m_axis_ch1_ftch_tdata_new => sig_sg2sgcntlr_ftch_tdata_new ,
m_axis_ch1_ftch_tvalid => sig_sg2sgcntlr_ftch_tvalid ,
m_axis_ch1_ftch_tvalid_new => sig_sg2sgcntlr_ftch_tvalid_new ,
m_axis_ch1_ftch_tready => sig_sgcntl2sg_ftch_tready ,
m_axis_ch1_ftch_tlast => sig_sg2sgcntlr_ftch_tlast ,
m_axis_ftch1_desc_available => sig_sg2sgcntlr_ftch_desc_available,
-- Channel 1 Pointer Update Stream In
s_axis_ch1_updt_aclk => axi_aclk ,
s_axis_ch1_updtptr_tdata => sig_sgcntl2sg_updptr_tdata ,
s_axis_ch1_updtptr_tvalid => sig_sgcntl2sg_updptr_tvalid ,
s_axis_ch1_updtptr_tready => sig_sg2sgcntlr_updptr_tready ,
s_axis_ch1_updtptr_tlast => sig_sgcntl2sg_updptr_tlast ,
-- Channel 1 Status Update Stream In
s_axis_ch1_updtsts_tdata => sig_sgcntl2sg_updsts_tdata ,
s_axis_ch1_updtsts_tvalid => sig_sgcntl2sg_updsts_tvalid ,
s_axis_ch1_updtsts_tready => sig_sg2sgcntlr_updsts_tready ,
s_axis_ch1_updtsts_tlast => sig_sgcntl2sg_updsts_tlast ,
-- Channel 2 Control and Status
ch2_run_stop => LOGIC_LOW ,
ch2_cyclic => '0',
ch2_desc_flush => LOGIC_LOW ,
ch2_ftch_idle => open ,
ch2_ftch_interr_set => open ,
ch2_ftch_slverr_set => open ,
ch2_ftch_decerr_set => open ,
ch2_ftch_err_early => open ,
ch2_ftch_stale_desc => open ,
ch2_updt_idle => open ,
ch2_updt_ioc_irq_set => open ,
ch2_updt_interr_set => open ,
ch2_updt_slverr_set => open ,
ch2_updt_decerr_set => open ,
ch2_dma_interr_set => open ,
ch2_dma_slverr_set => open ,
ch2_dma_decerr_set => open ,
ch2_tailpntr_enabled => LOGIC_LOW ,
ch2_taildesc_wren => LOGIC_LOW ,
ch2_taildesc_wren_pkt => LOGIC_LOW ,
ch2_taildesc => SG_ADDR_ZEROS ,
ch2_curdesc => SG_ADDR_ZEROS ,
-- Channel 2 Interrupt Coalescing Signals
ch2_irqthresh_rstdsbl => LOGIC_LOW ,
ch2_dlyirq_dsble => LOGIC_LOW ,
ch2_irqdelay_wren => LOGIC_LOW ,
ch2_irqdelay => IRQ_DLY_THRESH_ZEROS ,
ch2_irqthresh_wren => LOGIC_LOW ,
ch2_irqthresh => IRQ_DLY_THRESH_ZEROS ,
ch2_packet_sof => LOGIC_LOW ,
ch2_packet_eof => LOGIC_LOW ,
ch2_ioc_irq_set => open ,
ch2_dly_irq_set => open ,
ch2_irqdelay_status => open ,
ch2_irqthresh_status => open ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => axi_aclk ,
m_axis_ch2_ftch_tdata => open ,
m_axis_ch2_ftch_tvalid => open ,
m_axis_ch2_ftch_tready => LOGIC_LOW ,
m_axis_ch2_ftch_tlast => open ,
-- Channel 2 Pointer Update Stream In
s_axis_ch2_updt_aclk => axi_aclk ,
s_axis_ch2_updtptr_tdata => SG_UPDPTR_DATA_ZEROS ,
s_axis_ch2_updtptr_tvalid => LOGIC_LOW ,
s_axis_ch2_updtptr_tready => open ,
s_axis_ch2_updtptr_tlast => LOGIC_LOW ,
-- Channel 2 Status Update Stream In
s_axis_ch2_updtsts_tdata => SG_UPDSTS_DATA_ZEROS ,
s_axis_ch2_updtsts_tvalid => LOGIC_LOW ,
s_axis_ch2_updtsts_tready => open ,
s_axis_ch2_updtsts_tlast => LOGIC_LOW ,
-- Error addresses
ftch_error => sig_sg2sgcntlr_ftch_error ,
ftch_error_addr => sig_sg2reg_ftch_error_addr ,
updt_error => sig_sg2sgcntlr_updt_error ,
updt_error_addr => sig_sg2reg_updt_error_addr
);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DM_IF_MUX
--
-- Process Description:
-- THis process implements a multiplexer for the input controls
-- to the Main dataMover that are driven by the Simple Mode
-- Controller or the SG Mode Controller.
--
-------------------------------------------------------------
DM_IF_MUX : process (sig_reg2cntlr_sg_mode ,
sig_sgcntl2mm2s_cmd_tdata ,
sig_sgcntl2mm2s_cmd_tvalid ,
sig_sgcntl2mm2s_sts_tready ,
sig_sgcntl2s2mm_cmd_tdata ,
sig_sgcntl2s2mm_cmd_tvalid ,
sig_sgcntl2s2mm_sts_tready ,
sig_cntl2mm2s_cmd_tdata ,
sig_cntl2mm2s_cmd_tvalid ,
sig_cntl2mm2s_sts_tready ,
sig_cntl2s2mm_cmd_tdata ,
sig_cntl2s2mm_cmd_tvalid ,
sig_cntl2s2mm_sts_tready ,
sig_sgcntl2mm2s_halt ,
sig_sgcntl2s2mm_halt ,
sig_rst2mm2s_halt ,
sig_rst2s2mm_halt
)
begin
case sig_reg2cntlr_sg_mode is
when '1' => -- SG Mode Enabled
sig_dm_mm2s_cmd_tdata <= sig_sgcntl2mm2s_cmd_tdata ;
sig_dm_mm2s_cmd_tvalid <= sig_sgcntl2mm2s_cmd_tvalid ;
sig_dm_mm2s_sts_tready <= sig_sgcntl2mm2s_sts_tready ;
sig_dm_s2mm_cmd_tdata <= sig_sgcntl2s2mm_cmd_tdata ;
sig_dm_s2mm_cmd_tvalid <= sig_sgcntl2s2mm_cmd_tvalid ;
sig_dm_s2mm_sts_tready <= sig_sgcntl2s2mm_sts_tready ;
sig_dm_mm2s_halt <= sig_sgcntl2mm2s_halt ;
sig_dm_s2mm_halt <= sig_sgcntl2s2mm_halt ;
when others => -- Simple DMA Enabled
sig_dm_mm2s_cmd_tdata <= sig_cntl2mm2s_cmd_tdata ;
sig_dm_mm2s_cmd_tvalid <= sig_cntl2mm2s_cmd_tvalid ;
sig_dm_mm2s_sts_tready <= sig_cntl2mm2s_sts_tready ;
sig_dm_s2mm_cmd_tdata <= sig_cntl2s2mm_cmd_tdata ;
sig_dm_s2mm_cmd_tvalid <= sig_cntl2s2mm_cmd_tvalid ;
sig_dm_s2mm_sts_tready <= sig_cntl2s2mm_sts_tready ;
sig_dm_mm2s_halt <= sig_rst2mm2s_halt ;
sig_dm_s2mm_halt <= sig_rst2s2mm_halt ;
end case;
end process DM_IF_MUX;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DM_RDY_VLD_DEMUX
--
-- Process Description:
-- This process implements a demultiplexer for the DataMover
-- Ready/Valid signals driven back to the Simple Mode Controller
-- and the SG Mode Controller. Data and Strobes are not
-- Demux'd.
--
-------------------------------------------------------------
DM_RDY_VLD_DEMUX : process (sig_reg2cntlr_sg_mode ,
sig_dm_mm2s_cmd_tready ,
sig_dm_mm2s_sts_tvalid ,
sig_dm_s2mm_cmd_tready ,
sig_dm_s2mm_sts_tvalid
)
begin
case sig_reg2cntlr_sg_mode is
when '1' => -- SG Mode Enabled
sig_mm2s2cntl_cmd_tready <= '0';
sig_mm2s2sgcntl_cmd_tready <= sig_dm_mm2s_cmd_tready;
sig_mm2s2cntl_sts_tvalid <= '0';
sig_mm2s2sgcntl_sts_tvalid <= sig_dm_mm2s_sts_tvalid;
sig_s2mm2cntl_cmd_tready <= '0';
sig_s2mm2sgcntl_cmd_tready <= sig_dm_s2mm_cmd_tready;
sig_s2mm2cntl_sts_tvalid <= '0';
sig_s2mm2sgcntl_sts_tvalid <= sig_dm_s2mm_sts_tvalid;
when others => -- Simple DMA Mode Enabled
sig_mm2s2cntl_cmd_tready <= sig_dm_mm2s_cmd_tready;
sig_mm2s2sgcntl_cmd_tready <= '0';
sig_mm2s2cntl_sts_tvalid <= sig_dm_mm2s_sts_tvalid;
sig_mm2s2sgcntl_sts_tvalid <= '0';
sig_s2mm2cntl_cmd_tready <= sig_dm_s2mm_cmd_tready;
sig_s2mm2sgcntl_cmd_tready <= '0';
sig_s2mm2cntl_sts_tvalid <= sig_dm_s2mm_sts_tvalid;
sig_s2mm2sgcntl_sts_tvalid <= '0';
end case;
end process DM_RDY_VLD_DEMUX;
---------------------------------------------------------------------------------------
-- DataMover and support
-- Rip the basic status output from the DataMover S2MM status reply stream
sig_s2mm2sgcntl_sts_tdata <= sig_dm_s2mm_sts_tdata(BASE_STATUS_WIDTH-1 downto 0);
sig_s2mm2sgcntl_sts_tstrb <= sig_dm_s2mm_sts_tkeep((BASE_STATUS_WIDTH/8)-1 downto 0);
------------------------------------------------------------
-- Instance: I_DATAMOVER
--
-- Description:
--
-- Data Path DataMover
-- Reads data from the AXI MMAP Read Channel and Writes the data
-- to the AXI MMAP Write Channel via commands from the Controller
-- Module.
--
--
------------------------------------------------------------
I_DATAMOVER : entity axi_datamover_v5_1_16.axi_datamover
generic map(
C_INCLUDE_MM2S => MM2S_FULL_MODE ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_M_AXIS_MM2S_TDATA_WIDTH => DM_STREAM_DWIDTH ,
C_INCLUDE_MM2S_STSFIFO => DM_INCLUDE_STS_FIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => DM_SG_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => DM_USE_SYNC_CLOCKS ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_DRE ,
C_MM2S_BURST_SIZE => C_M_AXI_MAX_BURST_LEN ,
C_MM2S_BTT_USED => DM_BTT_WIDTH ,
C_MM2S_ADDR_PIPE_DEPTH => DM_READ_ADDR_PIPE_DEPTH ,
C_MM2S_INCLUDE_SF => 0 ,
C_ENABLE_CACHE_USER => 0 ,
C_ENABLE_SKID_BUF => "11000" ,
C_CMD_WIDTH => DM_CMD_WIDTH ,
C_INCLUDE_S2MM => S2MM_FULL_MODE ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH ,
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_S_AXIS_S2MM_TDATA_WIDTH => DM_STREAM_DWIDTH ,
C_INCLUDE_S2MM_STSFIFO => DM_INCLUDE_STS_FIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => DM_SG_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => DM_USE_SYNC_CLOCKS ,
C_INCLUDE_S2MM_DRE => DM_S2MM_DRE_DISABLED ,
C_S2MM_BURST_SIZE => C_M_AXI_MAX_BURST_LEN ,
C_S2MM_BTT_USED => DM_BTT_WIDTH ,
C_S2MM_SUPPORT_INDET_BTT => STORE_FORWARD_CNTL ,
C_S2MM_ADDR_PIPE_DEPTH => DM_WRITE_ADDR_PIPE_DEPTH ,
C_S2MM_INCLUDE_SF => 0 ,
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => axi_aclk ,
m_axi_mm2s_aresetn => sig_rst2dm_resetn ,
-- MM2S Soft Shutdown
mm2s_halt => sig_dm_mm2s_halt ,
mm2s_halt_cmplt => sig_dm_mm2s_halt_cmplt ,
-- MM2S Error output discrete
mm2s_err => sig_dm_mm2s_err ,
-- Memory Map to Stream Command FIFO and Status FIFO Async CLK/RST --------------
m_axis_mm2s_cmdsts_aclk => LOGIC_LOW ,
m_axis_mm2s_cmdsts_aresetn => LOGIC_HIGH ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => sig_dm_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => sig_dm_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => sig_dm_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => sig_dm_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => sig_dm_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => sig_dm_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => sig_dm_mm2s_sts_tkeep ,
m_axis_mm2s_sts_tlast => open ,
-- Address Posting contols
mm2s_allow_addr_req => sig_mm2s_allow_addr_req ,
mm2s_addr_req_posted => sig_mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => sig_mm2s_rd_xfer_cmplt ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_araddr ,
m_axi_mm2s_arlen => m_axi_arlen ,
m_axi_mm2s_arsize => m_axi_arsize ,
m_axi_mm2s_arburst => m_axi_arburst ,
m_axi_mm2s_arprot => m_axi_arprot ,
m_axi_mm2s_arcache => m_axi_arcache ,
m_axi_mm2s_aruser => open, --m_axi_arcache ,
m_axi_mm2s_arvalid => m_axi_arvalid ,
m_axi_mm2s_arready => m_axi_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_rdata ,
m_axi_mm2s_rresp => m_axi_rresp ,
m_axi_mm2s_rlast => m_axi_rlast ,
m_axi_mm2s_rvalid => m_axi_rvalid ,
m_axi_mm2s_rready => m_axi_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => sig_mm2s_axis_tdata ,
m_axis_mm2s_tkeep => sig_mm2s_axis_tkeep ,
m_axis_mm2s_tlast => sig_mm2s_axis_tlast ,
m_axis_mm2s_tvalid => sig_mm2s_axis_tvalid ,
m_axis_mm2s_tready => sig_mm2s_axis_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => axi_aclk ,
m_axi_s2mm_aresetn => sig_rst2dm_resetn ,
-- S2MM Soft Shutdown
s2mm_halt => sig_dm_s2mm_halt ,
s2mm_halt_cmplt => sig_dm_s2mm_halt_cmplt ,
-- S2MM Error output discrete
s2mm_err => sig_dm_s2mm_err ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => LOGIC_LOW ,
m_axis_s2mm_cmdsts_aresetn => LOGIC_HIGH ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => sig_dm_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => sig_dm_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => sig_dm_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => sig_dm_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => sig_dm_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => sig_dm_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => sig_dm_s2mm_sts_tkeep ,
m_axis_s2mm_sts_tlast => open ,
-- Address posting controls
s2mm_allow_addr_req => sig_s2mm_allow_addr_req ,
s2mm_addr_req_posted => sig_s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => sig_s2mm_ld_nxt_len ,
s2mm_wr_len => sig_s2mm_wr_len ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_awaddr ,
m_axi_s2mm_awlen => m_axi_awlen ,
m_axi_s2mm_awsize => m_axi_awsize ,
m_axi_s2mm_awburst => m_axi_awburst ,
m_axi_s2mm_awprot => m_axi_awprot ,
m_axi_s2mm_awcache => m_axi_awcache ,
m_axi_s2mm_awuser => open, --m_axi_awcache ,
m_axi_s2mm_awvalid => m_axi_awvalid ,
m_axi_s2mm_awready => m_axi_awready ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_wdata ,
m_axi_s2mm_wstrb => m_axi_wstrb ,
m_axi_s2mm_wlast => m_axi_wlast ,
m_axi_s2mm_wvalid => m_axi_wvalid ,
m_axi_s2mm_wready => m_axi_wready ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_bresp ,
m_axi_s2mm_bvalid => m_axi_bvalid ,
m_axi_s2mm_bready => m_axi_bready ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => sig_s2mm_axis_tdata ,
s_axis_s2mm_tkeep => sig_s2mm_axis_tkeep ,
s_axis_s2mm_tlast => sig_s2mm_axis_tlast ,
s_axis_s2mm_tvalid => sig_s2mm_axis_tvalid ,
s_axis_s2mm_tready => sig_s2mm_axis_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_SF
--
-- If Generate Description:
-- This IfGen includes the Store and Forward module
--
--
------------------------------------------------------------
GEN_INCLUDE_SF : if (C_INCLUDE_SF = 1) generate
begin
------------------------------------------------------------
-- Instance: I_STORE_FORWARD
--
-- Description:
-- This is the instance for the AXI CDMA Store and Forward
-- Module.
--
------------------------------------------------------------
I_STORE_FORWARD : entity axi_cdma_v4_1_14.axi_cdma_sf
generic map (
C_WR_ADDR_PIPE_DEPTH => DM_WRITE_ADDR_PIPE_DEPTH,
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_MAX_BURST_LEN => C_M_AXI_MAX_BURST_LEN ,
C_DRE_IS_USED => C_INCLUDE_DRE ,
C_STREAM_DWIDTH => C_M_AXI_DATA_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock input
aclk => axi_aclk ,
-- Reset input
reset => sig_sf_reset ,
-- DataMover Read Side Address Pipelining control Interface ----
ok_to_post_rd_addr => sig_mm2s_allow_addr_req ,
rd_addr_posted => sig_mm2s_addr_req_posted ,
rd_xfer_cmplt => sig_mm2s_rd_xfer_cmplt ,
-- Read Side Stream In from DataMover MM2S ---------------------
sf2sin_tready => sig_mm2s_axis_tready ,
sin2sf_tvalid => sig_mm2s_axis_tvalid ,
sin2sf_tdata => sig_mm2s_axis_tdata ,
sin2sf_tkeep => sig_mm2s_axis_tkeep ,
sin2sf_tlast => sig_mm2s_axis_tlast ,
-- DataMover Write Side Address Pipelining control Interface ---
ok_to_post_wr_addr => sig_s2mm_allow_addr_req ,
wr_addr_posted => sig_s2mm_addr_req_posted ,
wr_xfer_cmplt => sig_s2mm_wr_xfer_cmplt ,
wr_ld_nxt_len => sig_s2mm_ld_nxt_len ,
wr_len => sig_s2mm_wr_len ,
-- Write Side Stream Out to DataMover S2MM --------------------
sout2sf_tready => sig_s2mm_axis_tready ,
sf2sout_tvalid => sig_s2mm_axis_tvalid ,
sf2sout_tdata => sig_s2mm_axis_tdata ,
sf2sout_tkeep => sig_s2mm_axis_tkeep ,
sf2sout_tlast => sig_s2mm_axis_tlast
);
end generate GEN_INCLUDE_SF;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_SF
--
-- If Generate Description:
-- This IfGen includes the Store and Forward module
--
--
------------------------------------------------------------
GEN_OMIT_SF : if (C_INCLUDE_SF = 0) generate
begin
sig_mm2s_allow_addr_req <= LOGIC_HIGH;
sig_s2mm_allow_addr_req <= LOGIC_HIGH;
sig_mm2s_axis_tready <= sig_s2mm_axis_tready ;
sig_s2mm_axis_tvalid <= sig_mm2s_axis_tvalid ;
sig_s2mm_axis_tdata <= sig_mm2s_axis_tdata ;
sig_s2mm_axis_tkeep <= sig_mm2s_axis_tkeep ;
sig_s2mm_axis_tlast <= sig_mm2s_axis_tlast ;
end generate GEN_OMIT_SF;
end implementation;
-------------------------------------------------------------------------------
-- axi_cdma
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_cdma.vhd
-- Description: This entity is the top level entity for the AXI CDMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_cdma_v4_1_14;
use axi_cdma_v4_1_14.axi_cdma_pkg.all;
use axi_cdma_v4_1_14.axi_cdma_simple_wrap;
use axi_cdma_v4_1_14.axi_cdma_sg_wrap;
-------------------------------------------------------------------------------
entity axi_cdma is
generic(
-----------------------------------------------------------------------
-- AXI Lite Register Interface Parameters
-----------------------------------------------------------------------
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 6;
-- Address width of the AXI Lite Interface (bits)
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32;
-- Data width of the AXI Lite Interface (bits)
C_AXI_LITE_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the AXI Lite Register interface needs to
-- be asynchronous to the CDMA data transport path clocking
-- 0 = s_axi_lite_aclk is the same as m_axi_aclk
-- 1 = s_axi_lite_aclk is asynchronous to the m_axi_aclk
-----------------------------------------------------------------------
-- DataMover Parameters
-----------------------------------------------------------------------
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32;
-- DataMover Master AXI Memory Map Address Width (bits)
C_M_AXI_DATA_WIDTH : integer range 32 to 1024 := 32;
-- DataMover Master AXI Memory Map Data Width (bits)
C_M_AXI_MAX_BURST_LEN : integer range 2 to 256 := 16;
-- DataMover Maximum burst length to use for AXI MMAP requests
-- Allowed values are 16, 32, 64, 128, and 256 (data beats)
C_INCLUDE_DRE : integer range 0 to 1 := 0;
-- Include or exclude DataMover Data Realignment (DRE)
-- NOTE: DRE is only available for 32 and 64 bit data widths
-- 0 = Exclude DRE
-- 1 = Include DRE
C_USE_DATAMOVER_LITE : integer range 0 to 1 := 0;
-- Enable DataMover Lite mode
-- NOTE: Data widths limited to 32 and 64 bits, max burst
-- limited to 16, 32, and 64 data beats, no DRE, 4K address
-- guarding must be done by SW programmer.
-- 0 = Normal DataMover mode
-- 1 = Lite dataMover mode
C_READ_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter specifies the depth of the DataMover
-- read address pipelining queues for the Main data transport
-- channels. The effective address pipelining on the AXI4 Read
-- Address Channel will be the value assigned plus 2.
C_WRITE_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 4;
-- This parameter specifies the depth of the DataMover
-- write address pipelining queues for the Main data transport
-- channel. The effective address pipelining on the AXI4 Write
-- Address Channel will be the value assigned plus 2.
-----------------------------------------------------------------------
-- Store and Forward Parameters
-----------------------------------------------------------------------
C_INCLUDE_SF : integer range 0 to 1 := 1;
-- 0 = Omit Store and Forward functionality
-- 1 = Include Store and Forward functionality
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 0;
-- 0 = Omit Scatter Gather functionality
-- 1 = Include Scatter Gather functionality
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather
-- R/W Port (bits)
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather
-- R/W Port (bits)
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in clock ticks of axi_clk
-----------------------------------------------------------------------
-- Target FPGA Family Parameter
-----------------------------------------------------------------------
C_FAMILY : string := "virtex7";
-- Target FPGA Device Family
C_INSTANCE : string := "axi_cdma"
);
port (
-----------------------------------------------------------------------
-- Primary Clock
-----------------------------------------------------------------------
m_axi_aclk : in std_logic ;-- AXI4
-----------------------------------------------------------------------
-- Primary Reset Input (active low)
-----------------------------------------------------------------------
-- m_axi_aresetn : in std_logic ;-- AXI4
-----------------------------------------------------------------------
-- AXI Lite clock
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ;-- AXI4-Lite
-----------------------------------------------------------------------
-- AXI Lite reset
-----------------------------------------------------------------------
s_axi_lite_aresetn : in std_logic ;-- AXI4-Lite
-----------------------------------------------------------------------
-- Interrupt output
-----------------------------------------------------------------------
cdma_introut : out std_logic ;-- Interupt Out
---------------------------------------------------------------------------------
-- AXI4-Lite Register Access Interface
---------------------------------------------------------------------------------
-- AXI Lite Write Address Channel -- AXI4-Lite
s_axi_lite_awready : out std_logic ;-- AXI4-Lite
s_axi_lite_awvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_awaddr : in std_logic_vector -- AXI4-Lite
(5 downto 0);-- AXI4-Lite
-- s_axi_lite_awaddr : in std_logic_vector -- AXI4-Lite
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Write Data Channel -- AXI4-Lite
s_axi_lite_wready : out std_logic ;-- AXI4-Lite
s_axi_lite_wvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_wdata : in std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Write Response Channel -- AXI4-Lite
s_axi_lite_bready : in std_logic ;-- AXI4-Lite
s_axi_lite_bvalid : out std_logic ;-- AXI4-Lite
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ;-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Read Address Channel -- AXI4-Lite
s_axi_lite_arready : out std_logic ;-- AXI4-Lite
s_axi_lite_arvalid : in std_logic ;-- AXI4-Lite
s_axi_lite_araddr : in std_logic_vector -- AXI4-Lite
(5 downto 0);-- AXI4-Lite
-- s_axi_lite_araddr : in std_logic_vector -- AXI4-Lite
-- (C_S_AXI_LITE_ADDR_WIDTH-1 downto 0);-- AXI4-Lite
-- AXI4-Lite
-- AXI Lite Read Data Channel -- AXI4-Lite
s_axi_lite_rready : in std_logic ;-- AXI4-Lite
s_axi_lite_rvalid : out std_logic ;-- AXI4-Lite
s_axi_lite_rdata : out std_logic_vector -- AXI4-Lite
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);-- AXI4-Lite
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ;-- AXI4-Lite
----------------------------------------------------------------------------
-- AXI4 DataMover Read Channel
----------------------------------------------------------------------------
-- DataMover MMap Read Address Channel -- AXI4
m_axi_arready : in std_logic ;-- AXI4
m_axi_arvalid : out std_logic ;-- AXI4
m_axi_araddr : out std_logic_vector -- AXI4
(C_M_AXI_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_arlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_arsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_arburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_arprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_arcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- DataMover MMap Read Data Channel -- AXI4
m_axi_rready : out std_logic ;-- AXI4
m_axi_rvalid : in std_logic ;-- AXI4
m_axi_rdata : in std_logic_vector -- AXI4
(C_M_AXI_DATA_WIDTH-1 downto 0) ;-- AXI4
m_axi_rresp : in std_logic_vector(1 downto 0) ;-- AXI4
m_axi_rlast : in std_logic ;-- AXI4
-----------------------------------------------------------------------------
-- AXI4 DataMover Write Channel
-----------------------------------------------------------------------------
-- DataMover Write Address Channel -- AXI4
m_axi_awready : in std_logic ; -- AXI4
m_axi_awvalid : out std_logic ; -- AXI4
m_axi_awaddr : out std_logic_vector -- AXI4
(C_M_AXI_ADDR_WIDTH-1 downto 0) ; -- AXI4
m_axi_awlen : out std_logic_vector(7 downto 0) ; -- AXI4
m_axi_awsize : out std_logic_vector(2 downto 0) ; -- AXI4
m_axi_awburst : out std_logic_vector(1 downto 0) ; -- AXI4
m_axi_awprot : out std_logic_vector(2 downto 0) ; -- AXI4
m_axi_awcache : out std_logic_vector(3 downto 0) ; -- AXI4
-- AXI4
-- DataMover Write Data Channel -- AXI4
m_axi_wready : in std_logic ; -- AXI4
m_axi_wvalid : out std_logic ; -- AXI4
m_axi_wdata : out std_logic_vector -- AXI4
(C_M_AXI_DATA_WIDTH-1 downto 0) ; -- AXI4
m_axi_wstrb : out std_logic_vector -- AXI4
((C_M_AXI_DATA_WIDTH/8)-1 downto 0);-- AXI4
m_axi_wlast : out std_logic ; -- AXI4
-- AXI4
-- DataMover Write Response Channel -- AXI4
m_axi_bready : out std_logic ; -- AXI4
m_axi_bvalid : in std_logic ; -- AXI4
m_axi_bresp : in std_logic_vector(1 downto 0) ; -- AXI4
----------------------------------------------------------------------------
-- AXI4 Scatter Gather Interface
----------------------------------------------------------------------------
-- Scatter Gather Write Address Channel -- AXI4
m_axi_sg_awready : in std_logic := '0' ;-- AXI4
m_axi_sg_awvalid : out std_logic ;-- AXI4
m_axi_sg_awaddr : out std_logic_vector -- AXI4
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- Scatter Gather Write Data Channel -- AXI4
m_axi_sg_wready : in std_logic := '0' ;-- AXI4
m_axi_sg_wvalid : out std_logic ;-- AXI4
m_axi_sg_wdata : out std_logic_vector -- AXI4
(C_M_AXI_SG_DATA_WIDTH-1 downto 0);-- AXI4
m_axi_sg_wstrb : out std_logic_vector -- AXI4
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0);-- AXI4
m_axi_sg_wlast : out std_logic ;-- AXI4
-- AXI4
-- Scatter Gather Write Response Channel -- AXI4
m_axi_sg_bready : out std_logic ;-- AXI4
m_axi_sg_bvalid : in std_logic := '0' ;-- AXI4
m_axi_sg_bresp : in std_logic_vector(1 downto 0) := (others => '0') ;-- AXI4
-- AXI4
-- Scatter Gather Read Address Channel -- AXI4
m_axi_sg_arready : in std_logic := '0' ;-- AXI4
m_axi_sg_arvalid : out std_logic ;-- AXI4
m_axi_sg_araddr : out std_logic_vector -- AXI4
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;-- AXI4
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ;-- AXI4
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ;-- AXI4
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ;-- AXI4
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ;-- AXI4
-- AXI4
-- Scatter Gather Read Data Channel -- AXI4
m_axi_sg_rready : out std_logic ;-- AXI4
m_axi_sg_rvalid : in std_logic := '0' ;-- AXI4
m_axi_sg_rdata : in std_logic_vector -- AXI4
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0') ;-- AXI4
m_axi_sg_rresp : in std_logic_vector(1 downto 0) := (others => '0') ;-- AXI4
m_axi_sg_rlast : in std_logic := '0' ;-- AXI4
-----------------------------------------------------------------------
-- Test Support for Xilinx internal use
-----------------------------------------------------------------------
cdma_tvect_out : Out std_logic_vector(31 downto 0)
);
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
--attribute IP_GROUP : string;
--attribute IP_GROUP of axi_cdma : entity is "LOGICORE";
--attribute IPTYPE : string;
--attribute IPTYPE of axi_cdma : entity is "PERIPHERAL";
--attribute RUN_NGCBUILD : string;
--attribute RUN_NGCBUILD of axi_cdma : entity is "TRUE";
-----------------------------------------------------------------
-- End of PSFUtil MPD attributes
-----------------------------------------------------------------
end axi_cdma;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_cdma is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_max
--
-- Function Description:
-- Returns the greater of two integers.
--
-------------------------------------------------------------------
function funct_get_max (value_in_1 : integer;
value_in_2 : integer)
return integer is
Variable max_value : Integer := 0;
begin
If (value_in_1 > value_in_2) Then
max_value := value_in_1;
else
max_value := value_in_2;
End if;
Return (max_value);
end function funct_get_max;
-------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 128 and 8192.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 128) then
temp_pwr2 := 128;
elsif (input_value <= 256) then
temp_pwr2 := 256;
elsif (input_value <= 512) then
temp_pwr2 := 512;
elsif (input_value <= 1024) then
temp_pwr2 := 1024;
elsif (input_value <= 2048) then
temp_pwr2 := 2048;
elsif (input_value <= 4096) then
temp_pwr2 := 4096;
else
temp_pwr2 := 8192;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
function width_calc (value_in : integer)
return integer is
variable addr_value : integer := 32;
begin
if (value_in > 32) then
addr_value := 64;
else
addr_value :=32;
end if;
return(addr_value);
end function width_calc;
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
Constant SOFT_RST_TIME_CLKS : integer := 8;
-- Specifies the time of the soft reset assertion in
-- m_axi_aclk clock periods.
-- Calculates the minimum needed depth of the CDMA Store and Forward FIFO
Constant PIPEDEPTH_BURST_LEN_PROD : integer :=
(funct_get_max(C_READ_ADDR_PIPE_DEPTH, C_WRITE_ADDR_PIPE_DEPTH)+2)
* C_M_AXI_MAX_BURST_LEN;
-- Assigns the depth of the CDMA Store and Forward FIFO to the nearest
-- power of 2
Constant SF_FIFO_DEPTH : integer range 128 to 8192 :=
funct_rnd2pwr_of_2(PIPEDEPTH_BURST_LEN_PROD);
constant ADDR_WIDTH : integer := width_calc (C_M_AXI_ADDR_WIDTH);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- No signals Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
signal m_axi_aresetn : std_logic;
signal m_axi_sg_awaddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
signal m_axi_sg_araddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
signal m_axi_araddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
signal m_axi_awaddr_internal : std_logic_vector (ADDR_WIDTH-1 downto 0) ;
begin
m_axi_aresetn <= '1';
m_axi_araddr <= m_axi_araddr_internal (C_M_AXI_ADDR_WIDTH-1 downto 0);
m_axi_awaddr <= m_axi_awaddr_internal (C_M_AXI_ADDR_WIDTH-1 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SIMPLE_MODE
--
-- If Generate Description:
-- This IfGen Implements the CDMA with Simple Mode
--
--
------------------------------------------------------------
GEN_SIMPLE_MODE : if (C_INCLUDE_SG = 0) generate
begin
-----------------------------------------------------------
-- Housekeep the Scatter Gather output signals that are not
-- used in Simple DMA mode.
-----------------------------------------------------------
-- Scatter Gather Write Address Channel
m_axi_sg_awvalid <= '0' ;
m_axi_sg_awaddr <= (others => '0');
m_axi_sg_awlen <= (others => '0');
m_axi_sg_awsize <= (others => '0');
m_axi_sg_awburst <= (others => '0');
m_axi_sg_awprot <= (others => '0');
m_axi_sg_awcache <= (others => '0');
-- Scatter Gather Write Data Channel
m_axi_sg_wvalid <= '0';
m_axi_sg_wdata <= (others => '0');
m_axi_sg_wstrb <= (others => '0');
m_axi_sg_wlast <= '0' ;
-- Scatter Gather Write Response Channel
m_axi_sg_bready <= '0' ;
-- Scatter Gather Read Address Channel
m_axi_sg_arvalid <= '0' ;
m_axi_sg_araddr <= (others => '0');
m_axi_sg_arlen <= (others => '0');
m_axi_sg_arsize <= (others => '0');
m_axi_sg_arburst <= (others => '0');
m_axi_sg_arprot <= (others => '0');
m_axi_sg_arcache <= (others => '0');
-- Memory Map to Stream Scatter Gather Read Data Channel
m_axi_sg_rready <= '0' ;
------------------------------------------------------------
-- Instance: I_SIMPLE_MODE_WRAP
--
-- Description:
-- Instance for the CDMA Simple Mode Wrapper
--
------------------------------------------------------------
I_SIMPLE_MODE_WRAP : entity axi_cdma_v4_1_14.axi_cdma_simple_wrap
generic map (
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_M_AXI_ADDR_WIDTH => ADDR_WIDTH, --C_M_AXI_ADDR_WIDTH ,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_M_AXI_MAX_BURST_LEN => C_M_AXI_MAX_BURST_LEN ,
C_INCLUDE_DRE => C_INCLUDE_DRE ,
C_USE_DATAMOVER_LITE => C_USE_DATAMOVER_LITE ,
C_READ_ADDR_PIPE_DEPTH => C_READ_ADDR_PIPE_DEPTH ,
C_WRITE_ADDR_PIPE_DEPTH => C_WRITE_ADDR_PIPE_DEPTH ,
C_INCLUDE_SF => C_INCLUDE_SF ,
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_SOFT_RST_TIME_CLKS => SOFT_RST_TIME_CLKS ,
C_FAMILY => C_FAMILY
)
port map (
-- Primary Clock and Reset
axi_aclk => m_axi_aclk ,
axi_resetn => m_axi_aresetn ,
-- AXI Lite clock and Reset
axi_lite_aclk => s_axi_lite_aclk ,
axi_lite_resetn => s_axi_lite_aresetn ,
-- Interrupt output
cdma_introut => cdma_introut ,
-- Error Discrete output
cdma_error_out => open ,
-- AXI Lite Write Address Channel
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bready => s_axi_lite_bready ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bresp => s_axi_lite_bresp ,
-- AXI Lite Read Address Channel
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_araddr => s_axi_lite_araddr ,
-- AXI Lite Read Data Channel
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- DataMover MMap Read Address Channel
m_axi_arready => m_axi_arready ,
m_axi_arvalid => m_axi_arvalid ,
m_axi_araddr => m_axi_araddr_internal, --m_axi_araddr ,
m_axi_arlen => m_axi_arlen ,
m_axi_arsize => m_axi_arsize ,
m_axi_arburst => m_axi_arburst ,
m_axi_arprot => m_axi_arprot ,
m_axi_arcache => m_axi_arcache ,
-- DataMover MMap Read Data Channel
m_axi_rready => m_axi_rready ,
m_axi_rvalid => m_axi_rvalid ,
m_axi_rdata => m_axi_rdata ,
m_axi_rresp => m_axi_rresp ,
m_axi_rlast => m_axi_rlast ,
-- DataMover Write Address Channel
m_axi_awready => m_axi_awready ,
m_axi_awvalid => m_axi_awvalid ,
m_axi_awaddr => m_axi_awaddr_internal, --m_axi_awaddr ,
m_axi_awlen => m_axi_awlen ,
m_axi_awsize => m_axi_awsize ,
m_axi_awburst => m_axi_awburst ,
m_axi_awprot => m_axi_awprot ,
m_axi_awcache => m_axi_awcache ,
-- DataMover Write Data Channel
m_axi_wready => m_axi_wready ,
m_axi_wvalid => m_axi_wvalid ,
m_axi_wdata => m_axi_wdata ,
m_axi_wstrb => m_axi_wstrb ,
m_axi_wlast => m_axi_wlast ,
-- DataMover Write Response Channel
m_axi_bready => m_axi_bready ,
m_axi_bvalid => m_axi_bvalid ,
m_axi_bresp => m_axi_bresp ,
-- Debug test vector (Xilinx use only)
axi_cdma_tstvec => cdma_tvect_out
);
end generate GEN_SIMPLE_MODE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SG_MODE
--
-- If Generate Description:
-- This IfGen Implements the CDMA with Scatter Gather Mode
--
--
------------------------------------------------------------
GEN_SG_MODE : if (C_INCLUDE_SG = 1) generate
begin
------------------------------------------------------------
-- Instance: I_SG_MODE_WRAP
--
-- Description:
-- Instance for the CDMA Scatter Gather Mode Wrapper
--
------------------------------------------------------------
I_SG_MODE_WRAP : entity axi_cdma_v4_1_14.axi_cdma_sg_wrap
generic map (
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_M_AXI_ADDR_WIDTH => ADDR_WIDTH, --C_M_AXI_ADDR_WIDTH ,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH ,
C_M_AXI_MAX_BURST_LEN => C_M_AXI_MAX_BURST_LEN ,
C_INCLUDE_DRE => C_INCLUDE_DRE ,
C_READ_ADDR_PIPE_DEPTH => C_READ_ADDR_PIPE_DEPTH ,
C_WRITE_ADDR_PIPE_DEPTH => C_WRITE_ADDR_PIPE_DEPTH ,
C_INCLUDE_SF => C_INCLUDE_SF ,
C_SF_FIFO_DEPTH => SF_FIFO_DEPTH ,
C_M_AXI_SG_ADDR_WIDTH => ADDR_WIDTH, --C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION ,
C_SOFT_RST_TIME_CLKS => SOFT_RST_TIME_CLKS ,
C_ACTUAL_ADDR => C_M_AXI_SG_ADDR_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Primary Clock and Reset
axi_aclk => m_axi_aclk ,
axi_resetn => m_axi_aresetn ,
-- AXI Lite clock and Reset
axi_lite_aclk => s_axi_lite_aclk ,
axi_lite_resetn => s_axi_lite_aresetn ,
-- Interrupt output
cdma_introut => cdma_introut ,
-- Error Discrete output
cdma_error_out => open ,
-- AXI Lite Write Address Channel
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bready => s_axi_lite_bready ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bresp => s_axi_lite_bresp ,
-- AXI Lite Read Address Channel
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_araddr => s_axi_lite_araddr ,
-- AXI Lite Read Data Channel
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- DataMover MMap Read Address Channel
m_axi_arready => m_axi_arready ,
m_axi_arvalid => m_axi_arvalid ,
m_axi_araddr => m_axi_araddr_internal, --m_axi_araddr ,
m_axi_arlen => m_axi_arlen ,
m_axi_arsize => m_axi_arsize ,
m_axi_arburst => m_axi_arburst ,
m_axi_arprot => m_axi_arprot ,
m_axi_arcache => m_axi_arcache ,
-- DataMover MMap Read Data Channel
m_axi_rready => m_axi_rready ,
m_axi_rvalid => m_axi_rvalid ,
m_axi_rdata => m_axi_rdata ,
m_axi_rresp => m_axi_rresp ,
m_axi_rlast => m_axi_rlast ,
-- DataMover Write Address Channel
m_axi_awready => m_axi_awready ,
m_axi_awvalid => m_axi_awvalid ,
m_axi_awaddr => m_axi_awaddr_internal, --m_axi_awaddr ,
m_axi_awlen => m_axi_awlen ,
m_axi_awsize => m_axi_awsize ,
m_axi_awburst => m_axi_awburst ,
m_axi_awprot => m_axi_awprot ,
m_axi_awcache => m_axi_awcache ,
-- DataMover Write Data Channel
m_axi_wready => m_axi_wready ,
m_axi_wvalid => m_axi_wvalid ,
m_axi_wdata => m_axi_wdata ,
m_axi_wstrb => m_axi_wstrb ,
m_axi_wlast => m_axi_wlast ,
-- DataMover Write Response Channel
m_axi_bready => m_axi_bready ,
m_axi_bvalid => m_axi_bvalid ,
m_axi_bresp => m_axi_bresp ,
-- Scatter Gather Write Address Channel
m_axi_sg_awready => m_axi_sg_awready ,
m_axi_sg_awvalid => m_axi_sg_awvalid ,
m_axi_sg_awaddr => m_axi_sg_awaddr_internal, --m_axi_sg_awaddr ,
m_axi_sg_awlen => m_axi_sg_awlen ,
m_axi_sg_awsize => m_axi_sg_awsize ,
m_axi_sg_awburst => m_axi_sg_awburst ,
m_axi_sg_awprot => m_axi_sg_awprot ,
m_axi_sg_awcache => m_axi_sg_awcache ,
-- Scatter Gather Write Data Channel
m_axi_sg_wready => m_axi_sg_wready ,
m_axi_sg_wvalid => m_axi_sg_wvalid ,
m_axi_sg_wdata => m_axi_sg_wdata ,
m_axi_sg_wstrb => m_axi_sg_wstrb ,
m_axi_sg_wlast => m_axi_sg_wlast ,
-- Scatter Gather Write Response Channel
m_axi_sg_bready => m_axi_sg_bready ,
m_axi_sg_bvalid => m_axi_sg_bvalid ,
m_axi_sg_bresp => m_axi_sg_bresp ,
-- Scatter Gather Read Address Channel
m_axi_sg_arready => m_axi_sg_arready ,
m_axi_sg_arvalid => m_axi_sg_arvalid ,
m_axi_sg_araddr => m_axi_sg_araddr_internal, --m_axi_sg_araddr ,
m_axi_sg_arlen => m_axi_sg_arlen ,
m_axi_sg_arsize => m_axi_sg_arsize ,
m_axi_sg_arburst => m_axi_sg_arburst ,
m_axi_sg_arprot => m_axi_sg_arprot ,
m_axi_sg_arcache => m_axi_sg_arcache ,
-- Scatter Gather Read Data Channel
m_axi_sg_rready => m_axi_sg_rready ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
m_axi_sg_rdata => m_axi_sg_rdata ,
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rlast => m_axi_sg_rlast ,
-- Debug test vector (Xilinx use only)
axi_cdma_tstvec => cdma_tvect_out
);
m_axi_sg_araddr <= m_axi_sg_araddr_internal (C_M_AXI_ADDR_WIDTH-1 downto 0);
m_axi_sg_awaddr <= m_axi_sg_awaddr_internal (C_M_AXI_ADDR_WIDTH-1 downto 0);
end generate GEN_SG_MODE;
end implementation;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/ip/hdl/vhdl/convolve_kernel_adEe.vhd | 3 | 7926 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity convolve_kernel_adEe_AddSubnS_0 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(63 downto 0);
b: in std_logic_vector(63 downto 0);
s: out std_logic_vector(63 downto 0));
end entity;
architecture behav of convolve_kernel_adEe_AddSubnS_0 is
component convolve_kernel_adEe_AddSubnS_0_fadder is
port (
faa : IN STD_LOGIC_VECTOR (22-1 downto 0);
fab : IN STD_LOGIC_VECTOR (22-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (22-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component convolve_kernel_adEe_AddSubnS_0_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (20-1 downto 0);
fab : IN STD_LOGIC_VECTOR (20-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (20-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(63 downto 0);
signal b_reg : std_logic_vector(63 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(21 downto 0);
signal b0_cb : std_logic_vector(21 downto 0);
signal a1_cb : std_logic_vector(43 downto 22);
signal b1_cb : std_logic_vector(43 downto 22);
signal a2_cb : std_logic_vector(63 downto 44);
signal b2_cb : std_logic_vector(63 downto 44);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(21 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
type ramtypei1 is array (1 downto 0) of std_logic_vector(19 downto 0);
signal a2_cb_regi2 : ramtypei1;
signal b2_cb_regi2 : ramtypei1;
-- wires for each full adder sum
signal fas : std_logic_vector(63 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout2_co2 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
signal faccout1_co1_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo1 is array (1 downto 0) of std_logic_vector(21 downto 0);
signal s0_ca_rego0 : ramtypeo1;
type ramtypeo0 is array (0 downto 0) of std_logic_vector(21 downto 0);
signal s1_ca_rego1 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(63 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= std_logic_vector(resize(unsigned(a), 64));
b_reg <= std_logic_vector(resize(unsigned(b), 64));
-- small adder input assigments
a0_cb <= a_reg(21 downto 0);
b0_cb <= b_reg(21 downto 0);
a1_cb <= a_reg(43 downto 22);
b1_cb <= b_reg(43 downto 22);
a2_cb <= a_reg(63 downto 44);
b2_cb <= b_reg(63 downto 44);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
a2_cb_regi2 (0) <= a2_cb;
b2_cb_regi2 (0) <= b2_cb;
a2_cb_regi2 (1) <= a2_cb_regi2 (0);
b2_cb_regi2 (1) <= b2_cb_regi2 (0);
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
end if;
end if;
end process;
-- small adder generation
u0 : convolve_kernel_adEe_AddSubnS_0_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(21 downto 0),
facout => faccout0_co0);
u1 : convolve_kernel_adEe_AddSubnS_0_fadder
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(43 downto 22),
facout => faccout1_co1);
u2 : convolve_kernel_adEe_AddSubnS_0_fadder_f
port map
(faa => a2_cb_regi2(1),
fab => b2_cb_regi2(1),
facin => faccout1_co1_reg,
fas => fas(63 downto 44),
facout => faccout2_co2);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(21 downto 0);
s1_ca_rego1 (0) <= fas(43 downto 22);
s0_ca_rego0 (1) <= s0_ca_rego0 (0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(21 downto 0) <= s0_ca_rego0(1);
s_tmp(43 downto 22) <= s1_ca_rego1(0);
s_tmp(63 downto 44) <= fas(63 downto 44);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel_adEe_AddSubnS_0_fadder is
generic(N : natural :=22);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of convolve_kernel_adEe_AddSubnS_0_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel_adEe_AddSubnS_0_fadder_f is
generic(N : natural :=20);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of convolve_kernel_adEe_AddSubnS_0_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity convolve_kernel_adEe is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of convolve_kernel_adEe is
component convolve_kernel_adEe_AddSubnS_0 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
convolve_kernel_adEe_AddSubnS_0_U : component convolve_kernel_adEe_AddSubnS_0
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/7cc4809675563003/ip_design_zed_audio_ctrl_0_0_sim_netlist.vhdl | 1 | 177327 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:31 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_zed_audio_ctrl_0_0_sim_netlist.vhdl
-- Design : ip_design_zed_audio_ctrl_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
port (
\DataTx_R_reg[0]\ : out STD_LOGIC;
\DataTx_R_reg[0]_0\ : out STD_LOGIC;
\DataTx_R_reg[0]_1\ : out STD_LOGIC;
\DataTx_R_reg[0]_2\ : out STD_LOGIC;
\DataTx_R_reg[0]_3\ : out STD_LOGIC;
\DataTx_R_reg[0]_4\ : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DataTx_L_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
data_rdy_bit_reg_0 : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_bvalid_i_reg : out STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
s_axi_bvalid_i_reg_0 : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_WVALID_0 : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC;
data_rdy_bit : in STD_LOGIC;
\DataTx_R_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataTx_L_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataRx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
s_axi_rvalid_i_reg_0 : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
s_axi_bvalid_i_reg_1 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \^datatx_r_reg[0]\ : STD_LOGIC;
signal \^datatx_r_reg[0]_0\ : STD_LOGIC;
signal \^datatx_r_reg[0]_1\ : STD_LOGIC;
signal \^datatx_r_reg[0]_2\ : STD_LOGIC;
signal \^datatx_r_reg[0]_3\ : STD_LOGIC;
signal \^datatx_r_reg[0]_4\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0\ : STD_LOGIC;
signal S_AXI_ARREADY_INST_0_i_1_n_0 : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal ce_expnd_i_4 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal s_axi_bvalid_i0 : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[0]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[10]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[11]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[12]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[13]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[14]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[15]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[16]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[17]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[18]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[19]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[20]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[21]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[22]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[23]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[23]_i_3_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[23]_i_4_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[2]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[3]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[5]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[6]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[7]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[8]_i_2_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[9]_i_2_n_0\ : STD_LOGIC;
signal s_axi_rvalid_i0 : STD_LOGIC;
signal start : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of S_AXI_ARREADY_INST_0 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of S_AXI_AWREADY_INST_0 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of data_rdy_bit_i_2 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of s_axi_bvalid_i_i_2 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axi_rdata_i[0]_i_4\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \s_axi_rdata_i[23]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axi_rdata_i[23]_i_3\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of s_axi_rvalid_i_i_2 : label is "soft_lutpair0";
begin
\DataTx_R_reg[0]\ <= \^datatx_r_reg[0]\;
\DataTx_R_reg[0]_0\ <= \^datatx_r_reg[0]_0\;
\DataTx_R_reg[0]_1\ <= \^datatx_r_reg[0]_1\;
\DataTx_R_reg[0]_2\ <= \^datatx_r_reg[0]_2\;
\DataTx_R_reg[0]_3\ <= \^datatx_r_reg[0]_3\;
\DataTx_R_reg[0]_4\ <= \^datatx_r_reg[0]_4\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFFFFFF02020202"
)
port map (
I0 => S_AXI_ARVALID,
I1 => Q(0),
I2 => Q(1),
I3 => S_AXI_AWVALID,
I4 => S_AXI_WVALID,
I5 => \^datatx_r_reg[0]_4\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^datatx_r_reg[0]_4\,
R => '0'
);
\DataTx_L[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \^datatx_r_reg[0]_0\,
I1 => \^datatx_r_reg[0]_1\,
I2 => \^datatx_r_reg[0]_4\,
I3 => \^datatx_r_reg[0]_2\,
I4 => \^datatx_r_reg[0]_3\,
I5 => \^datatx_r_reg[0]\,
O => \DataTx_L_reg[0]\(0)
);
\DataTx_R[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \^datatx_r_reg[0]_1\,
I1 => \^datatx_r_reg[0]_0\,
I2 => \^datatx_r_reg[0]_4\,
I3 => \^datatx_r_reg[0]_2\,
I4 => \^datatx_r_reg[0]_3\,
I5 => \^datatx_r_reg[0]\,
O => E(0)
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202020202FF02"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(0),
I2 => S_AXI_ARADDR(1),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(0),
I5 => S_AXI_AWADDR(1),
O => ce_expnd_i_4
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_4,
Q => \^datatx_r_reg[0]_3\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080808FF080808"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(0),
I2 => S_AXI_ARADDR(1),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(0),
I5 => S_AXI_AWADDR(1),
O => ce_expnd_i_3
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_3,
Q => \^datatx_r_reg[0]_2\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080808FF080808"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(1),
I2 => S_AXI_ARADDR(0),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(1),
I5 => S_AXI_AWADDR(0),
O => ce_expnd_i_2
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_2,
Q => \^datatx_r_reg[0]_1\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\,
I1 => S_AXI_ARADDR(0),
I2 => S_AXI_ARADDR(1),
I3 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\,
I4 => S_AXI_AWADDR(0),
I5 => S_AXI_AWADDR(1),
O => ce_expnd_i_1
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => S_AXI_ARVALID,
I1 => Q(0),
I2 => Q(1),
I3 => S_AXI_ARADDR(2),
O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2_n_0\
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => S_AXI_ARVALID,
I1 => S_AXI_WVALID,
I2 => S_AXI_AWVALID,
I3 => Q(1),
I4 => Q(0),
I5 => S_AXI_AWADDR(2),
O => \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_3_n_0\
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_1,
Q => \^datatx_r_reg[0]_0\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FD"
)
port map (
I0 => S_AXI_ARESETN,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
I2 => S_AXI_ARREADY_INST_0_i_1_n_0,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"03020202"
)
port map (
I0 => S_AXI_ARVALID,
I1 => Q(0),
I2 => Q(1),
I3 => S_AXI_AWVALID,
I4 => S_AXI_WVALID,
O => start
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEAA"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0\,
I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0\,
I2 => S_AXI_AWADDR(1),
I3 => S_AXI_AWADDR(2),
I4 => S_AXI_AWADDR(0),
O => ce_expnd_i_0
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000400"
)
port map (
I0 => S_AXI_ARADDR(0),
I1 => S_AXI_ARADDR(2),
I2 => S_AXI_ARADDR(1),
I3 => S_AXI_ARVALID,
I4 => Q(0),
I5 => Q(1),
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_4_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00001000"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => S_AXI_AWVALID,
I3 => S_AXI_WVALID,
I4 => S_AXI_ARVALID,
O => \GEN_BKEND_CE_REGISTERS[4].ce_out_i[4]_i_5_n_0\
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => start,
D => ce_expnd_i_0,
Q => \^datatx_r_reg[0]\,
R => cs_ce_clr
);
S_AXI_ARREADY_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"F8"
)
port map (
I0 => \^datatx_r_reg[0]_4\,
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => S_AXI_ARREADY
);
S_AXI_ARREADY_INST_0_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^datatx_r_reg[0]\,
I1 => \^datatx_r_reg[0]_3\,
I2 => \^datatx_r_reg[0]_2\,
I3 => \^datatx_r_reg[0]_0\,
I4 => \^datatx_r_reg[0]_1\,
O => S_AXI_ARREADY_INST_0_i_1_n_0
);
S_AXI_AWREADY_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => \^datatx_r_reg[0]_4\,
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => S_AXI_AWREADY
);
data_rdy_bit_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^datatx_r_reg[0]\,
I1 => \^datatx_r_reg[0]_3\,
I2 => \^datatx_r_reg[0]_2\,
I3 => \^datatx_r_reg[0]_4\,
O => data_rdy_bit_reg_0
);
data_rdy_bit_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFEFFFF"
)
port map (
I0 => \^datatx_r_reg[0]_3\,
I1 => \^datatx_r_reg[0]_2\,
I2 => \^datatx_r_reg[0]_1\,
I3 => \^datatx_r_reg[0]_0\,
I4 => \^datatx_r_reg[0]\,
I5 => \^datatx_r_reg[0]_4\,
O => data_rdy_bit_reg
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => s_axi_bvalid_i0,
I1 => S_AXI_BREADY,
I2 => s_axi_bvalid_i_reg_1,
O => s_axi_bvalid_i_reg
);
s_axi_bvalid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"0000AE00"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \^datatx_r_reg[0]_4\,
I3 => Q(1),
I4 => Q(0),
O => s_axi_bvalid_i0
);
\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFAAEAAAEAAAEAAA"
)
port map (
I0 => \s_axi_rdata_i[0]_i_2_n_0\,
I1 => data_rdy_bit,
I2 => \^datatx_r_reg[0]\,
I3 => \s_axi_rdata_i[0]_i_3_n_0\,
I4 => \^datatx_r_reg[0]_0\,
I5 => \DataTx_R_reg[31]\(0),
O => \s_axi_rdata_i_reg[31]\(0)
);
\s_axi_rdata_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \s_axi_rdata_i[0]_i_4_n_0\,
I1 => \DataTx_L_reg[31]\(0),
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(0),
I4 => \DataRx_L_reg[23]\(0),
I5 => \s_axi_rdata_i[23]_i_2_n_0\,
O => \s_axi_rdata_i[0]_i_2_n_0\
);
\s_axi_rdata_i[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^datatx_r_reg[0]_4\,
I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
O => \s_axi_rdata_i[0]_i_3_n_0\
);
\s_axi_rdata_i[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I1 => \^datatx_r_reg[0]_4\,
I2 => \^datatx_r_reg[0]_1\,
O => \s_axi_rdata_i[0]_i_4_n_0\
);
\s_axi_rdata_i[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(10),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(10),
I4 => \s_axi_rdata_i[10]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(10)
);
\s_axi_rdata_i[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(10),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(10),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[10]_i_2_n_0\
);
\s_axi_rdata_i[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(11),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(11),
I4 => \s_axi_rdata_i[11]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(11)
);
\s_axi_rdata_i[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(11),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(11),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[11]_i_2_n_0\
);
\s_axi_rdata_i[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(12),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(12),
I4 => \s_axi_rdata_i[12]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(12)
);
\s_axi_rdata_i[12]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(12),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(12),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[12]_i_2_n_0\
);
\s_axi_rdata_i[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(13),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(13),
I4 => \s_axi_rdata_i[13]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(13)
);
\s_axi_rdata_i[13]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(13),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(13),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[13]_i_2_n_0\
);
\s_axi_rdata_i[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(14),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(14),
I4 => \s_axi_rdata_i[14]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(14)
);
\s_axi_rdata_i[14]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(14),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(14),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[14]_i_2_n_0\
);
\s_axi_rdata_i[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(15),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(15),
I4 => \s_axi_rdata_i[15]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(15)
);
\s_axi_rdata_i[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(15),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(15),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[15]_i_2_n_0\
);
\s_axi_rdata_i[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(16),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(16),
I4 => \s_axi_rdata_i[16]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(16)
);
\s_axi_rdata_i[16]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(16),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(16),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[16]_i_2_n_0\
);
\s_axi_rdata_i[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(17),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(17),
I4 => \s_axi_rdata_i[17]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(17)
);
\s_axi_rdata_i[17]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(17),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(17),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[17]_i_2_n_0\
);
\s_axi_rdata_i[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(18),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(18),
I4 => \s_axi_rdata_i[18]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(18)
);
\s_axi_rdata_i[18]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(18),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(18),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[18]_i_2_n_0\
);
\s_axi_rdata_i[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(19),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(19),
I4 => \s_axi_rdata_i[19]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(19)
);
\s_axi_rdata_i[19]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(19),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(19),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[19]_i_2_n_0\
);
\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(1),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(1),
I4 => \s_axi_rdata_i[1]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(1)
);
\s_axi_rdata_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(1),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(1),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[1]_i_2_n_0\
);
\s_axi_rdata_i[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(20),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(20),
I4 => \s_axi_rdata_i[20]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(20)
);
\s_axi_rdata_i[20]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(20),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(20),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[20]_i_2_n_0\
);
\s_axi_rdata_i[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(21),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(21),
I4 => \s_axi_rdata_i[21]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(21)
);
\s_axi_rdata_i[21]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(21),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(21),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[21]_i_2_n_0\
);
\s_axi_rdata_i[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(22),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(22),
I4 => \s_axi_rdata_i[22]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(22)
);
\s_axi_rdata_i[22]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(22),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(22),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[22]_i_2_n_0\
);
\s_axi_rdata_i[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(23),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(23),
I4 => \s_axi_rdata_i[23]_i_4_n_0\,
O => \s_axi_rdata_i_reg[31]\(23)
);
\s_axi_rdata_i[23]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I1 => \^datatx_r_reg[0]_4\,
I2 => \^datatx_r_reg[0]_3\,
O => \s_axi_rdata_i[23]_i_2_n_0\
);
\s_axi_rdata_i[23]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I1 => \^datatx_r_reg[0]_4\,
I2 => \^datatx_r_reg[0]_2\,
O => \s_axi_rdata_i[23]_i_3_n_0\
);
\s_axi_rdata_i[23]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(23),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(23),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[23]_i_4_n_0\
);
\s_axi_rdata_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(24),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(24),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(24)
);
\s_axi_rdata_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(25),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(25),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(25)
);
\s_axi_rdata_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(26),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(26),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(26)
);
\s_axi_rdata_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(27),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(27),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(27)
);
\s_axi_rdata_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(28),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(28),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(28)
);
\s_axi_rdata_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(29),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(29),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(29)
);
\s_axi_rdata_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(2),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(2),
I4 => \s_axi_rdata_i[2]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(2)
);
\s_axi_rdata_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(2),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(2),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[2]_i_2_n_0\
);
\s_axi_rdata_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(30),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(30),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(30)
);
\s_axi_rdata_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(31),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(31),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i_reg[31]\(31)
);
\s_axi_rdata_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(3),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(3),
I4 => \s_axi_rdata_i[3]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(3)
);
\s_axi_rdata_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(3),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(3),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[3]_i_2_n_0\
);
\s_axi_rdata_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(4),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(4),
I4 => \s_axi_rdata_i[4]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(4)
);
\s_axi_rdata_i[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(4),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(4),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[4]_i_2_n_0\
);
\s_axi_rdata_i[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(5),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(5),
I4 => \s_axi_rdata_i[5]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(5)
);
\s_axi_rdata_i[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(5),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(5),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[5]_i_2_n_0\
);
\s_axi_rdata_i[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(6),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(6),
I4 => \s_axi_rdata_i[6]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(6)
);
\s_axi_rdata_i[6]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(6),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(6),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[6]_i_2_n_0\
);
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(7),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(7),
I4 => \s_axi_rdata_i[7]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(7)
);
\s_axi_rdata_i[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(7),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(7),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[7]_i_2_n_0\
);
\s_axi_rdata_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(8),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(8),
I4 => \s_axi_rdata_i[8]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(8)
);
\s_axi_rdata_i[8]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(8),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(8),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[8]_i_2_n_0\
);
\s_axi_rdata_i[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFF888"
)
port map (
I0 => \DataRx_L_reg[23]\(9),
I1 => \s_axi_rdata_i[23]_i_2_n_0\,
I2 => \s_axi_rdata_i[23]_i_3_n_0\,
I3 => \DataRx_R_reg[23]\(9),
I4 => \s_axi_rdata_i[9]_i_2_n_0\,
O => \s_axi_rdata_i_reg[31]\(9)
);
\s_axi_rdata_i[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F800000088000000"
)
port map (
I0 => \DataTx_L_reg[31]\(9),
I1 => \^datatx_r_reg[0]_1\,
I2 => \DataTx_R_reg[31]\(9),
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I4 => \^datatx_r_reg[0]_4\,
I5 => \^datatx_r_reg[0]_0\,
O => \s_axi_rdata_i[9]_i_2_n_0\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => s_axi_rvalid_i0,
I1 => S_AXI_RREADY,
I2 => s_axi_rvalid_i_reg_0,
O => s_axi_rvalid_i_reg
);
s_axi_rvalid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"0000EA00"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
I1 => S_AXI_ARREADY_INST_0_i_1_n_0,
I2 => \^datatx_r_reg[0]_4\,
I3 => Q(0),
I4 => Q(1),
O => s_axi_rvalid_i0
);
\state[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF4"
)
port map (
I0 => Q(1),
I1 => S_AXI_ARVALID,
I2 => s_axi_bvalid_i0,
I3 => s_axi_bvalid_i_reg_0,
O => D(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF4454"
)
port map (
I0 => Q(0),
I1 => Q(1),
I2 => S_AXI_WVALID_0,
I3 => S_AXI_ARVALID,
I4 => \state_reg[1]\,
I5 => s_axi_rvalid_i0,
O => D(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser is
port (
lrclk_d1 : out STD_LOGIC;
sclk_d1 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\rdata_reg_reg[23]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\bit_cntr_reg[4]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sdata_reg_reg : out STD_LOGIC;
\FSM_onehot_iis_state_reg[0]\ : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
\FSM_onehot_iis_state_reg[0]_0\ : out STD_LOGIC;
\DataRx_L_reg[23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_R_reg[23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
data_rdy_bit : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
SDATA_I : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser is
signal \^datarx_l_reg[23]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \^datarx_r_reg[23]\ : STD_LOGIC_VECTOR ( 23 downto 0 );
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \FSM_sequential_iis_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_3_n_0\ : STD_LOGIC;
signal \FSM_sequential_iis_state[2]_i_4_n_0\ : STD_LOGIC;
signal \bit_cntr[4]_i_1_n_0\ : STD_LOGIC;
signal \bit_cntr_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal bit_rdy : STD_LOGIC;
signal data_rdy_bit_i_4_n_0 : STD_LOGIC;
signal eqOp : STD_LOGIC;
signal iis_state : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of iis_state : signal is "yes";
signal ldata_reg : STD_LOGIC;
signal ldata_reg0 : STD_LOGIC;
signal \^lrclk_d1\ : STD_LOGIC;
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal rdata_reg0 : STD_LOGIC;
signal \^sclk_d1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \DataRx_L[23]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \FSM_onehot_iis_state[4]_i_5\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \FSM_sequential_iis_state[2]_i_4\ : label is "soft_lutpair8";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_sequential_iis_state_reg[0]\ : label is "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_iis_state_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_sequential_iis_state_reg[1]\ : label is "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110";
attribute KEEP of \FSM_sequential_iis_state_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_sequential_iis_state_reg[2]\ : label is "reset:000,wait_left:001,skip_left:010,read_left:011,wait_right:100,skip_right:101,read_right:110";
attribute KEEP of \FSM_sequential_iis_state_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \bit_cntr[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \bit_cntr[1]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \bit_cntr[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \bit_cntr[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \bit_cntr[4]_i_2__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \bit_cntr[4]_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of sdata_reg_i_2 : label is "soft_lutpair10";
begin
\DataRx_L_reg[23]\(23 downto 0) <= \^datarx_l_reg[23]\(23 downto 0);
\DataRx_R_reg[23]\(23 downto 0) <= \^datarx_r_reg[23]\(23 downto 0);
E(0) <= \^e\(0);
lrclk_d1 <= \^lrclk_d1\;
sclk_d1 <= \^sclk_d1\;
\DataRx_L[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => eqOp,
I1 => iis_state(2),
I2 => iis_state(1),
I3 => iis_state(0),
O => \^e\(0)
);
\DataRx_L[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000020"
)
port map (
I0 => \bit_cntr_reg__0\(3),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(4),
I3 => \bit_cntr_reg__0\(1),
I4 => \bit_cntr_reg__0\(2),
O => eqOp
);
\FSM_onehot_iis_state[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^lrclk_d1\,
I1 => Q(1),
I2 => \out\(1),
O => \FSM_onehot_iis_state_reg[0]_0\
);
\FSM_onehot_iis_state[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => \^lrclk_d1\,
I1 => Q(1),
I2 => \out\(0),
O => \FSM_onehot_iis_state_reg[0]\
);
\FSM_sequential_iis_state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"75777F7745444044"
)
port map (
I0 => iis_state(0),
I1 => \FSM_sequential_iis_state[2]_i_2_n_0\,
I2 => iis_state(1),
I3 => iis_state(2),
I4 => \FSM_sequential_iis_state[2]_i_3_n_0\,
I5 => iis_state(0),
O => \FSM_sequential_iis_state[0]_i_1_n_0\
);
\FSM_sequential_iis_state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3A7B3F7B0A480048"
)
port map (
I0 => iis_state(0),
I1 => \FSM_sequential_iis_state[2]_i_2_n_0\,
I2 => iis_state(1),
I3 => iis_state(2),
I4 => \FSM_sequential_iis_state[2]_i_3_n_0\,
I5 => iis_state(1),
O => \FSM_sequential_iis_state[1]_i_1_n_0\
);
\FSM_sequential_iis_state[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FB33FB30F800080"
)
port map (
I0 => iis_state(0),
I1 => \FSM_sequential_iis_state[2]_i_2_n_0\,
I2 => iis_state(1),
I3 => iis_state(2),
I4 => \FSM_sequential_iis_state[2]_i_3_n_0\,
I5 => iis_state(2),
O => \FSM_sequential_iis_state[2]_i_1_n_0\
);
\FSM_sequential_iis_state[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFA33FF000A330F"
)
port map (
I0 => bit_rdy,
I1 => \FSM_sequential_iis_state[2]_i_4_n_0\,
I2 => iis_state(2),
I3 => iis_state(0),
I4 => iis_state(1),
I5 => eqOp,
O => \FSM_sequential_iis_state[2]_i_2_n_0\
);
\FSM_sequential_iis_state[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22A222A2EEAE22A2"
)
port map (
I0 => bit_rdy,
I1 => iis_state(2),
I2 => iis_state(0),
I3 => iis_state(1),
I4 => Q(1),
I5 => \^lrclk_d1\,
O => \FSM_sequential_iis_state[2]_i_3_n_0\
);
\FSM_sequential_iis_state[2]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => Q(1),
I1 => \^lrclk_d1\,
O => \FSM_sequential_iis_state[2]_i_4_n_0\
);
\FSM_sequential_iis_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_sequential_iis_state[0]_i_1_n_0\,
Q => iis_state(0),
R => '0'
);
\FSM_sequential_iis_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_sequential_iis_state[1]_i_1_n_0\,
Q => iis_state(1),
R => '0'
);
\FSM_sequential_iis_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_sequential_iis_state[2]_i_1_n_0\,
Q => iis_state(2),
R => '0'
);
\bit_cntr[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bit_cntr_reg__0\(0),
O => \plusOp__1\(0)
);
\bit_cntr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bit_cntr_reg__0\(0),
I1 => \bit_cntr_reg__0\(1),
O => \plusOp__1\(1)
);
\bit_cntr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \bit_cntr_reg__0\(1),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(2),
O => \plusOp__1\(2)
);
\bit_cntr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6CCC"
)
port map (
I0 => \bit_cntr_reg__0\(1),
I1 => \bit_cntr_reg__0\(3),
I2 => \bit_cntr_reg__0\(0),
I3 => \bit_cntr_reg__0\(2),
O => \plusOp__1\(3)
);
\bit_cntr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D7"
)
port map (
I0 => iis_state(1),
I1 => iis_state(0),
I2 => iis_state(2),
O => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Q(0),
I1 => \^sclk_d1\,
O => bit_rdy
);
\bit_cntr[4]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^sclk_d1\,
I1 => Q(0),
O => \bit_cntr_reg[4]_0\(0)
);
\bit_cntr[4]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"78F0F0F0"
)
port map (
I0 => \bit_cntr_reg__0\(3),
I1 => \bit_cntr_reg__0\(2),
I2 => \bit_cntr_reg__0\(4),
I3 => \bit_cntr_reg__0\(1),
I4 => \bit_cntr_reg__0\(0),
O => \plusOp__1\(4)
);
\bit_cntr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(0),
Q => \bit_cntr_reg__0\(0),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(1),
Q => \bit_cntr_reg__0\(1),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(2),
Q => \bit_cntr_reg__0\(2),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(3),
Q => \bit_cntr_reg__0\(3),
R => \bit_cntr[4]_i_1_n_0\
);
\bit_cntr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => bit_rdy,
D => \plusOp__1\(4),
Q => \bit_cntr_reg__0\(4),
R => \bit_cntr[4]_i_1_n_0\
);
data_rdy_bit_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CC00EA0000000000"
)
port map (
I0 => data_rdy_bit,
I1 => \^e\(0),
I2 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
I4 => data_rdy_bit_i_4_n_0,
I5 => S_AXI_ARESETN,
O => data_rdy_bit_reg
);
data_rdy_bit_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000090000000"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I2 => eqOp,
I3 => iis_state(2),
I4 => iis_state(1),
I5 => iis_state(0),
O => data_rdy_bit_i_4_n_0
);
\ldata_reg[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => iis_state(1),
I1 => iis_state(0),
I2 => iis_state(2),
O => ldata_reg
);
\ldata_reg[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => iis_state(2),
I1 => iis_state(0),
I2 => iis_state(1),
I3 => Q(0),
I4 => \^sclk_d1\,
O => ldata_reg0
);
\ldata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => SDATA_I,
Q => \^datarx_l_reg[23]\(0),
R => ldata_reg
);
\ldata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(9),
Q => \^datarx_l_reg[23]\(10),
R => ldata_reg
);
\ldata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(10),
Q => \^datarx_l_reg[23]\(11),
R => ldata_reg
);
\ldata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(11),
Q => \^datarx_l_reg[23]\(12),
R => ldata_reg
);
\ldata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(12),
Q => \^datarx_l_reg[23]\(13),
R => ldata_reg
);
\ldata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(13),
Q => \^datarx_l_reg[23]\(14),
R => ldata_reg
);
\ldata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(14),
Q => \^datarx_l_reg[23]\(15),
R => ldata_reg
);
\ldata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(15),
Q => \^datarx_l_reg[23]\(16),
R => ldata_reg
);
\ldata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(16),
Q => \^datarx_l_reg[23]\(17),
R => ldata_reg
);
\ldata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(17),
Q => \^datarx_l_reg[23]\(18),
R => ldata_reg
);
\ldata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(18),
Q => \^datarx_l_reg[23]\(19),
R => ldata_reg
);
\ldata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(0),
Q => \^datarx_l_reg[23]\(1),
R => ldata_reg
);
\ldata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(19),
Q => \^datarx_l_reg[23]\(20),
R => ldata_reg
);
\ldata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(20),
Q => \^datarx_l_reg[23]\(21),
R => ldata_reg
);
\ldata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(21),
Q => \^datarx_l_reg[23]\(22),
R => ldata_reg
);
\ldata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(22),
Q => \^datarx_l_reg[23]\(23),
R => ldata_reg
);
\ldata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(1),
Q => \^datarx_l_reg[23]\(2),
R => ldata_reg
);
\ldata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(2),
Q => \^datarx_l_reg[23]\(3),
R => ldata_reg
);
\ldata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(3),
Q => \^datarx_l_reg[23]\(4),
R => ldata_reg
);
\ldata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(4),
Q => \^datarx_l_reg[23]\(5),
R => ldata_reg
);
\ldata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(5),
Q => \^datarx_l_reg[23]\(6),
R => ldata_reg
);
\ldata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(6),
Q => \^datarx_l_reg[23]\(7),
R => ldata_reg
);
\ldata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(7),
Q => \^datarx_l_reg[23]\(8),
R => ldata_reg
);
\ldata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => ldata_reg0,
D => \^datarx_l_reg[23]\(8),
Q => \^datarx_l_reg[23]\(9),
R => ldata_reg
);
lrclk_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => Q(1),
Q => \^lrclk_d1\,
R => '0'
);
\rdata_reg[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00004000"
)
port map (
I0 => iis_state(0),
I1 => iis_state(1),
I2 => iis_state(2),
I3 => Q(0),
I4 => \^sclk_d1\,
O => rdata_reg0
);
\rdata_reg[23]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040FF4040404040"
)
port map (
I0 => Q(0),
I1 => \^sclk_d1\,
I2 => \out\(2),
I3 => \out\(0),
I4 => Q(1),
I5 => \^lrclk_d1\,
O => \rdata_reg_reg[23]_0\(0)
);
\rdata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => SDATA_I,
Q => \^datarx_r_reg[23]\(0),
R => ldata_reg
);
\rdata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(9),
Q => \^datarx_r_reg[23]\(10),
R => ldata_reg
);
\rdata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(10),
Q => \^datarx_r_reg[23]\(11),
R => ldata_reg
);
\rdata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(11),
Q => \^datarx_r_reg[23]\(12),
R => ldata_reg
);
\rdata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(12),
Q => \^datarx_r_reg[23]\(13),
R => ldata_reg
);
\rdata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(13),
Q => \^datarx_r_reg[23]\(14),
R => ldata_reg
);
\rdata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(14),
Q => \^datarx_r_reg[23]\(15),
R => ldata_reg
);
\rdata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(15),
Q => \^datarx_r_reg[23]\(16),
R => ldata_reg
);
\rdata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(16),
Q => \^datarx_r_reg[23]\(17),
R => ldata_reg
);
\rdata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(17),
Q => \^datarx_r_reg[23]\(18),
R => ldata_reg
);
\rdata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(18),
Q => \^datarx_r_reg[23]\(19),
R => ldata_reg
);
\rdata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(0),
Q => \^datarx_r_reg[23]\(1),
R => ldata_reg
);
\rdata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(19),
Q => \^datarx_r_reg[23]\(20),
R => ldata_reg
);
\rdata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(20),
Q => \^datarx_r_reg[23]\(21),
R => ldata_reg
);
\rdata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(21),
Q => \^datarx_r_reg[23]\(22),
R => ldata_reg
);
\rdata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(22),
Q => \^datarx_r_reg[23]\(23),
R => ldata_reg
);
\rdata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(1),
Q => \^datarx_r_reg[23]\(2),
R => ldata_reg
);
\rdata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(2),
Q => \^datarx_r_reg[23]\(3),
R => ldata_reg
);
\rdata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(3),
Q => \^datarx_r_reg[23]\(4),
R => ldata_reg
);
\rdata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(4),
Q => \^datarx_r_reg[23]\(5),
R => ldata_reg
);
\rdata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(5),
Q => \^datarx_r_reg[23]\(6),
R => ldata_reg
);
\rdata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(6),
Q => \^datarx_r_reg[23]\(7),
R => ldata_reg
);
\rdata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(7),
Q => \^datarx_r_reg[23]\(8),
R => ldata_reg
);
\rdata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => rdata_reg0,
D => \^datarx_r_reg[23]\(8),
Q => \^datarx_r_reg[23]\(9),
R => ldata_reg
);
sclk_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => Q(0),
Q => \^sclk_d1\,
R => '0'
);
sdata_reg_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => Q(0),
I1 => \^sclk_d1\,
O => sdata_reg_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser is
port (
SDATA_O : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
sclk_d1 : in STD_LOGIC;
lrclk_d1 : in STD_LOGIC;
\DataTx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataTx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\clk_cntr_reg[4]\ : in STD_LOGIC;
lrclk_d1_reg : in STD_LOGIC;
lrclk_d1_reg_0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
sclk_d1_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser is
signal \FSM_onehot_iis_state[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[3]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[4]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_iis_state[4]_i_2_n_0\ : STD_LOGIC;
signal \^sdata_o\ : STD_LOGIC;
signal \bit_cntr[4]_i_1__0_n_0\ : STD_LOGIC;
signal \bit_cntr_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal eqOp : STD_LOGIC;
signal ldata_reg : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of ldata_reg : signal is "yes";
signal \ldata_reg[0]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[10]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[11]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[13]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[14]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[15]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[17]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[18]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[19]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[1]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[21]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[22]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[23]_i_1__0_n_0\ : STD_LOGIC;
signal \ldata_reg[23]_i_2__0_n_0\ : STD_LOGIC;
signal \ldata_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[3]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[5]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[7]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[10]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[11]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[12]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[13]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[14]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[15]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[16]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[17]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[18]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[19]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[20]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[21]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[22]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[2]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[3]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[4]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[5]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[6]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[7]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[8]\ : STD_LOGIC;
signal \ldata_reg_reg_n_0_[9]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP of \^out\ : signal is "yes";
signal p_0_in2_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in2_in : signal is "yes";
signal p_1_in : STD_LOGIC_VECTOR ( 23 downto 0 );
signal p_2_in : STD_LOGIC;
signal \plusOp__2\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \rdata_reg_reg_n_0_[0]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[10]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[11]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[12]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[13]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[14]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[15]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[16]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[17]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[18]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[19]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[1]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[20]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[21]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[22]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[23]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[2]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[3]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[4]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[5]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[6]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[7]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[8]\ : STD_LOGIC;
signal \rdata_reg_reg_n_0_[9]\ : STD_LOGIC;
signal sdata_reg_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_onehot_iis_state[4]_i_4\ : label is "soft_lutpair11";
attribute FSM_ENCODED_STATES : string;
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[0]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP : string;
attribute KEEP of \FSM_onehot_iis_state_reg[0]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[1]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[1]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[2]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[2]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[3]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[3]\ : label is "yes";
attribute FSM_ENCODED_STATES of \FSM_onehot_iis_state_reg[4]\ : label is "reset:00001,wait_left:00010,write_left:00100,wait_right:01000,write_right:10000";
attribute KEEP of \FSM_onehot_iis_state_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM of \bit_cntr[0]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \bit_cntr[1]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \bit_cntr[2]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \bit_cntr[3]_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \bit_cntr[4]_i_3__0\ : label is "soft_lutpair11";
begin
SDATA_O <= \^sdata_o\;
\out\(2 downto 0) <= \^out\(2 downto 0);
\FSM_onehot_iis_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAABA"
)
port map (
I0 => ldata_reg,
I1 => p_0_in2_in,
I2 => \^out\(2),
I3 => \^out\(1),
I4 => \^out\(0),
O => \FSM_onehot_iis_state[1]_i_1_n_0\
);
\FSM_onehot_iis_state[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0ACA"
)
port map (
I0 => p_0_in2_in,
I1 => \^out\(0),
I2 => \FSM_onehot_iis_state[4]_i_1_n_0\,
I3 => ldata_reg,
O => \FSM_onehot_iis_state[2]_i_1_n_0\
);
\FSM_onehot_iis_state[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_0_in2_in,
I1 => ldata_reg,
I2 => \^out\(0),
O => \FSM_onehot_iis_state[3]_i_1_n_0\
);
\FSM_onehot_iis_state[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEEFFFFFEEEFFFF"
)
port map (
I0 => ldata_reg,
I1 => lrclk_d1_reg,
I2 => \^out\(2),
I3 => eqOp,
I4 => lrclk_d1_reg_0,
I5 => p_0_in2_in,
O => \FSM_onehot_iis_state[4]_i_1_n_0\
);
\FSM_onehot_iis_state[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => ldata_reg,
I1 => p_0_in2_in,
I2 => \^out\(1),
I3 => \^out\(0),
O => \FSM_onehot_iis_state[4]_i_2_n_0\
);
\FSM_onehot_iis_state[4]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"02000000"
)
port map (
I0 => \bit_cntr_reg__0\(0),
I1 => \bit_cntr_reg__0\(1),
I2 => \bit_cntr_reg__0\(2),
I3 => \bit_cntr_reg__0\(4),
I4 => \bit_cntr_reg__0\(3),
O => eqOp
);
\FSM_onehot_iis_state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => '0',
Q => ldata_reg,
R => '0'
);
\FSM_onehot_iis_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => \FSM_onehot_iis_state[1]_i_1_n_0\,
Q => \^out\(0),
R => '0'
);
\FSM_onehot_iis_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \FSM_onehot_iis_state[2]_i_1_n_0\,
Q => p_0_in2_in,
R => '0'
);
\FSM_onehot_iis_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => \FSM_onehot_iis_state[3]_i_1_n_0\,
Q => \^out\(1),
R => '0'
);
\FSM_onehot_iis_state_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \FSM_onehot_iis_state[4]_i_1_n_0\,
D => \FSM_onehot_iis_state[4]_i_2_n_0\,
Q => \^out\(2),
R => '0'
);
\bit_cntr[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bit_cntr_reg__0\(0),
O => \plusOp__2\(0)
);
\bit_cntr[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bit_cntr_reg__0\(0),
I1 => \bit_cntr_reg__0\(1),
O => \plusOp__2\(1)
);
\bit_cntr[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \bit_cntr_reg__0\(1),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(2),
O => \plusOp__2\(2)
);
\bit_cntr[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \bit_cntr_reg__0\(2),
I1 => \bit_cntr_reg__0\(0),
I2 => \bit_cntr_reg__0\(1),
I3 => \bit_cntr_reg__0\(3),
O => \plusOp__2\(3)
);
\bit_cntr[4]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^out\(2),
I1 => p_0_in2_in,
O => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr[4]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \bit_cntr_reg__0\(3),
I1 => \bit_cntr_reg__0\(1),
I2 => \bit_cntr_reg__0\(0),
I3 => \bit_cntr_reg__0\(2),
I4 => \bit_cntr_reg__0\(4),
O => \plusOp__2\(4)
);
\bit_cntr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(0),
Q => \bit_cntr_reg__0\(0),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(1),
Q => \bit_cntr_reg__0\(1),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(2),
Q => \bit_cntr_reg__0\(2),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(3),
Q => \bit_cntr_reg__0\(3),
R => \bit_cntr[4]_i_1__0_n_0\
);
\bit_cntr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => sclk_d1_reg(0),
D => \plusOp__2\(4),
Q => \bit_cntr_reg__0\(4),
R => \bit_cntr[4]_i_1__0_n_0\
);
\ldata_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \DataTx_L_reg[23]\(0),
I1 => \^out\(0),
I2 => Q(1),
I3 => lrclk_d1,
O => \ldata_reg[0]_i_1_n_0\
);
\ldata_reg[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[9]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(10),
O => \ldata_reg[10]_i_1_n_0\
);
\ldata_reg[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[10]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(11),
O => \ldata_reg[11]_i_1_n_0\
);
\ldata_reg[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[11]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(12),
O => \ldata_reg[12]_i_1_n_0\
);
\ldata_reg[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[12]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(13),
O => \ldata_reg[13]_i_1_n_0\
);
\ldata_reg[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[13]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(14),
O => \ldata_reg[14]_i_1_n_0\
);
\ldata_reg[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[14]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(15),
O => \ldata_reg[15]_i_1_n_0\
);
\ldata_reg[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[15]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(16),
O => \ldata_reg[16]_i_1_n_0\
);
\ldata_reg[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[16]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(17),
O => \ldata_reg[17]_i_1_n_0\
);
\ldata_reg[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[17]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(18),
O => \ldata_reg[18]_i_1_n_0\
);
\ldata_reg[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[18]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(19),
O => \ldata_reg[19]_i_1_n_0\
);
\ldata_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[0]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(1),
O => \ldata_reg[1]_i_1_n_0\
);
\ldata_reg[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[19]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(20),
O => \ldata_reg[20]_i_1_n_0\
);
\ldata_reg[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[20]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(21),
O => \ldata_reg[21]_i_1_n_0\
);
\ldata_reg[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[21]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(22),
O => \ldata_reg[22]_i_1_n_0\
);
\ldata_reg[23]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2020FF2020202020"
)
port map (
I0 => p_0_in2_in,
I1 => Q(0),
I2 => sclk_d1,
I3 => \^out\(0),
I4 => Q(1),
I5 => lrclk_d1,
O => \ldata_reg[23]_i_1__0_n_0\
);
\ldata_reg[23]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[22]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(23),
O => \ldata_reg[23]_i_2__0_n_0\
);
\ldata_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[1]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(2),
O => \ldata_reg[2]_i_1_n_0\
);
\ldata_reg[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[2]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(3),
O => \ldata_reg[3]_i_1_n_0\
);
\ldata_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[3]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(4),
O => \ldata_reg[4]_i_1_n_0\
);
\ldata_reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[4]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(5),
O => \ldata_reg[5]_i_1_n_0\
);
\ldata_reg[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[5]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(6),
O => \ldata_reg[6]_i_1_n_0\
);
\ldata_reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[6]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(7),
O => \ldata_reg[7]_i_1_n_0\
);
\ldata_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[7]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(8),
O => \ldata_reg[8]_i_1_n_0\
);
\ldata_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \ldata_reg_reg_n_0_[8]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_L_reg[23]\(9),
O => \ldata_reg[9]_i_1_n_0\
);
\ldata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[0]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[0]\,
R => ldata_reg
);
\ldata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[10]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[10]\,
R => ldata_reg
);
\ldata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[11]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[11]\,
R => ldata_reg
);
\ldata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[12]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[12]\,
R => ldata_reg
);
\ldata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[13]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[13]\,
R => ldata_reg
);
\ldata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[14]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[14]\,
R => ldata_reg
);
\ldata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[15]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[15]\,
R => ldata_reg
);
\ldata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[16]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[16]\,
R => ldata_reg
);
\ldata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[17]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[17]\,
R => ldata_reg
);
\ldata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[18]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[18]\,
R => ldata_reg
);
\ldata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[19]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[19]\,
R => ldata_reg
);
\ldata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[1]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[1]\,
R => ldata_reg
);
\ldata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[20]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[20]\,
R => ldata_reg
);
\ldata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[21]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[21]\,
R => ldata_reg
);
\ldata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[22]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[22]\,
R => ldata_reg
);
\ldata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[23]_i_2__0_n_0\,
Q => p_2_in,
R => ldata_reg
);
\ldata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[2]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[2]\,
R => ldata_reg
);
\ldata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[3]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[3]\,
R => ldata_reg
);
\ldata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[4]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[4]\,
R => ldata_reg
);
\ldata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[5]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[5]\,
R => ldata_reg
);
\ldata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[6]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[6]\,
R => ldata_reg
);
\ldata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[7]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[7]\,
R => ldata_reg
);
\ldata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[8]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[8]\,
R => ldata_reg
);
\ldata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \ldata_reg[23]_i_1__0_n_0\,
D => \ldata_reg[9]_i_1_n_0\,
Q => \ldata_reg_reg_n_0_[9]\,
R => ldata_reg
);
\rdata_reg[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0800"
)
port map (
I0 => \DataTx_R_reg[23]\(0),
I1 => \^out\(0),
I2 => Q(1),
I3 => lrclk_d1,
O => p_1_in(0)
);
\rdata_reg[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[9]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(10),
O => p_1_in(10)
);
\rdata_reg[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[10]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(11),
O => p_1_in(11)
);
\rdata_reg[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[11]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(12),
O => p_1_in(12)
);
\rdata_reg[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[12]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(13),
O => p_1_in(13)
);
\rdata_reg[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[13]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(14),
O => p_1_in(14)
);
\rdata_reg[15]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[14]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(15),
O => p_1_in(15)
);
\rdata_reg[16]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[15]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(16),
O => p_1_in(16)
);
\rdata_reg[17]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[16]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(17),
O => p_1_in(17)
);
\rdata_reg[18]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[17]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(18),
O => p_1_in(18)
);
\rdata_reg[19]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[18]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(19),
O => p_1_in(19)
);
\rdata_reg[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[0]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(1),
O => p_1_in(1)
);
\rdata_reg[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[19]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(20),
O => p_1_in(20)
);
\rdata_reg[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[20]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(21),
O => p_1_in(21)
);
\rdata_reg[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[21]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(22),
O => p_1_in(22)
);
\rdata_reg[23]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[22]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(23),
O => p_1_in(23)
);
\rdata_reg[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[1]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(2),
O => p_1_in(2)
);
\rdata_reg[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[2]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(3),
O => p_1_in(3)
);
\rdata_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[3]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(4),
O => p_1_in(4)
);
\rdata_reg[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[4]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(5),
O => p_1_in(5)
);
\rdata_reg[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[5]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(6),
O => p_1_in(6)
);
\rdata_reg[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[6]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(7),
O => p_1_in(7)
);
\rdata_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[7]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(8),
O => p_1_in(8)
);
\rdata_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AEAAA2AA"
)
port map (
I0 => \rdata_reg_reg_n_0_[8]\,
I1 => lrclk_d1,
I2 => Q(1),
I3 => \^out\(0),
I4 => \DataTx_R_reg[23]\(9),
O => p_1_in(9)
);
\rdata_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(0),
Q => \rdata_reg_reg_n_0_[0]\,
R => ldata_reg
);
\rdata_reg_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(10),
Q => \rdata_reg_reg_n_0_[10]\,
R => ldata_reg
);
\rdata_reg_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(11),
Q => \rdata_reg_reg_n_0_[11]\,
R => ldata_reg
);
\rdata_reg_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(12),
Q => \rdata_reg_reg_n_0_[12]\,
R => ldata_reg
);
\rdata_reg_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(13),
Q => \rdata_reg_reg_n_0_[13]\,
R => ldata_reg
);
\rdata_reg_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(14),
Q => \rdata_reg_reg_n_0_[14]\,
R => ldata_reg
);
\rdata_reg_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(15),
Q => \rdata_reg_reg_n_0_[15]\,
R => ldata_reg
);
\rdata_reg_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(16),
Q => \rdata_reg_reg_n_0_[16]\,
R => ldata_reg
);
\rdata_reg_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(17),
Q => \rdata_reg_reg_n_0_[17]\,
R => ldata_reg
);
\rdata_reg_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(18),
Q => \rdata_reg_reg_n_0_[18]\,
R => ldata_reg
);
\rdata_reg_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(19),
Q => \rdata_reg_reg_n_0_[19]\,
R => ldata_reg
);
\rdata_reg_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(1),
Q => \rdata_reg_reg_n_0_[1]\,
R => ldata_reg
);
\rdata_reg_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(20),
Q => \rdata_reg_reg_n_0_[20]\,
R => ldata_reg
);
\rdata_reg_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(21),
Q => \rdata_reg_reg_n_0_[21]\,
R => ldata_reg
);
\rdata_reg_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(22),
Q => \rdata_reg_reg_n_0_[22]\,
R => ldata_reg
);
\rdata_reg_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(23),
Q => \rdata_reg_reg_n_0_[23]\,
R => ldata_reg
);
\rdata_reg_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(2),
Q => \rdata_reg_reg_n_0_[2]\,
R => ldata_reg
);
\rdata_reg_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(3),
Q => \rdata_reg_reg_n_0_[3]\,
R => ldata_reg
);
\rdata_reg_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(4),
Q => \rdata_reg_reg_n_0_[4]\,
R => ldata_reg
);
\rdata_reg_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(5),
Q => \rdata_reg_reg_n_0_[5]\,
R => ldata_reg
);
\rdata_reg_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(6),
Q => \rdata_reg_reg_n_0_[6]\,
R => ldata_reg
);
\rdata_reg_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(7),
Q => \rdata_reg_reg_n_0_[7]\,
R => ldata_reg
);
\rdata_reg_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(8),
Q => \rdata_reg_reg_n_0_[8]\,
R => ldata_reg
);
\rdata_reg_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => p_1_in(9),
Q => \rdata_reg_reg_n_0_[9]\,
R => ldata_reg
);
sdata_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFCCAF0000CCA0"
)
port map (
I0 => \rdata_reg_reg_n_0_[23]\,
I1 => p_2_in,
I2 => \^out\(2),
I3 => p_0_in2_in,
I4 => \clk_cntr_reg[4]\,
I5 => \^sdata_o\,
O => sdata_reg_i_1_n_0
);
sdata_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => sdata_reg_i_1_n_0,
Q => \^sdata_o\,
R => ldata_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
port (
\DataTx_R_reg[0]\ : out STD_LOGIC;
\DataTx_R_reg[0]_0\ : out STD_LOGIC;
\DataTx_R_reg[0]_1\ : out STD_LOGIC;
\DataTx_R_reg[0]_2\ : out STD_LOGIC;
\DataTx_R_reg[0]_3\ : out STD_LOGIC;
\DataTx_R_reg[0]_4\ : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DataTx_L_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
data_rdy_bit_reg_0 : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC;
data_rdy_bit : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataTx_L_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataRx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal IP2Bus_Data : STD_LOGIC_VECTOR ( 31 downto 0 );
signal I_DECODER_n_46 : STD_LOGIC;
signal I_DECODER_n_47 : STD_LOGIC;
signal I_DECODER_n_7 : STD_LOGIC;
signal I_DECODER_n_8 : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
signal timeout : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair4";
begin
S_AXI_BVALID <= \^s_axi_bvalid\;
S_AXI_RVALID <= \^s_axi_rvalid\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
I3 => timeout,
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[0]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[1]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg_n_0_[2]\,
R => p_2_out
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => plusOp(3),
Q => timeout,
R => p_2_out
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
port map (
D(1) => I_DECODER_n_7,
D(0) => I_DECODER_n_8,
\DataRx_L_reg[23]\(23 downto 0) => \DataRx_L_reg[23]\(23 downto 0),
\DataRx_R_reg[23]\(23 downto 0) => \DataRx_R_reg[23]\(23 downto 0),
\DataTx_L_reg[0]\(0) => \DataTx_L_reg[0]\(0),
\DataTx_L_reg[31]\(31 downto 0) => \DataTx_L_reg[31]\(31 downto 0),
\DataTx_R_reg[0]\ => \DataTx_R_reg[0]\,
\DataTx_R_reg[0]_0\ => \DataTx_R_reg[0]_0\,
\DataTx_R_reg[0]_1\ => \DataTx_R_reg[0]_1\,
\DataTx_R_reg[0]_2\ => \DataTx_R_reg[0]_2\,
\DataTx_R_reg[0]_3\ => \DataTx_R_reg[0]_3\,
\DataTx_R_reg[0]_4\ => \DataTx_R_reg[0]_4\,
\DataTx_R_reg[31]\(31 downto 0) => Q(31 downto 0),
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0) => timeout,
Q(1 downto 0) => state(1 downto 0),
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(2 downto 0),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(2 downto 0),
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WVALID_0 => \state[1]_i_2_n_0\,
data_rdy_bit => data_rdy_bit,
data_rdy_bit_reg => data_rdy_bit_reg,
data_rdy_bit_reg_0 => data_rdy_bit_reg_0,
s_axi_bvalid_i_reg => I_DECODER_n_47,
s_axi_bvalid_i_reg_0 => \state[0]_i_2_n_0\,
s_axi_bvalid_i_reg_1 => \^s_axi_bvalid\,
\s_axi_rdata_i_reg[31]\(31 downto 0) => IP2Bus_Data(31 downto 0),
s_axi_rvalid_i_reg => I_DECODER_n_46,
s_axi_rvalid_i_reg_0 => \^s_axi_rvalid\,
\state_reg[1]\ => \state[1]_i_3_n_0\
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => SR(0),
Q => rst,
R => '0'
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_47,
Q => \^s_axi_bvalid\,
R => rst
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(0),
Q => S_AXI_RDATA(0),
R => rst
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(10),
Q => S_AXI_RDATA(10),
R => rst
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(11),
Q => S_AXI_RDATA(11),
R => rst
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(12),
Q => S_AXI_RDATA(12),
R => rst
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(13),
Q => S_AXI_RDATA(13),
R => rst
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(14),
Q => S_AXI_RDATA(14),
R => rst
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(15),
Q => S_AXI_RDATA(15),
R => rst
);
\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(16),
Q => S_AXI_RDATA(16),
R => rst
);
\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(17),
Q => S_AXI_RDATA(17),
R => rst
);
\s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(18),
Q => S_AXI_RDATA(18),
R => rst
);
\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(19),
Q => S_AXI_RDATA(19),
R => rst
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(1),
Q => S_AXI_RDATA(1),
R => rst
);
\s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(20),
Q => S_AXI_RDATA(20),
R => rst
);
\s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(21),
Q => S_AXI_RDATA(21),
R => rst
);
\s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(22),
Q => S_AXI_RDATA(22),
R => rst
);
\s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(23),
Q => S_AXI_RDATA(23),
R => rst
);
\s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(24),
Q => S_AXI_RDATA(24),
R => rst
);
\s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(25),
Q => S_AXI_RDATA(25),
R => rst
);
\s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(26),
Q => S_AXI_RDATA(26),
R => rst
);
\s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(27),
Q => S_AXI_RDATA(27),
R => rst
);
\s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(28),
Q => S_AXI_RDATA(28),
R => rst
);
\s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(29),
Q => S_AXI_RDATA(29),
R => rst
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(2),
Q => S_AXI_RDATA(2),
R => rst
);
\s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(30),
Q => S_AXI_RDATA(30),
R => rst
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(31),
Q => S_AXI_RDATA(31),
R => rst
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(3),
Q => S_AXI_RDATA(3),
R => rst
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(4),
Q => S_AXI_RDATA(4),
R => rst
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(5),
Q => S_AXI_RDATA(5),
R => rst
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(6),
Q => S_AXI_RDATA(6),
R => rst
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(7),
Q => S_AXI_RDATA(7),
R => rst
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(8),
Q => S_AXI_RDATA(8),
R => rst
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => s_axi_rdata_i,
D => IP2Bus_Data(9),
Q => S_AXI_RDATA(9),
R => rst
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_46,
Q => \^s_axi_rvalid\,
R => rst
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"07770000FFFF0000"
)
port map (
I0 => \^s_axi_bvalid\,
I1 => S_AXI_BREADY,
I2 => S_AXI_RREADY,
I3 => \^s_axi_rvalid\,
I4 => state(0),
I5 => state(1),
O => \state[0]_i_2_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => S_AXI_AWVALID,
I1 => S_AXI_WVALID,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"002A2A2A"
)
port map (
I0 => state(1),
I1 => \^s_axi_rvalid\,
I2 => S_AXI_RREADY,
I3 => S_AXI_BREADY,
I4 => \^s_axi_bvalid\,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_8,
Q => state(0),
R => rst
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => S_AXI_ACLK,
CE => '1',
D => I_DECODER_n_7,
Q => state(1),
R => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic is
port (
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
data_rdy_bit : out STD_LOGIC;
SDATA_O : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
\s_axi_rdata_i_reg[31]_0\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
\s_axi_rdata_i_reg[23]_0\ : out STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : in STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
SDATA_I : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic is
signal Inst_iis_deser_n_3 : STD_LOGIC;
signal Inst_iis_deser_n_33 : STD_LOGIC;
signal Inst_iis_deser_n_34 : STD_LOGIC;
signal Inst_iis_deser_n_35 : STD_LOGIC;
signal Inst_iis_deser_n_36 : STD_LOGIC;
signal Inst_iis_deser_n_37 : STD_LOGIC;
signal Inst_iis_deser_n_38 : STD_LOGIC;
signal Inst_iis_deser_n_39 : STD_LOGIC;
signal Inst_iis_deser_n_40 : STD_LOGIC;
signal Inst_iis_deser_n_41 : STD_LOGIC;
signal Inst_iis_deser_n_42 : STD_LOGIC;
signal Inst_iis_deser_n_43 : STD_LOGIC;
signal Inst_iis_deser_n_44 : STD_LOGIC;
signal Inst_iis_deser_n_45 : STD_LOGIC;
signal Inst_iis_deser_n_46 : STD_LOGIC;
signal Inst_iis_deser_n_47 : STD_LOGIC;
signal Inst_iis_deser_n_48 : STD_LOGIC;
signal Inst_iis_deser_n_49 : STD_LOGIC;
signal Inst_iis_deser_n_5 : STD_LOGIC;
signal Inst_iis_deser_n_50 : STD_LOGIC;
signal Inst_iis_deser_n_51 : STD_LOGIC;
signal Inst_iis_deser_n_52 : STD_LOGIC;
signal Inst_iis_deser_n_53 : STD_LOGIC;
signal Inst_iis_deser_n_54 : STD_LOGIC;
signal Inst_iis_deser_n_55 : STD_LOGIC;
signal Inst_iis_deser_n_56 : STD_LOGIC;
signal Inst_iis_deser_n_6 : STD_LOGIC;
signal Inst_iis_deser_n_7 : STD_LOGIC;
signal Inst_iis_deser_n_8 : STD_LOGIC;
signal Inst_iis_ser_n_1 : STD_LOGIC;
signal Inst_iis_ser_n_2 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \clk_cntr[10]_i_2_n_0\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[0]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[1]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[2]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[3]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[5]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[6]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[7]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[8]\ : STD_LOGIC;
signal \clk_cntr_reg_n_0_[9]\ : STD_LOGIC;
signal data_rdy : STD_LOGIC;
signal \^data_rdy_bit\ : STD_LOGIC;
signal ldata_reg : STD_LOGIC_VECTOR ( 23 downto 0 );
signal lrclk_d1 : STD_LOGIC;
signal p_0_in4_in : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \^s_axi_rdata_i_reg[31]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_rdata_i_reg[31]_0\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal sclk_d1 : STD_LOGIC;
signal write_bit : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \clk_cntr[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \clk_cntr[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \clk_cntr[3]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \clk_cntr[4]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \clk_cntr[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \clk_cntr[7]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \clk_cntr[8]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \clk_cntr[9]_i_1\ : label is "soft_lutpair15";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
SR(0) <= \^sr\(0);
data_rdy_bit <= \^data_rdy_bit\;
\s_axi_rdata_i_reg[31]\(31 downto 0) <= \^s_axi_rdata_i_reg[31]\(31 downto 0);
\s_axi_rdata_i_reg[31]_0\(31 downto 0) <= \^s_axi_rdata_i_reg[31]_0\(31 downto 0);
\DataRx_L_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(0),
Q => \s_axi_rdata_i_reg[23]\(0),
R => '0'
);
\DataRx_L_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(10),
Q => \s_axi_rdata_i_reg[23]\(10),
R => '0'
);
\DataRx_L_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(11),
Q => \s_axi_rdata_i_reg[23]\(11),
R => '0'
);
\DataRx_L_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(12),
Q => \s_axi_rdata_i_reg[23]\(12),
R => '0'
);
\DataRx_L_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(13),
Q => \s_axi_rdata_i_reg[23]\(13),
R => '0'
);
\DataRx_L_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(14),
Q => \s_axi_rdata_i_reg[23]\(14),
R => '0'
);
\DataRx_L_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(15),
Q => \s_axi_rdata_i_reg[23]\(15),
R => '0'
);
\DataRx_L_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(16),
Q => \s_axi_rdata_i_reg[23]\(16),
R => '0'
);
\DataRx_L_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(17),
Q => \s_axi_rdata_i_reg[23]\(17),
R => '0'
);
\DataRx_L_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(18),
Q => \s_axi_rdata_i_reg[23]\(18),
R => '0'
);
\DataRx_L_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(19),
Q => \s_axi_rdata_i_reg[23]\(19),
R => '0'
);
\DataRx_L_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(1),
Q => \s_axi_rdata_i_reg[23]\(1),
R => '0'
);
\DataRx_L_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(20),
Q => \s_axi_rdata_i_reg[23]\(20),
R => '0'
);
\DataRx_L_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(21),
Q => \s_axi_rdata_i_reg[23]\(21),
R => '0'
);
\DataRx_L_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(22),
Q => \s_axi_rdata_i_reg[23]\(22),
R => '0'
);
\DataRx_L_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(23),
Q => \s_axi_rdata_i_reg[23]\(23),
R => '0'
);
\DataRx_L_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(2),
Q => \s_axi_rdata_i_reg[23]\(2),
R => '0'
);
\DataRx_L_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(3),
Q => \s_axi_rdata_i_reg[23]\(3),
R => '0'
);
\DataRx_L_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(4),
Q => \s_axi_rdata_i_reg[23]\(4),
R => '0'
);
\DataRx_L_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(5),
Q => \s_axi_rdata_i_reg[23]\(5),
R => '0'
);
\DataRx_L_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(6),
Q => \s_axi_rdata_i_reg[23]\(6),
R => '0'
);
\DataRx_L_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(7),
Q => \s_axi_rdata_i_reg[23]\(7),
R => '0'
);
\DataRx_L_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(8),
Q => \s_axi_rdata_i_reg[23]\(8),
R => '0'
);
\DataRx_L_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => ldata_reg(9),
Q => \s_axi_rdata_i_reg[23]\(9),
R => '0'
);
\DataRx_R_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_56,
Q => \s_axi_rdata_i_reg[23]_0\(0),
R => '0'
);
\DataRx_R_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_46,
Q => \s_axi_rdata_i_reg[23]_0\(10),
R => '0'
);
\DataRx_R_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_45,
Q => \s_axi_rdata_i_reg[23]_0\(11),
R => '0'
);
\DataRx_R_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_44,
Q => \s_axi_rdata_i_reg[23]_0\(12),
R => '0'
);
\DataRx_R_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_43,
Q => \s_axi_rdata_i_reg[23]_0\(13),
R => '0'
);
\DataRx_R_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_42,
Q => \s_axi_rdata_i_reg[23]_0\(14),
R => '0'
);
\DataRx_R_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_41,
Q => \s_axi_rdata_i_reg[23]_0\(15),
R => '0'
);
\DataRx_R_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_40,
Q => \s_axi_rdata_i_reg[23]_0\(16),
R => '0'
);
\DataRx_R_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_39,
Q => \s_axi_rdata_i_reg[23]_0\(17),
R => '0'
);
\DataRx_R_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_38,
Q => \s_axi_rdata_i_reg[23]_0\(18),
R => '0'
);
\DataRx_R_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_37,
Q => \s_axi_rdata_i_reg[23]_0\(19),
R => '0'
);
\DataRx_R_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_55,
Q => \s_axi_rdata_i_reg[23]_0\(1),
R => '0'
);
\DataRx_R_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_36,
Q => \s_axi_rdata_i_reg[23]_0\(20),
R => '0'
);
\DataRx_R_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_35,
Q => \s_axi_rdata_i_reg[23]_0\(21),
R => '0'
);
\DataRx_R_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_34,
Q => \s_axi_rdata_i_reg[23]_0\(22),
R => '0'
);
\DataRx_R_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_33,
Q => \s_axi_rdata_i_reg[23]_0\(23),
R => '0'
);
\DataRx_R_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_54,
Q => \s_axi_rdata_i_reg[23]_0\(2),
R => '0'
);
\DataRx_R_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_53,
Q => \s_axi_rdata_i_reg[23]_0\(3),
R => '0'
);
\DataRx_R_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_52,
Q => \s_axi_rdata_i_reg[23]_0\(4),
R => '0'
);
\DataRx_R_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_51,
Q => \s_axi_rdata_i_reg[23]_0\(5),
R => '0'
);
\DataRx_R_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_50,
Q => \s_axi_rdata_i_reg[23]_0\(6),
R => '0'
);
\DataRx_R_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_49,
Q => \s_axi_rdata_i_reg[23]_0\(7),
R => '0'
);
\DataRx_R_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_48,
Q => \s_axi_rdata_i_reg[23]_0\(8),
R => '0'
);
\DataRx_R_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => data_rdy,
D => Inst_iis_deser_n_47,
Q => \s_axi_rdata_i_reg[23]_0\(9),
R => '0'
);
\DataTx_L_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(0),
Q => \^s_axi_rdata_i_reg[31]\(0),
R => \^sr\(0)
);
\DataTx_L_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(10),
Q => \^s_axi_rdata_i_reg[31]\(10),
R => \^sr\(0)
);
\DataTx_L_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(11),
Q => \^s_axi_rdata_i_reg[31]\(11),
R => \^sr\(0)
);
\DataTx_L_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(12),
Q => \^s_axi_rdata_i_reg[31]\(12),
R => \^sr\(0)
);
\DataTx_L_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(13),
Q => \^s_axi_rdata_i_reg[31]\(13),
R => \^sr\(0)
);
\DataTx_L_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(14),
Q => \^s_axi_rdata_i_reg[31]\(14),
R => \^sr\(0)
);
\DataTx_L_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(15),
Q => \^s_axi_rdata_i_reg[31]\(15),
R => \^sr\(0)
);
\DataTx_L_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(16),
Q => \^s_axi_rdata_i_reg[31]\(16),
R => \^sr\(0)
);
\DataTx_L_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(17),
Q => \^s_axi_rdata_i_reg[31]\(17),
R => \^sr\(0)
);
\DataTx_L_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(18),
Q => \^s_axi_rdata_i_reg[31]\(18),
R => \^sr\(0)
);
\DataTx_L_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(19),
Q => \^s_axi_rdata_i_reg[31]\(19),
R => \^sr\(0)
);
\DataTx_L_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(1),
Q => \^s_axi_rdata_i_reg[31]\(1),
R => \^sr\(0)
);
\DataTx_L_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(20),
Q => \^s_axi_rdata_i_reg[31]\(20),
R => \^sr\(0)
);
\DataTx_L_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(21),
Q => \^s_axi_rdata_i_reg[31]\(21),
R => \^sr\(0)
);
\DataTx_L_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(22),
Q => \^s_axi_rdata_i_reg[31]\(22),
R => \^sr\(0)
);
\DataTx_L_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(23),
Q => \^s_axi_rdata_i_reg[31]\(23),
R => \^sr\(0)
);
\DataTx_L_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(24),
Q => \^s_axi_rdata_i_reg[31]\(24),
R => \^sr\(0)
);
\DataTx_L_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(25),
Q => \^s_axi_rdata_i_reg[31]\(25),
R => \^sr\(0)
);
\DataTx_L_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(26),
Q => \^s_axi_rdata_i_reg[31]\(26),
R => \^sr\(0)
);
\DataTx_L_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(27),
Q => \^s_axi_rdata_i_reg[31]\(27),
R => \^sr\(0)
);
\DataTx_L_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(28),
Q => \^s_axi_rdata_i_reg[31]\(28),
R => \^sr\(0)
);
\DataTx_L_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(29),
Q => \^s_axi_rdata_i_reg[31]\(29),
R => \^sr\(0)
);
\DataTx_L_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(2),
Q => \^s_axi_rdata_i_reg[31]\(2),
R => \^sr\(0)
);
\DataTx_L_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(30),
Q => \^s_axi_rdata_i_reg[31]\(30),
R => \^sr\(0)
);
\DataTx_L_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(31),
Q => \^s_axi_rdata_i_reg[31]\(31),
R => \^sr\(0)
);
\DataTx_L_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(3),
Q => \^s_axi_rdata_i_reg[31]\(3),
R => \^sr\(0)
);
\DataTx_L_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(4),
Q => \^s_axi_rdata_i_reg[31]\(4),
R => \^sr\(0)
);
\DataTx_L_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(5),
Q => \^s_axi_rdata_i_reg[31]\(5),
R => \^sr\(0)
);
\DataTx_L_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(6),
Q => \^s_axi_rdata_i_reg[31]\(6),
R => \^sr\(0)
);
\DataTx_L_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(7),
Q => \^s_axi_rdata_i_reg[31]\(7),
R => \^sr\(0)
);
\DataTx_L_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(8),
Q => \^s_axi_rdata_i_reg[31]\(8),
R => \^sr\(0)
);
\DataTx_L_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => E(0),
D => S_AXI_WDATA(9),
Q => \^s_axi_rdata_i_reg[31]\(9),
R => \^sr\(0)
);
\DataTx_R_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(0),
Q => \^s_axi_rdata_i_reg[31]_0\(0),
R => \^sr\(0)
);
\DataTx_R_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(10),
Q => \^s_axi_rdata_i_reg[31]_0\(10),
R => \^sr\(0)
);
\DataTx_R_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(11),
Q => \^s_axi_rdata_i_reg[31]_0\(11),
R => \^sr\(0)
);
\DataTx_R_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(12),
Q => \^s_axi_rdata_i_reg[31]_0\(12),
R => \^sr\(0)
);
\DataTx_R_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(13),
Q => \^s_axi_rdata_i_reg[31]_0\(13),
R => \^sr\(0)
);
\DataTx_R_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(14),
Q => \^s_axi_rdata_i_reg[31]_0\(14),
R => \^sr\(0)
);
\DataTx_R_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(15),
Q => \^s_axi_rdata_i_reg[31]_0\(15),
R => \^sr\(0)
);
\DataTx_R_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(16),
Q => \^s_axi_rdata_i_reg[31]_0\(16),
R => \^sr\(0)
);
\DataTx_R_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(17),
Q => \^s_axi_rdata_i_reg[31]_0\(17),
R => \^sr\(0)
);
\DataTx_R_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(18),
Q => \^s_axi_rdata_i_reg[31]_0\(18),
R => \^sr\(0)
);
\DataTx_R_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(19),
Q => \^s_axi_rdata_i_reg[31]_0\(19),
R => \^sr\(0)
);
\DataTx_R_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(1),
Q => \^s_axi_rdata_i_reg[31]_0\(1),
R => \^sr\(0)
);
\DataTx_R_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(20),
Q => \^s_axi_rdata_i_reg[31]_0\(20),
R => \^sr\(0)
);
\DataTx_R_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(21),
Q => \^s_axi_rdata_i_reg[31]_0\(21),
R => \^sr\(0)
);
\DataTx_R_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(22),
Q => \^s_axi_rdata_i_reg[31]_0\(22),
R => \^sr\(0)
);
\DataTx_R_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(23),
Q => \^s_axi_rdata_i_reg[31]_0\(23),
R => \^sr\(0)
);
\DataTx_R_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(24),
Q => \^s_axi_rdata_i_reg[31]_0\(24),
R => \^sr\(0)
);
\DataTx_R_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(25),
Q => \^s_axi_rdata_i_reg[31]_0\(25),
R => \^sr\(0)
);
\DataTx_R_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(26),
Q => \^s_axi_rdata_i_reg[31]_0\(26),
R => \^sr\(0)
);
\DataTx_R_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(27),
Q => \^s_axi_rdata_i_reg[31]_0\(27),
R => \^sr\(0)
);
\DataTx_R_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(28),
Q => \^s_axi_rdata_i_reg[31]_0\(28),
R => \^sr\(0)
);
\DataTx_R_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(29),
Q => \^s_axi_rdata_i_reg[31]_0\(29),
R => \^sr\(0)
);
\DataTx_R_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(2),
Q => \^s_axi_rdata_i_reg[31]_0\(2),
R => \^sr\(0)
);
\DataTx_R_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(30),
Q => \^s_axi_rdata_i_reg[31]_0\(30),
R => \^sr\(0)
);
\DataTx_R_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(31),
Q => \^s_axi_rdata_i_reg[31]_0\(31),
R => \^sr\(0)
);
\DataTx_R_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(3),
Q => \^s_axi_rdata_i_reg[31]_0\(3),
R => \^sr\(0)
);
\DataTx_R_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(4),
Q => \^s_axi_rdata_i_reg[31]_0\(4),
R => \^sr\(0)
);
\DataTx_R_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(5),
Q => \^s_axi_rdata_i_reg[31]_0\(5),
R => \^sr\(0)
);
\DataTx_R_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(6),
Q => \^s_axi_rdata_i_reg[31]_0\(6),
R => \^sr\(0)
);
\DataTx_R_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(7),
Q => \^s_axi_rdata_i_reg[31]_0\(7),
R => \^sr\(0)
);
\DataTx_R_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(8),
Q => \^s_axi_rdata_i_reg[31]_0\(8),
R => \^sr\(0)
);
\DataTx_R_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0),
D => S_AXI_WDATA(9),
Q => \^s_axi_rdata_i_reg[31]_0\(9),
R => \^sr\(0)
);
Inst_iis_deser: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_deser
port map (
\DataRx_L_reg[23]\(23 downto 0) => ldata_reg(23 downto 0),
\DataRx_R_reg[23]\(23) => Inst_iis_deser_n_33,
\DataRx_R_reg[23]\(22) => Inst_iis_deser_n_34,
\DataRx_R_reg[23]\(21) => Inst_iis_deser_n_35,
\DataRx_R_reg[23]\(20) => Inst_iis_deser_n_36,
\DataRx_R_reg[23]\(19) => Inst_iis_deser_n_37,
\DataRx_R_reg[23]\(18) => Inst_iis_deser_n_38,
\DataRx_R_reg[23]\(17) => Inst_iis_deser_n_39,
\DataRx_R_reg[23]\(16) => Inst_iis_deser_n_40,
\DataRx_R_reg[23]\(15) => Inst_iis_deser_n_41,
\DataRx_R_reg[23]\(14) => Inst_iis_deser_n_42,
\DataRx_R_reg[23]\(13) => Inst_iis_deser_n_43,
\DataRx_R_reg[23]\(12) => Inst_iis_deser_n_44,
\DataRx_R_reg[23]\(11) => Inst_iis_deser_n_45,
\DataRx_R_reg[23]\(10) => Inst_iis_deser_n_46,
\DataRx_R_reg[23]\(9) => Inst_iis_deser_n_47,
\DataRx_R_reg[23]\(8) => Inst_iis_deser_n_48,
\DataRx_R_reg[23]\(7) => Inst_iis_deser_n_49,
\DataRx_R_reg[23]\(6) => Inst_iis_deser_n_50,
\DataRx_R_reg[23]\(5) => Inst_iis_deser_n_51,
\DataRx_R_reg[23]\(4) => Inst_iis_deser_n_52,
\DataRx_R_reg[23]\(3) => Inst_iis_deser_n_53,
\DataRx_R_reg[23]\(2) => Inst_iis_deser_n_54,
\DataRx_R_reg[23]\(1) => Inst_iis_deser_n_55,
\DataRx_R_reg[23]\(0) => Inst_iis_deser_n_56,
E(0) => data_rdy,
\FSM_onehot_iis_state_reg[0]\ => Inst_iis_deser_n_6,
\FSM_onehot_iis_state_reg[0]_0\ => Inst_iis_deser_n_8,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
Q(1 downto 0) => \^q\(1 downto 0),
SDATA_I => SDATA_I,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
\bit_cntr_reg[4]_0\(0) => write_bit,
data_rdy_bit => \^data_rdy_bit\,
data_rdy_bit_reg => Inst_iis_deser_n_7,
lrclk_d1 => lrclk_d1,
\out\(2) => Inst_iis_ser_n_1,
\out\(1) => Inst_iis_ser_n_2,
\out\(0) => p_0_in4_in,
\rdata_reg_reg[23]_0\(0) => Inst_iis_deser_n_3,
sclk_d1 => sclk_d1,
sdata_reg_reg => Inst_iis_deser_n_5
);
Inst_iis_ser: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_iis_ser
port map (
\DataTx_L_reg[23]\(23 downto 0) => \^s_axi_rdata_i_reg[31]\(23 downto 0),
\DataTx_R_reg[23]\(23 downto 0) => \^s_axi_rdata_i_reg[31]_0\(23 downto 0),
E(0) => Inst_iis_deser_n_3,
Q(1 downto 0) => \^q\(1 downto 0),
SDATA_O => SDATA_O,
S_AXI_ACLK => S_AXI_ACLK,
\clk_cntr_reg[4]\ => Inst_iis_deser_n_5,
lrclk_d1 => lrclk_d1,
lrclk_d1_reg => Inst_iis_deser_n_8,
lrclk_d1_reg_0 => Inst_iis_deser_n_6,
\out\(2) => Inst_iis_ser_n_1,
\out\(1) => Inst_iis_ser_n_2,
\out\(0) => p_0_in4_in,
sclk_d1 => sclk_d1,
sclk_d1_reg(0) => write_bit
);
\clk_cntr[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \clk_cntr_reg_n_0_[0]\,
O => \plusOp__0\(0)
);
\clk_cntr[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFFFFF08000000"
)
port map (
I0 => \clk_cntr_reg_n_0_[9]\,
I1 => \clk_cntr_reg_n_0_[7]\,
I2 => \clk_cntr[10]_i_2_n_0\,
I3 => \clk_cntr_reg_n_0_[6]\,
I4 => \clk_cntr_reg_n_0_[8]\,
I5 => \^q\(1),
O => \plusOp__0\(10)
);
\clk_cntr[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(0),
I1 => \clk_cntr_reg_n_0_[2]\,
I2 => \clk_cntr_reg_n_0_[0]\,
I3 => \clk_cntr_reg_n_0_[1]\,
I4 => \clk_cntr_reg_n_0_[3]\,
I5 => \clk_cntr_reg_n_0_[5]\,
O => \clk_cntr[10]_i_2_n_0\
);
\clk_cntr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \clk_cntr_reg_n_0_[0]\,
I1 => \clk_cntr_reg_n_0_[1]\,
O => \plusOp__0\(1)
);
\clk_cntr[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \clk_cntr_reg_n_0_[1]\,
I1 => \clk_cntr_reg_n_0_[0]\,
I2 => \clk_cntr_reg_n_0_[2]\,
O => \plusOp__0\(2)
);
\clk_cntr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \clk_cntr_reg_n_0_[2]\,
I1 => \clk_cntr_reg_n_0_[0]\,
I2 => \clk_cntr_reg_n_0_[1]\,
I3 => \clk_cntr_reg_n_0_[3]\,
O => \plusOp__0\(3)
);
\clk_cntr[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \clk_cntr_reg_n_0_[3]\,
I1 => \clk_cntr_reg_n_0_[1]\,
I2 => \clk_cntr_reg_n_0_[0]\,
I3 => \clk_cntr_reg_n_0_[2]\,
I4 => \^q\(0),
O => \plusOp__0\(4)
);
\clk_cntr[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(0),
I1 => \clk_cntr_reg_n_0_[2]\,
I2 => \clk_cntr_reg_n_0_[0]\,
I3 => \clk_cntr_reg_n_0_[1]\,
I4 => \clk_cntr_reg_n_0_[3]\,
I5 => \clk_cntr_reg_n_0_[5]\,
O => \plusOp__0\(5)
);
\clk_cntr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \clk_cntr[10]_i_2_n_0\,
I1 => \clk_cntr_reg_n_0_[6]\,
O => \plusOp__0\(6)
);
\clk_cntr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \clk_cntr_reg_n_0_[6]\,
I1 => \clk_cntr[10]_i_2_n_0\,
I2 => \clk_cntr_reg_n_0_[7]\,
O => \plusOp__0\(7)
);
\clk_cntr[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DF20"
)
port map (
I0 => \clk_cntr_reg_n_0_[7]\,
I1 => \clk_cntr[10]_i_2_n_0\,
I2 => \clk_cntr_reg_n_0_[6]\,
I3 => \clk_cntr_reg_n_0_[8]\,
O => \plusOp__0\(8)
);
\clk_cntr[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FF0800"
)
port map (
I0 => \clk_cntr_reg_n_0_[8]\,
I1 => \clk_cntr_reg_n_0_[6]\,
I2 => \clk_cntr[10]_i_2_n_0\,
I3 => \clk_cntr_reg_n_0_[7]\,
I4 => \clk_cntr_reg_n_0_[9]\,
O => \plusOp__0\(9)
);
\clk_cntr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(0),
Q => \clk_cntr_reg_n_0_[0]\,
R => '0'
);
\clk_cntr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(10),
Q => \^q\(1),
R => '0'
);
\clk_cntr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(1),
Q => \clk_cntr_reg_n_0_[1]\,
R => '0'
);
\clk_cntr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(2),
Q => \clk_cntr_reg_n_0_[2]\,
R => '0'
);
\clk_cntr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(3),
Q => \clk_cntr_reg_n_0_[3]\,
R => '0'
);
\clk_cntr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(4),
Q => \^q\(0),
R => '0'
);
\clk_cntr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(5),
Q => \clk_cntr_reg_n_0_[5]\,
R => '0'
);
\clk_cntr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(6),
Q => \clk_cntr_reg_n_0_[6]\,
R => '0'
);
\clk_cntr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(7),
Q => \clk_cntr_reg_n_0_[7]\,
R => '0'
);
\clk_cntr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(8),
Q => \clk_cntr_reg_n_0_[8]\,
R => '0'
);
\clk_cntr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => \plusOp__0\(9),
Q => \clk_cntr_reg_n_0_[9]\,
R => '0'
);
data_rdy_bit_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => S_AXI_ACLK,
CE => '1',
D => Inst_iis_deser_n_7,
Q => \^data_rdy_bit\,
R => '0'
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => S_AXI_ARESETN,
O => \^sr\(0)
);
slv_ip2bus_data: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000400040448"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => Bus_RNW_reg,
I2 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I5 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
O => \s_axi_rdata_i_reg[24]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
port (
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : out STD_LOGIC;
Bus_RNW_reg : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
data_rdy_bit_reg : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\DataTx_L_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
data_rdy_bit_reg_0 : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACLK : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC;
data_rdy_bit : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataTx_L_reg[31]\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\DataRx_R_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\DataRx_L_reg[23]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
port map (
\DataRx_L_reg[23]\(23 downto 0) => \DataRx_L_reg[23]\(23 downto 0),
\DataRx_R_reg[23]\(23 downto 0) => \DataRx_R_reg[23]\(23 downto 0),
\DataTx_L_reg[0]\(0) => \DataTx_L_reg[0]\(0),
\DataTx_L_reg[31]\(31 downto 0) => \DataTx_L_reg[31]\(31 downto 0),
\DataTx_R_reg[0]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
\DataTx_R_reg[0]_0\ => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\DataTx_R_reg[0]_1\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\DataTx_R_reg[0]_2\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\DataTx_R_reg[0]_3\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\DataTx_R_reg[0]_4\ => Bus_RNW_reg,
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
Q(31 downto 0) => Q(31 downto 0),
SR(0) => SR(0),
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(2 downto 0),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(2 downto 0),
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0),
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WVALID => S_AXI_WVALID,
data_rdy_bit => data_rdy_bit,
data_rdy_bit_reg => data_rdy_bit_reg,
data_rdy_bit_reg_0 => data_rdy_bit_reg_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_BVALID : out STD_LOGIC;
S_AXI_RVALID : out STD_LOGIC;
SDATA_O : out STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
SDATA_I : in STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WVALID : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl is
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_8 : STD_LOGIC;
signal DataRx_L : STD_LOGIC_VECTOR ( 23 downto 0 );
signal DataRx_R : STD_LOGIC_VECTOR ( 23 downto 0 );
signal DataTx_L : STD_LOGIC_VECTOR ( 31 downto 0 );
signal DataTx_R : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : STD_LOGIC;
signal USER_LOGIC_I_n_0 : STD_LOGIC;
signal USER_LOGIC_I_n_69 : STD_LOGIC;
signal data_rdy_bit : STD_LOGIC;
begin
AXI_LITE_IPIF_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
\DataRx_L_reg[23]\(23 downto 0) => DataRx_L(23 downto 0),
\DataRx_R_reg[23]\(23 downto 0) => DataRx_R(23 downto 0),
\DataTx_L_reg[0]\(0) => AXI_LITE_IPIF_I_n_12,
\DataTx_L_reg[31]\(31 downto 0) => DataTx_L(31 downto 0),
E(0) => AXI_LITE_IPIF_I_n_11,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => USER_LOGIC_I_n_0,
Q(31 downto 0) => DataTx_R(31 downto 0),
SR(0) => USER_LOGIC_I_n_69,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(2 downto 0),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(2 downto 0),
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0),
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WVALID => S_AXI_WVALID,
data_rdy_bit => data_rdy_bit,
data_rdy_bit_reg => AXI_LITE_IPIF_I_n_8,
data_rdy_bit_reg_0 => AXI_LITE_IPIF_I_n_13
);
USER_LOGIC_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_user_logic
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
E(0) => AXI_LITE_IPIF_I_n_12,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI_LITE_IPIF_I_n_8,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\(0) => AXI_LITE_IPIF_I_n_11,
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => AXI_LITE_IPIF_I_n_13,
Q(1 downto 0) => \out\(1 downto 0),
SDATA_I => SDATA_I,
SDATA_O => SDATA_O,
SR(0) => USER_LOGIC_I_n_69,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_WDATA(31 downto 0) => S_AXI_WDATA(31 downto 0),
data_rdy_bit => data_rdy_bit,
\s_axi_rdata_i_reg[23]\(23 downto 0) => DataRx_L(23 downto 0),
\s_axi_rdata_i_reg[23]_0\(23 downto 0) => DataRx_R(23 downto 0),
\s_axi_rdata_i_reg[24]\ => USER_LOGIC_I_n_0,
\s_axi_rdata_i_reg[31]\(31 downto 0) => DataTx_L(31 downto 0),
\s_axi_rdata_i_reg[31]_0\(31 downto 0) => DataTx_R(31 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
BCLK : out STD_LOGIC;
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_BVALID : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_zed_audio_ctrl_0_0,i2s_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "i2s_ctrl,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal \<const0>\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
attribute max_fanout : string;
attribute max_fanout of S_AXI_ACLK : signal is "10000";
attribute sigis : string;
attribute sigis of S_AXI_ACLK : signal is "Clk";
attribute x_interface_info : string;
attribute x_interface_info of S_AXI_ACLK : signal is "xilinx.com:signal:clock:1.0 S_AXI_signal_clock CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of S_AXI_ACLK : signal is "XIL_INTERFACENAME S_AXI_signal_clock, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET S_AXI_ARESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute max_fanout of S_AXI_ARESETN : signal is "10000";
attribute sigis of S_AXI_ARESETN : signal is "Rst";
attribute x_interface_info of S_AXI_ARESETN : signal is "xilinx.com:signal:reset:1.0 S_AXI_signal_reset RST";
attribute x_interface_parameter of S_AXI_ARESETN : signal is "XIL_INTERFACENAME S_AXI_signal_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of S_AXI_ARREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute x_interface_info of S_AXI_ARVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute x_interface_info of S_AXI_AWREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute x_interface_info of S_AXI_AWVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute x_interface_info of S_AXI_BREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute x_interface_info of S_AXI_BVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute x_interface_info of S_AXI_RREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute x_interface_info of S_AXI_RVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute x_interface_info of S_AXI_WREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute x_interface_info of S_AXI_WVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute x_interface_info of S_AXI_ARADDR : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute x_interface_info of S_AXI_AWADDR : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute x_interface_parameter of S_AXI_AWADDR : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute x_interface_info of S_AXI_BRESP : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute x_interface_info of S_AXI_RDATA : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute x_interface_info of S_AXI_RRESP : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute x_interface_info of S_AXI_WDATA : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute x_interface_info of S_AXI_WSTRB : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
S_AXI_AWREADY <= \^s_axi_awready\;
S_AXI_BRESP(1) <= \<const0>\;
S_AXI_BRESP(0) <= \<const0>\;
S_AXI_RRESP(1) <= \<const0>\;
S_AXI_RRESP(0) <= \<const0>\;
S_AXI_WREADY <= \^s_axi_awready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_i2s_ctrl
port map (
SDATA_I => SDATA_I,
SDATA_O => SDATA_O,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARADDR(2 downto 0) => S_AXI_ARADDR(4 downto 2),
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_AWADDR(2 downto 0) => S_AXI_AWADDR(4 downto 2),
S_AXI_AWREADY => \^s_axi_awready\,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => S_AXI_RDATA(31 downto 0),
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WDATA(31 downto 0) => S_AXI_WDATA(31 downto 0),
S_AXI_WVALID => S_AXI_WVALID,
\out\(1) => LRCLK,
\out\(0) => BCLK
);
end STRUCTURE;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_auto_pc_1/zqynq_lab_1_design_auto_pc_1_sim_netlist.vhdl | 1 | 452796 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:26:01 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top zqynq_lab_1_design_auto_pc_1 -prefix
-- zqynq_lab_1_design_auto_pc_1_ zqynq_lab_1_design_auto_pc_1_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_auto_pc_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
\m_axi_awaddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_0 : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \axaddr_incr[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_3_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_4_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal next_pending_r_i_5_n_0 : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_3\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_4\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of next_pending_r_i_5 : label is "soft_lutpair89";
begin
Q(0) <= \^q\(0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axlen_cnt_reg[3]_0\ <= \^axlen_cnt_reg[3]_0\;
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \next\,
O => \axaddr_incr[0]_i_1_n_0\
);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \next\,
I2 => \m_payload_i_reg[51]\(5),
I3 => \m_payload_i_reg[51]\(4),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT4
generic map(
INIT => X"0A6A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \next\,
I2 => \m_payload_i_reg[51]\(5),
I3 => \m_payload_i_reg[51]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"006A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \next\,
I2 => \m_payload_i_reg[51]\(4),
I3 => \m_payload_i_reg[51]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT4
generic map(
INIT => X"0006"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \next\,
I2 => \m_payload_i_reg[51]\(5),
I3 => \m_payload_i_reg[51]\(4),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \axaddr_incr[0]_i_1_n_0\,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(7),
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \^q\(0),
I4 => \^axlen_cnt_reg[3]_0\,
O => p_1_in(1)
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \^axlen_cnt_reg[3]_0\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \^axlen_cnt_reg[3]_0\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__0_n_0\
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8B88888B"
)
port map (
I0 => \m_payload_i_reg[51]\(9),
I1 => E(0),
I2 => \axlen_cnt[4]_i_2_n_0\,
I3 => \axlen_cnt[4]_i_3_n_0\,
I4 => \axlen_cnt_reg_n_0_[4]\,
O => p_1_in(4)
);
\axlen_cnt[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
I4 => \axlen_cnt_reg_n_0_[6]\,
I5 => \axlen_cnt[4]_i_4_n_0\,
O => \axlen_cnt[4]_i_2_n_0\
);
\axlen_cnt[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[4]_i_3_n_0\
);
\axlen_cnt[4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_4_n_0\
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FF88888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(10),
I2 => \axlen_cnt_reg_n_0_[5]\,
I3 => \axlen_cnt[5]_i_2_n_0\,
I4 => \^axlen_cnt_reg[3]_0\,
O => p_1_in(5)
);
\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[5]_i_2_n_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF282828"
)
port map (
I0 => \^axlen_cnt_reg[3]_0\,
I1 => \axlen_cnt_reg_n_0_[6]\,
I2 => \axlen_cnt[7]_i_3_n_0\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(11),
O => p_1_in(6)
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF828882888288"
)
port map (
I0 => \^axlen_cnt_reg[3]_0\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt[7]_i_3_n_0\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(12),
O => p_1_in(7)
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[4]\,
I5 => \axlen_cnt_reg_n_0_[5]\,
O => \axlen_cnt[7]_i_3_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => p_1_in(1),
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => p_1_in(4),
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => p_1_in(5),
Q => \axlen_cnt_reg_n_0_[5]\,
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => p_1_in(6),
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => p_1_in(7),
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \^axaddr_incr_reg[3]_0\(1),
I2 => \m_payload_i_reg[51]\(6),
I3 => \m_payload_i_reg[51]\(1),
O => \m_axi_awaddr[1]\
);
\next_pending_r_i_3__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"55555554"
)
port map (
I0 => E(0),
I1 => next_pending_r_i_5_n_0,
I2 => \axlen_cnt_reg_n_0_[4]\,
I3 => \axlen_cnt_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[5]\,
O => \^axlen_cnt_reg[3]_0\
);
next_pending_r_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => next_pending_r_i_5_n_0
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_0,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
port (
incr_next_pending : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_incr_reg[11]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axlen_cnt_reg[5]_0\ : out STD_LOGIC;
\m_axi_araddr[6]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 6 to 6 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^axaddr_incr_reg[11]_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \next_pending_r_i_5__0_n_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2__0\ : label is "soft_lutpair3";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\axaddr_incr_reg[11]_0\(6 downto 0) <= \^axaddr_incr_reg[11]_0\(6 downto 0);
\axaddr_incr_reg[11]_1\ <= \^axaddr_incr_reg[11]_1\;
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
incr_next_pending <= \^incr_next_pending\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \m_payload_i_reg[51]\(5),
I2 => \m_payload_i_reg[51]\(6),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(2),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => axaddr_incr_reg(6),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(1),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(6),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(5),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(4),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(3),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => axaddr_incr_reg(6),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt[4]_i_2__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(9),
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(1),
I3 => \^q\(0),
O => \axlen_cnt[4]_i_2__0_n_0\
);
\axlen_cnt[5]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt_reg[5]_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F88888F8F888F888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(10),
I2 => \state_reg[0]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
I4 => \^q\(3),
I5 => \^axlen_cnt_reg[7]_0\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[4]\,
I5 => \^q\(2),
O => \^axlen_cnt_reg[7]_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(2),
Q => \^q\(2),
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(3),
Q => \^q\(3),
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_araddr[6]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => axaddr_incr_reg(6),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(4),
O => \m_axi_araddr[6]\
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDCCFCFFDDFFFC"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \m_payload_i_reg[47]_0\,
I2 => next_pending_r_reg_n_0,
I3 => \state_reg[1]_rep\,
I4 => E(0),
I5 => \^next_pending_r_reg_0\,
O => \^incr_next_pending\
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \next_pending_r_i_5__0_n_0\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \^q\(3),
I3 => \axlen_cnt_reg_n_0_[4]\,
O => \^next_pending_r_reg_0\
);
\next_pending_r_i_5__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(1),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \^q\(2),
O => \next_pending_r_i_5__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^incr_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[5]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[0]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_i : out STD_LOGIC;
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[7]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axburst_eq1_reg : in STD_LOGIC;
\cnt_read_reg[2]\ : in STD_LOGIC;
\axlen_cnt_reg[6]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[50]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
\axlen_cnt_reg[3]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axlen_cnt_reg[5]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \wrap_cnt_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[0]\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \state[1]_i_1__0\ : label is "soft_lutpair0";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
axaddr_offset(1 downto 0) <= \^axaddr_offset\(1 downto 0);
\axlen_cnt_reg[5]\ <= \^axlen_cnt_reg[5]\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\wrap_cnt_r_reg[0]\ <= \^wrap_cnt_r_reg[0]\;
\wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first_reg_2,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAC0AAAA"
)
port map (
I0 => \axaddr_offset_r_reg[3]\(0),
I1 => \m_payload_i_reg[3]\,
I2 => \m_payload_i_reg[50]\(0),
I3 => \^q\(0),
I4 => si_rs_arvalid,
I5 => \^q\(1),
O => \^axaddr_offset\(0)
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]\(1),
I1 => \m_payload_i_reg[50]\(2),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset\(1)
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[50]\(0),
I4 => \axlen_cnt_reg[6]\(0),
I5 => \^axlen_cnt_reg[5]\,
O => D(0)
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[50]\(1),
I2 => \axlen_cnt_reg[6]\(1),
I3 => \axlen_cnt_reg[6]\(0),
I4 => \^axlen_cnt_reg[5]\,
O => D(1)
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF282828"
)
port map (
I0 => \^axlen_cnt_reg[5]\,
I1 => \axlen_cnt_reg[6]\(2),
I2 => \axlen_cnt_reg[4]\,
I3 => \^e\(0),
I4 => \m_payload_i_reg[50]\(3),
O => D(2)
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF282828"
)
port map (
I0 => \^axlen_cnt_reg[5]\,
I1 => \axlen_cnt_reg[6]\(3),
I2 => \axlen_cnt_reg[3]\,
I3 => \^e\(0),
I4 => \m_payload_i_reg[50]\(4),
O => D(3)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_arvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[7]\,
O => \^axlen_cnt_reg[5]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => r_push_r_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_1,
O => sel_first_i
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg,
I5 => \cnt_read_reg[2]\,
O => next_state(0)
);
\state[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]\,
I1 => s_axburst_eq1_reg,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8A5575AA8A5545"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \^wrap_cnt_r_reg[0]\,
I5 => \^axaddr_offset\(0),
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6AA56AAAAAAAA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \^e\(0),
I3 => \^wrap_cnt_r_reg[0]\,
I4 => \^axaddr_offset\(0),
I5 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(3),
I1 => \^wrap_second_len_r_reg[3]\(1),
I2 => \wrap_cnt_r[3]_i_2__0_n_0\,
I3 => \^wrap_second_len_r_reg[3]\(2),
O => \wrap_cnt_r_reg[3]\(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"D1D1D1D1D1D1DFD1"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^e\(0),
I2 => \^axaddr_offset\(0),
I3 => \m_payload_i_reg[35]\,
I4 => \m_payload_i_reg[46]\(0),
I5 => \^axaddr_offset\(1),
O => \wrap_cnt_r[3]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8AAA8AAA8AAABA"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_arvalid,
I3 => \^q\(1),
I4 => \^wrap_cnt_r_reg[0]\,
I5 => \^axaddr_offset\(0),
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000404"
)
port map (
I0 => \^axaddr_offset\(0),
I1 => \m_payload_i_reg[35]\,
I2 => \m_payload_i_reg[46]\(0),
I3 => \^e\(0),
I4 => \axaddr_offset_r_reg[3]\(1),
I5 => \m_payload_i_reg[35]_0\,
O => \^wrap_cnt_r_reg[0]\
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE0FFFF0FE00000"
)
port map (
I0 => \^axaddr_offset\(1),
I1 => \m_payload_i_reg[46]\(0),
I2 => \m_payload_i_reg[35]\,
I3 => \^axaddr_offset\(0),
I4 => \^e\(0),
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CC2CFFFFCC2C0000"
)
port map (
I0 => \^axaddr_offset\(1),
I1 => \m_payload_i_reg[46]\(0),
I2 => \m_payload_i_reg[35]\,
I3 => \^axaddr_offset\(0),
I4 => \^e\(0),
I5 => \wrap_second_len_r_reg[3]_0\(2),
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF4FF44444444"
)
port map (
I0 => \^e\(0),
I1 => \wrap_second_len_r_reg[3]_0\(3),
I2 => \^axaddr_offset\(0),
I3 => \m_payload_i_reg[35]\,
I4 => \m_payload_i_reg[46]\(0),
I5 => \m_payload_i_reg[35]_0\,
O => \^wrap_second_len_r_reg[3]\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0_0\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bresp_push : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
shandshake_r : in STD_LOGIC;
b_push : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 8 downto 0 );
aclk : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
signal \^bresp_push\ : STD_LOGIC;
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_2__0_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_5_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_6_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_7_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][4]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][5]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][6]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][7]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair91";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 ";
attribute srl_bus_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 ";
attribute srl_bus_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 ";
attribute srl_bus_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
begin
bresp_push <= \^bresp_push\;
\cnt_read_reg[0]_rep_0\ <= \^cnt_read_reg[0]_rep_0\;
\cnt_read_reg[1]_rep__0_0\ <= \^cnt_read_reg[1]_rep__0_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => areset_d1,
I1 => \^bresp_push\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => bvalid_i_reg_0,
I2 => si_rs_bready,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[0]_rep_0\,
I1 => \^cnt_read_reg[1]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1_n_0\
);
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^bresp_push\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"DB24"
)
port map (
I0 => \^cnt_read_reg[0]_rep_0\,
I1 => shandshake_r,
I2 => b_push,
I3 => \^cnt_read_reg[1]_rep__0_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1_n_0\,
Q => \^cnt_read_reg[0]_rep_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__0_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_2__0_n_0\,
I1 => \memory_reg[3][0]_srl4_i_3_n_0\,
I2 => \memory_reg[3][0]_srl4_i_4_n_0\,
I3 => \memory_reg[3][0]_srl4_i_5_n_0\,
O => \^bresp_push\
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \bresp_cnt_reg[7]\(7),
I1 => \memory_reg[3][7]_srl4_n_0\,
I2 => \memory_reg[3][1]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(1),
I4 => \memory_reg[3][0]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(0),
O => \memory_reg[3][0]_srl4_i_2__0_n_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF22F2"
)
port map (
I0 => \bresp_cnt_reg[7]\(3),
I1 => \memory_reg[3][3]_srl4_n_0\,
I2 => \memory_reg[3][6]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(6),
I4 => \memory_reg[3][0]_srl4_i_6_n_0\,
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF4F4FFF4F"
)
port map (
I0 => \memory_reg[3][6]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(6),
I2 => mhandshake_r,
I3 => \memory_reg[3][3]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][0]_srl4_i_7_n_0\,
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][0]_srl4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"66F666F6FFFF66F6"
)
port map (
I0 => \bresp_cnt_reg[7]\(2),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \bresp_cnt_reg[7]\(4),
I3 => \memory_reg[3][4]_srl4_n_0\,
I4 => \memory_reg[3][5]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(5),
O => \memory_reg[3][0]_srl4_i_5_n_0\
);
\memory_reg[3][0]_srl4_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F44"
)
port map (
I0 => \memory_reg[3][5]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(5),
I2 => \bresp_cnt_reg[7]\(4),
I3 => \memory_reg[3][4]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_6_n_0\
);
\memory_reg[3][0]_srl4_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^cnt_read_reg[0]_rep_0\,
I1 => \^cnt_read_reg[1]_rep__0_0\,
O => \memory_reg[3][0]_srl4_i_7_n_0\
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \memory_reg[3][4]_srl4_n_0\
);
\memory_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \memory_reg[3][5]_srl4_n_0\
);
\memory_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \memory_reg[3][6]_srl4_n_0\
);
\memory_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \memory_reg[3][7]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
port (
s_bresp_acc : out STD_LOGIC;
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
bresp_push : in STD_LOGIC;
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^mhandshake\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair93";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair93";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
mhandshake <= \^mhandshake\;
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => shandshake_r,
I3 => bresp_push,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => bresp_push,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => bresp_push,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => \^mhandshake\
);
\s_bresp_acc[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"2020A220"
)
port map (
I0 => \^mhandshake\,
I1 => \in\(1),
I2 => m_axi_bresp(1),
I3 => m_axi_bresp(0),
I4 => \in\(0),
O => s_bresp_acc
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[4]_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair9";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair7";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair7";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \^wr_en0\,
I2 => s_ready_i_reg,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AA9AA"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[4]_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \^cnt_read_reg[3]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
port (
m_valid_i_reg : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
\skid_buffer_reg[35]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_ready_i_reg : in STD_LOGIC;
r_push_r : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__2_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_4__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5__0_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_4__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5__0\ : label is "soft_lutpair12";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => cnt_read(0),
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9AA6"
)
port map (
I0 => cnt_read(1),
I1 => s_ready_i_reg,
I2 => r_push_r,
I3 => cnt_read(0),
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA96AAA"
)
port map (
I0 => cnt_read(2),
I1 => cnt_read(1),
I2 => cnt_read(0),
I3 => r_push_r,
I4 => s_ready_i_reg,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => cnt_read(3),
I1 => cnt_read(0),
I2 => cnt_read(1),
I3 => cnt_read(2),
I4 => r_push_r,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => cnt_read(4),
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read[4]_i_4__0_n_0\,
I4 => \cnt_read[4]_i_5__0_n_0\,
I5 => cnt_read(3),
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => cnt_read(1),
I1 => cnt_read(2),
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => cnt_read(0),
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => r_push_r,
O => \cnt_read[4]_i_4__0_n_0\
);
\cnt_read[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => cnt_read(2),
I1 => cnt_read(1),
I2 => cnt_read(0),
O => \cnt_read[4]_i_5__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => cnt_read(4),
I1 => cnt_read(3),
I2 => \cnt_read[4]_i_5__0_n_0\,
I3 => \cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[3]_rep__2\,
I5 => \cnt_read_reg[0]_rep__2_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[35]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[35]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => cnt_read(2),
I2 => cnt_read(1),
I3 => cnt_read(0),
I4 => cnt_read(3),
I5 => cnt_read(4),
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
port (
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[0]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\next\ : out STD_LOGIC;
\axaddr_wrap_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[48]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[46]_0\ : in STD_LOGIC;
\axlen_cnt_reg[2]\ : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\cnt_read_reg[0]_rep\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[0]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair87";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair85";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair87";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair86";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
axaddr_offset(1 downto 0) <= \^axaddr_offset\(1 downto 0);
b_push <= \^b_push\;
incr_next_pending <= \^incr_next_pending\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\wrap_cnt_r_reg[0]\ <= \^wrap_cnt_r_reg[0]\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[3]\(3 downto 0) <= \^wrap_second_len_r_reg[3]\(3 downto 0);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAC0AAAA"
)
port map (
I0 => \axaddr_offset_r_reg[3]\(0),
I1 => \m_payload_i_reg[3]\,
I2 => \m_payload_i_reg[47]\(1),
I3 => \^q\(0),
I4 => si_rs_awvalid,
I5 => \^q\(1),
O => \^axaddr_offset\(0)
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]\(1),
I1 => \m_payload_i_reg[47]\(2),
I2 => \^q\(0),
I3 => si_rs_awvalid,
I4 => \^q\(1),
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset\(1)
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[47]\(1),
I4 => \axlen_cnt_reg[0]_0\(0),
I5 => \axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[0]\(0)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF04"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \^next\,
O => \axaddr_wrap_reg[0]\(0)
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^b_push\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA20AA200000AA20"
)
port map (
I0 => \^q\(0),
I1 => s_axburst_eq1_reg_0,
I2 => m_axi_awready,
I3 => \^q\(1),
I4 => \cnt_read_reg[1]_rep__0\,
I5 => \cnt_read_reg[0]_rep\,
O => \^b_push\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[4]\,
I3 => \^next\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[46]_0\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[2]\,
I3 => \^next\,
I4 => next_pending_r_reg_0,
O => \^wrap_next_pending\
);
next_pending_r_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBFFFF00B00000"
)
port map (
I0 => \cnt_read_reg[0]_rep\,
I1 => \cnt_read_reg[1]_rep__0\,
I2 => m_axi_awready,
I3 => s_axburst_eq1_reg_0,
I4 => \^q\(0),
I5 => \^q\(1),
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF04FFFFFF04FF04"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => areset_d1,
I4 => \^next\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44444F44"
)
port map (
I0 => \^next\,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44444F44"
)
port map (
I0 => \^next\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BBBA"
)
port map (
I0 => \state[0]_i_2_n_0\,
I1 => \^q\(0),
I2 => si_rs_awvalid,
I3 => \^q\(1),
O => next_state(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00F000F055750000"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \cnt_read_reg[1]_rep__0\,
I3 => \cnt_read_reg[0]_rep\,
I4 => \^q\(0),
I5 => \^q\(1),
O => \state[0]_i_2_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08000800FC000800"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => m_axi_awready,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \cnt_read_reg[1]_rep__0\,
I5 => \cnt_read_reg[0]_rep\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
O => \^e\(0)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8A5575AA8A5545"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_awvalid,
I3 => \^q\(1),
I4 => \^wrap_cnt_r_reg[0]\,
I5 => \^axaddr_offset\(0),
O => D(0)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA6AA56AAAAAAAA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \^e\(0),
I3 => \^wrap_cnt_r_reg[0]\,
I4 => \^axaddr_offset\(0),
I5 => \^wrap_second_len_r_reg[3]\(1),
O => D(1)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(3),
I1 => \^wrap_second_len_r_reg[3]\(1),
I2 => \wrap_cnt_r[3]_i_2_n_0\,
I3 => \^wrap_second_len_r_reg[3]\(2),
O => D(2)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"D1D1D1D1D1D1DFD1"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^e\(0),
I2 => \^axaddr_offset\(0),
I3 => \m_payload_i_reg[35]\,
I4 => \m_payload_i_reg[46]\(0),
I5 => \^axaddr_offset\(1),
O => \wrap_cnt_r[3]_i_2_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA8AAA8AAA8AAABA"
)
port map (
I0 => \wrap_second_len_r_reg[3]_0\(0),
I1 => \^q\(0),
I2 => si_rs_awvalid,
I3 => \^q\(1),
I4 => \^wrap_cnt_r_reg[0]\,
I5 => \^axaddr_offset\(0),
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000404"
)
port map (
I0 => \^axaddr_offset\(0),
I1 => \m_payload_i_reg[35]\,
I2 => \m_payload_i_reg[46]\(0),
I3 => \^e\(0),
I4 => \axaddr_offset_r_reg[3]\(1),
I5 => \m_payload_i_reg[35]_0\,
O => \^wrap_cnt_r_reg[0]\
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0FE0FFFF0FE00000"
)
port map (
I0 => \^axaddr_offset\(1),
I1 => \m_payload_i_reg[46]\(0),
I2 => \m_payload_i_reg[35]\,
I3 => \^axaddr_offset\(0),
I4 => \^e\(0),
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CC2CFFFFCC2C0000"
)
port map (
I0 => \^axaddr_offset\(1),
I1 => \m_payload_i_reg[46]\(0),
I2 => \m_payload_i_reg[35]\,
I3 => \^axaddr_offset\(0),
I4 => \^e\(0),
I5 => \wrap_second_len_r_reg[3]_0\(2),
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF4FF44444444"
)
port map (
I0 => \^e\(0),
I1 => \wrap_second_len_r_reg[3]_0\(3),
I2 => \^axaddr_offset\(0),
I3 => \m_payload_i_reg[35]\,
I4 => \m_payload_i_reg[46]\(0),
I5 => \m_payload_i_reg[35]_0\,
O => \^wrap_second_len_r_reg[3]\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 18 downto 0 );
\next\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of next_pending_r_i_3 : label is "soft_lutpair90";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0);
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => Q(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => Q(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => Q(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => wrap_cnt_r(2),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => wrap_cnt_r(1),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => Q(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => Q(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => Q(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => Q(12),
I2 => Q(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => Q(12),
I2 => Q(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => Q(13),
I2 => Q(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => Q(12),
I2 => Q(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => Q(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => Q(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => Q(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => Q(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => Q(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => Q(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_5_n_0\,
S(2) => \axaddr_wrap[11]_i_6_n_0\,
S(1) => \axaddr_wrap[11]_i_7_n_0\,
S(0) => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => Q(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[0]_i_1_n_0\
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => Q(16),
O => \axlen_cnt[1]_i_1_n_0\
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => Q(17),
O => \axlen_cnt[2]_i_1_n_0\
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => Q(18),
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[0]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[1]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[2]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \state_reg[0]\(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => Q(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => Q(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => Q(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => Q(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => Q(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => Q(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(1),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(1),
I3 => Q(14),
I4 => sel_first_reg_2,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => Q(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => Q(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => Q(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => Q(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => Q(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => Q(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => Q(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => Q(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => Q(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => Q(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => Q(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => Q(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => Q(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => Q(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => Q(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => Q(9),
O => m_axi_awaddr(9)
);
next_pending_r_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => Q(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"313D020E"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(0),
I1 => E(0),
I2 => \axaddr_offset_r_reg[3]_1\,
I3 => \m_payload_i_reg[35]\,
I4 => \^wrap_second_len_r_reg[3]_0\(1),
O => wrap_cnt(1)
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_cnt(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \^wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \^wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \^wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \^wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
port (
sel_first_reg_0 : out STD_LOGIC;
s_axburst_eq0_reg : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_arvalid : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
incr_next_pending : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_2__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair4";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\wrap_second_len_r_reg[3]_0\(3 downto 0) <= \^wrap_second_len_r_reg[3]_0\(3 downto 0);
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_2\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \wrap_cnt_r_reg_n_0_[2]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \wrap_cnt_r_reg_n_0_[1]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap[11]_i_5__0_n_0\,
S(2) => \axaddr_wrap[11]_i_6__0_n_0\,
S(1) => \axaddr_wrap[11]_i_7__0_n_0\,
S(0) => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[2]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[5]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(6),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[6]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEAAFEAE"
)
port map (
I0 => \m_payload_i_reg[47]_0\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep\,
I3 => \next_pending_r_i_2__2_n_0\,
I4 => E(0),
O => wrap_next_pending
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[1]\(0),
I1 => si_rs_arvalid,
I2 => \state_reg[1]\(1),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_2__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_n_0,
R => '0'
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(14),
I2 => sel_first_i,
I3 => incr_next_pending,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(14),
I2 => sel_first_i,
I3 => incr_next_pending,
O => s_axburst_eq1_reg
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"313D020E"
)
port map (
I0 => \^wrap_second_len_r_reg[3]_0\(0),
I1 => E(0),
I2 => \axaddr_offset_r_reg[3]_1\,
I3 => \m_payload_i_reg[35]\,
I4 => \^wrap_second_len_r_reg[3]_0\(1),
O => \wrap_cnt_r[1]_i_1__0_n_0\
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_cnt_r[1]_i_1__0_n_0\,
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \^wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \^wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \^wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \^wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 47 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first_0 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_3__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair13";
begin
Q(47 downto 0) <= \^q\(47 downto 0);
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_0,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_0,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_0,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_0,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_0,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_0,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_0,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_0,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
O => \axaddr_offset_r_reg[2]\(0)
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F7F00004F7FFFFF"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(40),
I3 => \axaddr_offset_r[1]_i_3__0_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[2]_0\(0),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_3__0_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"C808FFFFC8080000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(41),
I2 => \^q\(35),
I3 => \axaddr_offset_r[2]_i_3__0_n_0\,
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[2]_0\(1),
O => \axaddr_offset_r_reg[2]\(1)
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first_0,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__0_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__0_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1__0_n_0\
);
\m_payload_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__0_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__0_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[48]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[49]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFBBBB"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(43),
I1 => \^q\(45),
I2 => \^q\(44),
I3 => \^q\(46),
O => next_pending_r_reg_0
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \^q\(42),
I2 => \^q\(40),
I3 => \^q\(39),
I4 => \^q\(41),
O => next_pending_r_reg
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888028AAAAA028A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(41),
I3 => \^q\(40),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A222A882AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(41),
I5 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_3__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r_reg[3]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 47 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice_0 : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice_0;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 53 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_3\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair39";
begin
Q(47 downto 0) <= \^q\(47 downto 0);
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
O => D(0)
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F7F00004F7FFFFF"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(35),
I2 => \^q\(40),
I3 => \axaddr_offset_r[1]_i_3_n_0\,
I4 => \state_reg[1]\,
I5 => \axaddr_offset_r_reg[2]\(0),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_3_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"C808FFFFC8080000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(41),
I2 => \^q\(35),
I3 => \axaddr_offset_r[2]_i_3_n_0\,
I4 => \state_reg[1]\,
I5 => \axaddr_offset_r_reg[2]\(1),
O => D(1)
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[1]_0\(0),
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_0\(1),
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(43),
I2 => \^q\(44),
I3 => \^q\(46),
I4 => \^q\(45),
O => next_pending_r_reg
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_awvalid,
I1 => \^s_axi_awready\,
I2 => b_push,
I3 => \^m_valid_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888028AAAAA028A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(41),
I3 => \^q\(40),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A222A882AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(41),
I5 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_3_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r_reg[3]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_bid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \skid_buffer[1]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \skid_buffer[2]_i_1\ : label is "soft_lutpair65";
begin
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
s_axi_bid(0) <= \^s_axi_bid\(0);
s_axi_bresp(1 downto 0) <= \^s_axi_bresp\(1 downto 0);
s_axi_bvalid <= \^s_axi_bvalid\;
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB8B8B800B8B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^m_valid_i_reg_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
I5 => \^s_axi_bresp\(0),
O => \m_payload_i[0]_i_1_n_0\
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB8B8B800B8B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^m_valid_i_reg_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
I5 => \^s_axi_bresp\(1),
O => \m_payload_i[1]_i_1_n_0\
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB8B8B800B8B8"
)
port map (
I0 => \out\(0),
I1 => \^m_valid_i_reg_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
I5 => \^s_axi_bid\(0),
O => \m_payload_i[2]_i_1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i[0]_i_1_n_0\,
Q => \^s_axi_bresp\(0),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i[1]_i_1_n_0\,
Q => \^s_axi_bresp\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i[2]_i_1_n_0\,
Q => \^s_axi_bid\(0),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^m_valid_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^m_valid_i_reg_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\skid_buffer[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^m_valid_i_reg_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\skid_buffer[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^m_valid_i_reg_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => skid_buffer(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[0]\ : out STD_LOGIC;
UNCONN_OUT : out STD_LOGIC_VECTOR ( 35 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_0\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_2\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_valid_i_i_1__2\ : label is "soft_lutpair66";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]\,
O => \cnt_read_reg[0]\
);
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[35]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_2_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]_0\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => UNCONN_OUT(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => UNCONN_OUT(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => UNCONN_OUT(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => UNCONN_OUT(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__1_n_0\,
Q => UNCONN_OUT(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => UNCONN_OUT(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => UNCONN_OUT(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => UNCONN_OUT(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => UNCONN_OUT(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => UNCONN_OUT(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => UNCONN_OUT(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => UNCONN_OUT(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => UNCONN_OUT(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => UNCONN_OUT(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => UNCONN_OUT(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => UNCONN_OUT(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => UNCONN_OUT(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => UNCONN_OUT(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => UNCONN_OUT(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => UNCONN_OUT(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => UNCONN_OUT(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => UNCONN_OUT(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => UNCONN_OUT(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => UNCONN_OUT(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => UNCONN_OUT(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => UNCONN_OUT(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => UNCONN_OUT(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => UNCONN_OUT(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_2_n_0\,
Q => UNCONN_OUT(35),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => UNCONN_OUT(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => UNCONN_OUT(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => UNCONN_OUT(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => UNCONN_OUT(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => UNCONN_OUT(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => UNCONN_OUT(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => UNCONN_OUT(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__2_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__2_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]_0\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 8 downto 0 )
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_b_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_b_channel is
signal bid_fifo_0_n_4 : STD_LOGIC;
signal bid_fifo_0_n_5 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc : STD_LOGIC;
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair95";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_4,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bresp_push => bresp_push,
bvalid_i_reg => bid_fifo_0_n_5,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_rep_0\ => \cnt_read_reg[0]_rep\,
\cnt_read_reg[1]_rep__0_0\ => \cnt_read_reg[1]_rep__0\,
\in\(8 downto 0) => \in\(8 downto 0),
mhandshake_r => mhandshake_r,
\out\(0) => \out\(0),
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_4,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
bresp_push => bresp_push,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
s_bresp_acc => s_bresp_acc,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_5,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E2"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => s_bresp_acc,
I2 => m_axi_bresp(0),
I3 => bresp_push,
I4 => areset_d1,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E2"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[1]\,
I1 => s_bresp_acc,
I2 => m_axi_bresp(1),
I3 => bresp_push,
I4 => areset_d1,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
\state_reg[1]\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 23 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd
port map (
CO(0) => CO(0),
D(0) => D(0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(0) => \axlen_cnt_reg[3]\(0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[3]_0\ => \axlen_cnt_reg[3]_0\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[1]\ => incr_cmd_0_n_16,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(12 downto 9) => Q(23 downto 20),
\m_payload_i_reg[51]\(8 downto 7) => Q(18 downto 17),
\m_payload_i_reg[51]\(6 downto 4) => Q(14 downto 12),
\m_payload_i_reg[51]\(3 downto 0) => Q(3 downto 0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg,
sel_first_reg_0 => sel_first_reg_1,
\state_reg[0]\(0) => \state_reg[0]\(0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => Q(15),
I2 => s_axburst_eq0,
O => \state_reg[1]\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
port map (
E(0) => E(0),
Q(18 downto 14) => Q(19 downto 15),
Q(13 downto 0) => Q(13 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(2 downto 1) => \^axaddr_incr_reg[3]\(3 downto 2),
\axaddr_incr_reg[3]\(0) => \^axaddr_incr_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \axaddr_offset_r_reg[3]_1\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_2,
sel_first_reg_2 => incr_cmd_0_n_16,
\state_reg[0]\(0) => \state_reg[0]\(0),
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
port (
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
\axlen_cnt_reg[5]\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_arvalid : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[48]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC;
\m_payload_i_reg[35]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_20 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
signal wrap_cmd_0_n_1 : STD_LOGIC;
signal wrap_cmd_0_n_2 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair5";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]_0\(6 downto 2) => axaddr_incr_reg(11 downto 7),
\axaddr_incr_reg[11]_0\(1 downto 0) => axaddr_incr_reg(5 downto 4),
\axaddr_incr_reg[11]_1\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[5]_0\ => \axlen_cnt_reg[5]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\,
incr_next_pending => incr_next_pending,
\m_axi_araddr[6]\ => incr_cmd_0_n_20,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[51]\(10 downto 9) => \m_payload_i_reg[51]\(21 downto 20),
\m_payload_i_reg[51]\(8) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(7 downto 5) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(4) => \m_payload_i_reg[51]\(6),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_cmd_0_n_1,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_cmd_0_n_2,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(6 downto 2) => axaddr_incr_reg(11 downto 7),
\axaddr_incr_reg[11]\(1 downto 0) => axaddr_incr_reg(5 downto 4),
\axaddr_incr_reg[3]\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \axaddr_offset_r_reg[3]_1\(3 downto 0),
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
s_axburst_eq0_reg => wrap_cmd_0_n_1,
s_axburst_eq1_reg => wrap_cmd_0_n_2,
sel_first_i => sel_first_i,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
sel_first_reg_2 => incr_cmd_0_n_20,
si_rs_arvalid => si_rs_arvalid,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_r_channel is
port (
m_valid_i_reg : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[35]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_arid_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_r_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 1 downto 0 );
signal transaction_fifo_0_n_2 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => s_arid_r,
Q => trans_in(1),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_2,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[0]_rep__2_0\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(1 downto 0) => trans_in(1 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[35]\(1 downto 0) => \skid_buffer_reg[35]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 47 downto 0 );
\s_arid_r_reg[0]\ : out STD_LOGIC_VECTOR ( 47 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[1]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC;
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\cnt_read_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[0]_0\ : out STD_LOGIC;
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
UNCONN_OUT : out STD_LOGIC_VECTOR ( 35 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
\cnt_read_reg[4]\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
b_push : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[2]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_0 : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_0\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_81 : STD_LOGIC;
begin
ar_pipe: entity work.zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice
port map (
Q(47 downto 0) => \s_arid_r_reg[0]\(47 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_81,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
\axaddr_offset_r_reg[0]\ => \axaddr_offset_r_reg[0]_0\,
\axaddr_offset_r_reg[1]\ => \axaddr_offset_r_reg[1]_0\,
\axaddr_offset_r_reg[2]\(1 downto 0) => \axaddr_offset_r_reg[2]\(1 downto 0),
\axaddr_offset_r_reg[2]_0\(1 downto 0) => \axaddr_offset_r_reg[2]_1\(1 downto 0),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i_reg_0 => ar_pipe_n_2,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_1,
next_pending_r_reg_0 => next_pending_r_reg_2,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_0 => sel_first_0,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_second_len_r_reg[3]\ => \wrap_second_len_r_reg[3]_0\
);
aw_pipe: entity work.zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice_0
port map (
CO(0) => CO(0),
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(47 downto 0) => Q(47 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_81,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
\axaddr_offset_r_reg[0]\ => \axaddr_offset_r_reg[0]\,
\axaddr_offset_r_reg[1]\ => \axaddr_offset_r_reg[1]\,
\axaddr_offset_r_reg[2]\(1 downto 0) => \axaddr_offset_r_reg[2]_0\(1 downto 0),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]\,
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
next_pending_r_reg_0 => next_pending_r_reg_0,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[1]\ => \state_reg[1]\,
\state_reg[1]_0\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_second_len_r_reg[3]\ => \wrap_second_len_r_reg[3]\
);
b_pipe: entity work.\zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
m_valid_i_reg_0 => si_rs_bready,
\out\(0) => \out\(0),
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid
);
r_pipe: entity work.\zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
UNCONN_OUT(35 downto 0) => UNCONN_OUT(35 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[0]\ => \cnt_read_reg[0]\,
\cnt_read_reg[4]\ => \cnt_read_reg[4]\,
\cnt_read_reg[4]_0\(33 downto 0) => \cnt_read_reg[4]_0\(33 downto 0),
r_push_r_reg(1 downto 0) => r_push_r_reg(1 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_ar_channel is
port (
s_arid_r : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 24 downto 0 );
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[2]\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[47]_0\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[48]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_ar_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_ar_channel is
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_11 : STD_LOGIC;
signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
signal ar_cmd_fsm_0_n_13 : STD_LOGIC;
signal ar_cmd_fsm_0_n_14 : STD_LOGIC;
signal ar_cmd_fsm_0_n_22 : STD_LOGIC;
signal ar_cmd_fsm_0_n_23 : STD_LOGIC;
signal ar_cmd_fsm_0_n_26 : STD_LOGIC;
signal ar_cmd_fsm_0_n_27 : STD_LOGIC;
signal ar_cmd_fsm_0_n_6 : STD_LOGIC;
signal ar_cmd_fsm_0_n_7 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_14 : STD_LOGIC;
signal cmd_translator_0_n_15 : STD_LOGIC;
signal cmd_translator_0_n_6 : STD_LOGIC;
signal cmd_translator_0_n_7 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
r_push_r_reg <= \^r_push_r_reg\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
ar_cmd_fsm_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
port map (
D(3) => ar_cmd_fsm_0_n_6,
D(2) => ar_cmd_fsm_0_n_7,
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => state(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_23,
axaddr_offset(1) => \wrap_cmd_0/axaddr_offset\(3),
axaddr_offset(0) => \wrap_cmd_0/axaddr_offset\(0),
\axaddr_offset_r_reg[3]\(1) => \wrap_cmd_0/axaddr_offset_r\(3),
\axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axaddr_wrap_reg[11]\(0) => ar_cmd_fsm_0_n_22,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_11,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[5]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[6]\(3) => cmd_translator_0_n_7,
\axlen_cnt_reg[6]\(2) => cmd_translator_0_n_8,
\axlen_cnt_reg[6]\(1) => cmd_translator_0_n_9,
\axlen_cnt_reg[6]\(0) => cmd_translator_0_n_10,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_12,
\cnt_read_reg[2]\ => \cnt_read_reg[2]\,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \m_payload_i_reg[0]\,
\m_payload_i_reg[0]_0\ => \m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[35]_0\ => \m_payload_i_reg[35]_0\,
\m_payload_i_reg[3]\ => \m_payload_i_reg[3]\,
\m_payload_i_reg[46]\(0) => \m_payload_i_reg[46]\(1),
\m_payload_i_reg[50]\(4 downto 3) => Q(22 downto 21),
\m_payload_i_reg[50]\(2) => Q(19),
\m_payload_i_reg[50]\(1 downto 0) => Q(17 downto 16),
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq1_reg => cmd_translator_0_n_14,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_26,
sel_first_reg_0 => ar_cmd_fsm_0_n_27,
sel_first_reg_1 => cmd_translator_0_n_0,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_6,
si_rs_arvalid => si_rs_arvalid,
\wrap_cnt_r_reg[0]\ => ar_cmd_fsm_0_n_14,
\wrap_cnt_r_reg[3]\(2) => ar_cmd_fsm_0_n_11,
\wrap_cnt_r_reg[3]\(1) => ar_cmd_fsm_0_n_12,
\wrap_cnt_r_reg[3]\(0) => ar_cmd_fsm_0_n_13,
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_cmd_0/wrap_second_len\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_cmd_0/wrap_second_len_r\(3 downto 0)
);
cmd_translator_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(3) => ar_cmd_fsm_0_n_6,
D(2) => ar_cmd_fsm_0_n_7,
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(3) => cmd_translator_0_n_7,
Q(2) => cmd_translator_0_n_8,
Q(1) => cmd_translator_0_n_9,
Q(0) => cmd_translator_0_n_10,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3) => \wrap_cmd_0/axaddr_offset_r\(3),
\axaddr_offset_r_reg[3]\(2 downto 1) => \axaddr_offset_r_reg[2]\(1 downto 0),
\axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axaddr_offset_r_reg[3]_0\ => ar_cmd_fsm_0_n_14,
\axaddr_offset_r_reg[3]_1\(3) => \wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_1\(2 downto 1) => \m_payload_i_reg[46]\(1 downto 0),
\axaddr_offset_r_reg[3]_1\(0) => \wrap_cmd_0/axaddr_offset\(0),
\axlen_cnt_reg[5]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_11,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[47]_0\ => \m_payload_i_reg[47]_0\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[51]\(21) => Q(23),
\m_payload_i_reg[51]\(20 downto 0) => Q(20 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => D(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_22,
next_pending_r_reg => cmd_translator_0_n_12,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_0,
sel_first_reg_1 => cmd_translator_0_n_6,
sel_first_reg_2 => ar_cmd_fsm_0_n_23,
sel_first_reg_3 => ar_cmd_fsm_0_n_26,
sel_first_reg_4 => ar_cmd_fsm_0_n_27,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]\ => ar_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_14,
\state_reg[1]\(1 downto 0) => state(1 downto 0),
\state_reg[1]_rep\ => \^r_push_r_reg\,
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_cmd_0/wrap_second_len_r\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_cmd_0/wrap_second_len\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(2) => ar_cmd_fsm_0_n_11,
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_12,
\wrap_second_len_r_reg[3]_1\(0) => ar_cmd_fsm_0_n_13
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(24),
Q => s_arid_r,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_aw_channel is
port (
\in\ : out STD_LOGIC_VECTOR ( 8 downto 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
sel_first_reg : out STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[2]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 24 downto 0 );
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
si_rs_awvalid : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC;
\m_payload_i_reg[35]_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[48]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\cnt_read_reg[0]_rep\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_aw_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_aw_channel is
signal aw_cmd_fsm_0_n_14 : STD_LOGIC;
signal aw_cmd_fsm_0_n_18 : STD_LOGIC;
signal aw_cmd_fsm_0_n_20 : STD_LOGIC;
signal aw_cmd_fsm_0_n_24 : STD_LOGIC;
signal aw_cmd_fsm_0_n_25 : STD_LOGIC;
signal aw_cmd_fsm_0_n_5 : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wrap_next_pending : STD_LOGIC;
begin
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
aw_cmd_fsm_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
port map (
D(2 downto 1) => wrap_cnt(3 downto 2),
D(0) => wrap_cnt(0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => sel_first_reg(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
axaddr_offset(1) => \wrap_cmd_0/axaddr_offset\(3),
axaddr_offset(0) => \wrap_cmd_0/axaddr_offset\(0),
\axaddr_offset_r_reg[3]\(1) => \wrap_cmd_0/axaddr_offset_r\(3),
\axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axaddr_wrap_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\axlen_cnt_reg[0]\(0) => p_1_in(0),
\axlen_cnt_reg[0]_0\(0) => cmd_translator_0_n_9,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_12,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_10,
b_push => b_push,
\cnt_read_reg[0]_rep\ => \cnt_read_reg[0]_rep\,
\cnt_read_reg[1]_rep__0\ => \cnt_read_reg[1]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\(0) => E(0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[35]_0\ => \m_payload_i_reg[35]_0\,
\m_payload_i_reg[3]\ => \m_payload_i_reg[3]\,
\m_payload_i_reg[46]\(0) => D(1),
\m_payload_i_reg[46]_0\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\(2) => Q(19),
\m_payload_i_reg[47]\(1 downto 0) => Q(16 downto 15),
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_14,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_18,
s_axburst_eq1_reg_0 => cmd_translator_0_n_11,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_24,
sel_first_reg_0 => aw_cmd_fsm_0_n_25,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\wrap_cnt_r_reg[0]\ => aw_cmd_fsm_0_n_5,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_cmd_0/wrap_second_len\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_cmd_0/wrap_second_len_r\(3 downto 0)
);
cmd_translator_0: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(0) => p_1_in(0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(23 downto 0) => Q(23 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3) => \wrap_cmd_0/axaddr_offset_r\(3),
\axaddr_offset_r_reg[3]\(2 downto 1) => \axaddr_offset_r_reg[2]\(1 downto 0),
\axaddr_offset_r_reg[3]\(0) => \wrap_cmd_0/axaddr_offset_r\(0),
\axaddr_offset_r_reg[3]_0\ => aw_cmd_fsm_0_n_5,
\axaddr_offset_r_reg[3]_1\(3) => \wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_1\(2 downto 1) => D(1 downto 0),
\axaddr_offset_r_reg[3]_1\(0) => \wrap_cmd_0/axaddr_offset\(0),
\axlen_cnt_reg[3]\(0) => cmd_translator_0_n_9,
\axlen_cnt_reg[3]_0\ => cmd_translator_0_n_10,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[35]\ => \m_payload_i_reg[35]\,
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_14,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_18,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_12,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_24,
sel_first_reg_2 => aw_cmd_fsm_0_n_25,
\state_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\state_reg[1]\ => cmd_translator_0_n_11,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 0) => \wrap_cmd_0/wrap_second_len_r\(3 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => wrap_cnt(0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_cmd_0/wrap_second_len\(3 downto 0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(24),
Q => \in\(8),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(19),
Q => \in\(3),
R => '0'
);
\s_awlen_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(20),
Q => \in\(4),
R => '0'
);
\s_awlen_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(21),
Q => \in\(5),
R => '0'
);
\s_awlen_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(22),
Q => \in\(6),
R => '0'
);
\s_awlen_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => Q(23),
Q => \in\(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
UNCONN_OUT : out STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bready : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_27\ : STD_LOGIC;
signal \RD.ar_channel_0_n_28\ : STD_LOGIC;
signal \RD.ar_channel_0_n_29\ : STD_LOGIC;
signal \RD.ar_channel_0_n_30\ : STD_LOGIC;
signal \RD.ar_channel_0_n_6\ : STD_LOGIC;
signal \RD.ar_channel_0_n_7\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_1\ : STD_LOGIC;
signal SI_REG_n_10 : STD_LOGIC;
signal SI_REG_n_11 : STD_LOGIC;
signal SI_REG_n_112 : STD_LOGIC;
signal SI_REG_n_113 : STD_LOGIC;
signal SI_REG_n_114 : STD_LOGIC;
signal SI_REG_n_115 : STD_LOGIC;
signal SI_REG_n_116 : STD_LOGIC;
signal SI_REG_n_117 : STD_LOGIC;
signal SI_REG_n_118 : STD_LOGIC;
signal SI_REG_n_119 : STD_LOGIC;
signal SI_REG_n_12 : STD_LOGIC;
signal SI_REG_n_120 : STD_LOGIC;
signal SI_REG_n_121 : STD_LOGIC;
signal SI_REG_n_122 : STD_LOGIC;
signal SI_REG_n_123 : STD_LOGIC;
signal SI_REG_n_124 : STD_LOGIC;
signal SI_REG_n_125 : STD_LOGIC;
signal SI_REG_n_126 : STD_LOGIC;
signal SI_REG_n_127 : STD_LOGIC;
signal SI_REG_n_128 : STD_LOGIC;
signal SI_REG_n_129 : STD_LOGIC;
signal SI_REG_n_132 : STD_LOGIC;
signal SI_REG_n_133 : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_150 : STD_LOGIC;
signal SI_REG_n_151 : STD_LOGIC;
signal SI_REG_n_152 : STD_LOGIC;
signal SI_REG_n_153 : STD_LOGIC;
signal SI_REG_n_154 : STD_LOGIC;
signal SI_REG_n_155 : STD_LOGIC;
signal SI_REG_n_156 : STD_LOGIC;
signal SI_REG_n_157 : STD_LOGIC;
signal SI_REG_n_158 : STD_LOGIC;
signal SI_REG_n_159 : STD_LOGIC;
signal SI_REG_n_160 : STD_LOGIC;
signal SI_REG_n_161 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_18 : STD_LOGIC;
signal SI_REG_n_57 : STD_LOGIC;
signal SI_REG_n_58 : STD_LOGIC;
signal SI_REG_n_59 : STD_LOGIC;
signal SI_REG_n_60 : STD_LOGIC;
signal SI_REG_n_66 : STD_LOGIC;
signal SI_REG_n_9 : STD_LOGIC;
signal \WR.aw_channel_0_n_14\ : STD_LOGIC;
signal \WR.aw_channel_0_n_34\ : STD_LOGIC;
signal \WR.aw_channel_0_n_35\ : STD_LOGIC;
signal \WR.aw_channel_0_n_36\ : STD_LOGIC;
signal \WR.aw_channel_0_n_37\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC;
signal b_awlen : STD_LOGIC_VECTOR ( 7 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_2\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 2 downto 1 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_1\ : STD_LOGIC_VECTOR ( 2 downto 1 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC;
signal s_arid_r : STD_LOGIC;
signal s_awid : STD_LOGIC;
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC;
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC;
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\RD.ar_channel_0\: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_ar_channel
port map (
CO(0) => SI_REG_n_125,
D(6) => SI_REG_n_155,
D(5) => SI_REG_n_156,
D(4) => SI_REG_n_157,
D(3) => SI_REG_n_158,
D(2) => SI_REG_n_159,
D(1) => SI_REG_n_160,
D(0) => SI_REG_n_161,
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_126,
O(2) => SI_REG_n_127,
O(1) => SI_REG_n_128,
O(0) => SI_REG_n_129,
Q(24) => s_arid,
Q(23) => SI_REG_n_57,
Q(22) => SI_REG_n_58,
Q(21) => SI_REG_n_59,
Q(20) => SI_REG_n_60,
Q(19 downto 16) => si_rs_arlen(3 downto 0),
Q(15) => si_rs_arburst(1),
Q(14) => SI_REG_n_66,
Q(13 downto 12) => si_rs_arsize(1 downto 0),
Q(11 downto 0) => si_rs_araddr(11 downto 0),
S(3) => \RD.ar_channel_0_n_27\,
S(2) => \RD.ar_channel_0_n_28\,
S(1) => \RD.ar_channel_0_n_29\,
S(0) => \RD.ar_channel_0_n_30\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_offset_r_reg[2]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(2 downto 1),
\cnt_read_reg[2]\ => \RD.r_channel_0_n_1\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_8\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[11]\(3) => SI_REG_n_121,
\m_payload_i_reg[11]\(2) => SI_REG_n_122,
\m_payload_i_reg[11]\(1) => SI_REG_n_123,
\m_payload_i_reg[11]\(0) => SI_REG_n_124,
\m_payload_i_reg[35]\ => SI_REG_n_139,
\m_payload_i_reg[35]_0\ => SI_REG_n_141,
\m_payload_i_reg[38]\ => SI_REG_n_164,
\m_payload_i_reg[3]\ => SI_REG_n_162,
\m_payload_i_reg[3]_0\(3) => SI_REG_n_117,
\m_payload_i_reg[3]_0\(2) => SI_REG_n_118,
\m_payload_i_reg[3]_0\(1) => SI_REG_n_119,
\m_payload_i_reg[3]_0\(0) => SI_REG_n_120,
\m_payload_i_reg[46]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 1),
\m_payload_i_reg[47]\ => SI_REG_n_142,
\m_payload_i_reg[47]_0\ => SI_REG_n_140,
\m_payload_i_reg[48]\ => SI_REG_n_143,
\m_payload_i_reg[6]\ => SI_REG_n_154,
r_push_r_reg => \RD.ar_channel_0_n_7\,
r_rlast => r_rlast,
s_arid_r => s_arid_r,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_6\
);
\RD.r_channel_0\: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_r_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_0\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_arid_r => s_arid_r,
s_ready_i_reg => SI_REG_n_144,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[35]\(1) => si_rs_rid,
\skid_buffer_reg[35]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_1\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_7\
);
SI_REG: entity work.zqynq_lab_1_design_auto_pc_1_axi_register_slice_v2_1_13_axi_register_slice
port map (
CO(0) => SI_REG_n_112,
D(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_113,
O(2) => SI_REG_n_114,
O(1) => SI_REG_n_115,
O(0) => SI_REG_n_116,
Q(47) => s_awid,
Q(46) => SI_REG_n_9,
Q(45) => SI_REG_n_10,
Q(44) => SI_REG_n_11,
Q(43) => SI_REG_n_12,
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_18,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_34\,
S(2) => \WR.aw_channel_0_n_35\,
S(1) => \WR.aw_channel_0_n_36\,
S(0) => \WR.aw_channel_0_n_37\,
UNCONN_OUT(35 downto 0) => UNCONN_OUT(35 downto 0),
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_3\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_121,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_122,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_123,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_124,
\axaddr_incr_reg[3]\(3) => SI_REG_n_126,
\axaddr_incr_reg[3]\(2) => SI_REG_n_127,
\axaddr_incr_reg[3]\(1) => SI_REG_n_128,
\axaddr_incr_reg[3]\(0) => SI_REG_n_129,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_117,
\axaddr_incr_reg[7]\(2) => SI_REG_n_118,
\axaddr_incr_reg[7]\(1) => SI_REG_n_119,
\axaddr_incr_reg[7]\(0) => SI_REG_n_120,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_125,
\axaddr_offset_r_reg[0]\ => SI_REG_n_153,
\axaddr_offset_r_reg[0]_0\ => SI_REG_n_162,
\axaddr_offset_r_reg[1]\ => SI_REG_n_132,
\axaddr_offset_r_reg[1]_0\ => SI_REG_n_139,
\axaddr_offset_r_reg[2]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 1),
\axaddr_offset_r_reg[2]_0\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_1\(2 downto 1),
\axaddr_offset_r_reg[2]_1\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(2 downto 1),
\axaddr_offset_r_reg[3]\ => SI_REG_n_145,
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_154,
\axlen_cnt_reg[3]\ => SI_REG_n_134,
\axlen_cnt_reg[3]_0\ => SI_REG_n_142,
b_push => b_push,
\cnt_read_reg[0]\ => SI_REG_n_144,
\cnt_read_reg[4]\ => \RD.r_channel_0_n_0\,
\cnt_read_reg[4]_0\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]_0\(31 downto 0) => si_rs_rdata(31 downto 0),
\m_axi_araddr[10]\ => SI_REG_n_164,
\m_axi_awaddr[10]\ => SI_REG_n_163,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_27\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_28\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_29\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_30\,
m_valid_i_reg(0) => \ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_135,
next_pending_r_reg_0 => SI_REG_n_136,
next_pending_r_reg_1 => SI_REG_n_140,
next_pending_r_reg_2 => SI_REG_n_143,
\out\(0) => si_rs_bid,
r_push_r_reg(1) => si_rs_rid,
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[0]\(47) => s_arid,
\s_arid_r_reg[0]\(46) => SI_REG_n_57,
\s_arid_r_reg[0]\(45) => SI_REG_n_58,
\s_arid_r_reg[0]\(44) => SI_REG_n_59,
\s_arid_r_reg[0]\(43) => SI_REG_n_60,
\s_arid_r_reg[0]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[0]\(38) => si_rs_arburst(1),
\s_arid_r_reg[0]\(37) => SI_REG_n_66,
\s_arid_r_reg[0]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[0]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[0]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_2\,
sel_first_0 => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\ => \WR.aw_channel_0_n_14\,
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \RD.ar_channel_0_n_6\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_8\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_146,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_147,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_148,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_149,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_150,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_151,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_152,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_155,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_156,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_157,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_158,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_159,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_160,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_161,
\wrap_second_len_r_reg[3]\ => SI_REG_n_133,
\wrap_second_len_r_reg[3]_0\ => SI_REG_n_141
);
\WR.aw_channel_0\: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_aw_channel
port map (
CO(0) => SI_REG_n_112,
D(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_113,
O(2) => SI_REG_n_114,
O(1) => SI_REG_n_115,
O(0) => SI_REG_n_116,
Q(24) => s_awid,
Q(23) => SI_REG_n_9,
Q(22) => SI_REG_n_10,
Q(21) => SI_REG_n_11,
Q(20) => SI_REG_n_12,
Q(19 downto 16) => si_rs_awlen(3 downto 0),
Q(15) => si_rs_awburst(1),
Q(14) => SI_REG_n_18,
Q(13 downto 12) => si_rs_awsize(1 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_34\,
S(2) => \WR.aw_channel_0_n_35\,
S(1) => \WR.aw_channel_0_n_36\,
S(0) => \WR.aw_channel_0_n_37\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_3\(3 downto 0),
\axaddr_offset_r_reg[2]\(1 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_1\(2 downto 1),
b_push => b_push,
\cnt_read_reg[0]_rep\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\,
\in\(8) => b_awid,
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[35]\ => SI_REG_n_132,
\m_payload_i_reg[35]_0\ => SI_REG_n_133,
\m_payload_i_reg[38]\ => SI_REG_n_163,
\m_payload_i_reg[3]\ => SI_REG_n_153,
\m_payload_i_reg[46]\ => SI_REG_n_136,
\m_payload_i_reg[47]\ => SI_REG_n_134,
\m_payload_i_reg[48]\ => SI_REG_n_135,
\m_payload_i_reg[6]\ => SI_REG_n_145,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_146,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_147,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_148,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_149,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_150,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_151,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_152,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_2\,
sel_first_reg(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
si_rs_awvalid => si_rs_awvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_14\
);
\WR.b_channel_0\: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__0\ => \WR.b_channel_0_n_2\,
\in\(8) => b_awid,
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(0) => si_rs_bid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
UNCONN_OUT(35) => s_axi_rid(0),
UNCONN_OUT(34) => s_axi_rlast,
UNCONN_OUT(33 downto 32) => s_axi_rresp(1 downto 0),
UNCONN_OUT(31 downto 0) => s_axi_rdata(31 downto 0),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_auto_pc_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_auto_pc_1 : entity is "zqynq_lab_1_design_auto_pc_1,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_auto_pc_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zqynq_lab_1_design_auto_pc_1 : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end zqynq_lab_1_design_auto_pc_1;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_1 is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 1;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.zqynq_lab_1_design_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_inst_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_inst_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(0) => '0',
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(0) => '0',
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(0) => NLW_inst_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => NLW_inst_s_axi_bid_UNCONNECTED(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_inst_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(0) => '0',
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_1_1/synth/zqynq_lab_1_design_axi_gpio_1_1.vhd | 1 | 9956 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_15;
USE axi_gpio_v2_0_15.axi_gpio;
ENTITY zqynq_lab_1_design_axi_gpio_1_1 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END zqynq_lab_1_design_axi_gpio_1_1;
ARCHITECTURE zqynq_lab_1_design_axi_gpio_1_1_arch OF zqynq_lab_1_design_axi_gpio_1_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_gpio_1_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zqynq_lab_1_design_axi_gpio_1_1_arch: ARCHITECTURE IS "axi_gpio,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zqynq_lab_1_design_axi_gpio_1_1_arch : ARCHITECTURE IS "zqynq_lab_1_design_axi_gpio_1_1,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zqynq_lab_1_design_axi_gpio_1_1_arch: ARCHITECTURE IS "zqynq_lab_1_design_axi_gpio_1_1,axi_gpio,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=5,C_GPIO2_WIDTH=32,C_ALL_INPUTS=1,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 5,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => gpio_io_i,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END zqynq_lab_1_design_axi_gpio_1_1_arch;
| mit |
khaledhassan/vhdl-examples | multiplexer/mux_2x1.vhd | 1 | 1798 | -- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Multiplexer 2:1
-- Implements a 2-to-1 multiplexer of a given width.
library ieee;
use ieee.std_logic_1164.all;
entity mux_2x1 is
generic (
WIDTH : positive := 1
);
port (
output : out std_logic_vector(WIDTH-1 downto 0);
sel : in std_logic;
in0 : in std_logic_vector(WIDTH-1 downto 0);
in1 : in std_logic_vector(WIDTH-1 downto 0)
);
end mux_2x1;
architecture BHV of mux_2x1 is
begin
output <=
in0 when sel = '0' else
in1 when sel = '1' else
(others => '0');
end BHV;
| mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-2/src/structure/prim/NOT.vhd | 2 | 176 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity NOT1 is port(
a: in std_logic;
z: out std_logic
);
end NOT1;
--
architecture NOT1 of NOT1 is
begin
z <= not a;
end NOT1; | mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-2/src/structure/prim/AND2.vhd | 2 | 179 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity AND2 is port(
a,b: in std_logic;
z: out std_logic
);
end AND2;
--
architecture AND2 of AND2 is
begin
z <=a and b;
end AND2; | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/ip/tmp.srcs/sources_1/ip/convolve_kernel_ap_fadd_7_full_dsp_32/hdl/xbip_utils_v3_0_vh_rfs.vhd | 7 | 171224 | `protect begin_protected
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`protect end_protected
| mit |
SumejjaPorca/PeekaBooCode | bower_components/bower_components/ace-builds/demo/kitchen-sink/docs/vhdl.vhd | 472 | 830 | library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
| mit |
dawsonjon/FPGA-TX | fpga_tx/bsp/cmod_a7_15/bsp.vhd | 2 | 14973 | -------------------------------------------------------------------------------
---
--- FPGA TX - FPGA Based Radio Transmitter
---
--- :Author: Jonathan P Dawson
--- :Date: 04/04/2014
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2014
---
--------------------------------------------------------------------------------
---
--- +--------------+
--- | CLOCK TREE |
--- +--------------+
--- | >-- CLK1 (50MHz) ---> CLK
--- CLK_IN >--> |
--- | >-- CLK2 (100MHz)
--- | | +-------+
--- | +-- CLK3 (125MHz) ->+ ODDR2 +-->[GTXCLK]
--- | | | |
--- | +-- CLK3_N (125MHZ) ->+ |
--- | | +-------+
--- RST >-----> >-- CLK4 (200MHz)
--- | |
--- | |
--- | | CLK >--+--------+
--- | | | |
--- | | +--v-+ +--v-+
--- | | | | | |
--- | LOCKED >------> >---> >-------> INTERNAL_RESET
--- | | | | | |
--- +--------------+ +----+ +----+
---
--- +-------------+
--- | USER DESIGN |
--- +-------------+
--- | |
--- | >-------> RF OUT
--- | |
--- | | +--------------+
--- | | | UART |
--- | | +--------------+
--- | >-----> >-----> RS232-TX
--- | | | |
--- | | | <-------< RS232-RX
--- +-------------+ +--------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity bsp is
port(
clk_in : in std_logic;
rst : in std_logic;
rf_out : out std_logic;
leds : out std_logic_vector(7 downto 0);
gps_tx : in std_logic;
gps_rx : out std_logic;
pps : in std_logic;
tx_rx : out std_logic;
tx_pa : out std_logic;
ld1 : out std_logic;
--rs232 interface
rs232_rx : in std_logic;
rs232_tx : out std_logic
);
end entity bsp;
architecture rtl of bsp is
component transmitter is
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
frequency_stb : in std_logic;
frequency_ack : out std_logic;
control : in std_logic_vector(31 downto 0);
control_stb : in std_logic;
control_ack : out std_logic;
amplitude : in std_logic_vector(31 downto 0);
amplitude_stb : in std_logic;
amplitude_ack : out std_logic;
rf : out std_logic;
tx_rx : out std_logic;
tx_pa : out std_logic
);
end component transmitter;
component user_design is
port(
clk : in std_logic;
rst : in std_logic;
output_tx_freq : out std_logic_vector(31 downto 0);
output_tx_freq_stb : out std_logic;
output_tx_freq_ack : in std_logic;
output_tx_am : out std_logic_vector(31 downto 0);
output_tx_am_stb : out std_logic;
output_tx_am_ack : in std_logic;
output_tx_ctl : out std_logic_vector(31 downto 0);
output_tx_ctl_stb : out std_logic;
output_tx_ctl_ack : in std_logic;
output_leds : out std_logic_vector(31 downto 0);
output_leds_stb : out std_logic;
output_leds_ack : in std_logic;
--gps pps count
input_gps_count : in std_logic_vector(31 downto 0);
input_gps_count_stb : in std_logic;
input_gps_count_ack : out std_logic;
--gps rx stream
input_gps_rx : in std_logic_vector(31 downto 0);
input_gps_rx_stb : in std_logic;
input_gps_rx_ack : out std_logic;
--gps tx stream
output_gps_tx : out std_logic_vector(31 downto 0);
output_gps_tx_stb : out std_logic;
output_gps_tx_ack : in std_logic;
--rs232 rx stream
input_rs232_rx : in std_logic_vector(31 downto 0);
input_rs232_rx_stb : in std_logic;
input_rs232_rx_ack : out std_logic;
--rs232 tx stream
output_rs232_tx : out std_logic_vector(31 downto 0);
output_rs232_tx_stb : out std_logic;
output_rs232_tx_ack : in std_logic
);
end component;
component serial_input is
generic(
clock_frequency : integer;
baud_rate : integer
);
port(
clk : in std_logic;
rst : in std_logic;
rx : in std_logic;
out1 : out std_logic_vector(7 downto 0);
out1_stb : out std_logic;
out1_ack : in std_logic
);
end component serial_input;
component serial_output is
generic(
clock_frequency : integer;
baud_rate : integer
);
port(
clk : in std_logic;
rst : in std_logic;
tx : out std_logic;
in1 : in std_logic_vector(7 downto 0);
in1_stb : in std_logic;
in1_ack : out std_logic
);
end component serial_output;
component gps_pps
port(
clk : in std_logic;
pps : in std_logic;
pps_count : out std_logic_vector(31 downto 0);
pps_count_stb : out std_logic;
pps_count_ack : in std_logic);
end component gps_pps;
--clock tree signals
signal clk : std_logic;
signal clkin1 : std_logic;
signal clkfb : std_logic;
signal clkfbout : std_logic;
signal clk100 : std_logic;
signal locked_internal : std_logic;
signal not_locked : std_logic;
signal internal_rst : std_logic;
--tx interface
signal output_tx_freq : std_logic_vector(31 downto 0);
signal output_tx_freq_stb : std_logic;
signal output_tx_freq_ack : std_logic;
signal output_tx_am : std_logic_vector(31 downto 0);
signal output_tx_am_stb : std_logic;
signal output_tx_am_ack : std_logic;
signal output_tx_ctl : std_logic_vector(31 downto 0);
signal output_tx_ctl_stb : std_logic;
signal output_tx_ctl_ack : std_logic;
signal input_gps_count : std_logic_vector(31 downto 0);
signal input_gps_count_stb : std_logic;
signal input_gps_count_ack : std_logic;
--rs232 rx stream
signal input_rs232_rx : std_logic_vector(31 downto 0);
signal input_rs232_rx_stb : std_logic;
signal input_rs232_rx_ack : std_logic;
--rs232 tx stream
signal output_rs232_tx : std_logic_vector(31 downto 0);
signal output_rs232_tx_stb : std_logic;
signal output_rs232_tx_ack : std_logic;
--gps rx stream
signal input_gps_rx : std_logic_vector(31 downto 0);
signal input_gps_rx_stb : std_logic;
signal input_gps_rx_ack : std_logic;
--gps tx stream
signal output_gps_tx : std_logic_vector(31 downto 0);
signal output_gps_tx_stb : std_logic;
signal output_gps_tx_ack : std_logic;
signal s_test_1 : std_logic := '0';
signal s_test_2 : std_logic := '0';
signal output_leds : std_logic_vector(31 downto 0);
signal output_leds_stb : std_logic;
signal output_leds_ack : std_logic;
begin
ld1 <= '1';
transmitter_inst_1 : transmitter port map(
clk => clk,
rst => internal_rst,
frequency => output_tx_freq,
frequency_stb => output_tx_freq_stb,
frequency_ack => output_tx_freq_ack,
control => output_tx_ctl,
control_stb => output_tx_ctl_stb,
control_ack => output_tx_ctl_ack,
amplitude => output_tx_am,
amplitude_stb => output_tx_am_stb,
amplitude_ack => output_tx_am_ack,
tx_rx => tx_rx,
tx_pa => tx_pa,
rf => rf_out
);
process
begin
wait until rising_edge(clk);
if output_tx_freq_stb = '1' then
s_test_1 <= not s_test_1;
end if;
if output_tx_am_stb = '1' then
s_test_2 <= not s_test_2;
end if;
end process;
user_design_inst_1 : user_design port map(
clk => clk,
rst => internal_rst,
--rs232 rx stream
input_rs232_rx => input_rs232_rx,
input_rs232_rx_stb => input_rs232_rx_stb,
input_rs232_rx_ack => input_rs232_rx_ack,
--rs232 tx stream
output_rs232_tx => output_rs232_tx,
output_rs232_tx_stb => output_rs232_tx_stb,
output_rs232_tx_ack => output_rs232_tx_ack,
--gps rx stream
input_gps_rx => input_gps_rx,
input_gps_rx_stb => input_gps_rx_stb,
input_gps_rx_ack => input_gps_rx_ack,
--gps tx stream
output_gps_tx => output_gps_tx,
output_gps_tx_stb => output_gps_tx_stb,
output_gps_tx_ack => output_gps_tx_ack,
input_gps_count => input_gps_count,
input_gps_count_stb => input_gps_count_stb,
input_gps_count_ack => input_gps_count_ack,
output_leds => output_leds,
output_leds_stb => output_leds_stb,
output_leds_ack => output_leds_ack,
--transmit interface
output_tx_freq => output_tx_freq,
output_tx_freq_stb => output_tx_freq_stb,
output_tx_freq_ack => output_tx_freq_ack,
output_tx_am => output_tx_am,
output_tx_am_stb => output_tx_am_stb,
output_tx_am_ack => output_tx_am_ack,
output_tx_ctl => output_tx_ctl,
output_tx_ctl_stb => output_tx_ctl_stb,
output_tx_ctl_ack => output_tx_ctl_ack
);
pps1 : gps_pps port map(
clk => clk,
pps => pps,
pps_count => input_gps_count,
pps_count_stb => input_gps_count_stb,
pps_count_ack => input_gps_count_ack
);
serial_output_inst_1 : serial_output generic map(
clock_frequency => 100000000,
baud_rate => 12000000
)port map(
clk => clk,
rst => internal_rst,
tx => rs232_tx,
in1 => output_rs232_tx(7 downto 0),
in1_stb => output_rs232_tx_stb,
in1_ack => output_rs232_tx_ack
);
serial_input_inst_1 : serial_input generic map(
clock_frequency => 100000000,
baud_rate => 12000000
) port map (
clk => clk,
rst => internal_rst,
rx => rs232_rx,
out1 => input_rs232_rx(7 downto 0),
out1_stb => input_rs232_rx_stb,
out1_ack => input_rs232_rx_ack
);
input_rs232_rx(15 downto 8) <= (others => '0');
serial_output_inst_2 : serial_output generic map(
clock_frequency => 100000000,
baud_rate => 9600
)port map(
clk => clk,
rst => internal_rst,
tx => gps_rx,
in1 => output_gps_tx(7 downto 0),
in1_stb => output_gps_tx_stb,
in1_ack => output_gps_tx_ack
);
serial_input_inst_2 : serial_input generic map(
clock_frequency => 100000000,
baud_rate => 9600
) port map (
clk => clk,
rst => internal_rst,
rx => gps_tx,
out1 => input_gps_rx(7 downto 0),
out1_stb => input_gps_rx_stb,
out1_ack => input_gps_rx_ack
);
input_gps_rx(15 downto 8) <= (others => '0');
process
begin
wait until rising_edge(clk);
if output_leds_stb = '1' then
leds <= output_leds(7 downto 0);
end if;
end process;
output_leds_ack <= '1';
-- input buffering
--------------------------------------
clkin1_buf : ibufg
port map
(o => clkin1,
i => clk_in);
mmcme2_base_inst : mmcme2_base
generic map (
bandwidth => "optimized", -- jitter programming (optimized, high, low)
clkfbout_mult_f => 50.0, -- multiply value for all clkout (2.000-64.000).
clkfbout_phase => 0.0, -- phase offset in degrees of clkfb (-360.000-360.000).
clkin1_period => 83.333, -- input clock period in ns to ps resolution (i.e. 33.333 is 30 mhz).
-- clkout0_divide - clkout6_divide: divide amount for each clkout (1-128)
clkout1_divide => 1,
clkout2_divide => 1,
clkout3_divide => 1,
clkout4_divide => 1,
clkout5_divide => 1,
clkout6_divide => 1,
clkout0_divide_f => 6.0, -- divide amount for clkout0 (1.000-128.000).
-- clkout0_duty_cycle - clkout6_duty_cycle: duty cycle for each clkout (0.01-0.99).
clkout0_duty_cycle => 0.5,
clkout1_duty_cycle => 0.5,
clkout2_duty_cycle => 0.5,
clkout3_duty_cycle => 0.5,
clkout4_duty_cycle => 0.5,
clkout5_duty_cycle => 0.5,
clkout6_duty_cycle => 0.5,
-- clkout0_phase - clkout6_phase: phase offset for each clkout (-360.000-360.000).
clkout0_phase => 0.0,
clkout1_phase => 0.0,
clkout2_phase => 0.0,
clkout3_phase => 0.0,
clkout4_phase => 0.0,
clkout5_phase => 0.0,
clkout6_phase => 0.0,
clkout4_cascade => false, -- cascade clkout4 counter with clkout6 (false, true)
divclk_divide => 1, -- master division value (1-106)
ref_jitter1 => 0.0, -- reference input jitter in ui (0.000-0.999).
startup_wait => false -- delays done until mmcm is locked (false, true)
)
port map (
clkout0 => clk100, -- 1-bit output: clkout0
clkout0b => open, -- 1-bit output: inverted clkout0
clkout1 => open, -- 1-bit output: clkout1
clkout1b => open, -- 1-bit output: inverted clkout1
clkout2 => open, -- 1-bit output: clkout2
clkout2b => open, -- 1-bit output: inverted clkout2
clkout3 => open, -- 1-bit output: clkout3
clkout3b => open, -- 1-bit output: inverted clkout3
clkout4 => open, -- 1-bit output: clkout4
clkout5 => open, -- 1-bit output: clkout5
clkout6 => open, -- 1-bit output: clkout6
-- feedback clocks: 1-bit (each) output: clock feedback ports
clkfbout => clkfbout, -- 1-bit output: feedback clock
clkfboutb => open, -- 1-bit output: inverted clkfbout
-- status ports: 1-bit (each) output: mmcm status ports
locked => locked_internal, -- 1-bit output: lock
-- clock inputs: 1-bit (each) input: clock input
clkin1 => clkin1, -- 1-bit input: clock
-- control ports: 1-bit (each) input: mmcm control ports
pwrdwn => '0', -- 1-bit input: power-down
rst => rst, -- 1-bit input: reset
-- feedback clocks: 1-bit (each) input: clock feedback ports
clkfbin => clkfb -- 1-bit input: feedback clock
);
process
begin
wait until rising_edge(clk);
not_locked <= not locked_internal;
internal_rst <= not_locked;
end process;
-- output buffering
-------------------------------------
bufg_inst2 : bufg
port map
(o => clkfb,
i => clkfbout);
bufg_inst3 : bufg
port map
(o => clk,
i => clk100);
end architecture rtl;
| mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-3/src/DELAS.vhd | 1 | 380 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DELAS is port(
D : in std_logic;
E : in std_logic;
PRE : in std_logic;
Q : out std_logic
);
end DELAS;
architecture behavior of DELAS is
signal S : std_logic;
begin
Main : process (D, E, PRE)
begin
if(PRE = '1') then
S <= '1';
elsif(E='1') then
S <= D;
end if;
end process;
Q <= S;
end behavior;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.cache/ip/2017.3/2d864de4d8e716fd/led_controller_design_led_controller_0_1_stub.vhdl | 1 | 2702 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:19:38 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_led_controller_0_1_stub.vhdl
-- Design : led_controller_design_led_controller_0_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "led_controller_v1_0,Vivado 2017.3";
begin
end;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution_OH/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fadd_7_full_dsp_32/synth/convolve_kernel_ap_fadd_7_full_dsp_32.vhd | 3 | 12833 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY convolve_kernel_ap_fadd_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END convolve_kernel_ap_fadd_7_full_dsp_32;
ARCHITECTURE convolve_kernel_ap_fadd_7_full_dsp_32_arch OF convolve_kernel_ap_fadd_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fadd_7_full_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fadd_7_full_dsp_32,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS" &
"=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C" &
"_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END convolve_kernel_ap_fadd_7_full_dsp_32_arch;
| mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-3/src/DL.vhd | 1 | 424 |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity DL is port(
D : in std_logic;
Q, nQ : out std_logic
);
end DL;
architecture DL of DL is
component RSL is port(
S,R : in std_logic;
Q, nQ : out std_logic
);
end component;
component NOT1 is port(
a : in std_logic;
z : out std_logic
);
end component;
signal nD : std_logic;
begin
M1: NOT1 port map (D, nD);
M2: RSL port map (D, nD, Q, nQ);
end DL;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_led_controller_0_0/led_controller_design_led_controller_0_0_stub.vhdl | 1 | 2761 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:44:51 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_led_controller_0_0/led_controller_design_led_controller_0_0_stub.vhdl
-- Design : led_controller_design_led_controller_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity led_controller_design_led_controller_0_0 is
Port (
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end led_controller_design_led_controller_0_0;
architecture stub of led_controller_design_led_controller_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "led_controller_v1_0,Vivado 2017.3";
begin
end;
| mit |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-5/src/Task2_TB/Task2_tb3.vhd | 1 | 5414 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task2_ent_tb3 is
end entity Task2_ent_tb3;
architecture Task2_arch_tb3 of Task2_ent_tb3 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task2 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task2;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_state_type is (S0, S1, S2, S3, S4, any_state);
signal test_state : test_state_type;
begin
UUT : Task2
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test reset - state(i)
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
IP <= "0011";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
IP <= "0011";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "1111";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 5;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 6;
wait for delay_wr_in;
RST <= '0';
IP <= "0011";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 7;
wait for delay_wr_in;
RST <= '0';
IP <= "1111";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 8;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 9;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 10;
wait for delay_wr_in;
RST <= '0';
IP <= "0011";
wait for delay_pos_edge;
test_state <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 11;
wait for delay_wr_in;
RST <= '0';
IP <= "1111";
wait for delay_pos_edge;
test_state <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 12;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_state <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 13;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_state <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 14;
wait for delay_wr_in;
RST <= '1';
wait for delay_pos_edge;
test_state <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
-- Test length 15
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task2_arch_tb3;
configuration Task2_cfg_tb3 of Task2_ent_tb3 is
for Task2_arch_tb3
for UUT : Task2 use entity work.Task2(Beh);
end for;
end for;
end Task2_cfg_tb3;
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/ip/tmp.srcs/sources_1/ip/convolve_kernel_ap_fmul_3_max_dsp_32/hdl/xbip_pipe_v3_0_vh_rfs.vhd | 7 | 30625 | `protect begin_protected
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20128)
`protect data_block
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`protect end_protected
| mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/ip/tmp.srcs/sources_1/ip/convolve_kernel_ap_fadd_7_full_dsp_32/hdl/xbip_pipe_v3_0_vh_rfs.vhd | 7 | 30625 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2017_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20128)
`protect data_block
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| mit |
kloboves/sicxe | vhdl/rs232_in.vhd | 1 | 4520 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rs232_in is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
input_i : in std_logic;
data_o : out std_logic_vector(7 downto 0);
receive_o : out std_logic
);
end rs232_in;
architecture behavioral of rs232_in is
-- input sync
signal input_sync : std_logic;
-- delay counter
signal delay_counter : std_logic_vector(8 downto 0);
signal delay_counter_reset : std_logic;
signal delay_counter_half : std_logic;
-- shift register
signal shift_register : std_logic_vector(7 downto 0);
signal shift_register_shift : std_logic;
-- FSM
type state_type is (READY, WAIT_HALF, RECV_START, RECV0, RECV1, RECV2, RECV3,
RECV4, RECV5, RECV6, RECV7, RECV_END);
signal state : state_type;
signal next_state : state_type;
begin
data_o <= shift_register;
-- input sync
input_sync_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
input_sync <= input_i;
end if;
end process;
-- delay counter (set for 115200 boud)
delay_counter_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1' or delay_counter_reset = '1') then
delay_counter <= (others => '0');
else
if (delay_counter = "110110010") then
delay_counter <= (others => '0');
else
delay_counter <= delay_counter + 1;
end if;
end if;
end if;
end process;
delay_counter_half_proc : process(delay_counter)
begin
if (delay_counter = "011011001") then
delay_counter_half <= '1';
else
delay_counter_half <= '0';
end if;
end process;
-- shift register
shift_register_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
shift_register <= (others => '0');
else
if (shift_register_shift = '1') then
shift_register <= input_sync & shift_register(7 downto 1);
else
shift_register <= shift_register;
end if;
end if;
end if;
end process;
-- FSM
sync_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
state <= READY;
else
state <= next_state;
end if;
end if;
end process;
state_proc : process(state, input_sync, delay_counter_half)
begin
next_state <= state;
case (state) is
when READY =>
if (input_sync = '0') then
next_state <= WAIT_HALF;
end if;
when WAIT_HALF =>
if (delay_counter_half = '1') then
next_state <= RECV_START;
end if;
when RECV_START =>
if (delay_counter_half = '1') then
next_state <= RECV0;
end if;
when RECV0 =>
if (delay_counter_half = '1') then
next_state <= RECV1;
end if;
when RECV1 =>
if (delay_counter_half = '1') then
next_state <= RECV2;
end if;
when RECV2 =>
if (delay_counter_half = '1') then
next_state <= RECV3;
end if;
when RECV3 =>
if (delay_counter_half = '1') then
next_state <= RECV4;
end if;
when RECV4 =>
if (delay_counter_half = '1') then
next_state <= RECV5;
end if;
when RECV5 =>
if (delay_counter_half = '1') then
next_state <= RECV6;
end if;
when RECV6 =>
if (delay_counter_half = '1') then
next_state <= RECV7;
end if;
when RECV7 =>
if (delay_counter_half = '1') then
next_state <= RECV_END;
end if;
when RECV_END =>
if (input_sync = '1') then
next_state <= READY;
end if;
when others =>
end case;
end process;
output_proc : process(state, input_sync, delay_counter_half)
begin
delay_counter_reset <= '0';
shift_register_shift <= '0';
receive_o <= '0';
case (state) is
when READY =>
if (input_sync = '0') then
delay_counter_reset <= '1';
end if;
when WAIT_HALF =>
when RECV_START | RECV0 | RECV1 | RECV2 | RECV3 | RECV4 | RECV5 | RECV6 =>
if (delay_counter_half = '1') then
shift_register_shift <= '1';
end if;
when RECV7 =>
if (delay_counter_half = '1') then
receive_o <= '1';
end if;
when RECV_END =>
when others =>
end case;
end process;
end behavioral;
| mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/sqrt/hdl/xbip_bram18k_v3_0_vh_rfs.vhd | 12 | 103154 | `protect begin_protected
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| mit |
ashikpoojari/Hardware-Security | Interfaces/UART_Version_3/Uart_working/RS232RefComp.vhd | 2 | 10758 |
-- Description: This file defines a UART which tranfers data from
-- serial form to parallel form and vice versa.
------------------------------------------------------------------------
-- Revision History:
-- 07/15/04 (Created) DanP
-- 02/25/08 (Created) ClaudiaG: made use of the baudDivide constant
-- in the Clock Dividing Processes
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Rs232RefComp is
Port (
TXD : out std_logic := '1';
RXD : in std_logic;
CLK : in std_logic; --Master Clock = 50MHz
DBIN: in std_logic_vector (7 downto 0); --Data Bus in
DBOUT: out std_logic_vector (7 downto 0); --Data Bus out
RDA : inout std_logic; --Read Data Available
TBE : inout std_logic := '1'; --Transfer Bus Empty
RD : in std_logic; --Read Strobe
WR : in std_logic; --Write Strobe
PE : out std_logic; --Parity Error Flag
FE : out std_logic; --Frame Error Flag
OE : out std_logic; --Overwrite Error Flag
RST : in std_logic := '0'); --Master Reset
end Rs232RefComp;
architecture Behavioral of Rs232RefComp is
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
------------------------------------------------------------------------
-- Local Type Declarations
------------------------------------------------------------------------
--Receive state machine
type rstate is (
strIdle, --Idle state
strEightDelay, --Delays for 8 clock cycles
strGetData, --Shifts in the 8 data bits, and checks parity
strCheckStop --Sets framing error flag if Stop bit is wrong
);
type tstate is (
sttIdle, --Idle state
sttTransfer, --Move data into shift register
sttShift --Shift out data
);
type TBEstate is (
stbeIdle,
stbeSetTBE,
stbeWaitLoad,
stbeWaitWrite
);
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
constant baudDivide : std_logic_vector(7 downto 0) := "10100011"; --Baud Rate dividor, set now for a rate of 9600.
--Found by dividing 50MHz by 9600 and 16.
signal rdReg : std_logic_vector(7 downto 0) := x"00"; --Receive holding register
signal rdSReg : std_logic_vector(9 downto 0) := "1111111111"; --Receive shift register
signal tfReg : std_logic_vector(7 downto 0); --Transfer holding register
signal tfSReg : std_logic_vector(10 downto 0) := "11111111111"; --Transfer shift register
signal clkDiv : std_logic_vector(8 downto 0) := "000000000"; --used for rClk
signal rClkDiv : std_logic_vector(3 downto 0) := "0000"; --used for tClk
signal ctr : std_logic_vector(3 downto 0) := "0000"; --used for delay times
signal tfCtr : std_logic_vector(3 downto 0) := "0000"; --used to delay in transfer
signal rClk : std_logic := '0'; --Receiving Clock
signal tClk : std_logic; --Transfering Clock
signal dataCtr : std_logic_vector(3 downto 0) := "0000"; --Counts the number of read data bits
signal parError: std_logic; --Parity error bit
signal frameError: std_logic; --Frame error bit
signal CE : std_logic; --Clock enable for the latch
signal ctRst : std_logic := '0';
signal load : std_logic := '0';
signal shift : std_logic := '0';
signal par : std_logic;
signal tClkRST : std_logic := '0';
signal rShift : std_logic := '0';
signal dataRST : std_logic := '0';
signal dataIncr: std_logic := '0';
signal trainingdone: std_logic:= '0';
signal strCur : rstate := strIdle; --Current state in the Receive state machine
signal strNext : rstate; --Next state in the Receive state machine
signal sttCur : tstate := sttIdle; --Current state in the Transfer state machine
signal sttNext : tstate; --Next state in the Transfer staet machine
signal stbeCur : TBEstate := stbeIdle;
signal stbeNext: TBEstate;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
frameError <= not rdSReg(9);
parError <= not ( rdSReg(8) xor (((rdSReg(0) xor rdSReg(1)) xor (rdSReg(2) xor rdSReg(3))) xor ((rdSReg(4) xor rdSReg(5)) xor (rdSReg(6) xor rdSReg(7)))) );
DBOUT <= rdReg;
tfReg <= DBIN;
par <= not ( ((tfReg(0) xor tfReg(1)) xor (tfReg(2) xor tfReg(3))) xor ((tfReg(4) xor tfReg(5)) xor (tfReg(6) xor tfReg(7))) );
--Clock Dividing Functions--
process (CLK, clkDiv) --set up clock divide for rClk
begin
if (Clk = '1' and Clk'event) then
if (clkDiv = baudDivide) then
clkDiv <= "000000000";
else
clkDiv <= clkDiv +1;
end if;
end if;
end process;
process (clkDiv, rClk, CLK) --Define rClk
begin
if CLK = '1' and CLK'Event then
if clkDiv = baudDivide then
rClk <= not rClk;
else
rClk <= rClk;
end if;
end if;
end process;
process (rClk) --set up clock divide for tClk
begin
if (rClk = '1' and rClk'event) then
rClkDiv <= rClkDiv +1;
end if;
end process;
tClk <= rClkDiv(3); --define tClk
process (rClk, ctRst) --set up a counter based on rClk
begin
if rClk = '1' and rClk'Event then
if ctRst = '1' then
ctr <= "0000";
else
ctr <= ctr +1;
end if;
end if;
end process;
process (tClk, tClkRST) --set up a counter based on tClk
begin
if (tClk = '1' and tClk'event) then
if tClkRST = '1' then
tfCtr <= "0000";
else
tfCtr <= tfCtr +1;
end if;
end if;
end process;
--This process controls the error flags--
process (rClk, RST, RD, CE)
begin
if RD = '1' or RST = '1' then
FE <= '0';
OE <= '0';
RDA <= '0';
PE <= '0';
elsif rClk = '1' and rClk'event then
if CE = '1' then
FE <= frameError;
OE <= RDA;
RDA <= '1';
PE <= parError;
rdReg(7 downto 0) <= rdSReg (7 downto 0);
end if;
end if;
end process;
--This process controls the receiving shift register--
process (rClk, rShift)
begin
if rClk = '1' and rClk'Event then
if rShift = '1' then
rdSReg <= (RXD & rdSReg(9 downto 1));
end if;
end if;
end process;
--This process controls the dataCtr to keep track of shifted values--
process (rClk, dataRST)
begin
if (rClk = '1' and rClk'event) then
if dataRST = '1' then
dataCtr <= "0000";
elsif dataIncr = '1' then
dataCtr <= dataCtr +1;
end if;
end if;
end process;
--Receiving State Machine--
process (rClk, RST)
begin
if rClk = '1' and rClk'Event then
if RST = '1' then
strCur <= strIdle;
else
strCur <= strNext;
end if;
end if;
end process;
--This process generates the sequence of steps needed receive the data
process (strCur, ctr, RXD, dataCtr, rdSReg, rdReg, RDA)
begin
case strCur is
when strIdle =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
CE <= '0';
if RXD = '0' then
ctRst <= '1';
strNext <= strEightDelay;
else
ctRst <= '0';
strNext <= strIdle;
end if;
when strEightDelay =>
dataIncr <= '0';
rShift <= '0';
CE <= '0';
if ctr(2 downto 0) = "111" then
ctRst <= '1';
dataRST <= '1';
strNext <= strGetData;
else
ctRst <= '0';
dataRST <= '0';
strNext <= strEightDelay;
end if;
when strGetData =>
CE <= '0';
dataRst <= '0';
if ctr(3 downto 0) = "1111" then
ctRst <= '1';
dataIncr <= '1';
rShift <= '1';
else
ctRst <= '0';
dataIncr <= '0';
rShift <= '0';
end if;
if dataCtr = "1010" then
strNext <= strCheckStop;
else
strNext <= strGetData;
end if;
when strCheckStop =>
dataIncr <= '0';
rShift <= '0';
dataRst <= '0';
ctRst <= '0';
CE <= '1';
strNext <= strIdle;
end case;
end process;
--TBE State Machine--
process (CLK, RST)
begin
if CLK = '1' and CLK'Event then
if RST = '1' then
stbeCur <= stbeIdle;
else
stbeCur <= stbeNext;
end if;
end if;
end process;
--This process gererates the sequence of events needed to control the TBE flag--
process (stbeCur, CLK, WR, DBIN, load)
begin
case stbeCur is
when stbeIdle =>
TBE <= '1';
if WR = '1' then
stbeNext <= stbeSetTBE;
else
stbeNext <= stbeIdle;
end if;
when stbeSetTBE =>
TBE <= '0';
if load = '1' then
stbeNext <= stbeWaitLoad;
else
stbeNext <= stbeSetTBE;
end if;
when stbeWaitLoad =>
if load = '0' then
stbeNext <= stbeWaitWrite;
else
stbeNext <= stbeWaitLoad;
end if;
when stbeWaitWrite =>
if WR = '0' then
stbeNext <= stbeIdle;
else
stbeNext <= stbeWaitWrite;
end if;
end case;
end process;
--This process loads and shifts out the transfer shift register--
process (load, shift, tClk, tfSReg)
begin
TXD <= tfsReg(0);
if tClk = '1' and tClk'Event then
if load = '1' then
tfSReg (10 downto 0) <= ('1' & par & tfReg(7 downto 0) &'0');
end if;
if shift = '1' then
tfSReg (10 downto 0) <= ('1' & tfSReg(10 downto 1));
end if;
end if;
end process;
-- Transfer State Machine--
process (tClk, RST)
begin
if (tClk = '1' and tClk'Event) then
if RST = '1' then
sttCur <= sttIdle;
else
sttCur <= sttNext;
end if;
end if;
end process;
-- This process generates the sequence of steps needed transfer the data--
process (sttCur, tfCtr, tfReg, TBE, tclk)
begin
case sttCur is
when sttIdle =>
tClkRST <= '0';
shift <= '0';
load <= '0';
if TBE = '1' then
sttNext <= sttIdle;
else
sttNext <= sttTransfer;
end if;
when sttTransfer =>
shift <= '0';
load <= '1';
tClkRST <= '1';
sttNext <= sttShift;
when sttShift =>
shift <= '1';
load <= '0';
tClkRST <= '0';
if tfCtr = "1100" then
sttNext <= sttIdle;
else
sttNext <= sttShift;
end if;
end case;
end process;
end Behavioral; | mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_rst_ps7_0_100M_0/sim/system_rst_ps7_0_100M_0.vhd | 1 | 5839 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_10;
USE proc_sys_reset_v5_0_10.proc_sys_reset;
ENTITY system_rst_ps7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_rst_ps7_0_100M_0;
ARCHITECTURE system_rst_ps7_0_100M_0_arch OF system_rst_ps7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END system_rst_ps7_0_100M_0_arch;
| mit |
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